Universal asynchronous receiver/transmitter.

The present invention relates to data communication between a data processing system and its associated peripherals, and more particularly to an improved universal asynchronous receiver / transmitter (UART) device. According to the invention, the multichannel UART allows rival writes to the same register of the same register group of each channel.

Data communication is a comprehensive term used to define the transfer of data from one point to another.

To ensure coherent data communications between two or more points, e.g. Between a data processing system and one of its peripherals, an interface standard is set to define the characteristics of the communication link.

The most common interface standard for data transmission is asynchronous communication. This standard specifies that each data symbol to be transmitted is preceded by a "start" bit, followed by one or more "stop" bits. Between the characters a marking condition is continuously maintained. Because each transmitted character is bracketed by these "start" and "stop" bits, the receiver is resynchronized with each transmission, allowing for unequal intervals between characters.

A commonly used asynchronous data communication device is the universal asynchronous receiver / transmitter or UART. A conventional UART relies on two separate serial shift registers, each with its own serial port and clock, to receive the data from a modem or peripheral device in response to control signals from the associated data processing system, or to send the data to a modem or peripheral device send. This architecture allows data to be simultaneously sent and received at different data rates through the UART.

To transmit the data from its associated data processing system to a selected modem or peripheral device, a UART may request the parallel transmission of data (typically an 8-bit character or a byte applied to the system's data bus) into the UART's station holding register , The transmitter holding register then transfers the data to a transmitter shift register which serially transmits each bit of data to the peripheral device. Initially, when the station hold register is empty, the UART signals the CPU that it is ready to receive data. The data is transmitted when a data strobe signal input from the system to the UART is appropriately clocked.

Because the transmitter holding register is "empty" as soon as the data is transferred in parallel to the transmitter shift register, even if the actual serial shift of the data by the shift register is not completed, the UART can indicate to the data processing system that a new data character can be loaded into the holding register , If the new data is loaded into the holding register, if the serial transmitter shift register is not yet free, the data is held in the holding register until the serial shift of the initial data is completed. The transmission of the new data into the shift register can then take place.

Thus, a conventional UART can store a maximum of two data characters for transmission from its associated data processing system. If the complete transmission requires transmission of more than two characters, the data transfer system, which can transfer the data much faster than the UART's sender shift register, must either wait for the shift register to complete its serial transfer or it must take on various tasks and then respond to multiple interrupts from the UART to complete the transfer. Both alternatives are an extremely inefficient use of data processing time.

The receipt of the data by the data processing system from a modem or other peripheral device via the UART is subject to the same time inefficiencies as the data transfer. That is, the processor is inhibited by the speed of operation and the data width of the receiver portion of the UART. As with data transfer, the UART uses a shift register and a holding register to receive the data. A data character is serially shifted by the modem or peripheral to a serial-to-parallel receiver shift register. When the complete data character in the shift register has been assembled, it is transferred to a receiver holding register, thereby freeing the receiver shift register to receive the next character from the transmission line. The UART indicates to the processor system that it has received data ready to be transmitted, applying the data to the system bus for parallel transmission when the system receives the appropriate alert signal.

The UARTs can be used in either an interrupt mode or in a polling configuration. In the interrupt configuration, the UART sends an interrupt to the data processing system, which processes it either by applying data to the system bus or by fetching data from the system bus. Because a conventional UART can store only a single data character in each of its receiver and transmitter holding registers, multiple interrupts are required if many data bytes are to be transmitted or received.

To lessen the interrupt overhead of the processor, a newer UART design has replaced the one-byte receiver and transmitter holding registers with multi-byte (multi-byte) FIFO memories. National Semiconductor Corporation's UART NS16550A uses two user-selectable 16-byte FIFO memory as the transmitter and receiver buffers. These transmitter and receiver FIFOs allow the accumulation of data characters within the UART, eliminating the need for multiple interruptions of the processor in its transmission and receipt of data. A UART of this type is disclosed in pending US patent application Ifd. No. 924,797, filed October 30, 1986 by Michael et al. For ASYNCHRONOUS COMMUNICATION ELEMENT; The just-identified application by Michael et al is hereby incorporated by reference in order to provide additional background information for the present invention.

Although the NS16550A-UART is a sophisticated device, its status indicators are mainly based on single-byte error indications.

In the overwhelming majority of cases, the data received by the UART is error free. Conventional status indicators, however, have not allowed the data processing system to detect the number of consecutive error-free data bytes in the receiver FIFO. This prevents the removal of consecutive bytes of data by the data processing system until the state for each byte is read first. Because the state of the error-free data is irrelevant, a significant portion of the access time of the data processing system is wasted, ie, a two-clock access for each data byte to be read in the case of error-free data.

There are also UARTs available that provide multiple channels for asynchronous communication between a data processing system and a number of dedicated peripherals. Each UART channel contains its own register group, which is identical to the register group of each of the other channels. This register group stores the information that identifies the channel with respect to its operation. The register group of each channel typically loads the appropriate digital information about the initialization of the UART; This information can then be dynamically modified to meet changing operational requirements. A problem inherent in conventional multi-channel UARTs is that although it may be desirable to load identical information into the respective registers of each channel, this information must be sequentially loaded into the registers of the individual channels. In this way, loading the registers with identical information, both initialization and dynamic modification, wastes valuable processing time.

The multi-port communication device disclosed in US 4,751,634 is based on such standard UARTs, thus showing the same inefficient register initialization procedure.

Data transmission in a data processing system can generally be assigned to one of three basic types: I / O compliant, memory compliant, or direct memory access (DMA). I / O-compliant and memory-compliant transfers require intervention by the processor, so the processor is busy during the time these data transfers are implemented. The DMA transfers between a peripheral device and the system memory provide a path for direct data transfer without the intervention of the processor. In this way, using this approach, the peripheral device can transfer data directly to or from memory at high speed while the processor is free to perform other tasks during the transfer.

Unfortunately, the DMA capabilities of conventional UARTs do not take into account the handling of control characters, errors, or changing amounts of data received by the UART during DMA while using either internal or external FIFOs. Traditional UARTs do not distinguish between control characters, errors, or changing amounts of valid data before requesting DMA transfer. Consequently, the data processing system must either resolve all exceptional data cases or prevent the DMA transfer of received data. However, because, as explained above, most of the received data is valid and without exceptions, the UART need only request processing time for data transfers when it detects an exceptional byte of data.

A universal asynchronous receiver / transmitter (UART) in accordance with the present invention provides a group of identical register groups, each of which is uniquely associated with one of a plurality of communication channels, each containing an initialization register. Setting the appropriate bit in the initialization register of any UART channel allows the data processing system to competitively write to the same selected register in the register group of each channel. This feature reduces the initialization time for all common parameters loaded into the registers of each channel.

Other features and advantages of the present invention will be apparent and appreciated by reference to the detailed description of the invention given below, which should be considered in conjunction with the accompanying drawings.

Fig. 1 is a schematic representation of a register group with extended features of a UART according to the present invention.

Fig. 2 is a block diagram illustrating the architecture of a UART according to the present invention.

Fig. 3 is a schematic representation of Rx FIFO and Tx FIFO data transfers in a UART in accordance with the present invention.

4 is a schematic representation of the format of the data, byte state, channel state, and channel exception registers of the extended feature register set of a UART in accordance with the present invention.

Fig. 5 is a schematic representation of the format of the control, channel I / O, Tx-CNT, and Rx-CNT registers of the extended feature register set of a UART according to the present invention.

Fig. 6 is a schematic representation of the format of the divisor and initialization registers, the comparison registers 0-3 and the comparison registers 4-7 of the alternative register group of a UART according to the present invention.

Fig. 7 is a flow chart illustrating the procedure of maintaining an internal and / or external sender FIFO associated with a system DMA unit.

Fig. 8 is a flowchart illustrating the procedure of maintaining an internal and / or external receiver FIFO associated with a system DMA unit.

In Fig. 1, the extended asynchronous receiver / transmitter (UART) register group A according to the present invention consists of eight 32-bit wide registers including five registers (addresses 00000 to 10000) for the standard serial channel operation, the DMA operation and the automated transmission -Tx flow control, a register (address 10100) for a modem or general purpose I / O features, and two registers (addresses 11000 and 11100) for controlling the external FIFO.

In addition to the modern register group A, by setting an alternate register bit, an alternate register group B containing eight 32-bit registers can be accessed. The alternate register group B is mainly used during UART initialization. Received data compare registers, a baud rate divisor, and an I / O data direction register (accessed at the addresses shown in FIG. 1 are displayed) can be accessed when the alternate register bit is set.

In Fig. 2, five address pins A0-A4 are used to select the internal registers. Identical register groups are located in each of the four serial channels available in the UART embodiment described below; the channel select pins are provided for accessing the register groups of each serial channel.

All four UART channels are reset to a compatibility mode. Two bits in a compatibility mode register group, shown in Figure 1, allow selection of 8, 16 or 32 bit bus width operation or compatibility mode operation. These two bits are IER6 and IER7 in the Interrupt Enable Register (IER), which is discussed in more detail below. If IER6,7 is set to 00, 01, 10, or 11 then the UART modes are compatibility, 8, 16, and 32 bits, respectively.

In Fig. 1, a DATA register (address 00000) is organized as 4, 2, or 1-byte wide fields depending on the programmed bus width. In Fig. 2, in the case of both the receiver and transmitter portions of the UART, the DATA register represents the memory location at the top of a FIFO, which is used to read the data from a receiver Rx FIFO 12 or to write the data into a transmitter Tx FIFO 14. (Any reference to the "Rx FIFO" or "Tx FIFO" in the following description is a reference to the internal UART FIFOs 12 and 14, respectively. Any reference to an external Tx FIFO or external Rx FIFO will precede the word "external.")

The Rx and Tx FIFOs 12 and 14, respectively, have a constant length regardless of the bus width. That is, compared to the 8-bit mode in the 16-bit mode, half the number of accesses is required to transfer the data to / from these FIFOs while compared to the 8-bit mode. Operating mode in the 32-bit mode, a quarter of the number of accesses is required to transfer the data to these / these FIFOs.

As shown in FIG. 3 1, while during a single access (16-bit or 32-bit mode), multiple bytes are being transferred from the Rx FIFO 12 through the data buffer 10, the least significant byte on the CPU bus is the byte earlier when the other bytes were received; while, during a single access (16-bit or 32-bit mode), several bytes are transferred from the Tx FIFO 14 through the data bus buffer 10, the least significant byte on the CPU bus is the first byte sent on the serial line is.

The byte state register (BSR) 16 provides the associated line state and byte match information for each byte that the CPU reads from the Rx FIFO 12. As shown in Figure 1, the BSR 16 (address 00100) contains 4, 2 or 1 byte wide fields depending on the programmed bus width. The type of information provided by the BSR 16 for each byte of data received is the overflow, parity, and frame errors; the interrupt indication, the byte match, and the byte match ID. The single byte state remains in the BSR 16 until the associated data has been read from the Rx FIFO 12. The BSR 16 is updated with the state for the next group of data bytes as soon as these bytes can be read from the Rx FIFO 12. In the block mode, described in more detail below, the BSR 16 accumulates the state of each byte until it is read. If there are fewer data bytes than the full bus width to be given during data read, the status bytes in the BSR 16 will correspond to the position of the data bytes that can be read from the Rx FIFO 12.

A channel state register (CSR) provides status indication for all interrupt conditions. As shown in Fig. 1, the CSR (address 01000) contains two byte wide fields called interrupt identification (IIR) and bytes to exception (BTE) and two byte wide reserved fields.

The bits of the IIR field are set when their associated interrupt condition is active. The appropriate bit in the IER must be set before any indication in the IIR field can activate the external interrupt signal. However, the IIR bit is set if there is an active interrupt condition regardless of setting the interrupt enable bit.

The following interrupt conditions set each IIR bit:

1. Reaching a programmed receiver trip level or an active receiver timeout condition sets bit IIR7.

Second A match in any of the comparison registers (described above) sets bit IIR6.

Third A line condition error condition (parity, framing, overflow, interruption) sets bit IIR5.

4th A change in any input status indication from the general purpose I / O lines programmed as inputs to the data direction register (described above) sets bit IIR4.

5th A match in any of the compare Tx flow control registers sets bit IIR3.

6th A Tx FIFO empty condition (TFE condition) or the completion of a pre-programmed number of transmitter transmissions by DMA sets bit IIR2. The TFE condition is cleared after the transmitter enable bit is reset or a byte is loaded into the Tx FIFO 14.

7th The completion of a previously programmed number of receiver transmissions by DMA sets bit IIR1.

The IRR bit 0 (TEMT) is set when the transmitter is completely empty. Setting this bit can not cause an interrupt to occur but is included in this register for the convenience of checking the transmitter during half-duplex operation.

In Fig. 2, byte-to-exception register (BTE) register 18 according to the present invention indicates how many bytes remain in Rx FIFO 12 until an exception occurs. An exception in this context is defined as anything other than valid data, e.g. An empty Rx FIFO 12, a line state error, or a match with the compare register. The BTE count is the status display that the system will most often use because the data is normally received by the UART without error. The count in the BTE 18 is updated by the CPU after each read from the Rx FIFO 12.

The BTE 18 eliminates the need to check the state on each byte because the CPU can now allow the UART to perform this function. The UART then provides the count of consecutive valid data bytes from the top of the Rx FIFO 12 to the first exception. The CPU uses this variable count to determine the number of bytes to extract from the Rx FIFO 12 in a read access.

In the 16-bit mode, the channel state is accessed by a 16-bit wide register, in the 8-bit mode, the channel state is accessed by the two byte-wide registers IIR and BTE.

In Fig. 1, the channel exception register (CER) (address 01100) contains two byte wide fields called interrupt enable (IER) and FIFO state (FSR), and two byte wide reserved fields.

The IER field holds the interrupt release data. The eight possible breaks are:

1. Receiver FIFO trigger level (RFT) or receiver count (RCR);

Second Match (MCH);

Third Line condition (LSI);

4th Input state (ISI);

5th Transmitter FIFO Flow Control (TFC);

6th Transmitter FIFO Empty (TFE) or Transmitter Count (TCR); and

7th Receiver timeout (RTO).

The RFT and RCR interrupts are mutually exclusive operations in the UART, as are the TFE and TCR interrupts. All interrupt priorities are user-defined.

The FSR field indicates the number of voids in the Tx FIFO 14 whether a match or error is detected anywhere in the Rx FIFO 12 and which bytes in the DATA register are valid receiver serial data. Bits FSR7,6 indicate the number of voids in Tx FIFO 14 according to the following code:

The FSR5 bit indicates that at least one byte is loaded into the Rx FIFO 12 that matches one byte in the compare registers 2-7. This bit is used as an extended signal that there is a control character to be processed.

Bit FSR4 indicates that there is at least one line status indication associated with the byte of data in Rx FIFO 12. This bit is used as an extended signal that an error or interrupt has occurred.

Bits FSR3-0 indicate the byte positions at the top of the Rx FIFO 12 that contain valid data. This is only needed by the CPU if there is less than an integer number of data bytes transferred during a 16 or 32-bit wide read. If there are fewer bytes of valid receiver data in the DATA register than the bus is wide, then bits FSR3-0 are set in the FSR field to indicate the valid data byte locations. Only the consecutive data bytes valid at the time the FSR field is read will be output to the CPU during the next read of the DATA register. In this way, by comparing the bits set in the FSR with the bytes received from the DATA register, the user can determine which bytes are valid. This technique means that the UART will not move any additional data into the top of the FIFO until the CPU reads the DATA register. Therefore, the CPU should read the DATA register as soon as possible after reading the FSR to "free" any unused space at the top of the FIFO. During this time, the bytes are still being taken into the open space, which is not included in the top of the FIFO.

The following example is given using a 32-bit wide CPU data bus. The CPU reads the FSR field if there are only three consecutive valid data bytes in the Rx FIFO 12 and no other data. Consequently, the three least significant bits are set in the FSR. When the CPU then reads the DATA register, the UART will output only three valid data bytes in the least significant byte positions and one 00 characters in the most significant byte position. This is the case even if a valid byte of data is input to the Rx FIFO 12 between the time the CPU reads the FSR field and the time it reads the DATA register. At all other times, the data transferred to the CPU bus will be as wide as the bus.

The following example is given using a 16-bit wide CPU data bus. The CPU reads the FSR field if there is only one valid byte of data in the Rx FIFO 12 and no other data. Consequently, the least significant bit is set in the FSR. When the CPU then reads the DATA register, the UART will only issue a valid byte of data in the least significant byte positions and a 00 in the most significant byte position. This is the case even if a valid byte of data is input to the Rx FIFO 12 between the time the CPU reads the FSR field and the time it reads the DATA register. At all other times, the data transferred to the CPU bus will be as wide as the bus.

The control register (address 10000) is the heart of the UART operations. It contains four byte-wide fields identified as channel format (CFR), channel operations (COR), transmitter operation (TOR), and receiver operation (ROR) in Figs.

The CFR field controls the release of the UART block mode and the serial data format. The block mode determines if 16 receiver errors will be accumulated in the BSR. If the block mode is enabled, the BSR 16 accumulates all errors, interrupts, and match information associated with the data passing through the top of the Rx FIFO 12. The results of this accumulation are indicated by the LSI and Match bits in the IIR field. After the CPU reads the BSR 16, all status bits including the associated IIR bits are cleared. Setting the CFR6 bit enables the block mode.

The specification of the serial data format includes the data length (5-8 bits), the stop bits (1, 1 1/2, 2) and the parity. If the CFR5 bit is 0, a stop bit is sent with all data combinations. When the CFR5 bit is 1, two stop bits are sent with all the combinations of the data, except for 5-bit data sent with 1.5 stop bits. The setting of the CFR5 bit does not affect the receiver; it only checks 1 stop bit. The bits CFR4,3 select the number of data bits sent or received in each character. If the bits CFR4,3 are 00, 01, 10 or 11, 5, 6, 7 or 8 bits are serially transmitted or received. Setting the CFR2 bit enables transmission and receipt of parity. When the parity is enabled, setting the bit CFR1 selects the even parity. If the parity is enabled, clearing the CFR1 bit results in odd parity. Setting the CFR0 bit enables the tag or space parity if the parity enable bit CFR2 is set. If bits CFR2 and CFR0 are set, CFR1 determines whether the tag parity (CFR1 = 0) or space parity (CFR1 = 1) is sent and received.

The CFR7 bit is reserved. When it is written, this bit should be set to 0, while it will always show 0 when read.

The COR field controls the selection of alternative registers, the receiver coupling, the access width of the data bus, the selection of the DMA mode, the enabling of the transmitter DMA, and the enabling of the receiver DMA. The alternate registers (baud rate divisor, alternate function register, data direction register, and compare registers can be accessed when the COR7 bit is set. As explained above, these alternative registers are mainly used during initialization to set the configuration of the basic serial of the serial channel.

Two bits are used to determine the receiver coupling (00 = normal mode, 01 = local loopback mode, 10 = remote loopback mode and 11 = echo mode). Selecting the normal mode (default) transmits all data that the receiver receives to the Rx FIFO 12. Selecting the local loopback mode causes the data transmitted to the transmitter to be internally sent to the receiver. Selecting the remote loopback mode causes the transmitter to send each byte that the receiver receives without entering those bytes into the Rx FIFO 12. Selecting the echo mode will cause the transmitter to send a duplicate of every valid data byte located at the top of the Rx FIFO 12. No bytes causing exceptions, ie an LSI condition or a match condition) are returned. If the next byte to be returned is one byte with one exception, setting COR6.5 to 00 (normal mode) will automatically disable the echo mode. At this point, the CPU should respond to the exception and return the appropriate one. The CPU will release the ECHO mode after the exception is processed.

Using the comparison registers in conjunction with the echo mode and the Rx DMA requires intervention of the CPU only during the receipt of control characters or corrupted data. Because there are many controls in the ASCII set below 1F hexadecimal that are not returned, compare register 2 has additional capability. It may agree with any byte input to the Rx FIFO that is less than or equal to its programmed value if TOR5 sets the "less than or equal" option. If TOR5 = 0, compare register 2 will only work on an "equal" basis. Thus, in the case of the automatic return of ASCII characters, the CPU can:

1. Put TOR5;

Second Load 1F hexadecimal into the CMP2;

Third Load 7F hexadecimal into the CMP3; respectively.

4th Set COR6.5 to 11.

Any characters received in hex between 20 and 7E will be automatically returned by the UART. All other values ​​would produce exceptions, thus giving the CPU characters and locking the echo mode.

The bits COR4,3 determine the width of the data bus. The data bus can be either 8, 16 or 32 bits wide. The 8-bit data bus has two modes of operation: the compatibility mode or the 8-bit mode. If the bits COR4,3 are 00, 01, 10, or 11, the modes are the compatibility mode, the 8-bit mode, the 16-bit mode, and the 32-bit mode, respectively.

The bits COR2,1,0 control the Tx and Rx DMA. The bit COR2 determines the DMA mode, the two options are single transmission (bit COR2 = 0) and multiple transmission (bit COR2 = 1). Setting bit COR1 enables the transmitter DMA; Setting the COR0 bit enables the receiver DMA. If any of these options are disabled, their output signals (DMA request) are inactive (high).

The TOR field controls the transmitter and compare register operations. This byte allows the CPU to:

1. enable or disable the transmitter;

Second delete the Tx FIFO 14;

Third program a station interruption;

4th enable transmitter control by / CTS;

5th enable the CMP2 to satisfy either a less than or equal condition;

6th enable the transmitter flow control by the comparison registers;

7th delete the comparison registers.

The transmitter enable bit allows the CPU to directly control the transmitter and also to override any automatic process control changes that affected the transmitter enable state. The deletion of the Tx FIFO 14 is useful if a retransmission of data is required. The transmitter interrupt bit (TOR2) asserts the SOUT signal as long as it is equal to one. The / CTS-Tx Flow Control enables or disables the transmitter as the multipurpose I / O bit 0 changes from active to inactive. The compare Tx scheduler enables or disables the transmitter as compare registers 0 and 1 match the incoming data. These last two transmitter control options automatically set and clear the transmitter enable bit. As explained above, bit TOR5 enables the less than or equal option for compare register 2. If TOR5 = 0, CMP2 will only match if the byte entered into Rx FIFO 12 is equal to its programmed value. If TOR5 = 1, CMP2 will match if the byte entered into RxFIFO 12 is less than or equal to its programmed value. Bit TOR6 enables the general purpose compare registers (COMPO-7). Of these registers, those in which data is loaded after a reset or compare register clear are those that are actually compared to the incoming data bytes. The TOR6 is used to clear the compare registers without resetting the UART; this bit is self-erasing. This feature may be useful when loading a new data set containing fewer bytes than the previous group into the compare registers.

The ROR field controls the receiver Rx operations. This byte allows the user to control the insertion of a sequence control character into the transmitter's data stream, the receiver's clock source, the number of delayed receive character times until a receiver timeout is issued, set the trigger level of the receiver, and clear the Rx FIFO 12.

Writing in ROR7 causes the UART to insert the byte programmed in compare register 1 (ie, XOFF) into Tx shift register 20 once the character present in Tx shift register 20 has been sent.

The receiver clock (RCLK) for each of the four UART channels can be derived independently from any of four sources. Setting bits ROR6,5 to 00, 01, 10 and 11 selects the RCLK source equal to the output of the baud rate generator, 1/2 the baud rate generator output, 1/4 the baud output Rate generator or the signal at the RCLK pin. After reset, the default value of the bits is ROR6,5 00. These options are primarily provided to allow high-speed transfer of data to a peripheral device that provides only slow keyboard or flow control data back to the CPU. Second, it requires fewer pins to support a multi-receiver UART. The transmitter is unaffected by this selection, being always driven by the output of the baud rate generator.

A receiver timeout interrupt is used by each serial channel of the UART to indicate that data is in its Rx FIFO 12 and that no activity of the CPU or serial channel has occurred during a specified time period. This feature is activated when there are data in the Rx FIFO 12 that can not reach the interrupt trigger level. It assures that the CPU will receive an interrupt indicating the presence of receiver data. The amount of delay before a timeout interrupt is issued is programmable using bits 4 and 3 of the ROR field. This delay is based on the receiver clock, being equal to a whole number of receive times. If the ROR4,3 bits are 00, 01, 10, or 11, the number of delayed receiver character times before a timeout interrupt is issued is 1, 2, 3, or 4 receive character times, respectively. A dunning time-out interrupt is issued if the following conditions are true:

1. The Rx FIFO 12 contains data;

Second during the timeout period, the CPU has not accessed the Rx FIFO 12; and

Third During the timeout period, no new serial number has been entered into the Rx FIFO 12.

The timer of the receiver timeout interrupt is reset whenever a CPU access occurs or a byte is added to the Rx FIFO 12. It is started when there is one byte in Rx FIFO 12.

Bits ROR2,1 determine the number of bytes that must be in Rx FIFO 12 before a receiver interrupt is issued. Setting bits ROR2,1 to 00, 01, 10, 11 will cause a receiver interrupt to be issued if there are 1, 4, 8, or 15 bytes in Rx FIFO 12, respectively.

The clearing of the Rx FIFO 12 is useful when there is an error in the FIFO and it is not desired to extract each byte one at a time before retransmitting.

In the 16-bit mode, the control register is accessed by two 16-bit wide registers, called the channel and Tx / Rx operations. In the 8-bit mode, the control register is accessed by the four byte-wide registers CFR, COR, TOR and ROR.

In Figs. 1 and 2, the channel I / O register (address 10100) controls all eight UART I / O pins that can be used for a modem interface or general-purpose I / O. The modem interface is automatically configured after reset, providing all the standard inputs (/ CTS, / DSR, / DCD, / RI) and outputs (/ RTS, / DTR). The Channel I / O Register contains four byte wide fields: Set I / O (SIO), Clear I / O (COR), I / O Register (IOR), and Delta Input (DIR).

The Set I / O field is used to set the individual output pins. The corresponding output pins will be set with the falling edge of the write strobe signal if their bits in that field have written len to them. These eight bits are read-protected.

The Clear I / O field is used to clear the individual output pins. The corresponding output pins will be set with the falling edge of the write strobe signal if their bits in that field have written len to them. These eight bits are just writing.

Simultaneous writing to bits in both the set and clear I / O fields corresponding to the same output pin will result in no change in the output pin. Simultaneous setting and clearing of various output pins by these fields is allowed. Setting or clearing the input pins sets or clears only the corresponding output latch.

The IOR field determines the state of the outgoing I / O lines. Writing a 1 to any of the IOR bits will increment the corresponding output pin; writing a zero puts it deep. All writes to the IOR field are on a byte-wide basis. If the corresponding pin is an input, the 1 is written to the output latch, but it does not affect the pin. The bits of this field are both to read and to write. When the bits that are designated outputs are read, the value of the output latch is returned. Reading the bits, which are designated inputs, provides the state of the pins.

The DIR field provides the input state information for each of the I / O pins programmed as inputs (a change in each of the input lines sets the corresponding bit in this register). The setting of any delta bits in the DIR field may cause an interrupt to be issued to the CPU if the ISI interrupts are enabled in the IER field. These status bits are read-only; writing to them does nothing. When the / CTS-Tx flow control bit is enabled in the DIR field, the I / O bit 0 is automatically made to look like an input. The line becomes the / CTS input line which enables and disables the transmitter.

After the reset, the IOR, DIR, and DDR fields are automatically initialized to a state that requires the UART to be connected to a modem or Electronic Industries Association (I / O) interface.

In this configuration, all bits are programmed to 1, assigned to specific functions (ie, / CTS, / RTS, etc.), and have a predetermined direction set in the DDR 22. Because this is basically a multipurpose I / O port that allows for different configurations, the default pin and bit assignments are used when communicating with a modem or I / O interface to maintain system compatibility. The default assignments for the bits are as follows:

The falling edge of the / RI signal (call indication signal) sets the status bit in the DIR field.

In the 16-bit mode, the I / O register is accessed by two 16-bit wide registers called the set / clear and the IOR / DIR registers. In 8-bit mode, I / O fields are accessed by four byte wide registers SIO, CIO, IOR, and DIR.

In Figs. 1 and 2, the TCR and RCR registers 24 and 26, respectively, contain four byte wide fields, three of which are called Tx count (TCR) and Rx count (RCR), respectively. These registers, along with the UART's DMA capability, can be used to create and control external FIFOs for the data, as described in greater detail below.

The TCT register 24 (address 11000) is a programmable counter that is used to track the number of bytes loaded into the Tx FIFO 14 by DMA. The number of bytes to be transferred by DMA to the Tx FIFO 14 before a TCR interrupt is issued by the UART is programmed. The TCR counter 24 is decremented for each byte transmitted to the Tx FIFO 14. When the zero count is reached, the transmitter DMAs are disabled with the TCR bit set in the IIR field. If the TCR bit is enabled in the IER field, the interrupt pin will go to negative logic. If the TCR bit is not enabled in the IER field, only the TCR bit is set in the IIR field. These operations associated with the TCR counter 24 only occur if the transmitter DMA is enabled and the counter 24 is loaded with a non-zero value. If, after reset, the TCR counter 24 is not loaded or loaded with a value of zero, the operations associated with that counter will not occur. This DMA process may be halted by inhibiting the transmitter DMA or loading a zero into the counter 24 at any time.

The RCR register 26 (address 111) is a programmable counter that is used to track the number of bytes loaded into system memory (RAM) by DMA. The number of bytes to be transferred by DMA from the Rx FIFO 12 before a receiver DMA interrupt is generated by the UART is programmed. The RCR codewinder 26 is decremented for each byte transmitted by the Rx FIFO 12. When the zero count is reached, the UART disables the receiver DMAs. The Rx DMA bit in the IIR field is set, with the INTR line of the UART going to negative logic if it is enabled in the IER field. The operations associated with counter 26 occur only if the receiver DMA is enabled and a non-zero value is loaded in counter 26. If, after reset, the counter 26 is not loaded or loaded with a value of zero, the operations associated with the counter 26 will not occur. The DMA process may be halted by disabling the recipient DMA or by loading a zero into the counter 26 at any one time.

In Figs. 1 and 2, the baud rate divisor register (address 00000 in the alternative register group) includes two byte wide fields called higher order divisor (HDR) and low order divisor (LDR) and two byte wide reserved fields. The HDR and LDR fields hold the 16-bit wide divisor for the baud rate generator 24 of the channel. The HDR field contains the high-order byte of the divisor, while the LDR field contains the low-order byte. This register is reset to 000C hexadecimal. This is the 9600 baud divisor if XIN is connected to a 1.8432 MHz clock input.

The initialization register (address 00100 in the alternate register group) contains two byte wide fields called alternate function (AFR) and data direction (DDR) and two reserved fields. The AFR field contains three active bits. According to the present invention, setting the AFR0 bit in any of the four channels of the UART allows the CPU to competitively write to the same selected register in the register group of each channel. This feature reduces the initialization time for all common parameters loaded into the registers of each channel. By accessing the register group of any channel, the CPU can set or clear bit AFR0. If bit AFR0 is set, the channel select pins will still determine which channel is being accessed during the read operations. Setting or clearing the AFR0 bit has no effect on the read operations.

The bit AFR1 determines the function of the / MF pin. If AFR1 = 0 (default state), the IMF pin will provide the normal ring display function (the ring display signal is normally activated by a modem that has detected an incoming phone call). If AFR1 = 1, the IMF pin will provide the output for the BAUDOUT signal of that channel.

Setting bit AFR7 resets the assigned channel. This is a user reset that is channel specific, as opposed to the reset, which resets all channels.

The DDR field sets the data direction for the general-purpose I / O. Setting any bit in the DDR field to 1 causes the corresponding I / O bit to become an output. This field is always accessed on a byte-wide basis. After reset, the DDR field is automatically initialized to the default modem configuration. The six least significant bits in the DDR field are used in the modem interface and function, as previously described, with the two upper bits programmed as inputs. This is reset to OC, which determines the direction for the standard modem and EIA interface signal assignments.

The compare registers (addresses 01000 and 01100 in the alternate register group) are byte wide registers that are compared to the bytes in Rx FIFO 12 for a match. Both registers consist of four byte-wide fields called Comparison 0 (CPO) to Comparison 3 (CP3) and Comparison 4 (CP4) to Comparison 7 (CP7). These registers are programmed during initialization with the data (typically the hexadecimal representation of the control characters) that must match during the receiver operation. Once released by setting the COR5 bit, they are compared with the received data as they are input to the Rx FIFO 12. Each time a match occurs with a received byte, bit 6 will be set in the IIR field if the matching byte is at the top of the Rx FIFO 12. An interrupt will be issued to the CPU if it is enabled in the IER field. The match state bit in the BSR 16 associated with the matching data byte will be set so that the matching byte can be identified. In addition, in the appropriate BSR 16, the compare register ID bits will be set. Only the compare registers which have been loaded by the CPU since the last reset or since the activation of the compare register clear bit are compared with the received data stream.

The flow control of the transmitted data stream can be directly controlled by the UART. This is done by programming the comparison registers 0 and 1 with the start and stop characters for the sequence. If any of these programmed start or stop sequence flags in the Rx FIFO 12 match, the UART automatically releases the transmitter or automatically locks the transmitter. The transmitter will complete the transmission of any byte in its Tx shift register 20 as the scheduler stops transmission of the characters from the Tx FIFO 14 to the shift register 20. These scheduling compare registers enable the transmitter or disable the transmitter by changing the state of the transmitter enable bit. The sequence control characters are received on the SIN line to the Rx shift register 26, which may be 8-byte characters. The automatic scheduling feature can be unlocked by the CPU at any time via the transmitter enable bit. This feature can be disabled via the auto sequencer bit to allow binary file transfer. After resetting, the comparison registers 0 and 1 are automatically loaded with the XON character (11 hexadecimal) or the XOFF character (13 hexadecimal). If the compare flow bit is enabled, the matching characters are not put into the Rx FIFO 12, immediately setting the TFC status bit in the IIR. If the compare flow control bit is not enabled, the matching characters are put into the Rx FIFO 12, and when they reach the top of the FIFO 12 they set the TFC state bit in the HR.

The automatic sequencer is also available through the / CTS pin. This feature, when enabled, starts and stops transmissions to the Tx shift register 20 when the / CTS is active or inactive. Transmitter sequencing via the / CTS is achieved by setting or clearing the transmitter enable bit. The transmitter sequence control over both the comparison registers and the / CTS is allowed. If this is the selected mode, the most recent entry in the transmitter enable bit is from the compare registers, the / CTS pin, or the CPU.

In 16-bit mode, two compare registers are accessed at once. In the 8-bit mode, a compare register is accessed at once.

Each of the UART's four serial channels can control both internal and external FIFOs for the UART transmitter. The internal Tx FIFO 14 for each channel is 16 bytes deep. Based on 24-bit registers, the external Tx FIFOs can be up to 16.777216 MB deep.

In an internal Tx-FIFO transfer, the CPU writes data into the Tx FIFO 14 in bus wide groups. As explained above, the data is serially transmitted by the transmitter with the least significant bit sent first. The transmitter sends all data in the Tx FIFO 14 as long as the Tx FIFO 14 is enabled. If the Tx FIFO 14 is disabled while a byte is being shifted out, that particular byte will be completed, but no further bytes will be transferred to the Tx shift register 20.

If the number of data bytes to be transferred to the Tx FIFO 14 is less than one bus width, the CPU will send an extended message to the UART. As explained above, this is done by activating the / HBE and A0 input signals. The data in the Tx FIFO 14 is always stored in consecutive byte locations regardless of the number of bytes in each CPU transfer.

The CPU must program bits 2 and 1 of the channel operation register (COR2,1) for DMA mode and Tx DMA enable, respectively. The transmissions made by the DMA to the Tx FIFO 14 are started when the Tx FIFO 14 is empty. In DMA mode 0, the transmit request pin is disabled after the first transfer of data to the Tx FIFO 14. In DMA mode 1, the transmit request pin is disabled when the Tx FIFO 14 is full. All transmitter DMA communications must be in the full width of the bus, or the / HBE and A0 bus signals must indicate one byte wide transmission.

The UART also provides for maintaining an external Tx FIFO associated with a system DMA unit. This is done to allow the increased transmitter FIFO length without a significant increase in UART chip size.

In order to maintain an external Tx FIFO, in Fig. 7 the DMA control circuitry requests DMA transfers and notifies the CPU when a preselected number of bytes are to be transferred from system memory via DMA. An additional register is provided for the control of the external FIFO. This is the Tx DMA count register. It tracks the number of bytes transferred from the memory by DMA. The CPU programs this counter with the number of bytes to be transferred. The counter is decremented for each byte transmitted during the Tx DMA. When the counter reaches 0, the Tx counter bit is set in the IIR field, and further the Tx DMA requests are automatically disabled by clearing the Tx DMA enable bit (COR1). If it is enabled, ie bit IER2 is set, an interrupt will be sent to the CPU. The CPU responds to this interruption by:

1. Checking the CSR to determine the interruption;

Second Checking the Tx DMA counter to inhibit the interruption;

Third Restart the system DMA for another Tx transfer; and

4th Set the Tx DMA enable bit (COR1) to continue further Tx DMA requests through the UART.

The TX DMA counter 24 is automatically reloaded after the Tx DMA enable bit is set. The CPU may reprogram the DMA counter 24 at any time. If the DMA counter 24 is reprogrammed to 0, or if it is not programmed after a reset, control of the external FIFO is not active.

If the number of bytes to be transferred per Tx-DMA is less than an integer number of bus widths, one of two options is available.

1. If the system DMA is sophisticated enough to detect and report the less than the bus width data transmission to the UART, it can perform the transmission through the / HBE and A0 inputs itself;

Second if the DMA can not perform this transfer, the CPU must perform the last transfer.

Each serial channel of the UART can also control internal and external FIFOs for the receiver. The internal Rx FIFO 12 for each channel is 16 bytes deep. The external Rx FIFOs can be up to 16.777216 MB deep.

In a Rx FIFO transfer without DMA, bits 2 and 1 in the ROR field are set to determine the number of bits in the Rx FIFO 12 before an interrupt is triggered (00 = 1 char, 01 = 1 / 4-full, 10 = 1/2-full, 11 = 7/8-full). Setting bit 7 in the IER field allows an interrupt to be issued when the Rx FIFO 12 fills to a predetermined trigger level. Bits 4 and 3 of the ROR field determine the duration expressed in character times that a data byte must wait in Rx FIFO 12 until a timeout interrupt is issued to the CPU. This interrupt, if enabled, is issued when at least one data byte has been in the Rx FIFO 12 for a number of specified character times and there has been no CPU access during this time or no serial data entry into the Rx FIFO 12 has taken place Has. Setting bit IER1 enables the timeout interrupts.

Upon receiving an interrupt, the CPU will read the IIR field and check each bit for a pending interrupt. Finding bit 7 as set indicates that Rx FIFO 12 is at its trigger level or that a timeout interrupt is pending. The CPU reads the byte to exception register (BTE) 18 to obtain the count of the number of valid bytes that it can remove from the Rx FIFO 12. Then it reads these bytes from the data register until this count is reached.

Because the CPU data bus can be wider than one byte and the serial data is always received in one-byte increments, it is possible to have fewer bytes in the Rx FIFO 12 than the bus is wide. This possibility will occur only during the last access by the CPU before the count of the BTE 18 reaches zero. If z. B. For example, if the data bus is 2 bytes wide and 15 bytes are to be removed from the Rx FIFO 12, as indicated by the BTE 18, the CPU may execute seven consecutive 2-byte wide reads without any further need to validate the data state. Before the last read from the DATA register, the CPU reads the FSR field to get the valid byte locations. It then reads the DATA register for the last time to extract the remaining data bytes.

If another byte is input to the Rx FIFO 12 after the CPU has read the FSR field but before reading the DATA register, the new byte will not be put to the top of the Rx FIFO 12. It is not added to the data that the CPU could read from the Rx FIFO 12 until after the reading of the DATA register is complete.

The DMA transfers using only the Rx FIFO 12 are prepared by the execution of the following initialization steps. The Rx FIFO trigger level bits in the ROR field (ROR3,2) and the timeout delay bits ROR5,4 are set to the required level. The Rx DMA mode selection bit (COR2) is programmed for either single or multiple DMA transfers (0 or 1). Assuming DMA mode 1 is selected and Rx DMA enabled (COR2,0 set), the following happens.

The automatic DMA requests to transfer data from the UART will begin each time the data reaches the trigger level. All successive valid data will be transferred until either an exception occurs or until the number of remaining valid data bytes is less than one bus width. If the first occurring exception is an empty Rx FIFO 12, the DMA requests are stopped until the trigger level is reached.

If the first exception is a line state error, the DMA transfers are stopped if that byte is below those to be next transferred. The appropriate line state error bit (s) will be set in the IIR field and BSR 16. An interrupt, if enabled, is issued to the CPU. At this point, the CPU responds as follows:

1. Reading the CSR field to determine the type of interrupt (s);

Second Reading the FSR field to determine the position of the valid data;

Third Reading the BSR 16 to accurately determine the specific nature of the exception and to clear the interruption (s);

4th Executing the utility for the specific LSI; and

5th Clearing the Rx FIFO 12 and executing the clear routine to clear the remaining incoming data associated with that block, whereupon the retransmission of the data is requested.

The automatic Rx DMA transfers will start again after the trip level is reached or a timeout occurs.

If the first exception is a match to the compare register, the appropriate bits in the IIR field and the BSR 16 will be set. An interrupt, if enabled, is issued to the CPU. At this point, the CPU responds as follows:

1. Reading the CSR field to determine the type of interrupt (s);

Second Reading the FSR field to determine the locations of the valid data bytes;

Third Reading the BSR 16 to determine the matching bytes;

4th Reading the data register, discarding the matching bytes and holding the data bytes; and

5th Execute the appropriate control-character utility.

If the number of consecutive valid data bytes at the top of the Rx FIFO 12 is less than one data bus width (e.g., 3, 2 or 1 byte in 32-bit access mode; 1 in 16-bit access mode ), the DMA requests are stopped and the UART will wait until enough bytes arrive to reach the trigger level or until a timeout occurs. If a timeout occurs, the CPU will need to remove the remaining valid data bytes and set the Rx DMA enable bit to restart the Rx DMA requests. The procedures for handling data with a width smaller than the data bus are as follows:

1. Checking the CSR field to determine the interruption and the consecutive valid data;

Second Reading the Rx FIFO 12 to extract all remaining bytes (checking the FSR field, if appropriate);

Third Prepare the system DMA for the next transfer; and

4th Set the Rx DMA enable bit to allow the continuation of the DMA transfers.

DMA mode 0 operation is handled in the same manner as mode 1, except that the DMA requests are started as soon as one data bus width of valid data (4 bytes in the 32-bit mode, 2 in the 16-bit mode). Bits mode) have been accumulated. The automatic DMA requests are stopped for each of the exceptions mentioned for DMA mode 1. The DMA transfers are restarted (according to the mode 0 criterion) after each of the exceptions, timings or conditions of insufficient width of the valid data has been cleared and the Rx DMA enable bit is set.

The UART also provides for maintaining an external Rx FIFO associated with a system DMA unit. This is done to allow for increased Rx FIFO lengths without significantly extending the UART chip size. To do this, in Fig. 8 the control circuitry requests DMA transfers, notifying the CPU when a preselected number of bytes that have been transferred are provided. An additional register is provided for the control of the external Rx FIFO. This is the Rx-CNT count register 26. It keeps track of the number of bytes transferred by DMA from the Rx FIFO 12. The CPU programs this counter with the number of bytes to be transferred. This counter is decremented with each valid byte transferred. If it reaches 0, the Rx-CNT bit is set in the IIR field and an interrupt, if enabled (IER7 set), is output. The Rx DMA bit in the control register (COR0) is cleared at this time, further disabling the Rx DMA. UART operation returns to the non-DMA transfer mode until the CPU resets the Rx DMA enable bit. The CPU responds to the Rx-CNT interrupt by:

1. Reading the CSR field to determine the interruption;

Second Reading the Rx CNT register to clear the interruption;

Third Processing the bytes stored in the external Rx FIFO;

4th Preparing the system DMA for subsequent transfers; and

5th Set the RX DMA enable bit in the channel operation register to allow subsequent DMA transfers.

In mode 1, the DMA reaching the trigger level of the Rx FIFO 12 starts transmission to the external Rx FIFO. Transmission continues until all successive valid data bytes have been transferred in the Rx FIFO 12, there is a line condition condition, or until a byte match condition occurs at the top of the Rx FIFO 12. If the counter is not zero and there is less than one bus width of valid data at the top of the Rx FIFO 12, the UART will wait until enough bytes arrive to reach the trigger level and with DMA transfer in full bus width Continue. If insufficient bytes arrive, a timeout interrupt will be issued to the CPU. The CPU's response to a timeout interrupt is:

1. Checking the CSR field to determine the interruption and the consecutive valid data;

Second Checking the RCR to clear the interrupt and to determine the number of bytes in the external Rx FIFO that need to be processed;

Third Reading the Rx FIFO 12 to extract all remaining bytes (checking the FSR field, if appropriate);

4th Processing the bytes stored in the external Rx FIFO; and

5th Starting a routine to handle the incoming bytes remaining in that block.

The Rx DMA counter 26 is again loaded to the preprogrammed value after the Rx DMA enable bit is set. The released Rx DMA transfer will start again as soon as the trip level is reached. In the DMA mode 0, the transmission will start as soon as enough data is assembled to carry out the transmission with the full bus width.

The CPU can reprogram the DMA counter at any time. If the DMA counter is reprogrammed to 0, or if it is not programmed after a chip reset, external Rx FIFO control is not active. The line state or byte match conditions are handled in the same way as in the internal Rx FIFO mode.

There are eight types of interrupts that the CPU can release through the IER field. Two report the receiver status, three report the transmitter status, and the other three report the input status, line status, and matches to the compare register.

The setting of bit IER7 allows an Rx FIFO 12 at the trigger level indication (IIR7) to activate the interrupt. If the interruption is pending, the response from the CPU is:

1. Checking the IIR field to determine the interruption;

Second Checking the byte-to-exception register 4 to determine the number of bytes to an exception;

Third Extracting all consecutive valid data bytes to one exception (the IIR7 bit is cleared if the data falls below the trigger levels); and

4th Reading the FSR and BSR fields and extracting all remaining valid data bytes along with any relevant line state or match information about the invalid data bytes.

When the external Rx FIFOs are in use, setting the IER7 bit of the RCR indicator (IIR1 indicator) allows the interrupt signal to be asserted. The RCR indicator IIR1 is set when the RCR reaches 0.

Another Rx interrupt enabled by setting bit IER1 is the timeout interrupt. The display becomes active when an internal timer reaches zero. The indication means that the data has been sitting longer than a preprogrammed limit in the Rx FIFO 12 without the CPU taking steps or additional data arriving. This timeout interruption prevents data that can not reach the trigger level from being stuck indefinitely in the FIFO. It triggers the same display (IIR7) as the RFT because the CPU response for the timeout is the same as for the RFT display.

The internal timer for the timeout indication is started when the first byte is input to the Rx FIFO 12 while it is stopped when the last byte is removed from the Rx FIFO 12. The timer is incremented each time the CPU removes one byte from the Rx FIFO 12, or each time the Rx shift register 27 loads a byte 27 from the Rx FIFO 12, or each time the Rx shift register inserts a byte into it loads, restarts automatically. The duration of the timer is programmed by setting bits 4 and 3 in the ROR. All timer durations are increments of 1 character time (00 = 1 character, 01 = 2 characters, 10 = 3 characters, 11 = 4 characters). If the programmed duration of the timer expires before the CPU accesses the Rx FIFO 12 or another fetched byte is loaded into the Rx FIFO 12, the Time Trigger Indicator (IIR7) is set.

An external Rx FIFO is considered to be in use when both the Rx DMA enable bit is set and the RCR 26 is loaded. An Rx timeout operation, when using an external Rx FIFO, is identical to that listed above for the Rx FIFO 12, except in two respects.

1. The time duration is extended by 100 times. This is because it is assumed that the system will receive files instead of capturing input from a user terminal, and therefore the time-to-release periods should be much longer. If the file is transferred specifically at 9600 baud using 8 bits, 1 stop [-] and no parity [sbit], then the Rx timeout delays available to the user are about 100, 200, 300, 400 ms.

Second Once the timeout timer is started, it will only be disabled if both the Rx FIFO 12 is empty and the RCR 26 = 0. This allows the timer to monitor the time delays for both the internal and external Rx FIFOs. This is useful because it is conceivable that the data could be stuck in either the internal, external or both Rx FIFOs.

The setting of bit IER6 allows the indication of the match with the compare register to issue an interrupt. The compare match will occur when the compare register enable bit TOR6 is set and a data byte at the top of the Rx FIFO 12 matches a byte loaded in the compare register. In response to the interruption, the CPU will:

1. Read the IIR field to determine the break;

Second read the FSR field to determine if there is valid data at the top of the Rx FIFO 12;

Third read the BSR 16 to determine the byte that matches and what it was (this clears the interrupt); and

4th read the DATA register.

Setting bit IER5 allows the line status indications (LSI) to enable an interrupt when the bytes come to the top of Rx FIFO 12. This is done either by an overflow error (OE), a parity error (PE), a framing error (FE) or an interruption indicator (BI). The specific indication is associated with the byte that caused it in the BSR 16. However, the OE will be displayed as soon as the UART detects this condition. In response to an LSI, the CPU will:

1. Check the IIR field to determine the interruption;

Second check the FSR field to determine if there is valid data at the top of the Rx FIFO 12;

Third check the BSR 16 to determine the byte (s) that caused the LSI (this clears the interrupt); and

4th read the data register 10.

Setting bit IER4 allows the input state indicator (ISI) to enable an interrupt. A 151 occurs when any of the multi-use input lines changes. If bit IER4 is set, this indication will activate an interrupt. The CPU's response to the interruption is:

1. Reading the IIR field to determine the interruption; and

Second Reading the DIR field (this clears the interruption).

Setting the bit IER3 allows the Tx Flow Indicator (TFC) to activate an interrupt. The TFC indication occurs when a change in the Tx enable bit has been made, caused by a match in the Rx FIFO 12 with the compare register 0 or 1 or caused by a change to the / CTS pin. This assumes that these scheduling options are enabled. The Tx sequencer consists of automatically starting or stopping the sender when the user has certain bytes, such as a. As XON or XOFF, are detected in the data stream. Reading the TOR field to check the Tx enable state clears the interrupt. Its purpose is to inform the CPU that a change of state has occurred at the Tx enable bit. The CPU can cancel the automatic setting of the Tx enable bit at any time by simply writing to it. This interruption will immediately be matched if TOR3 is set. If TOR3 is 0 and a match occurs, the interrupt will become active when the flow control character reaches the top of the FIFO. If TOR3 is set, the sequence control characters are not placed in the FIFO.

Setting the IER2 bit allows the Tx FIFO empty display or the Tx DMA counter reading = 0 to activate an interrupt. If the Tx FIFO 14 is empty, an indication is given by bit IIR2. The CPU responds to this interruption by:

1. Reading the IIR field to determine the interruption; and

Second Either loading the data into the Tx FIFO 14, or if it is the beginning of the Tx DMA, releasing the Tx DMA bit (this clears the interrupt). If there is no data to transfer, the CPU can clear the Tx enable bit to clear the interrupt.

If an external Tx FIFO is in use, the IIR2 indicator is activated when the Tx DMA counter reaches its 0 count.

Once the compare registers have been programmed and enabled, each byte entered into the Rx FIFO 12 is checked for a match. The UART contains 8 compare registers, with only those that are explicitly loaded by the CPU being actively compared. Therefore, any number of "tax" signs up to 8 can be in use. A match to any compare register except compare registers 0 and 1 is indicated by bit IIR6 and the appropriate BSR bits if it is among the next data to be taken from the top of Rx FIFO 12. Assuming that an active interrupt has been caused by a match to the compare register, the CPU will:

1. Read the IIR field to determine the break;

Second read the FSR field to determine the valid data at the top of the Rx FIFO 12;

Third read the BSR 16 to determine which byte matches and what it was; and

4th read the data register 10 to extract the bytes from the Rx FIFO 12.

The CPU retrieves the valid data to separate it from the control character (s). A match with the comparison registers handling the flow control (0 and 1) is indicated by IIR3.

Transferring byte-wide serial data to a word-wide (ie 16 bits) parallel data bus and vice versa requires an additional restriction that does not participate in the memory / CPU exchange. In theory, the CPU can access any serial channel in any of three ways: odd byte, even byte, or word transfer. Because the data from each channel is always ordered byte by byte, they must be delivered to the CPU in the original order received. Two signals output by the CPU typically control the way in which the data is transferred. The / HBE and A0 inputs to the UART used to control the byte transfers indicate the number of bytes and which part of the 16-bit CPU bus is used, but not which bytes in the UART -FIFOs will be accessed.

The following describes typical 16-bit bus transfers to a peripheral device and then the 16-bit bus transfers to the UART.

As explained above, a 16-bit wide bus allows the CPU to transfer data from a peripheral device in three different ways. Table 1 below shows the manner in which the UART will enable the data bus for the given states of / HBE and A0. During conventional transmissions, the CPU sets the control signals / HBE and A0, transmitting the data using normal transmission procedures. When the data is sent, they have a predetermined location to go to based on the address and data location on the data bus. This applies to each of the three transmission types. When the data is received from the CPU, it is also handled in the CPU by the address and data location on the data bus.

When simultaneously transmitting from the CPU to the 16-bit UART data to be serially transmitted, the predetermined position of the data in the UART FIFO depends on the address and byte position of the data on the data bus. However, if only 8 bits of data are sent to the UART for serial transmission, the predetermined position in the FIFO of the UART depends on the address and the number of bytes sent and not on the position of the byte on the data bus.

If the transmitted data has been received serially by the UART and transmitted to the CPU via a 16-bit wide bus, the "order of receipt" of the data must be obtained during transmission over the 16-bit data bus. During a 16-bit data transfer this order is obtained with the conventional restrictions of address and position on the data bus. During an 8-bit transfer, however, the next byte available in the UART FIFO will be transferred to the data bus, regardless of the location on that bus that it will occupy, in other words, regardless of whether it is in the higher byte position or lower byte position. Table 1

As explained above, the odd and even byte transfers determine to which part of the bus the next byte in the Rx FIFO 12 will be applied. The data and status registers work in the same way. The state must be read before the data to map the state byte to the appropriate byte of data.

Writing to the DATA register loads the data into the Tx FIFO 14. The data may be written to the DATA register using any IHBE and A0 combination. During single byte transfers, the data will be in the next available space in the Tx FIFO 14, regardless of its location on the CPU bus (D15-D8 or D7-D0). The word-wide data is loaded into the Tx FIFO 14 assuming that the data byte should be transferred to D7-D0 immediately before the data on D15-D8.

All other registers except the data and state registers can be addressed on a byte by byte basis using / HBE and A0. If z. For example, in the 16-bit access mode, if the register at address 5 is accessed with / HBE = 0 and A0 = 1, then the register contents will be set to D15-D8. The writes to odd and even byte wide registers are similarly accomplished using these strobe signals, which are word wide strobe signals.