Code shift keying (csk) apparatus and method for spectrum spread communication

Background of the invention

The present invention generally relates to a device with a Code Shift Keying (CSK) and a spread spectrum communication method. The invention is in the field of spread spectrum communication by CSK modulation and relates to a corresponding method and apparatus for carrying out the method. More particularly, the invention relates to a communication method according to a variable encoding keying (CSK) modulation system and a communication device for carrying out the method.

Recently, SS communication systems have been extensively used in the fields of satellite communication, radio communication and network communication. The conventional SS communication system will be described below with reference to Figs. At the signal transmission side, the output a of a PN (Pseudo Noise) code series generator 1 and transmission data b are supplied to an XOR circuit 2. The output c of the EXCLUSIVE-OR circuit 2 is passed to an amplifier 3. The output of the EXCLUSIVE-OR circuit 2 is passed as a transmission signal to a signal transmission path. At the signal receiving side, an input signal is supplied to an amplifier 4. The amplified signal from the output of the amplifier 4 is passed to a synchronous PN code series generator 5 and also to a correlator 6, where it is correlated with the output d of the synchronous PN code series generator 5. The output of the correlator 6 represents a correlation value (or a signal e) which is compared by the comparator 7 with a predetermined threshold value. The output of the comparator 7 is provided as receive data f.

The signal transmission path may be wireless or wired; it may be formed of any signal transmission medium suitable for such a purpose. Transmission signals are passed directly to such a signal transmission medium; often they are then converted for transmission to signals that can actually be transmitted through the signal transmission medium. In network communication, interfaces must be provided for the isolation of transmitted signal from the power network. As described above, the system parts which act on the signal transmission medium, by which the transmission signals are either converted to suitable corresponding signals for transmission or isolated from the current, are referred to as "signal receiving interface", depending on the application. Such interfaces are a means for connection to the signal transmission medium.

In the conventional communication system, the PN series generated by the synchronous PN code series generator 5 on the signal reception side needs to be synchronized with the PN series provided on the signal transmission side. For this purpose, it is essential to search for a synchronous point. When the signal transmission path in the signal transmission characteristic is satisfactory, the correlation waveform shows a peak at the synchronous point as shown in FIG. 3A is shown. On the other hand, in a signal transmission path whose signal transmission characteristic is markedly low, as in the case of network communication, and which has an onset point in the signal transmission path as shown in Figs. 3B and 3C, the correlation waveform is degraded. In this case, the sign (+ and -) of the correlation value is reversed; that is, the level of the data is reversed ("1" and "0"). In addition, the same condition causes a disadvantage because the synchronization can not be maintained. Sust and Kowach in "Proceedings of melecon '87", page 157ff., Describe a spread spectrum communication system that uses a digital matched filtering technique to correlate the pseudo noise codes and a preamble code. The digitized input data stream is correlated with the contents of reference registers in three matched filters, two for the pseudo noise codes and one for the preamble code. Each matched filter outputs the sum of the correlated signals. Pseudo noise codes, and preamble codes are indicated by peaks of this sum. The detection of a preamble is an indication of the arrival of data pseudo noise codes that follow the preamble. The system then displays an adaptive sampling window technique, the arrival of such a preamble serving to start a timer which determines a known interval corresponding to the length of a pseudo-noise code and a sampling window contained therein in which occurrence of the correlation peaks is expected. The correlation peaks appearing in each sampling window are compared to determine the value of the transmitted bit.

Kohno et al. describe in "Conference Record Volume 1 of the Global Telecommunications Conference 1987", page 16.8.1ff, a spread spectrum multiple access system. They propose the use of Manchester M coded pseudo noise sequences to simplify the necessary hardware by eliminating the modulation / demodulation steps.

SUMMARY OF THE INVENTION

It is an object of this invention to provide a spread spectrum (SS) communication method according to a novel variable-keying (CSK) system which does not have the above-described difficulties associated with a conventional SS communication system, and to provide an SS communication device for carrying out this method. This object is achieved by the CSK methods according to independent claims 12 and 18 and by the CSK device according to independent claims 1 and 6. The introductory part of claims 1 and 6 is based on the aforementioned prior art document by Sust and Kowach. Further advantageous features of the method and the device will become apparent from the dependent claims.

The invention provides a CSK signal transmission method and a CSK signal reception method used for SS communication, and provides a CSK signal transmission device and a CSK signal reception device used for SS communication.

There is provided a signal demodulating apparatus in the CSK signal receiving apparatus capable of stably demodulating the received CSK signal and suppressing an error even when the signal transmission characteristic of the transmission path is small.

A correlator is provided in the CSK signal receiving apparatus capable of correlating the received CSK signal with a Manchester M series at high speed and in real time.

There is provided a peak position detecting device in the CSK signal receiving apparatus capable of accurately detecting a peak position of the received CSK signal.

There is provided a peak position determining device in the CSK signal receiving apparatus capable of determining a peak position without being affected by variations in the signal transmission characteristic.

There is provided a carrier detecting apparatus in the CSK signal receiving apparatus capable of accurately detecting a carrier included in the received CSK signal even when the signal transmission characteristic is small.

There is provided a determining means for establishing synchronization in the CSK signal receiving apparatus by which a starting point of communication can be stably and accurately determined without being affected by noise.

There is provided a determination device for not establishing synchronization in the CSK signal receiving device, which is capable of accurately determining a non-establishment of synchronization at all times.

In the CSK communication system, one of two Manchester M series generated at a predetermined period and code length is transmitted as a transmission signal; the choice depends on whether the transmission data is "1" or "0". In the Manchester M series to be actually transmitted, a maximum value of the absolute value of its autocorrelation is always greater than that of the cross-correlation of the two Manchester M series, even if the value of the autocorrelation or cross-correlation due to the noise signal, a Distortion of the signal or the like changes. The received signal is correlated with the two different Manchester M series to obtain two correlation outputs; the receive data "1" or "0" are formed after comparing the peak value between the two correlation outputs.

At the transmission side of this CSK communication system, one of the two Manchester M series is transmitted as a transmission signal every predetermined period; the choice depends on whether the transmission data is "1" or "0". The corresponding CSK signal transmission device includes:

first and second Manchester M series generators for generating two Manchester M series of the same code length; and a circuit for transmitting one of the output signals of the first and second Manchester M series generators as a transmission signal (the choice depends on whether the transmission data is "1" or "0"). In the Manchester M series to be actually transmitted, a maximum value of the absolute value of its autocorrelation is always greater than that of the cross-correlation of the two Manchester M series.

At the receiving side, a received signal is compared with two Manchester M series which are the same as those used at the signal transmitting side to obtain two correlation outputs; the reception data "1" or "0" are formed in accordance with the comparison of the peak value between the correlation outputs. The corresponding CSK signal receiving apparatus includes: a pair of correlators for comparing a received signal with two Manchester M series which are the same as those used at the signal transmission side to obtain correlation outputs; and a demodulator circuit for forming the received data "1" or "0" in accordance with the comparison of the peak value between the correlation outputs of the correlators.

The term "M series" as used herein is intended to denote those having the largest period of a series of code series generated with a shift register having a plurality of stages and a linear arithmetic circuit. For a shift register with n stages, the length of a generated M series is 2n-1.

The term "Manchester code" as used herein refers to a code in which a cycle of a rectangular wave having a certain phase is provided for a binary input signal "1", and in which a cycle of a square wave having a phase similar to that mentioned above is provided for a binary input signal "0".

The term CSK (interchangeable keying) as used herein refers to a signal modulation system in which two binary PN (pseudo noise) code series (including the M series and the Manchester M series) each having the same code length , binary values ​​"0" and "1" correspond to the transmission data, and in which one of the two PN code series is actually transmitted in accordance with the transmission data, the PN code series which is actually transmitted has a maximum value of the absolute value of its autocorrelation always greater than that of the cross-correlation of the two PN code series.

Fig. 1 is a circuit diagram, partly in block diagram form, showing the arrangement of a conventional SS communication system;

Fig. 2 is a timing chart for a description of the operation of the conventional SS communication system shown in Fig. 1;

Figs. 3A-3C are graphs explaining the disadvantages associated with a conventional SS communication system;

Fig. 4 is a block diagram showing a first CSK communication system according to the present invention;

Fig. 5 is a block diagram showing a second CSK communication system of the invention;

Fig. 6 is a circuit diagram, partly in block diagram form, showing an example of a modulator shown in Fig. 5;

Fig. 7 is a circuit diagram for a description of the operation of the modulator shown in Fig. 6;

Fig. 8 is a circuit diagram, partly in block diagram form, showing another example of the modulator shown in Fig. 6;

Fig. 9 is a circuit diagram, partly in block diagram form, showing another example of the modulator;

Fig. 10 is a timing chart for a description of the operation of the modulator;

Fig. 11 is a block diagram showing a two-series modulator on a signal transmission side as shown in Fig. 4;

Fig. 12 shows a relationship between transmission data and a two-series at a signal transmission side and waveforms of demodulated signals of a two-series demodulator at a signal reception side;

Fig. 13 is a circuit diagram, partly in block diagram form, showing an example of the demodulator shown in Fig. 4 using a SAW (Surface Acoustic Wave) convolver;

Fig. 14 is a timing chart showing demodulation waveforms in case of short transmission data:

Fig. 15 is a circuit diagram, partly in block diagram form, showing an example of a correlator shown in Fig. 11;

Fig. 16 is a circuit diagram, partly in block diagram form, showing another example of a correlator shown in Fig. 11;

Fig. 17 is a circuit diagram, partly in block diagram form, showing another example of a correlator shown in Fig. 11;

Fig. 18 is a circuit diagram, partly in block diagram form, showing another example of a correlator shown in Fig. 11;

Fig. 19 is a table explaining an operation for a bidirectional counter shown in Fig. 18;

Fig. 20 is a circuit diagram, partly in the form of a block diagram, showing an overall construction of the correlator shown in Fig. 11;

Fig. 21 is a circuit diagram, partly in block diagram form, showing another example of a correlator shown in Fig. 11;

Fig. 22 is a circuit diagram, partly in block diagram form, showing a pair of correlators shown in Fig. 5;

Fig. 23 is a circuit diagram, partly in block diagram form, showing a modification of the correlators shown in Fig. 5;

Fig. 24 is a circuit diagram, partly in block diagram form, showing another example of the correlators;

Fig. 25 is a circuit diagram, partly in block diagram form, showing another example of the correlators;

Fig. 26 is a circuit diagram showing an example of a register shown in Fig. 25;

Fig. 27 is an explanatory diagram showing relationships between a Manchester series and a Manchester M series;

Fig. 28 is a circuit diagram, partly in block diagram form, showing an example of a demodulator shown in Fig. 5;

Fig. 29 is a waveform diagram for a description of the operation of the demodulator shown in Fig. 28;

Fig. 30 is a circuit diagram, partly in block diagram form, showing an example of a synchronous control circuit shown in Fig. 5;

Fig. 31 is a waveform diagram for a description of a peak position detection process;

Fig. 32 is a waveform diagram for a description of a synchronization establishment determination process;

Fig. 33 is a waveform diagram for a description of a synchronization non-production determination process;

Fig. 34 is a block diagram showing an arrangement of a CSK modem;

Fig. 35 is a graph showing a correlation signal, a data interval and observation intervals set in the data interval; and

Fig. 36 is a circuit diagram, partly in the form of a block diagram, showing another example of the synchronous control circuit having a synchronous tracking circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

1. CSK modulation system

Figures 4 and 5 show two different system arrangements of an SS communication system using CSK modulation. These two systems are based on a single concept of the present invention in which a plurality of Manchester M series of the same code length are used. In the Manchester M series actually transmitted, a maximum value of the absolute value of its autocorrelation is always greater than that of the cross-correlation of the two Manchester M series.

Fig. 4 shows the entire arrangement of a first communication system according to a CSK system using Manchester code M series.

The signal transmission side of the system has a two-series modulator 11 and a transmission interface 12. Transmission data a (TXD) is input to the two-series modulator 11, which outputs one of two PN (pseudo noise) code series as the output signal b (TXO). The transmission data a consists of binary signals ("1" and "0"). The two-series modulator 11 outputs one series for a level of digital data "1" or "0" and another series for the other level. For example, as will be described later in detail in conjunction with FIG. 12, the two-series modulator 11 outputs a first series PN1 when the transmission data a is "0", and outputs a second series PN2 when the transmission data a is "1" , The output of the two-series modulator 11 is passed via the transmission interface 12 to a transmission path.

As described in BACKGROUND OF THE INVENTION, the transmission interface 12 provides for modulation of a carrier or composition with the network in a network transmission. In general, it is a mechanism or means for connection to the transmission medium. Likewise, the receive interface 13 provides for demodulation of the carrier or isolation of a signal from the network during network transmission. The reception interface 13 outputs a received signal c (RXI) which is sent to a two-row demodulating apparatus 14 which outputs received data e (RXD) corresponding to the binary number "0" or "1" of the transmission data a (TXD) , The two-row demodulating apparatus 14 further outputs a carrier detection signal f when a carrier signal is received.

Fig. 5 shows the entire arrangement of a second communication system according to a CSK system using Manchester code M series. The signal transmission side of this system has a DSK modulator 111 comprising two Manchester M series generators 131 and 132 which synchronously generate two different Manchester code M series with a predetermined period. The two series have the same code length, and the Manchester M series actually transmitted has a maximum value of the absolute value of their autocorrelation, which is always greater than that of the cross-correlation of the two Manchester M series. The code outputs of the generators 131 and 132 are routed to a circuit 133 which is also included in the DSK modulator 111. The switching circuit 133 is independently operated according to the binary number of the transmission data ("1" and "0"). For example, when the transmission data is "0", the circuit 133 selects the code output of the generator 131; and if they are "1", the circuit 133 selects the code output of the generator 132. The thus-selected code output is transmitted as a transmission signal TXU. The operation of the circuit 133 is carried out in synchronism with the period of the generated Manchester code M series, and all the binary number data ("1" and "0") are represented by a Manchester M series of one period. The transmission signal TXO is passed through a transmission interface 112A to a signal transmission path or signal transmission medium.

The choice of circuit to be made between the two different Manchester code M series, ie the choice of which series is switched, is determined by the code ("1" or "0") of the data to be transmitted. Therefore, the modulation system is referred to as a "variable encoding keying (CSK) modulation system". It will be readily apparent to one skilled in the art that with a CSK modulation system, the PN code series, and not just the Manchester M series, can be used.

The signal receiving side of the system shown in Figure 5 includes a receive interface 112B which provides demodulation of a carrier, isolation of a signal from the network, and A / D (analog to digital) conversion. The receiving interface 112B converts a signal received by the signal transmission medium into a digital received signal RXI.

The signal receiving side further includes a signal receiving device 114 that includes two correlators 121 and 122, a demodulator 123, a carrier detection circuit 124, and a synchronous control circuit 125. The digital received signal RXI output from the receiving interface 112B is sent to the first and second correlators 121 and 122. The Manchester code M series generated by the Manchester M series generator 131 has been set in the first correlator 131, so that the thus set Manchester code M series is correlated with the received signal RXI. Also, the Manchester code M series generated by the Manchester M series generator 132 has been set in the second correlator 132, so that the thus set Manchester code M series is correlated with the received signal RXI. The correlation outputs of each of the correlators 121 and 122 are supplied to the demodulator 123 by selecting a demodulating signal "1" or "0" after the inputted correlation values; This demodulating signal is output as received data RXD. In particular, when the correlation output of the first correlator 121 has a larger correlation peak than that of the second correlator 122, the received data "0" is provided from the demodulator 123; and when the correlation output of the second correlator 122 has a larger correlation peak than that of the first correlator 121, the received data "1" is provided from the demodulator 123.

The correlation outputs are further passed to the carrier detection circuit 124 and the synchronous control circuit 125. The carrier detection circuit 124 detects the presence or absence of a carrier in the received correlation output to provide a detection signal. The detection signal is supplied to the synchronous control circuit 125. The presence or absence of the carrier is used to determine whether the received signal RXI is received or not. When the carrier is detected, the synchronous control circuit 125 forms a clock signal for demodulation and carrier detection, which is supplied to the demodulator 123 and the carrier detection circuit 124.

As described above, in the CSK communication system, the two correlation outputs on the signal receiving side are compared, and the received data "0" or "1" are determined on the basis of the difference detected by this comparison. Therefore, the Manchester M series on the signal reception side is not always strictly synchronous with that on the signal transmission side, and the data can be demodulated without error. Furthermore, if the outputs of the correlators are used in the form of absolute values, no error will be caused even if the signal transmission path, due to its adverse effect on a transmission signal, makes the transmission peak negative. In addition, the use of the Manchester code M series can reduce the low frequency components of the received signal, thereby significantly suppressing the coupling loss associated with the signal transmission path.

II. Signal transmission side

CSK modulator 111

FIG. 6 shows an exemplary embodiment of the CSK modulator 111 of the exemplary embodiment of the invention illustrated in FIG. 5. For the embodiment shown in Fig. 6, Fig. 7 shows the waveforms of various signals at various points in this.

Each Manchester M series generator 131, 132 includes a three-stage (n = 3) shift register 190, 191. The shift register 190 of the generator 131 has the stages FF11, FF12 and FF12. and FF & sub1; & sub3 ;, and the shift register 191 of the generator 132 has the stages FF & sub2; & sub1 ;, FF & sub2; & sub2; and FF & sub2; & sub3 ;. These shift registers shift data with the clocking of a clock signal CK generated by a clock signal generator 134. The feedback circuit of the first shift register 190 (FF11 to FF13) is different from that of the second shift register (FF21 to FF23). In the shift register 190, the second and third stage codes FF & sub1; & sub2; and FF & sub1; & sub3; to the input stage FF & sub1; & sub1; fed back by EXCLUSIVE OR (EX-OR) circuit 131a; and in the shift register 191, the first and third stage codes FF & sub2; & sub1; and FF & sub2; & sub3; to the input stage FF & sub2; & sub1; fed back by an EXCLUSIVE-OR circuit 132a. The shift registers and their feedback circuits form the M series generators (PN code generators, where PN means "pseudo noises"). The clock signal CK and the code output of the last stage FF & sub1; & sub3; of the shift register 190 are supplied to an EX-OR circuit 137, while the clock signal CK and the code output of the last stage FF & sub2; & sub3; of the shift register 191 are supplied to an EX-OR circuit 138 so that the Manchester codes are formed.

A phase synchronization circuit is provided to cause the state that when the Manchester M series generator 131 is in a certain phase (continuous), the Manchester M series generator 132 is in a predetermined phase (initial phase). The phase synchronization circuit includes a NAND circuit 136 and an initial phase setting unit 135. The initial phase setting unit 135 is intended to operate in the stages FF & sub2; & sub1; to FF & sub2; & sub3; of the shift register 191 set initial codes. It can set arbitrary codes (except permanent zero codes). When all stages FF & sub1; & sub1; to FF & sub1; & sub3; of the shift register 190 is "1" (which occurs once per period T of the Manchester code M series), the output of the NAND circuit 136 is set to "L", and at the subsequent rise of the clock signal CK, the codes derived from of the initial phase setting unit 135 are set in the stages FF & sub2; & sub1; to FF & sub2; & sub3; the shift register 191 is loaded.

The outputs of the Manchester M series generators 131 and 132, that is, the outputs of the EX-OR circuits 137 and 138 are supplied to the switching circuit 133. With the aid of the transmission data TXD, the circuit 133 is operated at each period (each data interval) T of the Manchester code M series. The output of the NAND circuit 136 is passed as a transmission request signal to a transmission data processing section (such as a microprocessor). Each time the transmission request signal is sent to the transmission data processing section, it outputs one bit ("1" or "0") of the transmission data TXD and supplies it to the switching circuit 133.

Fig. 8 shows another embodiment of the CSK modulator 111 '. In contrast to the CSK modulator shown in FIG. 6, the CSK modulator 111 'of FIG. 8 does not include EX-OR circuits 137 and 138 within the corresponding Manchester M series generator 131A and 132A (131 and 132 in FIG. 6). Instead, an EX-OR circuit 139 which receives the modulation output MDout of the switching chip 133 and the clock signal CK is provided on the output side of the Manchester code providing circuit 133. The outputs of the Manchester M series generators represented by the codes of the last stages of the shift registers are sent to the circuit 133. The in Fig. 8th The arrangement shown is advantageous because the number of EX-OR circuits is reduced to one.

The switching circuit 133 switches the outputs of the Manchester M series generators 131A and 131B in each time period in accordance with the binary number "0" or "1" of the transmission data TXD. In the drawings, the output PN1 of the generator 131A is selected when the transmission data TXD is "0", and the output PN2 of the generator 131B is selected when the transmission data TXD is "1".

A one-clock memory circuit may be provided on the output side of the circuit 133 in Fig. 6 or on the output side of the EX-OR circuit 139 in Fig. 8 to form the waveform of the transmission signal TXO.

Fig. 9 shows another embodiment of the CSK modulator 111 ", and Fig. 10 shows the waveforms of various signals at different points in this CSK modulator.

In the embodiment of Fig. 9, the Manchester M series generators consist of a shift register having a plurality of stages, feedback circuits coupled to the shift register, and an EX-OR circuit receiving the output of the shift register and the clock signal. In particular, in the CSK modulator shown in FIG. 9 1, the first Manchester M-series generator includes a shift register 192 having stages FF & sub1 ;, FF & sub2; and FF & sub3 ;, an EX-OR circuit 131a which is a feedback circuit, and an EX-OR circuit 139 for forming a Manchester code; the second Manchester M series generator comprises the shift register 192 (FF 1, FF 2 and FF 3), an EX-OR circuit 131b which is a feedback circuit, and the EX-OR circuit 139 for forming a Manchester code. The shift register 192 (FF 1, FF 2 and FF 3, where the shift register has three stages, n = 3) is common to both Manchester M series generators, as is the EX-OR circuit 139 for forming a Manchester code. In other words, the shift register 192 (FF 1, FF 2 and FF 3) and the EX-OR circuit 131a constitute a first M-series generator, while the same shift register 192 (FF 1, FF 2 and FF 3) and the EX- OR circuit 131b constitute a second M series generator; and the first M series generator and the EX-OR circuit 139 form a first Manchester M series generator, while the second M series generator and the EX-OR circuit 139 form the second Manchester M series generator.

The feedback circuit, that is, the EX-OR circuit 131a, operates to feedback the second and third stage codes FF & sub2; and FF & sub3; of the shift register 192 to the input stage FF & sub1; connect to; and the EX-OR circuit 131b operates to feedback the first and second stage codes FF & sub1; and FF & sub2; with the input FF & sub1; connect to. The feedback circuits of the two Manchester M series generators differ from each other. The circuit 133 is connected to the feedback circuits such that the outputs D & sub1; and D & sub2; of the EX-OR circuits 131a and 131b are supplied to the switching circuit 133, respectively. The output of the circuit 133 is fed to the input stage FF & sub1; the shift register 192 (FF 1, FF 2 and FF 3).

The switching circuit 133 is operated in accordance with the transmission signal TXD by the Q output (SW) of a D flip-flop circuit 130 in each period (each data interval) T of the Manchester code M series. The output clock signal CK of the clock signal generator 134 is supplied to the shift register 192 to control the timing of the shift operation therein, and is supplied to the D flip-flop circuit 130. When all stages FF & sub1 ;, FF & sub2; and FF & sub3; of shift register 192 are "1" (which is once per period T), the output of NAND circuit 136 is set to "L". The "L" output is passed to the D flip-flop circuit 130 as the enable signal EN. Therefore, when the enable signal EN has an "L" level, the D flip-flop circuit 130 fetches the transmission data TXD at the fall of the clock signal CK and supplies it to the switching circuit 133 as a switching control signal SW. In response to the switching operation of the circuit 133, the feedback circuit of the Manchester M series generator (the first or second M series generator) is completed, and the output MDout of the M series generator whose feedback circuit is completed (or the output of the last stage of the shift register ) is passed to the EX-OR circuit 139. The clock signal CK is supplied to the EX-OR circuit 139; the output MDout of the M series generator is thus Manchester coded and is output as a transmission signal TXO.

If necessary, the output of the NAND circuit 136 may be output as a transmission request signal to the transmission data processing section (such as a microprocessor) to cause the latter to generate the following one bit of the transmission data TXD. In addition, a one-clock memory circuit may be provided on the output side of the EX-OR circuit 139 to form the waveform of the transmission signal TXO.

III. Signal receiving side

Two-series demodulating device 14

Fig. 11 is a block diagram showing the two-series demodulating apparatus 14 of the embodiment of the invention shown in Fig. 4. Fig. 12 shows the waveforms of the points a, b, e, f, d & sub1; and d & sub2; of Fig. 4 and 11.

The modulated received signal c (RXI) is passed both to a first correlator 141, where the signal c is correlated with the first series PN1, and to a second correlator 142, where the signal c is correlated with the second series PN2. The corresponding outputs d & sub1; and d & sub2; The correlators 141 and 142 are each compared by separate corresponding comparators 143 and 144 with a threshold VR. The comparators 143 and 144 output a pulse "1" when the signal c is greater than the threshold VR. The outputs of the comparators 143 and 144 are routed to the R and S terminals of an RS flip-flop circuit 145, respectively. As shown in Figure 11, the output of comparator 143 is directed to the R terminal and the output of comparator 144 is passed to the S terminal. Since the transmission data "0" corresponds to the first series PN1, the input terminals of the RS flip-flop circuit 145 are arranged to reset the RS flip-flop circuit 145 when the received signal c is the first series PN1 (the output of the Circuit 145 is "0"), and so that the RS flip-flop circuit 145 is set when the received signal c is the second series PN2 (the output of the circuit 145 is "1"). The waveforms of the correlation outputs d & sub1; and d & sub2; at the signal reception side and the demodulated data e from the RS flip-flop circuit 145 are shown in FIG. As shown in Fig. 12, the correlation peaks appear at the end of each time period.

If no carrier signal is received, the carrier detection circuit 15 outputs a signal f. The carrier detection circuit 14 is provided with an OR circuit 15A and a timer 15B. Each output of the comparators 143 and 144 is sent to the timer 15B via the OR circuit 15A. The timer 15B is set by an output pulse of the OR circuit 15A and outputs a signal f of "1" for a predetermined period of time, and then outputs a signal f of "0" after the elapse of the time period. The predetermined time period is set longer than the time period T of the PN code (see Fig. 12). Therefore, the signal f is always "1" when one of the correlation outputs is present during the predetermined time period of the signal f, and the signal f is "0" when there is no correlation output after the elapse of the time period, so that the non-carrier state is detected.

According to the two-unit demodulating apparatus 14 of the first system of the invention as described above, the reception data "1" or "0" can be obtained simply by detecting the synchronization and operation of the RS flip-flop circuit. This is unlike the conventional system shown in Fig. 1 in which the received data "0" or "1" is formed as a correlation waveform from the modulated received signal. Therefore, it is not necessary that the phase synchronization of the PN code on the signal reception side be strictly synchronous with that on the signal transmission side. Furthermore, no error is caused in the data demodulation when the absolute value of the output of the correlator is used.

In principle, as shown in Fig. 11, the two-row demodulator 14 is connected to a correlation part in which the received signals are correlated with PN1 and PN2 output from the two internal PN code generators, a data demodulation part in which the data is in coincidence are demodulated with an output of the correlation part, and a carrier detection circuit.

Fig. 13 is a circuit diagram showing another embodiment of the two-series demodulator. In this embodiment, a surface acoustic wave (SAW) convolver is used. The circuit arrangement shown in Fig. 13 is substantially the same as that shown in Fig. 11. That is, the first PN code series corresponding to the transmission data of the binary number "0" is correlated with PN1 by a first SAW (surface acoustic wave) convolver 41, while the second PN code series corresponding to the binary data transmission data " 1 ", is correlated to PN2 by a second SAW convolver 42. Here, the received signal c is an analog signal.

Fig. 14 shows waveforms of signals in the circuit shown in Fig. 13 in connection with four bits of transmission data. The output f of the carrier detection circuit 15 returns to "0" after a time t + T (t> T, a timing of one-bit data) after the timer 15B is set, and then the data transmission is completed.

The correlation part of the signal demodulating device will now be described in several embodiments. In one embodiment, the correlator input data is an analog signal; In another embodiment, the correlator input data is a digital signal obtained by converting an analog signal to a digital form.

Fig. 15 shows the correlation part where the received signal is a digital signal. The received signal is passed to both correlators 50 (1) and 50 (2), which have the same construction. In Fig. 15, only the correlator 50 (1) is shown in detail. The received signal is correlated with the first series PN1 by the correlator 50 (1) and with the second series PN2 by the correlator 50 (2).

A state pattern of the first series PN1 is set by a register 51 and stored therein. Therefore, the number of stages of the first series PN1 is equal to the code length N. Such a data pattern is designated as PN1-1, PN1-2, ...., PN1-n. The received signal is passed to a shift register 52 in which the content of the received signal is changed stepwise in its stages. The output of each stage of the shift register 52 is passed to an input of a corresponding EX-OR circuit of an EX-OR circuit group 53 comprising n (= N * m) EX-OR circuits. The fixed data pattern PN1-1 - PN1-n stored in register 51 is supplied to the other input of corresponding EX-OR circuits in the EX-OR circuit group 53. All outputs of the EX-OR circuit group 53 are summed by a summing circuit 54 which outputs a correlation output d & sub1; outputs.

To improve the accuracy of the correlation process, the shift register 52 has n (= N * m) stages for correlating all the data of the number m with each bit of the fixed data pattern. Furthermore, the shift clock is multiplied by m.

By providing a delay line with n (= N * m) taps instead of the shift register 52, a multiplier group instead of the EX-OR circuit group 53, and an analog adder instead of the summing circuit 54, the correlation part can be adapted to an analog received signal.

Fig. 16 shows another embodiment of the correlation part, wherein a single shift register is generally used, so that the number of required circuits is reduced. Memory registers 611 and 621 respectively store a fixed pattern of the first series PN1 and the second series PN2. A shift register 610 with n (= N * m) stages for inputting the received signal is used in common both for correlation with the first and second series. The simple shift register 610 is connected both to a first series circuit group including an EX-OR circuit group 612 and a summing circuit 613 for outputting a first correlation output d & sub1; and a second series circuit group including an EX-OR circuit group 622 and a summing circuit 623 for outputting a second correlation output d & sub2; contains.

The device shown in Fig. 16 is for a received signal. However, it may be adapted to an analog received signal by providing a delay line with a tap instead of the shift register 610, a multiplier group instead of the EX-OR circuit group 612 and 622, and an analog adder in place of the summing circuits 613 and 623.

Fig. 17 is a circuit diagram showing still another embodiment of the part of the signal receiving apparatus which carries out the correlation and in which the number of circuits shown in Fig. 15 is reduced. This circuit is disclosed in detail in Japanese Patent Application No. 160954/88 filed by the same applicant.

In Fig. 15, as described above, one bit of the fixed pattern is supplied to each EX-OR circuit in an EX-OR circuit group 53 with n (= N · m) EX-OR circuits, and the outputs of all EX -OR circuits are summed by the summing circuit 54. If the received signal is a digital signal, therefore, the outputs of two consecutive adjacent EX-OR circuits are added by a corresponding first adder circuit; then the outputs of two consecutive adjacent first adder circuits are added by a corresponding second adder circuit. Therefore, the number of adders in a plurality of adder circuits becomes extremely large overall. According to the in Fig. 17 On the other hand, a correlator part 70 is composed of a plurality of correlation circuits 71 (1) -71 (7). In the example of Fig. 17, the M series code has a code length of 7 bits. Each of the correlation circuits 71 correlates, for example, one bit of the fixed pattern with data of the number m (corresponding to SF1-SFm in FIG. 15) of the reception data N * m.

According to the example of Fig. 17, the correlation values ​​with respect to data of the number m are added at one time by the use of a bidirectional counter in terms of a ratio between the input value and the output value of the m-stage shift register. More specifically, first, the register 72 inputs the first series PN1 having the code length of 7 bits and stores each bit value M1-M7 therefrom. Thereafter, the correlation part 70 inputs the received signal, and the data contained therein is shifted by the correlation circuits 71 (1) -71 (7), and each block correlates them.

As shown in Fig. 18, each correlation circuit 71 includes an 8-stage shift register 71A, a pair of EX-OR circuits 71B, 71C, and a bidirectional counter 71D. The bi-directional counter 71D counts a correlation of an input signal D & sub1; with a bit value M of the PN1. Fig. 19 is a table showing a correlation counting operation of the counter 71D. All correlated counts from the correlation circuit 71 (1) -71 (7) are read by an addition part 73 shown in FIG. 17 is added, so that a correlation signal d & sub1; can be obtained.

With respect to PN2, a correlation signal d & sub2; be obtained by the same circuit structure. According to the example described above, the total number of adders can be significantly reduced, thereby providing a simple circuit. Furthermore, such a device is advantageous because a phase delay is effectively reduced.

In Fig. 17, a pair of the correlation part 70 is arranged separately for PN1 and PN2. However, the shift register 71A may be shared for PN1 and PN2. Fig. 20 is a circuit diagram showing an entire structure of the device, and Fig. 21 is a circuit diagram showing a specific construction of the correlation circuit 71.

Correlators 121 and 122

The two correlators 121 and 122 of the embodiment of the invention illustrated in FIG. 5 will now be described together with reference to FIG. Correlators 121 and 122 have registers 241a and 241b, each having N stages (register 241a in correlator 121 and register 241b in correlator 122). The Manchester code M series generated by the Manchester M series generators 131 and 132 in the modulator 111 were recorded in the registers 241a and 241a, respectively. 241b set in advance The code length of the M series generated by an n-stage shift register is 2n-1. In the modulator 111, the M series is Manchester encoded; thus, the number of stages N of the registers 241a and 241b is as follows:

N = 2 (2n - 1)

On the other hand, the digital received signal RXI input through the receiving interface 112B is supplied to the shift registers 242a and 242b provided in the correlators 121 and 122, respectively. These shift registers 242a and 242b also have N stages and are driven by the clock signal CK whose frequency is twice that of the clock signal in the modulator 111.

In the correlator 121, the codes set in the stages of the register 241a and the received signal codes supplied to the respective stages of the shift register 242a are respectively supplied to EX-OR circuits 243a where they are subjected to comparison , The outputs of all the EX-OR circuits 243a are passed to an adder 244a where they are subjected to addition. The output of the adder 244a represents the degree of correspondence between the codes at the stages of the register 241a and the codes at the stages of the shift register 242a, and is the correlation output Ra of the correlator 121. The received signal RXI is input to the shift register in response each clock signal CK is shifted, and therefore the correlation output Ra changes with each clock signal CK.

In the same manner as in the above-described correlator 121, in the other correlator 122, EX-OR circuits 243b determine whether or not the codes set in the stages of the register 241b coincide with the received signal codes corresponding to the corresponding ones Stages of the shift register 242b are passed. The outputs of all the EX-ORs 243b are passed to an adder 244b where they are summed. The adder 244b outputs a correlation output Rb representing the degree of correspondence between the Manchester M series set in the register 241b and the input digital received signal RXI.

Fig. 23 shows a modification of the correlator 121. The modification uses a register 241A and a shift register 242A each having N · m stages (where m is the positive integer greater than one (1)) instead of the register 241a and the shift register 242a , The shift register 242A is driven by a clock signal CKm whose frequency is m times as high as that of the above-described clock signal CK. The correlator 121 includes Nxm EX-OR circuits 243A which receive the codes set in the stages of the register 241A and those in the stage of the shift register 242A, respectively. The outputs of all the EX-OR circuits 243A are passed to an adder 244A where they are summed. As a result, the adder 244A provides a correlation output Ra. By multiplying the number of stages of the register and the shift register by a factor of m, the accuracy of the correlation operation can be increased. The other correlator 122 may be modified in the same way.

Fig. 24 shows another embodiment of the correlators 121 and 122. Here, the correlators 121 and 122 include one and the same shift register 242 to which the received signal RXI is routed. That is, the number of shift registers is reduced, thereby simplifying the arrangement. Likewise, the shift register whose number of stages is multiplied by m as shown in FIG. 23 may be generally included in both correlators 121 and 122.

Fig. 25 shows another example of the correlators 121 and 122. An N-level register 241a and a N × m stage shift register 242A are shown. Here, one stage of the register 241a corresponds to m stages of the shift register 242A. Therefore, the codes set in the stages of the register 241a and the codes in the stages of the shift registers 242A are supplied to m EX-OR circuits 243A to determine the degree of coincidence therebetween.

Fig. 26 shows an arrangement of the register 241a. As shown in Fig. 27, the Manchester M series codes are formed in accordance with the codes of the original M series. This will be described in more detail. As shown in Fig. 26, the codes of the M series are set in a register 241d of N / 2 stages, and are outputted as they are and outputted by NOT circuits 241c to obtain the Manchester M series codes.

Demodulator 123

Fig. 28 shows an embodiment of the demodulator 123 and the carrier detection circuit 124 of the embodiment of the invention shown in Fig. 5. Fig. 29 shows the waveforms of various signals at various points in the circuit shown in Fig. 28. For the sake of simplicity, the correlation outputs Ra and Rb are shown as an analog signal.

First, the principle of demodulating data in accordance with the correlation outputs Ra and Rb of the correlator pair 121 and 122 will be described. In Fig. 29 a data interval T (equal to one period of the Manchester M series) is divided into three parts; a central part, that is, a window part (which will be referred to simply as "W part" hereinafter) and two parts on each side of the W part (which, if appropriate, will be referred to simply as " E-parts "are called). The two E-parts have the same length. It is not always necessary to provide the two E parts with the same length or provide the W part in the middle of the data interval T. That is, the W part and the E parts can be represented as follows:

W part - interval between (T - d) / 2 and (T + d) / 2

E-parts - interval between 0 and (T - d) / 2 and interval between (T + d) / 2 and T (where 0 <d <T)

The W part is called "observation interval".

When data is transmitted, one of the correlation outputs Ra and Rb has a correlation peak during the data interval T. The correlator peak is detected by the synchronous control circuit 125, and a data interval end signal ED for defining the end of a data interval is formed so that the correlation peak is in the middle of the data interval T is coming. The synchronous control circuit 125 forms, in accordance with the data interval end signal ED, a window start pulse WL for the starting point of the W part and a window stop pulse WH for defining the end point of the W part.

In the following description, the characters Paw, Pbw, AaE and AbE shall have the following meaning:

Paw: the peak value (maximum value) of the W part of the correlation output Ra;

Pbw: the peak value (maximum value) of the W part of the correlation output Rb;

AaE: the sum (the addition value) of the E parts of the correlation output Ra; and

AbE: The sum (the addition value) of the E parts of the correlation output Rb.

The modulation data (received data RXD) is generated as follows:

If Pbw.AaE> Paw.AbE, then the data is "1".

If Pbw.AaE <Paw.AbE, then the data is "0".

Theoretically, the data at Pbw> Paw is "1"; and at Pbw <Paw the data is "0". However, if noise is included, comparison of the peak values ​​in the correlation outputs may lead to demodulation errors. In general, in a correlation output having a correlation peak, the values ​​of parts on both sides of the peak are smaller than the correlation value of a correlation output having no correlation peak. For example, in the case where the correlation output Rb has a correlation peak, the sum AbE is smaller than the sum AaE of the correlation output Ra without the correlation peak. Due to this fact, the products of the peak values ​​and the sums of the various correlation outputs, that is, Pbw.AaE and Paw.AbE are compared to form demodulation data. Thus, demodulation can be stably achieved even in the case where, for example, the signal transmission path has a small signal transmission characteristic and thus causes noise.

The principle of carrier detection will now be described. The carrier detection is determined when the absolute value of (Pbw · AaE - Paw · AbE) exceeds a predetermined threshold Thp. The presence of the carrier means that one of the correlation outputs has a correlation peak. Therefore, the absolute value of the difference between the products of the peaks and the sum of different correlation outputs is relatively large. On the other hand, in the case where there is no carrier, the above-described absolute value is very close to zero (0). Thus, similar to the case of the data modulation, the presence or absence of the carrier can be detected without being affected by noise, etc.

The circuit shown in Fig. 28, which is a digital circuit, operates in synchronization with the clock signal CK or CKn; however, because of the simple description, the clock signal is not shown here.

In the circuit, the correlation output Ra is latched by a latch for one clock pulse and sent to an absolute value circuit 252a. The output of the absolute value circuit 252a is supplied to an adder 255a and a maximum value hold circuit 254a. On the other hand, the window start pulse VdL and the window stop pulse WE are supplied to a window generating circuit 253 which outputs a window signal WS raised to the "H" level with the W part. The window signal WS is sent as an operation control signal to a latch 248 in the adder 255a and to a latch 246 in the maximum hold circuit 254a.

In the adder 255a, the memory circuit 248 operates only when the window signal WS is at "L" level in accordance with the E-part. The storage timing is controlled by the clock signal. The absolute value of the input correlation output Ra is supplied to an adder 247 where it is added to the previous addition result supplied from the memory circuit 248 with each clock signal, and the addition result is latched by the memory circuit 248. Thus, the adder 255a outputs the sum AaE which is supplied to a multiplier 256a.

In the maximum hold circuit 254a, the memory circuit 246 operates only when the window signal WS is at a "H" level in accordance with the W-part. The previous maximum value latched by the memory circuit 246 is compared with the absolute value of the current correlation value Ra in a comparator 245. If the absolute value of the current correlation value is larger, it is latched as the last maximum value from the memory circuit 246. Thus, the maximum value hold circuit 254a outputs the peak value Paw, which is supplied to a multiplier 256b.

As in the case of the correlation output Ra, a latch circuit 251b, an absolute value circuit 252b, a maximum value hold circuit 254b, and an adder circuit 255b are provided for the correlation output Rb. The maximum value hold circuit 254b supplies the peak value Pbw which is supplied to the multiplier 256a. The adding circuit 255b supplies the sum AbE which is supplied to the multiplier 256b.

The multiplier 256a outputs the product Pbw.AaE, which is passed to a comparator 257 and to a subtraction and absolute value circuit 259. The multiplier 256b outputs the product Paw.AbE, which is passed to the comparator 257 and to the subtraction and absolute value circuit 259.

In the comparator 257, the product Pbw.AaE and the product Paw.AbE are compared, and a signal "1" or "0" is output in accordance with the result of the comparison. The output signal is latched by a latch 258 at the timing of the data interval end signal ED and output as the reception data RXD. The data interval end signal ED resets the adder circuits 255a and 255b and the maximum value hold circuits 254a and 254b.

On the other hand, in the subtraction and absolute value circuit 259, the subtraction of (Pbw.AaE Paw.AbE) is carried out and the absolute value of the result of the subtraction is obtained. The absolute value is passed to a comparison circuit 260, where it is compared to the threshold Thp. When the absolute value is greater than the threshold value Thp, the comparison circuit 260 outputs a carrier detection signal PAS.

Synchronous control circuit 125

Fig. 30 shows an example of the arrangement of the synchronous control circuit 125 of the embodiment of the invention shown in Fig. 5. The circuit 125 includes a peak position detection circuit 226A, a peak position determination circuit 226B, a synchronization production determination circuit 228, and a synchronization non-production determination circuit 229.

The peak position detection circuit 2 is to detect the position of the peak of the correlation output in the data interval T. As shown in Fig. 31, the peak position PP is measured as a time period elapsing from the time point at which the maximum value appears in the correlation output until the occurrence of the data interval end signal ED. In the embodiment, the peak position is where the sum of the two correlation outputs Ra and Rb has a maximum absolute value.

The two correlation outputs Ra and Rb are passed to an adder 261 where they are subjected to addition. The output of the adder 261 is passed to an absolute value circuit 264 so that the absolute value of the sum of the correlation outputs is obtained. The absolute value is supplied to an input terminal of a comparison circuit 262 and a latch circuit 263. When the signal ED indicative of the end of the previous data interval is sent as a memory clock signal to the memory circuit 263 through an OR circuit 165A, the output of the absolute value circuit 264 is latched as an initial value. The value latched by the memory circuit 263 is supplied to the other input terminal of the comparison circuit 262. Thereafter, the output of the absolute value circuit 264 is compared with the value latched by the memory circuit 263 (every clock pulse of the clock signal CK). When the absolute value circuit 264 supplies an output larger than the value latched by the memory circuit 263, the output of the comparison circuit 262 is supplied to the memory circuit 263 through the OR circuit 265A, and the output of the absolute value circuit 264 is designated as the last value is latched by the memory circuit 263. Thus, the memory circuit 263 always stores a largest value.

On the other hand, a counter 266 for counting the clock signal CK is reset (cleared) by the data interval end signal ED applied by an OR circuit 265B or by the comparison output of the comparison circuit 252 also applied through the OR circuit 265B that the counter starts its counting process starting with zero (0). The output of the counter 266 is latched by a latch 267 in response to the next data interval end signal ED. Thus, the counter 266 counts the clock signal CK for the period of time elapsing from the time when the peak occurs in the data interval T to the signal ED indicating the end of the data interval T. The count value of the counter is latched by the memory circuit 267, thereby representing the peak position PP.

The data PP indicating the thus detected peak position is sent to the peak position determining circuit 226B. The peak position determining circuit 226B is for determining whether or not the detected peak position is in the W part. As is apparent from the foregoing description, the correlation peak should be in the W part in both the receive data demodulation and the carrier detect. When the correlation peak is not in the W part, it is impossible to correctly perform the reception data demodulation and carrier detection.

In the peak position determination circuit 226B, comparators 268 and 269 and an AND circuit 270 constitute a window-like digital comparison circuit. Data representing the start position of the W part was set in the comparator 268, and data representing the stop (or end) position of the W part was set in the other comparator 269. Only when the data representing the peak position PP is between the start position and the stop position, the AND circuit 270 outputs a peak position determination signal PH. Corresponding waveform timing diagrams are shown in FIG.

The arrangement and operation of a synchronization production circuit including the synchronization production determination circuit 228 will be described with reference to FIG. 30. Corresponding waveform timing diagrams are shown in FIG.

The circuit includes two registers 272 and 273. The data representing the peak position PP are passed to the register 272 where the data representing ((3/2) T-PP) is set, where T is the data which represent the length (time) of the data interval. On the other hand, the data T has been set in the register 273. The registers 272 and 273 are connected to a selector 274. The selector 274 selects data set in either the registers 272 or 273 in accordance with the state of the peak position designating signal PH and supplies them to an input terminal of a digital comparator 275.

On the other hand, a counter 271 counts the clock signal CK, and the counter output is supplied to the other input terminal of the digital comparator 275. The digital comparator 275 generates the data interval end signal (coincidence signal) ED when the count value of the counter 271 is equal to the set data received by the selector 274. The counter 271 is reset by the signal ED, and thus its counting starts from zero (0).

For example, when the power switch is turned on, the correlation output is out of sync with the data interval, and therefore, there is sometimes no correlation peak in the W part. In this case, the peak position determination signal PH is set to the "L" level, and the selector 274 selects the set data ((3/2) T - PP) of the register 272 and supplies it to the comparator 275. The set data ((3/2) T - PP) is to generate the next data interval end signal ED so that the length (time) between the next peak and the next data interval end signal is T / 2. Thereafter, when the peak is found in the W part, the peak position determination signal PH is raised to the "H" level, and the selector 274 selects the set data T of the register 273. As a result, thereafter, the data interval end signal ED appears with a period of T.

It is said that synchronization was made when the provision of the peak position in the W part of the data interval takes place successively with a certain number of repetitions (x times). In the synchronization establishment determination circuit 228, a counter 282 is brought into a clock enable state by the "H" level peak position designation signal PH supplied through an AND gate 281, whereby the data interval end signal ED is counted. When the signal PH is at the "L" level, the counter 282 is reset by the signal PH supplied through a NOT circuit 284 and an OR circuit 285. The counter output of counter 282 is passed to a digital comparator 283 in which the predetermined number of repetitions (X times) used to determine the synchronization establishment has been set. Therefore, when the counter value of the counter 282 reaches X, the digital comparator 283 outputs a coincidence signal for setting a flip-flop circuit 219, and this 219 outputs a synchronization production signal DSR ("L" level). The match signal output from the comparator 283 is passed through the OR circuit 285 to the counter 282 to reset the latter 282. The synchronization production signal DSR is supplied to the AND circuit 281 to close it; thus, the application of the peak position determination signal PH is interrupted.

If the peak position determination signal PH is set to "L" level only once while the counter 282 counts the signal ED, the counter 282 is reset. Therefore, only when the signal PH x times in succession is input, while the signal PH is at the "H" level, the synchronization production is determined. When the signal PH is set to the "L" level before the synchronization establishment is determined, the selector 274 selects the register 272, and the timing of generation of the data interval end signal ED is adjusted.

The synchronization non-production determination circuit 229 is provided for determining the state in which the carrier detection signal PAS is not provided in a predetermined number (Y) of data intervals. This state indicates that no synchronization has been established.

The synchronization non-production determination circuit 229 will be described with reference to FIG. 33. When the synchronization is established, a NAND gate 291 is opened by the synchronization manufacturing signal DSR of "L" level. When the carrier is detected, the carrier detection signal PAS is at an "H" level. And when the carrier is not detected, the carrier detection signal PAS is at an "L" level. The signal PAS is passed through the NAND gate 291 to a counter 292; that is, an enable signal of "H" level is supplied to the clock enable terminal CE of the counter 292. The carrier detection signal PAS of "H" level is supplied through the NAND gate 291, a NOT circuit 294 and an OR circuit 295 to the counter 292 to reset the counter 292. When the counter 292 is brought into a release state, it counts the data interval end signal ED. The count value of the counter 292 is supplied to a digital comparator 293 in which the predetermined number Y has been set in advance. Therefore, when the count value of the counter 292 reaches the value Y, the comparator 293 outputs a coincidence signal to reset the flip-flop circuit 219, so that the synchronization establishment signal DSR is raised to the "H" level. The "DSR" signal DSR closes the NAND gate 291. The output of the comparator 293 is passed through the OR circuit 295 to the counter 292 to reset the counter 292.

When the carrier detect signal PAS is raised to the "H" level while the counter 292 is in operation, the counter 292 is reset. That is, only when the carrier is not detected with a Y number of data intervals, it is determined that the synchronization has not been established.

Thus, the temporary non-detection of the carrier, for example due to variations in the transmission characteristic of the signal transmission path, and the non-detection of the carrier due to the termination of the communication (the synchronization is intentionally not established) can be clearly distinguished from each other.

IV. CSK modem

Fig. 34 shows an embodiment of a modem 510 including a CSK signal transmission device and a CSK signal reception device according to the present invention. The CSK modem includes a signal transmission device having the in Fig. 5 and a signal receiving device including the correlators 121 and 122, the demodulator 123, the carrier detection circuit 124, and the synchronous control circuit 125 of FIG. 5, and the transmission interface 112A comprising the reception interface 122B.

The signal transmission device includes the modulator 111 configured to CSK modulate transmission data TXD using Manchester M serial codes. The modulated transmission signal TXO provided by the modulator is routed to a mains AC in-line interface 112. In this embodiment, the network communication is performed using a mains AC line (for example, 100V) as the signal transmission line. The transmission signal TXO is converted by the interface 112 to a signal suitable for network communication, and the signal superimposed on the AC power supply is conducted to the power line.

In the interface 112, a signal transmitted via the power line from another modem is received and disconnected from the AC power, and subjected to signal conversion (including digital conversion) as needed. The thus processed signal is passed as a received signal RXI to the signal receiving device in the modem.

The signal receiving apparatus includes the correlators 121 and 122, the demodulator 123, the carrier detection circuit 124, the peak position detection circuit 226A, the peak position determination circuit 226B, a sync tracking circuit 227, the synchronization production determination circuit 228, the synchronization non-production determination circuit 229, and the flip-flop circuit 219 for outputting the synchronization preparation signal DSR. The circuits 226A, 226B, 227, 228, 229 and 219 correspond to the synchronous control circuit 125 of FIG. 5 and are thus substantially similar to those shown in FIG. In Fig. 30, the synchronous control circuit does not include a synchronous tracking circuit for the sake of simplicity of description.

An embodiment of the synchronous control circuit with the synchronous tracking circuit is as shown in FIG. The circuit 227 has the above-described synchronization producing function for providing synchronization so that the correlation point occurs with the W part of the data interval; and a function for slightly adjusting the timing of generation of the data interval end signal ED such that the peak position is in the middle of the W-part.

In Fig. 36, the peak position detection circuit 226A and the peak position determination circuit 226B are arranged slightly differently than those in Fig. 30. This will be described in more detail.

In the peak position detection circuit 226A shown in Fig. 30, the two correlation outputs Ra and Rb are subjected to addition, and the peak value of the absolute value thereof is detected. On the other hand, in the circuit in Fig. 36, the peak positions of the correlation outputs Ra and Rb are separately detected and their peak values ​​are also detected separately. And the peak position whose peak value is larger is determined as the final peak position.

The correlation outputs Ra and Rb are supplied to the maximum value hold circuits (peak detection circuits) 400a and 400b, respectively. Each of the maximum value holding circuits is composed of an absolute value circuit 264, a latch 263, a comparator 261 and an OR circuit 265A similar to those shown in FIG. 30, and the maximum value of each data interval is held by the memory circuit 263 , The maximum values ​​(peak values) of the data intervals of the correlation outputs Ra and Rb are supplied to a comparison circuit 402 where they are subjected to comparison.

Peak position hold circuits 401a and 401b are provided for the correlation outputs Ra and Rb, respectively. Each of the peak position holding circuits is composed of an OR circuit 265B, a counter 266, and a latch 267, which are similar to those shown in FIG. The holding tip positions of the tip position holding circuits 401a and 401b are supplied to a changeover switch 403.

The changeover switch 403 is to select the larger one of the peak values ​​to be compared by the comparison circuit 402. The peak value selected by the changeover switch 403 is latched by a latch 404 in response to the propagation of the data interval end signal ED.

The peak position determining circuit 226B shown in Fig. 36 can be obtained by adding a comparator 406 and AND gates 407 and 408 controlled by the output of the comparator 406 to the circuit elements of the peak position determining circuit shown in Fig. 30. Data representing the center position of the window part (W part) was set in the comparator 406 (see Fig. 35). The detected peak position PP is supplied to the comparator 406, so that it is determined whether the detected peak position PP is at the left side of the center of the W part (which is the region closer to the start position (in the sequence, if applicable, referred to as "LT region") or located on the right side (which is the region closer to the stop position (hereinafter referred to as "RT region" if applicable)). When the peak position is in the LT region, the AND gate 407 is opened and the output of the comparator 368 is therefore provided as the left side decision signal Lf; when in the RT region, the output of the comparator 369 is provided as the right side decision signal Rh through the AND gate 408. The signals Rh and Lf are supplied to the OR circuit 409. The latter 409 outputs a signal Ct corresponding to the peak position designation signal Ph, which is sent to a synchronization establishment determination circuit. When the peak position PP is in the W part, the signal Ct is at the "H" level. When the peak position PP is in one of the E parts (OT regions) of the data interval, the signal Ct is at "L" level. These signals Lf, Ct and Rh are sent to the synchronous tracking circuit 227.

In the synchronous tracking circuit, therefore, circuit elements described with reference to FIG. 30 are denoted by the same reference numerals or numerals. The synchronous tracking circuit has, in addition to the registers 273 and 272 in which the data T and (3/2) T-PP have been set, registers 276 and 277 in which the data T-1 and T + 1 have been set. In the data T-1 and T + 1, the value "1" is much smaller than the value "T". For example, in the case where the shift register receiving the received signal RXI has 248 stages (for example, a 31-bit Manchester M series is used and each bit thereof is assigned eight cells: m = 8), T 248 set. The data T-1 and T + 1 of the registers 276 and 277 are used for slightly adjusting the data interval, whereby the peak positions of the correlation outputs Ra and Rb are slightly shifted (synchronous tracking) to approach the center of the W part. The data set in these registers 273, 276, 277 and 272 are passed to a selector 274A. The selector 274A selects the data T-1 of the register 276 when a signal S1 ("H" level) is input, the data (3/2) T-PP of the register 272 when a signal S2 ("H") is input. Level); the data T + 1 of the register 277 when a signal S3 ("H" level) is input; and the data T of the register 273 in the other cases when the signals S1, S2 and S3 are at "L" level. The data thus selected are passed to a comparator 275.

When the synchronization is not established yet, the synchronization establishment signal DSR is at the "H" level, and an AND gate 417 is open. In this case, when the detected peak position is in the OT region (the E part), the signal Ct is at the "L" level, and the output of the AND gate 417 becomes "H" level lifted. The output signal of "H" level is passed through an OR circuit 416 as the signal S2 to the selector 274A. Therefore, the data (3/2) T-PP of the register 272 is supplied to the comparator 275, and the above-described synchronization establishment processing is performed.

AND gates 421, 411 and 431 which receive the above-described signals Lf, Ct and Rh, respectively, are controlled by the synchronization establishment signal DSR and the carrier detection signal PAS. That is, when the synchronization has been established (with the signal DSR at the "L" level) and the carrier has been detected (with the signal PAS at the "H" level), the AND gates 421, 411 and 431 become opened to transmit the signals Lf, Ct and Rh.

A circuit receiving the signal Lf will be described. The left side decision signal Lf ("H" level) which is output when the peak position is in the LT region is passed through the AND gate 421 to the clock enable terminal CE of a counter 422. In response to the enable signal, the counter 422 counts the data interval end signal ED. The count value of the counter 422 is supplied to a comparator 423 in which a predetermined value Z (greater than one (1)) has been set in advance. When the count of counter 422 reaches the set value Z, comparator 423 provides an output ("H" level), which is passed as signal S2 to selector 274A. As a result, the selector 274A selects the data T-1, and therefore the period of the next data interval is set to (T-1), a value smaller than T. When the peak position of the correlation output in the LT region appears Z times in succession, the period of the next data interval is slightly decreased so that the peak position approaches the center of the W part.

The counter 422, the comparator 423, a NOT circuit 423, and an OR circuit 425 constitute a deflection determination circuit. With the deflection determination circuit, it is detected whether the peak position in the LT region appears Z times in succession. Therefore, instead of the temporary deflection of the peak position, the steady deflection tendency of the peak position can be detected, and the data interval end signal ED is formed so that the deflection of the peak position is corrected. Thus, the synchronous tracking operation is stably performed.

The counter 422 is driven by the "L" level output of the AND gate 421 (which is raised to "H" level by the NOT circuit 424) or the "H" level output of the comparator 423 leading to the OR gate. Circuit 425 is routed, reset.

Another deflection determination circuit is constituted by a counter 432, a comparator 433, a NOT circuit 434, and an OR circuit 435. The deflection determining circuit thus formed detects whether the peak position in the RT region appears Z times in succession. When the peak position in the RT region appears Z times in succession, the comparator 433 outputs the signal S3. As a result, the period of the next data interval is set to (T + 1), a value slightly larger than T, so that the peak position approaches the center of the W part.

A counter 412, a comparator 413, a NOT circuit 414, and an OR circuit 415 collectively form a non-synchronization detection circuit. When the peak position is in the E part (the OT region), the signal Ct is at the "L" level. The "L" level signal Ct is supplied to the AND gate 411, so that the "H" level signal is supplied to the clock enable terminal EC of the counter 412, and the latter 412 starts counting the AND gate 411 Data Interval End Signal ED. When the count value of the counter 412 reaches the value Z, the comparator 413 outputs a signal of "H" level, which is passed through an OR circuit 416 as the signal S2 to the selector 274. *** " Thus, the non-synchronization detecting circuit detects that the peak position does not appear in the W-part Z consecutively. And when the data ((3/2) T-PP) of the register 272 is supplied to the comparator 275, the synchronization manufacturing process is executed again.

In other cases than described above (the outputs of the comparators 413, 423 and 433 are at the "L" level), the data T of the register 273 is selected and the period of the data interval is set to T. In the embodiment described above, the same number of repetitions Z are set in the comparators 413, 423 and 433; however, different numbers of repetitions can be set.

The synchronization is made and corrected in the manner described above. Therefore, the peak position can be kept in the middle of the W part even if the signal transmission characteristic changes or the clock signal shifts.

In the present invention, it is not necessary that the Manchester M series on the signal receiving side be strictly synchronous with that on the signal transmitting side. The difference would not cause an error in the data demodulation. Furthermore, the outputs of the correlators are provided as absolute values; thus, no error is caused even with a deterioration in the signal transmission characteristic of the signal transmission path, whereby the transmission peak becomes negative. In addition, the use of the Manchester code M series reduces the low frequency components of the received signal, thereby suppressing the coupling loss associated with the signal transmission path. Thus, power lines having a high noise level can be effectively used as a signal transmission path. That is, although the noise of the power line includes a large range of low frequency components, the communication system according to the invention is hardly affected by such noise.