DE60217221T2

System on a chip for packet processing

Abstract

This record has no abstract on file.

DE60217221T2, drawing sheet 1 — Sheet 1 of 9

Term

Term ended

Projected expiry passed 20 May 2022, 4.3 years ago.

16 claims: 5 independent, 11 dependent

1
device ( 10 ) Comprising:a processor ( 12A . 12B ) Connected to an intermediate compound ( 24 ) Is coupled;a cache memory ( 14 ) of the with the intermediate ( 24 ) Is coupled;a Storage controller ( 16 ) Connected to the intermediate compound ( 24 ) Is coupled;and a packet interface circuit ( 22A . 22B . 22C ), Which packages ( 50 ) from a packet interface ( 44A . 44B . 44C ) receives and causing the packets ( 50 ) To store on the intermediate compound ( 24 ) be transmitted;in which the processor ( 12A . 12B ) For the processing of the of the Packet interface ( 44A . 44B . 44C ) received packages ( 50 ) Is programmable, characterized . that the processor ( 12A . 12B ), The cache memory ( 14 ), The memory controller ( 16 ), And the packet interface circuit ( 22A . 22B . 22C ) In a single semiconductor substrate are integrated;the packet interface circuit ( 22A . 22B . 22C ) in response to receiving a packet ( 50 ) from the packet interface ( 44A . 44B . 44C ) is configured to cause a first portion package ( 50 ) In the cache memory ( 14 ) saved is, and a remaining portion of the packet ( 50 ) in a memory ( 26 ) Is stored, with the memory controller ( 16 ) Is coupled;and the memory controller ( 16 ) is coupled to a first block signal for the packet interface circuit ( 22A . 22B . 22C ) And a second block signal for others, with the intermediate ( 24 ) gecoupled devices to disposal represents, and wherein the initiation of memory transactions from the packet interface circuit ( 22A . 22B . 22C ) on the interconnect ( 24 ) In response to an activation of the first frame signal is locked, and wherein the other devices are configured such that they on the initiation of memory transactions the intermediate compound ( 24 ) In response to an activation the second block signal lock.
4
Device according to one of claims 1 to 3, wherein the packet interface ( 44A . 44B . 44C ) Ethernet Media Access Controller has.
5
Device according to one of claims 1 to 4, wherein the memory controller ( 16 ) Comprises an input queue having a plurality of entries for transactions and wherein the memory controller ( 16 ) Configured to is to activate the second block signal in response thereto, that a number of the plurality of entries which are available, less than a first number is.
8
Device according to one of claims 1 to 7, wherein the packet interface circuit ( 22A . 22B . 22C ) With the intermediate compound ( 24 ) Through a bus bridge ( 20 ) Is coupled.
9
carrier medium ( 300 ) For carrying one or more databases, which the device ( 10 ) According to one of claims 1 to 8 represents and by a program for the manufacture of hardware which the device ( 10 ) Which is readable.
10
A method comprising:receiving a package ( 50 ) From a packet interface ( 44A . 44B . 44C ) in a packet interface circuit ( 22A . 22B . 22C );and Transfer package ( 50 ) For storage on an interconnect ( 24 ), With a cache memory ( 14 ), A memory controller, ( 16 ) And a processor ( 12A . 12B ) coupled are;characterized in that the processor ( 12A . 12B ) the cache memory ( 14 ), The memory controller ( 16 ) and the packet interface circuit ( 22A . 22B . 22C ) are integrated into a single semiconductor substrate;in which the method further comprises the steps of: saving a the first portion of the packet ( 50 ) In the cache memory ( 14 ) In response to the receipt of the packet ( 50 ) from the packet interface ( 44A . 44B . 44C );Save a remaining portion of the packet ( 50 ) In a memory ( 26 ), With which the memory controller ( 16 ) coupled is;Providing by the memory controller ( 16 ) Of a first Block signal for the packet interface circuit ( 22A . 22B . 22C ) and a second block signal for other devices to the interconnect ( 24 ) are coupled;Disabling the initiation of memory transactions on the intermediate compound ( 24 ) From the packet interface circuit ( 22A . 22B . 22C ) In response to a Activation of the first block signal;and Locking the initiation memory transactions on the interconnect ( 24 ) by the other devices in response to an activation of the second block indication.
14
A computer program comprising machine or computer-readable Program elements, operable to configure a computer is to implement one of the methods of claims 10 to 13th
16
A computer program carrier medium ( 300 ) after Claim 15, wherein the carrier at least one of the following group of media comprising:signal including an optical, electronic or RF carrier signal, or magnetic disk or Elastic, solid state memory, an optical readable and / or recordable disc, a Compact Disk (CD) and a Digital Versatile Disk (DVD).

Independent claims8

124 paragraphs, as filed

0001The present invention relates to the field of processing and, in particular - but not exclusively - packet processing, Cross-linking, and a one-chip system.

0002The Networking of computer systems and other electronic devices continues at all levels of the network by more and more. computer systems in offices and sometimes even households are linked in local area networks (LANs). Geographically remote computer systems in wide area networks (WANs) are crosslinked. The Internet can be considered an example of a WAN be considered.

0003Typically communicating systems on a network with each other using of packets. The packet has a header and data. The header identifies the transmitting and receiving systems, and may contain other information such as the length of the packet having a packet type, etc.. Depending on the topology the network it may be necessary be that packets routed from the transmission system to the receiving system will. Routing generally involves one or more devices in the network, which check the package to to determine its destination and the packet to another device transferred to, until the packet arrives at the destination device. In addition, packets can be checked during the transfer, for features, such as Quality of Service (QoS), caching of Information, etc. available to put. Therefore, a powerful packet processing for performance the network as a whole is of crucial importance.

0004It will be described an exemplary packet processing system. On Processor, a cache memory, a memory controller and at least one Packet interface circuit can be integrated in a single integrated circuit. In an exemplary Implementation can take advantage of the integration the design to a tight coupling between the processor, the cache, the memory controller and to form the packet interface circuit. For example, interrupts are closely coupled to the processor and thereby have low latency to interrupt and accessing interrupt status / Cause Register possess with a low latency. The memory coherency among the devices can be maintained, the latency period, to a letter by a device for other devices visible is capable of reducing. The memory coherency and access low Latency to memory by the packet interface circuit may tight coupling for Descriptors available filters, which are used to store packet data.

0005at an exemplary embodiment (the are used in integrated or non-integrated systems can) is the packet interface circuit configured to a Allocation in the cache of a portion of a received packet cause. In particular, the part of bytes may include, of which is expected to be processed by the processors, while the remaining Packet data can be stored in memory. The processors can access Cache memory latencies for access impinge on the packet data, and a load of the cache memory through data, on which is not accessed by the processors may be avoided will.

0006at an exemplary embodiment (the are used in integrated or non-integrated systems can) may be configured to the memory controller that it Memory transactions selectively blocked. In particular, the Memory controller at least two block signals - one for the packet interface circuit and one for Other devices - implement. The block signals used to control the initiation of memory transactions be when the input queue of the memory controller the full state approaches. Particularly, the block signal for the other devices are activated when the queue still has other items (eg when a degree of filling although programmed by 75%, the threshold value at each level may be) to reduce the latency, the read memory transactions from the packet interface circuit (for reading packet data, to be transmitted to the external packet interface meet) can, when the queue fills with transactions. may in some embodiments a failure of the continuous transferring a full package lead to the external packet interface to the packet transfer fails and retransmission accomplished must become. By reducing the latency, the likelihood be reduced, that subsequent cache blocks of the Packet in the packet interface circuit if required are not available.

0007General speaking, an exemplary apparatus is contemplated, comprising: a processor with an intermediate compound coupled; a cache memory coupled to the intermediate compound coupled; a Spei chercontroller which coupled to the interconnect is; and a packet interface circuit which packets from a Package interface receives and causing the packets transmitted on the interconnect for storing will. The processor, the cache, the memory controller and the packet interface circuit are integrated into a single semiconductor substrate integrated. processorcan be programmed by the to process packet interface received packets.

0008Further an exemplary method is pulled into consideration. A package is received from a packet interface in a packet interface circuit. The packet is transmitted for storage on an interconnect, with a cache memory, a memory controller and a processor are coupled. The processor, the cache memory, the memory controller and the packet interface circuit are integrated into a single semiconductor substrate.

0009The font <patcit><text>EP 0498201</text></patcit> describes a relevant Adapter architecture with great Bandwidth, comprising a packet memory. Packets addressed to a Connection arrive are stored in the packet memory. A Packet memory interface stores a received packet along with a data header control information in the packet memory.

0010The font <patcit><text>US 5778414</text></patcit> describes a frame processing engine for receiving and processing of a Data frame with a header and a payload.

0011It An object of the present invention, an apparatus and a method for tight coupling of interrupts to the processor to disposal question about, with low latency to the interrupt and an access with low latency to interrupt status / Cause register.

0012These Object is achieved by a device as specified in the independent claim 1, a carrier medium (Claim 9), a computer program (claim 14) and a computer program carrier medium (Claim 15) dissolved.

0013advantageous embodiments the invention are defined in the dependent claims.

0014The following detailed Description is to be exemplary only and refers to the annexed Drawing of the following is a brief description is given.

0015<figref idrefs="S45">1</figref> is a block diagram of an embodiment a system.

0016<figref idrefs="S46">2</figref> is a block diagram of an embodiment a packet.

0017<figref idrefs="S46">3</figref> is a diagram showing the queue ( "targeting") of packet header data in the L2 cache memory illustrated.

0018<figref idrefs="S47">4</figref> is a timing diagram of an embodiment of the forestomach Erkens illustrates packet header data in the L2 cache memory.

0019<figref idrefs="S48">5</figref> is a block diagram of an embodiment descriptors one in <figref idrefs="S45">1</figref> Packet interface circuit shown.

0020<figref idrefs="S49">6</figref> is a flow chart illustrating operation of one embodiment of the in <figref idrefs="S45">1</figref> shown packet interface circuit during the Packet reception.

0021<figref idrefs="S50">7</figref> is a flow diagram illustrating the operation of an embodiment a processor which was interrupted.

0022<figref idrefs="S51">8</figref> is a block diagram of an embodiment various units <figref idrefs="S45">1</figref>which provided between the units for blocking the block signals Initiating transactions illustrated.

0023<figref idrefs="S52">9</figref> is a flow diagram illustrating the operation of an embodiment of the in <figref idrefs="S51">8</figref> shown memory controller to activate the block signals.

0024<figref idrefs="S53">10</figref> is a block diagram of an embodiment a carrier medium.

0025While the Invention to various modifications and alternative forms accessible, are concrete embodiments which by way of example shown in the drawing and will be described herein in detail. It is likely but of course be that the drawing and detailed description thereof is not are intended to limit the invention to the particular described to restrict the form, but on the contrary, it is intended that the invention encompasses all Modifications, equivalents and Alternative covers that within the scope of the present Invention fall.

0026Among with reference to <figref idrefs="S45">1</figref> there is shown a block diagram of one embodiment a system <figref>10</figref> shown. Other embodiments are possible and are contemplated. In the embodiment of<figref idrefs="S45">1</figref> has the system <figref>10</figref> processors <figref>12A</figref>-<figref>12B</figref>, An L2 cache memory <figref>14</figref>, a memory controllers <figref>16</figref>, An input / output (I / O) -Bridge <figref>20</figref>. a group of packet interface circuits <figref>22A</figref>-<figref>22C</figref> and an interrupt mapper <figref>28</figref> on. The system<figref>10</figref> can a bus <figref>24</figref> comprise the various components of the the system <figref>10</figref> connecting with each other. As in<figref idrefs="S45">1</figref> illustrated is, the processors are <figref>12A</figref>-<figref>12B</figref>, The L2 cache memory <figref>14</figref>. the memory controller <figref>16</figref> and the I / O bridge <figref>20</figref> each by bus <figref>24</figref> coupled. Thus, all processors <figref>12A</figref>-<figref>12B</figref>. the L2 cache memory <figref>14</figref>, The memory controller <figref>16</figref> and the I / O bridge <figref>20</figref> each an agent on the bus <figref>24</figref> for the illustrated embodiment be. The interrupt controller<figref>28</figref> is also by bus <figref>24</figref> coupled shown in order with the processors <figref>12A</figref>-<figref>12B</figref> to communicate (The processors <figref>12A</figref>-<figref>12B</figref> can eg Status / Cause register in the interrupt controller <figref>28</figref> read). The I / O bridge <figref>20</figref> is connected to the packet interface circuits <figref>22A</figref>-<figref>22C</figref> coupled, further with each physical layer circuits (PHYs) <figref>30A</figref>-<figref>30C</figref> coupled are. The interrupt mapper<figref>28</figref> is coupled to interrupts for processors <figref>12A</figref>-<figref>12B</figref> to disposal represents, and is further coupled to receive interrupt requests of the packet interface circuits <figref>22A</figref>-<figref>22C</figref> (the Coupling of the packet interface circuit <figref>22A</figref> is exemplary in <figref idrefs="S45">1</figref> illustrated) and from other devices in the system <figref>10</figref> (Not shown). The L2 cache memory<figref>14</figref> is to the memory controller <figref>16</figref> coupled with the further a memory <figref>26</figref> coupled. The packet interface circuit<figref>22A</figref> is in <figref idrefs="S45">1</figref> shown in more detail, and the packet interface circuits <figref>22B</figref>-<figref>22C</figref> can similarly configured be. In particular, the packet interface circuit<figref>22A</figref> in embodiment from <figref idrefs="S45">1</figref> a Tx / Rx control circuit <figref>32</figref>, a Rx FIFO <figref>34</figref>, A Tx FIFO <figref>36</figref>, A DMA controller <figref>38</figref> and one or more descriptor configuration registers <figref>40</figref> on, and a configuration register <figref>42</figref>Storing an L2 target value. The DMA controller <figref>38</figref> is connected to the Tx / Rx control circuit <figref>32</figref>. Rx FIFO <figref>34</figref>. the Tx FIFO <figref>36</figref>, The descriptor configuration registers <figref>40</figref> and the configuration register <figref>42</figref> coupled. The Tx / Rx control circuit<figref>32</figref> is further comprising the Tx FIFO <figref>36</figref> and the Rx FIFO <figref>34</figref> coupled.

0027at one implementation, the system <figref>10</figref> (Which in the illustrated embodiment by the dashed box is limited, which the processors <figref>12A</figref>-<figref>12B</figref>. L2 cache memory <figref>14</figref>, The memory controller <figref>16</figref>. the interrupt mapper <figref>28</figref>, The I / O bridge <figref>20</figref>, the Packet interface circuits <figref>22A</figref>-<figref>22C</figref> and the bus <figref>24</figref> wraps) in a single integrated circuit integrated into a one-chip system configuration be. The system<figref>10</figref> may be designed so that it is the uses integration by close coupling of the components to a powerful Packet processing available deliver. can Concretely processors <figref>12A</figref>-<figref>12B</figref>. the L2 cache memory <figref>14</figref>, The memory controller <figref>16</figref> and the packet interface circuits <figref>22A</figref>-<figref>22C</figref> (Through the I / O bridge <figref>20</figref>) are closely linked to received packets, process them, and the packets take (if necessary).

0028The tight coupling can manifest itself in several ways. For example can interrupts be tightly coupled. An I / O device (for example, the Packet interface circuits <figref>22A</figref>-<figref>22C</figref>) Can an interrupt Request, the (over the interrupt mapper <figref>28</figref>) On one of the processors <figref>12A</figref>-<figref>12B</figref> is mapped. The transfer the interrupt to the processor can be fast, because the signals can be transmitted with the clock frequency of the integrated circuit, which the system <figref>10</figref> comprises (in contrast to the intermediate compound of separate integrated circuits). If the processor<figref>12A</figref>-<figref>12B</figref> the Interrupt Service performs routine typically one or more status registers in the interrupt mapper <figref>28</figref> and or read the interrupting device. This status register read operations can a relatively low latency via the bus <figref>24</figref> and the I / O bridge <figref>20</figref> take place (for example, compared with a peripheral bus with high latency, such as PCI). Latency the status register read operations can, in some embodiments one or more orders of magnitude be less than that of a peripheral bus such as PCI.

0029A Another consequence of the tight coupling may be the use of hardware based memory coherency among be the integrated devices. The bus<figref>24</figref> can support coherent transactions, so that cached copies of data in the agent (and in the case of I / O bridge <figref>20</figref> in the coupled with this agent devices) be handled in a suitable manner, so that a read of certain data gets the latest update for the given data. The forced coherence can improve the close communication between the devices, as carried out by a device updates quickly for the Devices are visible, which read the updated data.

0030A Packet processing, in the system <figref>10</figref> in general take place as follows: A packet interface circuit <figref>22A</figref>-<figref>22C</figref> can a packet from the external interface <figref>44A</figref>-<figref>44C</figref> at the packet interface circuit (for example, the interface of the PHY circuits <figref>30A</figref>-<figref>30C</figref>) receive. The packet interface circuit is provided with one or more descriptors provided that data buffers in memory for storing packets specify, and selects a descriptor for the package. The packet interface circuit forwards the packet by DMA (Direct Memory Access) into the memory through the I / O bridge <figref>20</figref> and the memory controller <figref>16</figref>, If the packet is completely (Or if in some embodiments several packages completely are), the packet interface circuit may be one of the processors <figref>12A</figref>-<figref>12B</figref> interrupt. Alternatively, one or both of the processors <figref>12A</figref>-<figref>12B</figref> the status information monitor in the descriptors. The packet interface circuits can update the descriptors, when a packet completely is, and the processors <figref>12A</figref>-<figref>12B</figref> can they Akcapture tualisierung because the transaction to update the descriptor coherent is. processor<figref>12A</figref>-<figref>12B</figref> processed the package or packages and may, if desired, the package (by a the packet interface circuits <figref>22A</figref>-<figref>22C</figref> or another one retransmitted I / O device or interface). The system<figref>10</figref> can also generate packets in response to applications running on the processors <figref>12A</figref>-<figref>12B</figref> to run, and these packages may be transferred as will. To book a package through the packet interface circuits transmitted, can the processor <figref>12A</figref>-<figref>12B</figref> the Package in a desired from the Packet interface circuit used copy descriptor, and a status bit in the descriptor may be changed to indicate that the package for the transfer ready. Since the change coherent is, the packet interface circuit can receive the change quickly and can with passing the packet start.

0031The Tx / Rx control circuit <figref>32</figref> , a Media Access Controller (MAC) circuit according to the Ethernet specification exhibit. In particular, in one implementation, the Tx / Rx control circuit<figref>32</figref> the MAC part of the Institute of Electrical and Electronic Engineers (IEEE) specification 802.3 for rates of 10 megabits, 100 megabits / s and meet 1 Gigabit / s. at one implementation, the Tx / Rx control circuit <figref>32</figref> also configurable be to work as a generic packet receiver / transmitter. For example can be the beginning or end of packets using control signals on the external interface <figref>44A</figref>-<figref>44C</figref> be marked and between successive beginnings or ends trasmitted data can are treated as a package. Finally, an implementation can enable that the three packet interface circuits <figref>22A</figref>-<figref>22C</figref> as two 16-bit packet receiver / transmitter operate.

0032The Interface between each packet interface circuit <figref>22A</figref>-<figref>22C</figref> and external devices (numeral <figref>44A</figref>-<figref>44C</figref> in <figref idrefs="S45">1</figref>) can they Media Independent Interface (MII) or the Gigabit MII (GMII) interfaces to the PHY circuits <figref>30A</figref>-<figref>30C</figref> be. can as an alternative the external interface to be a generic packet interface, in either the top or bottom of packages using is marked by control signals. In yet another alternative can the three external interfaces as two wider packet interfaces be operated (eg the previously mentioned 16-bit interfaces). The packet interface circuits may be configurable (eg while the resetting) to the interface to operate in any of the aforementioned modes of operation.

0033The Packet interface circuit <figref>22A</figref> is an embodiment in <figref idrefs="S45">1</figref> in more detail illustrated. As already mentioned was able the other packet interface circuits <figref>22B</figref>-<figref>22C</figref> similarly Way be configured. The Tx / Rx control circuit<figref>32</figref> can the circuits for implementing an Ethernet MAC operation , and may further circuits for implementing the generic have packet interfaces as described previously. The Rx FIFO <figref>34</figref> is a first-in, first-out buffer for receiving packets from the interface <figref>44A</figref> to store the Memory. The Tx FIFO<figref>36</figref> is similarly a FIFO for Receiving packets from memory for transmission on the interface <figref>44A</figref>, In general, any of the FIFOs <figref>34</figref> and <figref>36</figref> a Plurality of entries for storing packet data having (the a header, the data payload can and include a trailer). The FIFOs may not big enough, to a package store at once, but can be used in general are to the system <figref>10</figref> of the line rate of the external interface <figref>44A</figref> by bus <figref>24</figref> buffering. While Packet data to the interface <figref>44A</figref> have been received, the Tx / Rx control circuit <figref>32</figref> the data is generally in the Rx FIFO <figref>34</figref>, additionally reads the Tx / Rx control circuit <figref>32</figref> Data from the Tx FIFO <figref>36</figref> for the transmission at the interface <figref>44A</figref> out.

0034Of the DMA controller <figref>38</figref> is provided to the packet data to and from memory (and / or the L2 cache memory <figref>14</figref>) transferred to. The descriptor Configurati register <figref>40</figref> locate the Descriptors that the packet interface circuit <figref>22A</figref> assigned are. Each descriptor includes a pointer to at least one data buffer in memory (a reserved area in the memory, of the Descriptor is allocated by software on the processors <figref>12A</figref>-<figref>12B</figref> running). Of the Descriptor may also include status information, the data buffer the correspond. The DMA controller manages data by DMA to the Tx FIFO<figref>36</figref> (for the transmission at the interface <figref>44A</figref>) From a data buffer, the a to be transmitted Package stores, and routes data via DMA from the Rx FIFO <figref>34</figref> to a data buffer in response to receiving packets. Of the DMA has one or more transactions on the bus <figref>24</figref> on. The bus <figref>24</figref> may be configured such that it comprises up to Cache block of data per transaction transmits, so that the number of Transactions per packet to the number of cache blocks in the Package depends. In general, the DMA controller <figref>38</figref> allow a cache block of packet data in the Rx FIFO <figref>34</figref> accumulates, and then a transaction on the bus <figref>24</figref> initiate, to transfer the cache block. When the last byte of a packet has been received and an incomplete cache block remains, , the DMA controller <figref>38</figref> transfer the incomplete cache block (Eg as a Wenitransmitted ger-than-cache block or first through Reading of the block, modifying the block with the received data, and writing the cache block back to memory). Similarly Example, if the Tx FIFO <figref>36</figref> having enough free entries, a cache memory block of a transmission packet contained in the store, the DMA controller <figref>38</figref> a transaction to Reading of the next Cache block of the packet and store the block in the Tx FIFO <figref>36</figref> initiate.

0035For received Packets, the Tx / Rx control circuit <figref>32</figref> configured be they in the Rx FIFO the beginning of the packet <figref>34</figref> displays. In one implementation, the Rx FIFO <figref>34</figref> for example Status information for have each entry. The status information may indicate, whether the entry of the start of a packet is. can as an alternative the Rx / Tx control circuit <figref>32</figref> directly to the DMA controller <figref>38</figref> communicate, to indicate which items are the beginning of a packet.

0036Of the DMA controller <figref>38</figref> can be configured in one embodiment as be that he, on the one part of a received packet storing in the L2 cache memory <figref>14</figref> prior notice. can Concretely desirable be, that the header of a packet in the L2 cache memory <figref>14</figref> is stored, while the data payload in the memory can be saved. processor<figref>12A</figref>-<figref>12B</figref>. which processes the packet may typically be on the header information operate, and can not operate on the data payload. If the header in the L2 cache memory <figref>14</figref> is stored, can be reduced the latency time, the processor of the <figref>12A</figref>-<figref>12B</figref> at the undergoes reading of the header. While require many packet processing functions access to only the header can, it is customary, when processing a packet data part of the payload also to process (eg, to more complex features such as web caching to try). Therefore, it may be desirable be also a part of the data payload of a packet in the L2 cache memory <figref>14</figref> to save. However, it may be desirable to save his, parts of the package, where not from the processors <figref>12A</figref>-<figref>12B</figref> in the Memory is operated, in order to prevent that the L2 cache memory <figref>14</figref> with data is loaded on the processors of the <figref>12A</figref>-<figref>12B</figref> not is accessed. Thus comprises the packet interface circuit<figref>22A</figref> the configuration register <figref>42</figref>Which with a size of the part is programmed at the beginning of a packet in the L2 cache memory <figref>14</figref> saved shall be. The remaining bytes can are stored in memory. Additional details regarding the Storing a portion of the packet in the L2 cache memory <figref>14</figref> will continue given below. It is noted that, although the size of the partial the packet, the L2 cache memory <figref>14</figref> saved is to be, in the illustrated embodiment in the configuration register <figref>42</figref> programmed may be that the size but as desired in other embodiments in the hardware can be set. The size can be used as a number of Bytes (which the DMA controller <figref>38</figref> convert into a number of cache blocks can, which include the bytes), a number of cache blocks, etc. be programmed.

0037As already mentioned was, it may be that the Tx FIFO <figref>36</figref> not big enough is to an entire packet for the transfer save. To transmit a packet, , the DMA controller <figref>38</figref> Transactions for reading can perform packet data from the memory and the data in the Tx FIFO <figref>36</figref> save. If the DMA controller<figref>38</figref> the Tx FIFO <figref>36</figref> fills, , the DMA controller <figref>38</figref> delay further transactions until the Tx / Rx control circuit <figref>32</figref> enough data out of the Tx FIFO <figref>36</figref> out transferred to accommodate to create a different cache block of the packet data. As soon as on the Ethernet begins a packet with the transmission (and if there is no packet collisions) will carry the packet continuously. If the packet can not be transmitted continuously, it from the recipient dropped and must be retransmitted will. Thus, it may be desirable, To prevent the Tx FIFO <figref>36</figref> empty, until the package fully transferred has been.

0038In some cases the combination of competition for the bus <figref>24</figref> and the Number of storage transactions in the memory controller <figref>16</figref> strung are, the DMA controller <figref>38</figref> delay long enough for the Tx FIFO <figref>36</figref> empty is. To this effect, at least partially to counteract the memory controller can <figref>16</figref> selectively block transactions from other agents when the input buffer the memory controller <figref>16</figref> the full state approaches. For example , the system <figref>10</figref> Apply a transaction blocking scheme, wherein the memory controller <figref>16</figref> at least two block signals used: one for the packet interface circuits <figref>22A</figref>-<figref>22C</figref> and another for the others Agents. The block signals are used, the placement of new Transactions to the memory controller block (for example, because the input buffer of the memory controller is full). A source, an activated block the signal from the memory controller <figref>16</figref> receives is prevented from transactions to the memory controller <figref>16</figref> to initiate. The source may inhibit arbitration for the bus when the source has only to perform memory transactions.

0039the Block signal to the other agent can be activated before the input buffer actually full (eg when the buffer to approximately 75% full is), whereby the other agents are held and the packet interface circuits <figref>22A</figref>-<figref>22C</figref> is made possible, the implementation of transactions to the memory controller <figref>16</figref> continue, when the memory controller <figref>16</figref> filled with transactions have to be processed. the Block signal for the packet interface circuits <figref>22A</figref>-<figref>22C</figref> turn can are activated when the input buffer is almost full. The Usage of separate block signals may have the effect that the maximum Latency time is reduced, which the packet interface circuits <figref>22A</figref>-<figref>22C</figref> learn when the memory controller <figref>16</figref> large numbers of requests receives. Further, since the other agents may inhibit arbitration if they only perform memory transactions can use the block signals have the effect that the packet interface circuits <figref>22A</figref>-<figref>22C</figref> is made possible, to bypass the arbitration mechanism and during such times more bus bandwidth on the bus <figref>24</figref> to obtain, as the case would be if it all other agents would be allowed to arbitrate. For example if the arbitration mechanism is a round robin priority process would (at the arbitration priority of an Agent is changed to lowest priority when the agent arbitration for the bus <figref>24</figref> wins, and the agent requesting the highest priority, the Arbitration wins), can the packet interface circuits <figref>22A</figref>-<figref>22C</figref> the granted bus once and then no longer be granted again until the bus every other arbitrating agent has been granted. This additional latency could Tx FIFO <figref>36</figref> further cause, before the final the transfer of a packet to be emptied. Since all other arbitrating agents (If they only have to perform memory transactions) an Arbitration stop in response to the block signal it from the memory controller received bypass the packet interface circuits <figref>22A</figref>-<figref>22C</figref> effective arbitration and can the Arbitration frequently to win.

0040at one embodiment , the DMA controller one or more transmit DMA channels and one or more receive DMA channels. The size of the part of the packet in the L2 cache memory <figref>14</figref> get saved to, may on a channel-by-channel basis be programmable If desired, each channel further with separate groups of descriptors about the Descriptor configuration registers <figref>40</figref> provided will.

0041It is noted that, while Ethernet MACs in the present embodiment be used and that other embodiments, any type support of packet interface can. For example, support those mentioned above embodiments in some modes a generic packet interface. Other can package interfaces X.25, Frame Relay, Asynchronous Transfer Mode (ATM), etc. include. Thus embodiments the system <figref>10</figref> considered that any type of packet interface circuit include. A packet interface circuit is a circuit, which is configured to packets from a packet interface receiving and storing the packets for processing. In various implementations may Packet interface packets based on specified filter criteria (Eg addresses), filter, remove overhead from the packet data, of the level of the packet interface circuit corresponds (for example, Check the MAC overhead), the package on error (eg, CRC error, size error etc.).

0042Of the Interrupt mapper <figref>28</figref> may use any mapping mechanism. In one embodiment, , the interrupt mapper <figref>28</figref> a mask bit and a map register for every Interrupt request and for each processor <figref>12A</figref>-<figref>12B</figref> exhibit. The mask bit indicates whether the interrupt for the specific processor <figref>12A</figref> or <figref>12B</figref>. is masked, and the map register indicates which of the interrupt lines on the particular processor <figref>12A</figref> or <figref>12B</figref> the Interrupt request is mapped. If an embodiment the processors <figref>12A</figref>-<figref>12B</figref> just has an interrupt line, the map registers can be deleted. Generally, when an interrupt request is received and is not masked, enabled the interrupt mapper <figref>28</figref> the interrupt signal according to the information in the map registers on the processor <figref>12A</figref> or <figref>12B</figref>,

0043The processors <figref>12A</figref>-<figref>12B</figref> can for each instruction set architecture be designed and can programs run, the for this instruction set architecture are written. Illustrative can instruction set architectures the MIPS instruction set architecture (including the MIPS-3D and MIPS MDMX application specific extensions), the Intel Corp. developed Instruction set architectures IA-32 or IA-64, PowerPC instruction set architecture, the Alpha instruction set architecture, the ARM instruction set architecture, or any other instruction set architecture. While the system <figref>10</figref>, this in <figref idrefs="S45">1</figref> shown is, having two processors, other embodiments may include as desired a processor or more than two processors.

0044Of the L2 cache <figref>14</figref> is a high speed cache memory. The L2 cache memory <figref>14</figref> becomes referred to as "L2" because processors <figref>12A</figref>-<figref>12B</figref> internal Using cache memory - Level 1 ( "L1") can. If the processors <figref>12A</figref>-<figref>12B</figref> no L1 cache are included, the L2 cache memory <figref>14</figref> be an L1 cache. Further, when multiple caching levels in processors <figref>12A</figref>-<figref>12B</figref> contain are, the L2 cache memory <figref>14</figref> a cache memory with be a level other than L2. The L2 cache memory<figref>14</figref> can Use any organization, including direct mapped, set-associative and fully associative organizations. In a particular implementation the L2 cache <figref>14</figref> a set associative cache memory (Generally N times, where N is an integer, although at a Implementing a 4-way cache memory can be used) with 32 bytes of cache blocks be. A set associative cache is a cache memory, of several sets is arranged, each set comprising two or more entries. A portion of the address (the "Index") is used, one of the sets select (Ie each encoding of the index selects another set). The entries in the selected Set are available, to the cache memory block store is accessed by the address. Each of entries in the set is called a "way" of the sentence. The part of the address, after removing the index (and the offset in the cache block) remains, is referred to as "tag" and is in each entry stored to the cache memory block in this Listing identify. The stored tags with the corresponding Tagteil the address of a memory transaction compared, to determine whether the memory transaction in the cache memory a hit or a miss, and is used to to choose way is detected at which the results (if a hit detected becomes).

0045Of the memory controllers <figref>16</figref> is configured in response to memory transactions on the bus <figref>24</figref> receive were, to the memory <figref>26</figref> access. The memory controller<figref>16</figref> receives a Hit signal from the L2 cache memory <figref>14</figref>, And if a hit in the L2 cache memory <figref>14</figref> for a memory transaction is detected, the memory controller responds <figref>16</figref> not in this memory transaction. Other embodiments can also L2 cache <figref>14</figref> do not have, and the memory controller <figref>16</figref> can respond to each memory transaction. If a failure of the L2 cache memory <figref>14</figref> is detected, or the memory transaction not in the cache is stored, the memory controller can <figref>16</figref> on memory <figref>26</figref> access to the read or write operation perform. The memory controller <figref>16</figref> may be designed to act on access any of a variety of types of memory. For example , the memory controller <figref>16</figref> for Synchronous Dynamic Random Access memory (SDRAM), and in particular for Double Data Rate (DDR) SDRAM be designed. As an alternative, the memory controller<figref>16</figref> for DRAM, Rambus DRAM (RDRAM), SRAM, or any other suitable storage device be designed.

0046The I / O bridge <figref>20</figref> connects the packet interface circuits <figref>22A</figref>-<figref>22C</figref> (and potentially with one or more other I / O devices or I / O interfaces) by bus <figref>24</figref>, The I / O Bridges<figref>20</figref> can to serve, the electrical load on the bus <figref>24</figref> to reduce. In general, leads the I / O bridge <figref>20</figref> Transactions on the bus <figref>24</figref> for the packet interface circuits <figref>22A</figref>-<figref>22C</figref> by and conducts transactions which packet interface circuits the <figref>22A</figref>-<figref>22C</figref> mark, by bus <figref>24</figref> in this packet interface circuit <figref>22A</figref>-<figref>22C</figref> continue. Similarly Example, the I / O bridge <figref>20</figref> Transactions to or from routes other I / O devices or interfaces with which it is coupled. In one implementation, a second I / O bridge (Not shown) a bridge to a PCI interface and to a Lightning Data Transport (LDT) I / O fabric be that of Advanced Micro Devices, Inc. designed. The LDT interface is as the HyperTransport interface designated, although LDT can be used herein. The PCI bus and the LDT fabric can outside the system <figref>10</figref> to connect PCI or LDT peripheral be provided devices. Other I / O devices / interfaces (including the packet interface circuits<figref>22A</figref>-<figref>22C</figref>) can of the I / O bridge <figref>20</figref> be bridged. The other I / O interfaces (Not shown) can one or more serial interfaces, Personal Computer Memory Card International Association, etc. comprise (PCMCIA) interfaces.

0047Of the bus <figref>24</figref> in one embodiment, a split transaction bus be. The bus<figref>24</figref> in one embodiment, a distributed arbitration method apply. In one embodiment, The bus may <figref>24</figref> be pipelined. The bus<figref>24</figref> can Apply any suitable signaling technique. For example in one embodiment, a Differentialsignalgebung for the high-speed signal transmission be used. Other embodiments can any other signaling technique (eg TTL, CMOS, GTL, HSTL etc.) apply.

0048It is noted that the system <figref>10</figref> (And in particular the processors <figref>12A</figref>-<figref>12B</figref>. the L2 cache memory <figref>14</figref>, The memory controller <figref>16</figref>. the packet interface circuits <figref>22A</figref>-<figref>22C</figref>, The I / O bridge <figref>20</figref>. the interrupt mapper <figref>26</figref> and the bus <figref>24</figref>) in the Although the above-described embodiment on a single integrated circuit as a one-chip system configuration can be integrated that but other embodiments one or more of the devices as separate integrated circuits can implement. In another configuration, the memory <figref>26</figref> also be integrated. Alternatively, one or more of the components be implemented as separate integrated circuits, or by desire can all Components may be separate integrated circuits. Any level of integration can be used.

0049It is noted that the illustrated embodiment, although a split Transaction bus with separate arbitration for the address and data buses applies, but that other embodiments Non-Split Transaction buses can apply that with a single Arbitration for Address and data are arbitrated, and / or a split transaction bus, wherein the data bus is not explicitly is arbitrated. Either a central arbitration or a distributed arbitration method can be used in accordance with the draft choice will. If desired, The bus may <figref>24</figref> not further be pipelined. While the present embodiment, a shared bus is used, in other embodiments be used any kind of interconnect (eg crossbar interconnects, Point-to-point connections in a ring, star, or any other topology, meshes, Cube o. the like.). In general, a Interconnect any type of communication medium.

0050It is noted that <figref idrefs="S45">1</figref> Although the packet interface circuits <figref>22A</figref>-<figref>22C</figref> as by means of the I / O bridge <figref>20A</figref> by bus <figref>24</figref> coupled illustrated, but that other embodiments, if desired, packet interface circuits <figref>22A</figref>-<figref>22C</figref> show can, the direct bus <figref>24</figref> are coupled. Further, the Number of packet interface circuits <figref>22A</figref>-<figref>22C</figref> ever be varied as desired from one to many.

0051Of the as used herein refers to a term transaction Communication between two or more agents on an interconnect (Eg bus <figref>24</figref>). An agent that initiated the transaction, may be the requesting agent or the source, and an agent, responsive to the transaction is a responding agent or an answering goal. The term "memory transaction" refers to a communication between a device and the memory system. The memory transaction comprises an address a memory location in the memory identified. In the illustrated embodiment, the memory transaction is on the bus <figref>24</figref> to the memory controller <figref>16</figref> transfer (And may of the L2 cache memory <figref>14</figref> at Location of the memory controller <figref>16</figref> are processed). Memory transactions can Read transactions (a transfer of data from memory to the device) and write transactions (a transfer of data from the device include, for memory). More generally, a read transaction a transfer of data from a target of the transaction to the source (Or the Ini Tiator) be the transaction, and a write transaction , a transfer of data from a source of the transaction to be the target of the transaction.

0052Among with reference to <figref idrefs="S46">2</figref> there is shown a block diagram of an exemplary package <figref>50</figref> shown. Other embodiments are possible and are contemplated. In the embodiment of<figref idrefs="S46">2</figref> includes the package <figref>50</figref> a header <figref>52</figref>, A data payload <figref>54</figref> and an optional trailer <figref>56</figref>, Each of the header<figref>52</figref>. the data payload <figref>54</figref> and the trailer <figref>56</figref> can any having number of bytes. The header<figref>52</figref> is in a exploded view of shown an Ethernet packet being used to a transport control protocol / Internet protocol (TCP / IP) packet to be transmitted, and includes an Ethernet header <figref>58</figref>, An IP header <figref>60</figref> and a TCP header <figref>62</figref>,

0053Of the header <figref>52</figref> describes the package <figref>50</figref>So that the receiver of the Package can interpret it correctly. For example, the header of one or more of the following exhibit: source and destination addresses for the Package, the size of the package, the size of the header, and status / control information for the packet. The status / control information can error checking, Priority information, Package type include so.

0054As is illustrated in the exploded view, can the header <figref>52</figref> actually several include header, the different layers of the networking protocol Suite correspond. In general, additional in each layer Information is used to describe the packet. The additional Information encapsulate the information from the higher layers, so that a communication on this layer, the format of the information of the higher Layers do not need to know.

0055at the example of <figref idrefs="S46">2</figref> includes the header <figref>52</figref> the Ethernet header <figref>58</figref> with 14 bytes, the IP header <figref>60</figref> With 20 bytes, and the TCP header <figref>62</figref> with 20 bytes. Therefore, the header <figref>52</figref> 54 bytes long in this example. The Ethernet header <figref>58</figref> can two 6byte Ethernet addresses (A source address and a destination address) and a length field comprise two bytes. The IP header<figref>60</figref> can two 4 byte IP addresses (Again, source and destination address) and a variety of other information including the length both the header and the IP packet, an IP version number, a Type of Service field, an identification field, fragment offset, a time to live field, a protocol field and a header checksum exhibit. Optionally additional Radio buttons can be provided (which the size of the IP header <figref>60</figref> enlarge). Of the TCP header <figref>62</figref> can source and destination port numbers, a Sequence number, which the packet in a sequence of Paketene identified a confirmation number, a header length, a set of flag bits, a checksum, have an urgent pointer and a window size. The TCP header may, if desired, in turn optionally be expanded to additional options to contain a package.

0056ever about the spyware Packet processing, the processor <figref>12A</figref> or <figref>12B</figref> at a part of the header, the entire header, or even the entire operate header and a part of the data payload. If the parcel For example, simply routed to an Ethernet, can at the Ethernet header <figref>58</figref> surgery. If the packet on is routed to an IP-network (ie, the system <figref>10</figref> is part an IP router), both the Ethernet header to <figref>58</figref> as also to the IP header <figref>60</figref> be operated on, or only on the IP header <figref>60</figref> can be operated, etc.

0057The data payload <figref>54</figref> are transferred to the packet Data. In some packages, the data payload<figref>54</figref> not be included. For example, some TCP packets acknowledgment packets being sent in order to acknowledge the receipt of a previous packet. On Such a packet need not contain data.

0058Of the optional trailer <figref>56</figref> may be similar to the header <figref>52</figref> additional Package description information included. For example, Ethernet packets a cyclical redundancy check (CRC) value in the trailer <figref>56</figref> contain.

0059It is noted that the illustrated packet <figref>50</figref> indeed an Ethernet packet is carrying a TCP / IP packet, but that other Ethernet packets can carry other types of data. Further, other types of packets encapsulate the TCP / IP packet.

0060It is noted that the example of <figref idrefs="S46">3</figref> Although the entire header in the L2 cache memory <figref>14</figref> and the entire data payload in the memory <figref>26</figref> illustrates but that other examples of a portion of the L2 cache memory <figref>14</figref> saved headers may have (For example, if this part is not included in the L2 count, which in the packet interface circuits <figref>22A</figref>-<figref>22C</figref> is programmed) or some of the L2 cache memory <figref>14</figref> stored data (For example if it is expected that the data is processed, is the header of the packet is smaller than other packets, or the data located in the same cache block as the header).

0061Among with reference to <figref idrefs="S46">3</figref> there is shown a block diagram of shown, the example of a the queue of the packet header in the L2 cache memory <figref>14</figref> illustrated. In <figref idrefs="S46">3</figref> are the processor <figref>12A</figref>, The L2 cache memory <figref>14</figref>. the memory <figref>26</figref> and the packet interface circuit <figref>22A</figref> illustrated. It Arrows are used to control the flow of information between the in <figref idrefs="S46">3</figref> blocks shown to illustrate. Two cache block storage locations<figref>70</figref> and <figref>72</figref> are in the L2 cache memory <figref>14</figref> illustrates and two locations (the size of a cache block) <figref>74</figref> and <figref>76</figref> are in the memory <figref>26</figref> illustrated.

0062at the example of <figref idrefs="S46">3</figref> receives the packet interface circuit <figref>22A</figref> on Packet sent from the system <figref>10</figref> to be processed. The Packet interface circuit <figref>22A</figref> in this example is to programmed (using the configuration register <figref>42</figref>) the first two cache blocks of the packet in the L2 cache memory <figref>14</figref> (and the remaining blocks of the packet in the memory <figref>26</figref>) save. If the first two cache blocks transmit the packet will cause the packet interface circuit <figref>22A</figref> therefore, that the cache blocks in the L2 cache memory <figref>14</figref> (Arrow <figref>78</figref>) get saved. Generally, the packet interface circuit provides<figref>22A</figref> informations To display in the transactions, which cache blocks in the L2 cache memory <figref>14</figref> saved to be. An example is below in<figref idrefs="S47">4</figref> shown. The L2 cache memory <figref>14</figref> stores the blocks (shown as "headers" <figref idrefs="S46">3</figref>).

0063When transferring the rest Cache memory blocks of the packet is the packet interface circuit <figref>22A</figref> not that the cache blocks in the L2 cache memory (Arrow <figref>80</figref>) Should be saved. The memory<figref>26</figref> stores the remaining blocks (Shown as "Data" in <figref idrefs="S46">3</figref>).

0064in the Following transfer of the packet to memory, the packet interface circuit <figref>22A</figref> the processor <figref>12A</figref> interrupt. Alternatively, the packet interface circuit<figref>22A</figref> the Update the Package corresponding descriptor to indicate that the packet is complete; and the processor <figref>12A</figref> can query the descriptor to to detect the update. In each of these cases, the processor <figref>12A</figref> the packet processing. Since the part of the packet, which is expected that operates the processor to it, <figref>14</figref> during the DMA of packet by the packet interface circuit <figref>22A</figref> in the L2 cache memory is stored, the processor can <figref>12A</figref> to L2 cache hit for the Access to the packet data hit (arrow <figref>82</figref>). Latency the access can thus be shortened be what shorter to a total required time for perform the processing of the packet can.

0065As already mentioned was delivers the packet interface circuit <figref>22A</figref> informations both Transactions for transferring a received packet to the memory, which indicate which Cache memory blocks in the L2 cache memory <figref>14</figref> to be stored and what not. Concretely speaking, a transmitted during the address phase of the transaction Control signal (hereinafter referred to as L2CA) as the indication be used. Other embodiments can command information or use any other signaling to transfer the indication, or can the statement while transfer of other phases of the transaction. While the address phase of the first N transactions of a packet (which N by the value in the configuration register <figref>42</figref> certainly is), the packet interface circuit <figref>22A</figref> the L2CA signal Enable to the L2 cache memory <figref>14</figref> to cause you to store the data. During the remaining transactions, the Packet interface circuit <figref>22A</figref> disable L2CA signal.

0066Of the L2 cache <figref>14</figref> responds to the L2CA signal for a transaction as follows: If the cache memory block a failure in the L2 cache memory <figref>14</figref> is and the L2CA signal is asserted, the L2 cache has <figref>14</figref> a Cache block storage location in order to store the cache block. In general, the allocation selecting a cache block storage location for storing the block, removing the currently therein stored block (if any), and the updating of Cache block storage location include with the cache memory block. In one embodiment, , the memory controller <figref>16</figref> memory <figref>26</figref> not with the L2 cache memory <figref>14</figref> Update allocated cache blocks, although the memory <figref>26</figref> in other embodiments can also be updated. On the other hand, the cache memory block a failure in the L2 cache memory <figref>14</figref> is and the L2CA signal is deactivated is, the L2 cache memory <figref>14</figref> no memory for the cache memory block to assign. The cache memory block, in this case from the memory controller<figref>16</figref> just In the storage room <figref>26</figref> get saved. Thus, a cache load when data is avoided, in which it is not likely that by the processor <figref>12A</figref>-<figref>12B</figref> during the Processing of the packet is accessed. If a cache memory block Results in the L2 cache memory <figref>14</figref> is, in the present embodiment the the results Performing cache block storage location with during the transaction transferred Dates updated (regardless whether the L2CA signal is on or off).

0067It it is noted that a signal can be defined as active, when it is driven at a first voltage, the logic for a one is, or as an alternative, when set to a second voltage is driven, the for a logical zero is. The signal can be defined as disabled be when it is driven at the level of the activated to the Level opposite. In embodiments in which a Differentialsignalgebung is used, the signal is activated when a first lower of the differential pair than the second, and is deactivated when the second of the differential pair lower than the first.

0068Among with reference to <figref idrefs="S47">4</figref> there is shown a timing chart shown, illustrating several address phases of transactions, by the packet interface circuit <figref>22A</figref> (Specifically from the DMA controller <figref>38</figref> through the I / O bridge <figref>20</figref>) be performed, to transmit a packet. There are shown a plurality of clock cycles of the clock signal CLK which the bus <figref>24</figref> equivalent. Each clock cycle is at the top of<figref idrefs="S47">4</figref> named (CLK0, CLK1 etc.). Phases of clock cycles are broken by vertical Lines limited.

0069<figref idrefs="S47">4</figref> illustrated an example in which the first five cache blocks of a transfer the received packet to the memory / L2 cache will. The while the address periods of five Transactions transferred Addresses are horizontal from the label "Addr" illustrates. Of the command for the transaction is horizontal from the label "CMD" is illustrated. For every Transaction is the command post. can Concretely the command be a letter Devalidieren, thereby causing is that all copies of the cached cache block be invalidates (except in the L2 cache memory <figref>14</figref>Which operates to the latency the memory <figref>26</figref> to decrease and no specific associated Agen th). If cached copies of Cache block exist in agent caches are the data out of date because the data is overwritten with the packet data will. The L2CA signal finally horizontal illustrated by the label L2CA. The L2CA signal in this embodiment as active high and disabled illustrates low.

0070at this example, the packet interface circuit <figref>22A</figref> to programmed (via the configuration register <figref>42</figref>), The first two cache blocks of a received packet in the L2 cache memory <figref>14</figref> save. Thus activated, the packet interface circuit <figref>22A</figref> the L2CA signal for the first two transactions to the received packet on the bus <figref>24</figref> transferred to, and disables the L2CA signal for other transactions. It is noted that the packet interface circuit <figref>22A</figref> programmed may be any of the cache blocks in the L2 cache memory, the cache blocks, or more than two the cache blocks to store, according to the part of the packet, which is expected that by the processors <figref>12A</figref>-<figref>12B</figref> processed is.

0071The first transaction is the first cache block of the packet (Clock cycle CLK0). The address of the transaction is the address of the Data buffer of in response to the receipt of the packet selected the descriptor is (address "A" in <figref idrefs="S47">4</figref> - Numeral <figref>90</figref>). Since the first transaction is the first cache block of the packet is additionally the L2CA signal for This transaction enabled (Numeral <figref>92</figref>). The L2 cache memory<figref>14</figref> has a cache block storage location storing the addressed by address "A" cache block for, if the address is a bust, or updates the Cache block if the address is a hit. Similarly Way, the second transaction is the second cache block of the packet, and therefore directly to the first cache memory block of the packet stored in the memory space. Therefore, the address the second transaction, the address "A + 1" where "A + 1" is the address "A" plus a cache memory block. The second transaction is in clock cycle CLK1 shown (Numeral <figref>94</figref>). The L2CA signal is also for the second transaction is activated, thereby causing the Block in the L2 cache memory <figref>14</figref> saved is.

0072The remaining three Transactions to consecutive cache blocks (addresses "A + 2", "A + 3", and "A + 4" at reference numerals <figref>98</figref>. <figref>100</figref> or. <figref>102</figref>) are not in the L2 cache memory <figref>14</figref> be assigned to. Thus, the L2CA signal for this Transactions disabled (Numeral <figref>104</figref>. <figref>106</figref> or. <figref>108</figref>). If the addresses randomly a hit in the L2 cache memory <figref>14</figref> represent, updated the L2 cache <figref>14</figref> With the cache memory block. If the addresses but a bust in represent L2 cache, the cache memory blocks are the memory controller <figref>16</figref> In the storage room <figref>26</figref> stored, and the L2 cache memory <figref>14</figref> is not updated. During the L2 cache the cache block for a cache hit updated if the L2CA signal is deasserted, other can Embodiments, if desired, the cache memory block devalidieren if the L2CA signal is deactivated is.

0073It is noted that address phases in the illustrated embodiment while a phase of the clock signal CLK occur (eg during high phase of the clock signal, although the low phase used can be). In the illustrated embodiment, signals may on the bus <figref>24</figref> while a phase of the clock cycle to be driven, and the other phase may be idle. More specifically, the other phase, in one embodiment be used to precharge the differential signal lines. Thus, the signal lines in response to an edge of the clock signal CLK (eg, the rising edge) and driving can Scan signal lines on the falling edge of the response. Other embodiments can driving as many external bus in response to the same edge and scan, or can driving on both edges of the clock and scan, such as source synchronous Designs. The L2CA signal is during the low phase of the clock in <figref idrefs="S47">4</figref> polka dots shown to indicate that during is this stage is not actively driven (and to be preloaded can).

0074It is noted that in <figref idrefs="S47">4</figref> Although successive Clock cycles to transfer of cache memory blocks a package is shown, however, that other transactions in general between each cache block transaction (eg, from other Agents on the bus <figref>24</figref>may occur). Further delays occur between cache block transactions, while the consecutive cache blocks of the packet interface circuit <figref>22A</figref> receive will. Thus, the transactions need not sequentially take place, as in <figref idrefs="S47">4</figref> is shown.

0075After this in the <figref idrefs="S47">4</figref> complete illustrated five transactions are (assuming no additional transactions and that the Addresses A, A + 1, A + 2, A + 3 and A + 4 to different cache block storage locations in the L2 cache memory <figref>14</figref> binders) would Then, the addresses A and A + 1 corresponding cache blocks in the cache memory stored. The address A + 2, A + 3 and A + 4 can in Cache will be stored when in front of the clock cycle CLK0 Cache were stored, but in response to the in <figref idrefs="S47">4</figref> illustrated Transactions were not assigned.

0076Among with reference to <figref idrefs="S48">5</figref> is a block diagram of a embodiment a set of descriptors shown, a DMA controller <figref>38</figref> assigned is. Other embodiments are possible and are contemplated. In<figref idrefs="S48">5</figref> are configuration register <figref>40A</figref>. <figref>40B</figref>. <figref>40C</figref> and <figref>40D</figref> shown and a set of descriptors <figref>110</figref> (including the descriptors <figref>110A</figref>. <figref>110B</figref>. <figref>110C</figref>. <figref>110D</figref> and <figref>110E</figref>). The descriptor <figref>110D</figref> is shown in more detail. It is also from the descriptor <figref>110D</figref> Displayed data buffer <figref>112</figref> in <figref idrefs="S48">5</figref> shown.

0077The configuration register <figref>40A</figref>-<figref>40D</figref> can be part the in <figref idrefs="S45">1</figref> shown configuration register <figref>40</figref> be. The configuration register <figref>40A</figref> stores a Deskriptorbasisadresse, what a Speicherberich indicating the descriptors <figref>110</figref> stores. The configuration register <figref>40B</figref> stores a Deskriptorzählwert, indicating the total number of descriptors. In combination with the Deskriptorbasisadresse can Deskriptorzählwert the extent of the memory area specify which stores the descriptors. In this embodiment, the descriptors are arranged as a ring. The next descriptor in the ring from the packet interface circuit <figref>22A</figref> used is, by the current is Descriptor specified in the configuration register <figref>40C</figref> saved is. A current Deskriptorzählwert (Of the Configuration tab, <figref>40D</figref> is stored) is the number of descriptors on that are currently available for use by the Packet interface circuit <figref>22A</figref> Are available. The packet interface circuit<figref>22A</figref> can not use descriptors, apart from the descriptors between the current Descriptor and the value specified by the current Deskriptorzählwert Descriptor.

0078in the Generally, the ring of descriptors <figref>110</figref> by software are created on the system <figref>10</figref> is performed, and, the packet interface circuit <figref>22A</figref> by updating the configuration register <figref>40</figref> be assigned to. Similar rings can of descriptors the other packet interface circuits <figref>22B</figref>-<figref>22C</figref> assigned will. A separate set of descriptors<figref>110</figref> can each DMA channel within each packet interface circuits <figref>22A</figref>-<figref>22C</figref> be assigned to. For example, in one embodiment, each DMA controller <figref>38</figref> two DMA receive channels (For transferring of received packets to memory) and two transmit DMA channels (for transmitting packets from the memory to the packet interface circuit) exhibit. Thus sets of similar configuration registers the configuration registers <figref>40A</figref>-<figref>40D</figref> for each DMA channel be included.

0079Of the descriptor <figref>110D</figref> is shown in more detail, and other Descriptors can be similar. Of the descriptor <figref>110D</figref> has a flag (Numeral <figref>114</figref>) a packet size (Numeral <figref>116</figref>) a data buffer size (Numeral <figref>118</figref>) and a data buffer pointer (Numeral <figref>120</figref>) on. Of the Data buffer pointer <figref>120</figref> is the address of a data buffer, in which the packet data is to be stored. The data buffer size<figref>118</figref> is the size of the data buffer. The packet size <figref>116</figref> is the size of the in the data buffer <figref>112</figref> stored packet (and possibly in data buffers following descriptors, if the packet size is greater than the data buffer size is, as described below in more detail). The Flag<figref>114</figref> is an indication of whether a packet in said data buffer <figref>112</figref> or not. For example can the flag <figref>114</figref> be a bit indicating that the descriptor a packet storing, if it is set, and indicating that the Descriptor stores no packet if it is not set. As alternative can the set and unset state of the bit on the opposite Way be defined.

0080It is noted that, although the illustrated embodiment a ring of descriptors <figref>110</figref> shows, but that other embodiments the descriptors may order in other ways. For example, a shortcut list use of descriptors. In such an embodiment can Deskriptorbasisadresse in the configuration register <figref>40A</figref> the head the shortcut list be, and the Deskriptorzählwert in the configuration register <figref>40B</figref> the number of descriptors be in the link list. The current Descriptor in the configuration register <figref>40C</figref> can on the current Descriptor in the linked list point, and the current Deskriptorzählwert in the configuration register <figref>40D</figref> can, beginning with the current Descriptor, the number of descriptors in the linked list indicate that for use by the packet interface circuit <figref>22A</figref> Are available. Since the members of a linked list need not be stored in adjacent addresses can An additional descriptors Pointer field (in addition to the in <figref idrefs="S48">5</figref> shown data buffer pointer <figref>120</figref>) exhibit to the next to assign descriptor. In a specific embodiment, the system support both the ring and the Verknüpfungslistenmodi. at such an embodiment, can be used to the second pointer, in the ring mode to a to have second data buffer (ie, the descriptors may each two data buffers specify).

0081It is noted that depending on desire in addition to the <figref idrefs="S48">5</figref> shown Information, a variety of other information in the descriptors <figref>110</figref> contain can be. For example, Status information while reception detected errors, etc. for received packets be.

0082Among with reference to <figref idrefs="S49">6</figref> Next is shown as a flow diagram, the operation of the packet interface circuit <figref>22A</figref> (or of each of the other packet interface circuits <figref>22B</figref>-<figref>22C</figref>) while the reception of a packet from the external packet interface for Processing in the system <figref>10</figref> illustrated. Other embodiments are possible and are contemplated. In the<figref idrefs="S49">6</figref> shown blocks are for a simplified understanding illustrated in a particular order, but may vary as desired, any other sequence used.

0083The Packet interface circuit <figref>22A</figref> detects whether a start a packet to the packet interface <figref>44A</figref> Will be received or not (decision block <figref>130</figref>). If no initial a packet is received, the packet reception logic circuit be idle. Depending on the mode, a beginning of a Packet are recorded in a variety of ways. If the packet interface circuit<figref>22A</figref> as Ethernet MAC works, the start of a packet according to the Ethernet specification is detected. If the generic packet interface is used, control signals, which the beginning of the packet (or the end of the previous packet) Mark can be used for detecting the beginning of a packet.

0084If a start of a packet is received, selects the packet interface circuit <figref>22A</figref> (especially the DMA controller <figref>38</figref>) The next descriptor <figref>110</figref>, at to transmit the packet (block <figref>132</figref>). The specified by the current descriptor Descriptor is selected. The packet interface circuit <figref>22A</figref> collects packet bytes in Rx FIFO <figref>34</figref> (Block <figref>134</figref>) Until at least one cache block for transmission ready (decision block <figref>136</figref>). If desired, the packet interface circuit <figref>22A</figref> in some embodiments wait until more than one cache block is ready for transmission.

0085If a cache memory block for the transfer is ready to transmit, the DMA controller <figref>38</figref> the Cache block to the memory <figref>26</figref> or the L2 cache memory <figref>14</figref>, Specifically, the DMA controller determines whether the in the configuration register <figref>42</figref> specified Number of cache blocks (Measured from the beginning of the packet) has been transferred or not in terms of the package that is received (decision block <figref>138</figref>). The DMA controller <figref>38</figref> the number of transmitted blocks pursue a specific DMA receive channel to determine whether transfer the number of indicated cache memory blocks already was, and is the count comparing the specified number of blocks. As alternative , the DMA controller <figref>38</figref> a counter with the number of specified Cache memory blocks initialize and the counter decrement while transmitted blocks will.

0086If the number of transmitted Cache memory blocks still less than or equal to the L2 count (decision block <figref>138</figref>), Transfers, the DMA controller <figref>38</figref> the Cache memory block is activated in a transaction with the L2CA signal (Block <figref>140</figref>). On the other hand, the number of transferred blocks greater than the L2 count is, transfers, the DMA controller the cache block in a transaction with the L2CA signal disabled (Block <figref>142</figref>).

0087The Packet interface circuit <figref>22A</figref> is also configured the capture end of the packet (decision block <figref>144</figref>). The package may end by the length the package can be specified (in Ethernet packets in the packet indicated) or can be specified by control signals (such as in the generic packet interface). When the end of the packet is not detected, the packet interface circuit <figref>22A</figref> determine, whether the end of the data buffer has been reached (decision block <figref>146</figref>). The data buffer specified by the descriptors or can not big enough be to contain the entire packet. When the data buffer so as big as the biggest package are, the block of the decision <figref>146</figref> illustrated exam be omitted. When the end of the data buffer has been reached is (as indicated by the data buffer size <figref>118</figref> in is the descriptor specified), the DMA controller <figref>38</figref> the next descriptor choose and begin to store the packet in the data buffer, the specified by this descriptor (block <figref>132</figref>). If On the other hand, the end of the current Data buffer has not been reached, the packet interface circuit <figref>22A</figref> With the current continue data buffer.

0088If the end of the packet has been reached, the DMA controller <figref>38</figref> the update descriptor (block <figref>148</figref>). Concretely , the DMA controller <figref>38</figref> the packet size <figref>116</figref> Update to the size of the package specify in the data buffer indicated by the descriptor. In addition, the DMA controller <figref>38</figref> the flag bit <figref>114</figref> put in order indicate that the packet is available for processing in the data buffer. As already mentioned was a package in some embodiments, depending on the size of a occupy or more data buffers that one or more descriptors correspond. In one embodiment, , the first descriptor for voted the parcel be, is updated if more than one descriptor is used is.

0089Of the DMA controller <figref>38</figref> in addition the configuration register <figref>40C</figref> update, to the next unused descriptor specify and can the current Deskriptorzählwert in the configuration register <figref>40D</figref> decrement to the use of of one or more descriptors to reflect for storing the packet. If the current Deskriptorzählwert Is zero (or below a threshold value, depending on the embodiment), , the DMA controller <figref>38</figref> the processor interrupt, thus more descriptors the use to be validated.

0090Optional the packet interface circuit <figref>22A</figref> a processor interrupt (block <figref>150</figref>). The processor may thus in Apprised whothe that the packet is available for processing. Alternatively, the processors query the descriptors periodically what being grasped by DMA receive channels corresponds to whether the flag bit is set.

0091It is noted that the packet interface circuit <figref>22A</figref> certain error checks perform on received packets can (eg detection of Paketkolli sion of the received packet, CRC error, etc.), which in <figref idrefs="S49">6</figref> is not illustrated. If a packet error is detected, the packet can be dropped be, and the error can be (in some embodiments) logged.

0092It is noted that the detection of packet start and end, and the accumulation of packet data from the Tx / Rx control circuit <figref>32</figref> independent and can be carried out parallel to the Deskriptorverwaltung and the transfer of blocks, of the DMA controller <figref>38</figref> can be treated. The in <figref idrefs="S49">6</figref> blocks shown can thus a simplified view for illustrating the L2 cache allocation be.

0093Among with reference to <figref idrefs="S50">7</figref> next is a flow chart for Illustrating the operation of a processor <figref>12A</figref>-<figref>12B</figref> in the Response shown at his interruption. Other embodiments are possible and are contemplated. It is noted that the blocks of<figref idrefs="S50">7</figref> in Software can be implemented, the processor on the <figref>12A</figref>-<figref>12B</figref> running (eg an interrupt service routine), as hardware, or a combination of these. While the blocks shown for a simplified understanding are illustrated in a particular sequence, other sequences be used.

0094Of the Processor reads one or more resources in the system <figref>10</figref>. to determine the source of the interrupt (block <figref>160</figref>). For example , the interrupt mapper <figref>28</figref> a source register include, indicating the source of an interrupt. If the source is not a Packet interface circuit (PIC or in <figref idrefs="S50">7</figref>) (Decision block <figref>162</figref>) , the processor within the interrupt processing can on any arbitrary way to proceed (block <figref>164</figref>). If the source a packet interface circuit, the processor may further read a packet interface circuit cause register to the cause of to determine the interrupt (block <figref>166</figref>). The cause register could depending on the request in the interrupt mapper <figref>28</figref> or in the packet interface circuit <figref>22A</figref>-<figref>22C</figref> . are

0095If the cause of the interrupt is different than that one or more packets for processing willing (decision block <figref>168</figref>), The processor can the other causes in any manner to process (block <figref>170</figref>). One cause may be, for example, that the packet interface circuit all available has used descriptors (or less than a threshold number descriptors use left Has). The processor can assign data buffer descriptors in Group of descriptors that the packet interface circuit (and the DMA channel in the packet interface circuit) are assigned to the data buffer exhibit, and the configuration register <figref>40</figref> update, the assigned data buffer and updated descriptors to reflect. In one embodiment, is the current Deskriptorzählwert updated by the number of newly added descriptors in the configuration register <figref>40D</figref> written is. The DMA controller<figref>38</figref> the number in response to the letter to the current Deskriptorzählwert Add. A Variety of other causes of an interrupt by the packet interface circuits can to support request will.

0096If the cause of the interrupt is that one or more packets are ready, the Read processor the descriptor storing the packet (or the Beginning of the packet stores, if Date npuffer of more than one descriptor are used to store the packet) to the address the beginning to obtain the packet (block <figref>172</figref>). For example the processor configuration register <figref>40C</figref> read and in the reverse direction Search through the ring after the first descriptor, which set a Flagbit <figref>114</figref> having. Alternatively, the packet interface circuit prepare the descriptor of the first for processing deliver descriptor in a register which is read by the processor can. In another alternative, the processor may again the Deskriptorbasisadresse register <figref>40A</figref> Read and forward Search until a descriptor having a set flag bit <figref>114</figref> localized is. The processor may localized by the descriptor package process (block <figref>174</figref>). If the L2CA signal used was a part of the package during the transfer from the packet interface circuit to the L2 cache memory <figref>14</figref>/Memory <figref>26</figref> in L2 cache memory <figref>14</figref> assign, the processor can L2 cache on Results for the processed part of the package encounter what the latency of may reduce access to the packet (and therefore also the performance of can improve the packet processing).

0097As already mentioned was, when a certain packet interface circuit <figref>22A</figref>-<figref>22C</figref> a package of the system <figref>10</figref> transmits to the packet interface, can the transfer the package may fail (the package may fall by the receiver left be and retransmission require) if the packet to the packet interfacestelle not transmitted continuously is. A possible source a delay in transmission of the package, which can lead to a failure in the transmission, is the latency in reading the packet from memory. The Latency may be partly attributable to transactions that of other agents be initiated (eg the processors <figref>12A</figref>-<figref>12B</figref>. the L2 cache memory <figref>14</figref> to the Removing back copies, or read / write transactions from other I / O devices). Further can the packet interface circuits during periods of strong Competition for the bus <figref>24</figref> by the round-robin priority method for the delayed Arbitration will. The memory controller<figref>16</figref> , another block signal for the Packet interface circuits <figref>22A</figref>-<figref>22C</figref> as for the other deploy agents to the problem, the dropping of transferred mitigate packages. More specifically, the block signals at a embodiment Part of a general blocking scheme for flow control on the bus <figref>24</figref> be like in <figref idrefs="S51">8</figref> illustrated is. Alternatively, other embodiments, if desired, block signals only by the memory controller <figref>16</figref> to implement. A description the general blocking scheme follows.

0098in the generally, processors <figref>12A</figref>-<figref>12B</figref>. the L2 cache memory <figref>14</figref> and / or the I / O bridge <figref>20</figref> transactions on the bus <figref>24</figref> initiate. The system<figref>10</figref> supports various Types of transactions on the bus <figref>24</figref>, Including memory transactions (As previously described) and I / O transactions, which a I / O device (eg, a through the I / O bridge <figref>20</figref> or another, not shown I / O bridge coupled device) mark. Each of the processors <figref>12A</figref>-<figref>12B</figref>, The L2 cache memory <figref>14</figref>. the memory controller <figref>16</figref> or the I / O bridge <figref>20</figref> can be a participant in the transactions. In general, the "participation" of an agent is to a transaction occurs when one of the agents during the transaction is action required for the transaction completed properly is. The agent "not participate" assumes a transaction, if the by the agent during Transaction No action is required in order for the transaction duly completed is. Similarly Way is the agent a "participant" in the transaction, when it is required that the agent during the transaction an action undertakes to ensure that the transaction is completed properly. an Agent even as a subscriber to a particular transaction designated if this transaction is not on the bus <figref>24</figref> initiated has been, if this agent during would the specific transaction take action as soon as that particular transaction is performed. The agent is a "non-runner" in the transaction, if it is not required that the A gent during the Transaction takes an action, so that the transaction completed properly is. An agent is even as a non-participant in a specific transaction referred to, if the transaction is not on the bus <figref>24</figref> has been initiated, if this agent during the would take particular transaction no action once these specific performed transaction is. The earmarked by the Transaction Agent in the transaction part. additionally can other agents take part in various transactions. For example can they processors <figref>12A</figref>-<figref>12B</figref> (and in some embodiments the I / O bridge <figref>20</figref>) To coherent memory transactions participate by taking an action to the coherency question about (eg snooping of internal cache memories and Specifying the result of the snoop). The L2 cache memory<figref>14</figref> can attend cache storable memory transactions by determines whether the transaction is a hit, and in response the transaction supplies the data or the data stored therein Data updated. As used herein, the term "snoop" or "snooping" on the review of a Cache memory to determine whether data received from one of a Transaction correspond affected memory location in the cache memory are present, and signaling the state of the data to to ensure that the coherence the data is preserved.

0099On addressable range of the system <figref>10</figref> is by the size of the addresses defined, on the bus <figref>24</figref> can be transferred. Of the addressable area may be divided into multiple address spaces, including a Memory address space and various I / O address spaces. at this embodiment , the address space that contains the address of a transaction, the Type of transaction identification. Thus, outputs an address in the Memory address space indicates that the transaction is a memory transaction , and the address identifies a location earmarked in the memory <figref>26</figref> (Which is why the memory controller <figref>16</figref> and the L2 cache memory <figref>14</figref> responsive to the transaction can, and the processors <figref>12A</figref>-<figref>12B</figref> by snooping may participate in the transaction). A Address in the I / O address spaces indicates that the transaction is an I / O transaction and the address of a I / O device vormerkt. The I / O devices may packet interface circuits<figref>22A</figref>-<figref>22C</figref>, other I / O devices, or through the I / O bridge <figref>20</figref> with the bus <figref>24</figref> coupled interfaces, and any other I / O bridges (not shown) or interfaces coupled devices exhibit. Each of the I / O address spaces the I / O bridge are associated with the corresponding I / O device coupled or Bridge.

0100During address spaces used will, to determine which type is performed by transaction (And to determine the destination of the transaction), other embodiments determine these attributes in other ways. For example, various Instructions are used to different types of transactions to induce or reserve to various devices. control signals can on the bus be used to identify the destination.

0101Among with reference to <figref idrefs="S51">8</figref> there is shown a block diagram of shown, the additional Details of one embodiment the processors <figref>12A</figref>-<figref>12B</figref>. the L2 cache memory <figref>14</figref>, The memory controller <figref>16</figref> and the I / O bridge <figref>20</figref> illustrated. <figref idrefs="S51">8</figref> illustrated also an embodiment a specific interconnection between the agents mentioned above. Other embodiments are possible and are contemplated. In the embodiment of<figref idrefs="S51">8</figref> has the processor <figref>12A</figref> a request circuit <figref>230A</figref>. a block circuit <figref>232A</figref>, An output queue <figref>234A</figref> and an input queue <figref>236A</figref> on. The request circuit<figref>230A</figref> is coupled to a block signal from each other agent on the bus <figref>24</figref> receive (specifically the Block_MC1 signal from the memory controller <figref>16</figref>), And is connected to the output queue <figref>234A</figref> coupled. The block circuit <figref>232A</figref> is connected to the input queue <figref>236A</figref> coupled and configured to generate a Block_P0 signal. processor<figref>12B</figref> has a similar group by on elements including the request circuit <figref>230B</figref>, The block circuit <figref>232B</figref>, of the output queue <figref>234B</figref> and the input queue <figref>236B</figref>, The I / O bridge <figref>20</figref> is also configured in a similar manner and includes the acquisition circuit <figref>230C</figref>, The block circuit <figref>232C</figref>. the output queue <figref>234C</figref> and the input queue <figref>236C</figref> on. The L2 cache memory <figref>14</figref> can be configured in a similar manner his and a request circuit <figref>230E</figref>, A block circuit <figref>232E</figref>. an output queue <figref>234E</figref> and an input queue <figref>236E</figref> exhibit. The memory controller <figref>16</figref> has a block circuit <figref>232D</figref> and an input queue <figref>236D</figref> and a configuration register <figref>238</figref> on. The block circuit <figref>232D</figref> is connected to the input queue <figref>236D</figref> and the configuration register <figref>238</figref> coupled.

0102in the Generally, each agent captures the transactions for which this Agent is a participant. The transactions are in the input queue<figref>236A</figref>-<figref>236E</figref> this Agents captured. The agent, the transaction from its input queue<figref>236A</figref>-<figref>236E</figref> remove, to process the transaction. The size of each input queue<figref>236A</figref>-<figref>236E</figref> can size (ie, the number of specific entries) based on the expected latency for processing the transactions in the participating agents and the number of additional, while This latency period anticipated transactions, are listed. It is typically not desirable, a queue with enough entries provide to store the maximum number of transactions, which could take place, as often many of the queue entries would remain unused and thus wasting circuit area in the agent. Therefore can the input queues for the most likely number of transactions during ordinary transaction sequences be sized, and the queue can sense in some cases will. For example, tend I / O transactions to a longer latency as memory transactions, but are also tend to be less often before. Therefore, the input queue<figref>236C</figref> relative few items exhibit. On the other hand, occur more frequently memory transactions with lower latency, and therefore can the input queues <figref>236A</figref>-<figref>236B</figref> and <figref>236E</figref> a greater number of entries exhibit. Each of the input queues<figref>236A</figref>-<figref>236E</figref> however, are full, so the containing the full input queue may not Agent is capable of additional Transactions in part to take up command queue entries for saving additional Transactions are free.

0103The block circuits <figref>232A</figref>-<figref>232E</figref> are provided to determine whether the corresponding input queue <figref>236A</figref>-<figref>236E</figref> full is, and to generate a block signal if the corresponding input queue <figref>236A</figref>-<figref>236E</figref> full is. In the illustrated embodiment, each block circuit generates<figref>232A</figref>-<figref>232E</figref> on separate block signal as follows: The block circuit <figref>232A</figref> generates Block_P0; the block circuit <figref>232B</figref> generates Block_P1; the block circuit<figref>232C</figref> Block_IO generated; the block circuit <figref>232D</figref> generates Block_MC1 and Block_MC2; and the block circuit <figref>232E</figref> Block_L2 generated. The block signal can be activated to indicate that the corresponding agent for the Participation in additional Transactions not available is, and will be disabled, to indicate that the corresponding Agent for participation in additional is transactions.

0104Each requesting agent (eg the processors <figref>12A</figref>-<figref>12B</figref>. the I / O bridge <figref>20</figref> and the L2 cache memory <figref>14</figref>) refuses a request circuit <figref>230A</figref>-<figref>230E</figref> on that block signals and an output queue <figref>234A</figref>-<figref>234E</figref>, The requesting agent may transactions on the bus <figref>24</figref> be initiated should, in the appropriate output queue <figref>234A</figref>m<figref>234E</figref> set. The request circuits <figref>230A</figref>-<figref>230E</figref> are with the respective output queues <figref>234A</figref>-<figref>234E</figref> coupled and determine whether it is the appropriate agent allows transactions from the respective output queue in response to the block signals on the bus <figref>24</figref> to initiate. More specifically blocked the request circuit <figref>230A</figref>-<figref>230E</figref> the initiation a first transaction in the corresponding output queue <figref>234A</figref>-<figref>234E</figref>. if any agent who is a participant in the first transaction is its block signal is activated. Thus, the source can each Transaction selectively initiating the transaction function block them or not block if the / the other participant (s) present in the transaction to participate in the situation is / are. In the illustrated embodiment the L2 cache <figref>14</figref> on requesting agent only may be storage space transactions, and therefore only for memory transactions Signals used to receive (eg Block_P0, Block_P1, and Block_MC1). Other embodiments can the Block_IO signal also exhibit (for example, if the I / O Bridges temporarily Data cache store- and therefore can track memory transactions).

0105On Thus, transactions that are not complete can, because a participating Agent is unable to participate, not on the bus <figref>24</figref> initiated. On the other hand, it is authorized, that transactions, for a block signal that no participant activated on the bus <figref>24</figref> be initiated. In other words, a given transaction is not of a blocking agents, of a non-participant in this transaction is. Therefore, Transactions due to the granularity of locking (with eg each agent independently its ability to participate indicates) be performed even if a non-participating Agent these transactions blocked.

0106The requestor circuits <figref>230A</figref>-<figref>230E</figref> can they block initiation of transactions in a number of ways. For example, if a block signal for a participating agent is activated before the corresponding agent of the Arbitration the bus <figref>24</figref> wins to perform the blocked transaction, can the request circuit <figref>230A</figref>-<figref>230E</figref> the Arbitration (Or another Arbitration) stop to the blocked transaction perform, is disabled until the block signal. If desired, the corresponding Agent arbitrate to perform other, non-blocked transactions. If On the other hand, the block signal is not asserted before the corresponding Agent arbitration wins, the request circuit <figref>230A</figref>-<figref>230E</figref> the causing agents to an invalid command code on to drive the bus. In this case, the bandwidth is not guaranteed, but the transaction is not performed and therefore no retry the transaction takes place.

0107While the Most of the in <figref idrefs="S51">8</figref> illustrated subscriber produce a single block signal, the memory controller <figref>16</figref> two block signals on: Block_MC1 and Block_MC2. The request circuits<figref>230A</figref>. <figref>230B</figref>. and <figref>230E</figref> are each coupled to the Block_MC1 signal to receive, and the request circuit <figref>230C</figref> is coupled, to receive the Block_MC2 signal. In some embodiments, (Eg embodiments, in which the I / O bridge <figref>20</figref> with other I / O devices is coupled), the request circuit <figref>230C</figref> also be coupled to the Block_MC1 signal for use in blocking to receive requests from the other I / O devices.

0108Each the requestor circuits <figref>230A</figref>-<figref>230E</figref> uses the from the memory controller <figref>16</figref> received block signal to block memory transactions (if the block signal is activated). Thus, processors <figref>12A</figref>-<figref>12B</figref> and the L2 cache memory <figref>14</figref> memory transactions block if the Block_MC1 signal is asserted, while the I / O bridge <figref>20</figref> Transactions may block when the signal Block_MC2 is enabled. Thus, other agents are blocked, and it can make the packet interface circuits <figref>22A</figref>-<figref>22C</figref> be allowed continue initiating memory transactions by the memory controllers <figref>16</figref> the Block_MC1 signal activates and the Block_MC2 signal disabled. Particularly, the Block_MC1 signal be activated when the number of transactions in the input queue <figref>236D</figref> a exceeds the first threshold value, and Block_MC2 the-signal may be asserted when the input queue <figref>236D</figref> full (or full), similar the other block signals from the other agents. In general , the first threshold value less than the number of transactions in the input queue <figref>236D</figref> be, in which the signal Block_MC2 is activated.

0109at one embodiment the threshold value for activating the Block_MC1 signal in the configuration register <figref>238</figref> be programmable. The configuration register <figref>238</figref> can an indication of the first Save threshold. The indication may be the number of entries, the for storing transactions must be free before the Block_MC1 signal is deactivated, the number of entries, which, if by transactions are occupied, causing the activation of the Block_MC1 signal, a percentage the total number of entries, which the activation or deactivation of Block_MC1 signal cause, etc. If desired, may be set as an alternative to the first threshold.

0110As already mentioned was, a block circuit <figref>232A</figref>-<figref>232E</figref> the corresponding Blocksigactivate signal if the corresponding input queue <figref>236A</figref>-<figref>236E</figref> full is. More specifically, the circuit block<figref>232A</figref>-<figref>232E</figref> the activate corresponding block signal when the number of free (currently unused) entries drops to a predetermined threshold value. The threshold can zero be when the block signal early enough can be generated to any subsequent transaction to block the participation by the appropriate agent may require. In one embodiment, are Arbitration and transaction initiation but pipelined. Therefore , the initiation of a transaction that the last free input queue entry to fill would, parallel with the arbitration for a transaction take place, which is also an input queue entry would require this agent. Thus, the threshold value may in such an embodiment To be one. In response to a transaction which the penultimate filled free queue entry and a queue entry can be freely selected the appropriate block circuit <figref>232A</figref>-<figref>232E</figref> their block signal.

0111It it is noted that each of the input queues <figref>236A</figref>-<figref>236E</figref> a appropriate number of entries may include, by the number of entries in other input queues <figref>236A</figref>-<figref>236E</figref> different can be. Similarly, each of the output queues <figref>234A</figref>-<figref>234E</figref> a have suitable number of entries, by the number of entries in other output queues <figref>234A</figref>-<figref>234E</figref> different can be.

0112It is further noted that the above description While on scenarios with full input queues as the cause unavailability to participate in additional transactions relates that but as desired for a given agent other reasons for this may be that he for participation in additional Transactions not available is. The block signals used as previously described for such scenarios will.

0113Among with reference to <figref idrefs="S52">9</figref> shown next, a flow diagram, the operation of an embodiment of in <figref idrefs="S51">8</figref> shown memory controller <figref>16</figref> illustrated. Other embodiments are possible and are contemplated. In the<figref idrefs="S52">9</figref> shown blocks are for a simplified understanding illustrated in a particular order. However, it may any order may be used. Concretely speaking, the blocks are<figref>180</figref> and <figref>182</figref> as Group and the blocks <figref>184</figref> and <figref>186</figref> as group independently and can in any order or in parallel. Concretely , the combinational logic circuit in the memory controller <figref>16</figref> the run parallel groups.

0114If the number of transactions in the input queue <figref>236D</figref> greater than the in the configuration register <figref>238</figref> (Decision block <figref>180</figref>) set Threshold is activated, the memory controller <figref>16</figref> the Block_MC1 signal (block <figref>182</figref>). Otherwise, the Block_MC1 signal disabled. equivalently , The test may in block <figref>180</figref> be that the number of free entries in the input queue <figref>236D</figref> less than in the configuration register <figref>238</figref> set Threshold.

0115If the input queue <figref>236D</figref> full (or full, as described previously) (decision block <figref>184</figref>) activates the memory controller the Block_MC2 signal (block <figref>186</figref>). Otherwise is disabled the Block_MC2 signal.

0116Among with reference to <figref idrefs="S53">10</figref> is there a next Block diagram of a carrier medium <figref>300</figref> With shown a database representative of the system <figref>10</figref> is. Generally speaking, a carrier medium Storage media such as magnetic or optical media, eg, disk or CD-ROM, volatile or non-volatile Storage media such as RAM (eg SDRAM, RDRAM, SRAM, etc.), ROM etc., as well as transmission media or signals such as electrical, electromagnetic, or digital include signals over a communication medium such as a network and / or a wireless transfer connection will.

0117in the Generally, the database on the carrier medium of the <figref>300</figref> supported Systems <figref>10</figref> be a database from a program can be read and used directly or indirectly to the hardware establish which system the <figref>10</figref> having. For example the database may be a behavioral level description or register-transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL to be. The description can of a synthesis tool are read, which synthesize the description can, to produce a netlist, of a list of gates having a synthesis library. The Netlist has a group of Gates, which also represent the functionality of the hardware, which the system <figref>10</figref> having. The Netlist can then placed and be routed to produce a data set on masks applicable geometric shapes describes. The masks may then be used in various semiconductor fabrication steps to produce a semiconductor circuit or semiconductor circuits, the system <figref>10</figref> correspond. Alternatively, the Database on the carrier medium <figref>300</figref> on If desired, the netlist (with or without the synthesis library) or the his record.

0118While the carrier medium <figref>300</figref> a Representation of the system <figref>10</figref> transmits, other embodiments may as desired, a representation of any portion of the system <figref>10</figref> carry, including any Group of agents (eg the processors <figref>12A</figref>-<figref>12B</figref>. the L2 cache memory <figref>14</figref>, The memory controller <figref>16</figref> and or the I / O bridge <figref>20</figref>) Packet interface circuits <figref>22A</figref>-<figref>22C</figref> or parts thereof, the bus <figref>24</figref> etc. The above-mentioned databases can a have circuit comprising a mechanism for the system <figref>10</figref> or Parts thereof defined.

0119Numerous Variations and modifications will occur to those skilled in the art, a thorough assessment the above description. It is intended that the following claims be interpreted to mean that all such variations and modifications with include.

0120So far Embodiments previously described the invention, at least in part, using software-controlled programmable processing device such as a digital Signal processor, microprocessor, other processing devices, a data processing device or computer system can be implemented, it will be seen that a computer program or program element for configuring a programmable device, a programmable device, or System for implementing the method previously described, Mechanisms and / or modules as an aspect of the present invention is contemplated. The computer program or program element can designed as a source his and a compilation of the implementation on a processing device, a device or system undergo, or may for example be embodied as object code. For the Skilled artisan would be easily seen that the term computer / calculator in its basic meaning programmable devices as those mentioned above, and data processing equipment and computer systems includes with.

0121On appropriately is the computer program or program element a carrier medium stored in a readable by a machine or device form, eg in solid state memory, optical or magneto-optical storage such as a readable and / or writable disk such as a CD and a DVD, or Magnetic memory such as disc or tape and the processing device used the program, program element or a part thereof to it for To configure the operation. The computer program or program element can be supplied from a remote source, which in a Communication medium such as running an electronic signal, including radio frequency carrier wave or optical carrier wave. Such carrier media are also considered aspects of the present invention contemplates drawn.

0122in the With respect to the previous advance description of certain embodiments the invention should it for be a skilled person that various additions, Modifications and alternatives can be provided for.

0123in the Referring to the attached claims can Features from dependent claims be combined with features of the independent claims, and Features from respective independent claims may suitably and not only in the claims enumerated specific combinations are combined.

0124Around to avoid uncertainty, the term should be "comprising" in the description and the patent claims is used, can not be interpreted so that it only "consisting of" means.

9 members in 3 offices

This recordMember, by publication datePriority claim

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Priority claims
Document	Office	Kind	Date
86118801	United States of America	A	2001-05-18
86118801	United States of America	A	2001-05-18
86118801	United States of America	–	2001-05-18
861188	–	–	–
US20010861188	–	–	–

Members9

Family members, oldest first
Document	Office	Kind
US2002174252A1	United States of America	A1	2002-11-21
US2002174255A1	United States of America	A1	2002-11-21
EP1261173A2	European Patent Office (EPO)	A2	2002-11-27
EP1261173A3	European Patent Office (EPO)	A3	2005-01-05
EP1261173B1	European Patent Office (EPO)	B1	2007-01-03
DE60217221D1	Germany	D1	2007-02-15
DE60217221T2This record	Germany	T2	2007-10-04
US7287649B2	United States of America	B2	2007-10-30
US7320022B2	United States of America	B2	2008-01-15

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2010-01-14	Change in the person/name/address of the agent8328	8328
2008-01-24	No opposition during term of oppositionOpposition8364	8364