Personal communications device with gps receiver and comon clock source

These Invention relates generally to a personal communication device with global positioning system receiver means, via a Clock signal to be clocked, which is obtained from a clock source, which is shared with CDMA based radio. In particular, creates the invention provides a fractional-N synthesizer a feedback signal provides for controlling an oscillator signal output frequency.

Personal Communication devices with global positioning (GPS) are -Tauglichkeit More and more popular. In these devices have circuits and components, the for providing the global positioning capability required are, the same housing and the same platinum extent with the circuits and components share, which it have been made, for example, Mobiltelephontauglichkeit be able to provide. Further, circuits and components for both GPS capability as for Mobiltelephontauglichkeit powered by the same power source with power, normally a platinum battery. Although battery technology is improving, it is typical that with increasing power consumption of a device physical Size of the battery, the for the provision of a certain operating time is required becomes larger.

The Demand for smaller, more compact personal communication devices taking to. Simultaneously with this increasing demand for compactness If the demand for devices having an improved functionality and usability offer. With the increase of functionality and suitability normally rises the demand for electricity and the circuit scale within the personal Communication device.

at personal communication devices as in the block diagram in <figref idrefs="S16">1</figref> shown, wherein a personal communication device given that a Global Positioning (GPS) receiver <figref>100</figref> and a CDMA-based (Code Division Multiple Access) telecommunications device <figref>200</figref> contains, are separate clock sources (oscillators) normally the GPS receiver <figref>100</figref> and the CDMA device <figref>200</figref> assigned. In particular, the GPS receiver includes<figref>100</figref> a associated oscillator <figref>101</figref>While the CDMA device <figref>200</figref> a zugeord Neten oscillator <figref>201</figref> contains. Each of the oscillators<figref>101</figref> and <figref>201</figref> provides of each circuit, it is associated with a clock signal.

<figref idrefs="S17">2</figref> shows a GPS receiver <figref>100</figref>. of an oscillator <figref>101</figref> contains. The oscillator<figref>101</figref> provides the phase <figref>146</figref> a signal of a particular frequency. The phase <figref>146</figref> also receives an input from the frequency divider <figref>136</figref> and outputs a signal to the loop filter <figref>145</figref> out. The loop filter<figref>145</figref> provides a signal to the voltage controlled oscillator (VCO) <figref>115</figref>. which produces an output signal whose frequency by the input signal from the loop filter <figref>145</figref> is caused. The signal from the voltage-controlled oscillator VCO <figref>115</figref> is the mixer <figref>110</figref> fed, where it with a radio frequency (RF) signal from the amplifier with low noise (LNA) <figref>105</figref> is combined to a first intermediate frequency signal (IF) to produce S1. This first intermediate frequency signal S1 is to the variable amplifier <figref>112</figref> and then the mixer <figref>120</figref> and the mixer <figref>121</figref> delivered. In mixer <figref>120</figref> the signal S1 with a signal S2 from frequency divider <figref>130</figref> combined to an in-phase second intermediate frequency output signal to produce S3. In mixer<figref>121</figref> the signal S1 with a Signal S4 from frequency divider <figref>130</figref> combined to a four-phase second intermediate frequency output signal to generate S5. The signal S3 is applied to the comparator and A / D processor <figref>125</figref> delivered, to a digitized signal I for output to GPS baseband section <figref>150</figref> to produce. The signal S5 is supplied to the comparator and A / D processor<figref>126</figref> delivered, to a digitized signal Q for output to GPS baseband section <figref>150</figref> to produce. The frequency divider<figref>130</figref> provides its output S4 also to the frequency divider <figref>135</figref> and the frequency divider <figref>136</figref>, The output of the voltage controlled oscillator VCO <figref>115</figref> becomes also to the frequency divider <figref>130</figref> delivered. The frequency divider<figref>130</figref> gives a signal S5 from which the mixer <figref>121</figref> with a signal is mixed S1 to produce a signal S4.

There two separate oscillators within the same personal communication device <figref>10</figref> are provided, a scope for printed and / or integrated circuits provided to each the oscillators accommodate, and the power consumption of two Oscillators is higher than by an oscillator. Consequently exists in the industry a unspoken need, to the above-mentioned disadvantages and shortcomings turn.

The <patcit><text>US 5,841,396</text></patcit> and <patcit><text>US 6,041,222</text></patcit> reveal each a personal communication device, with a Telecommunications unit, a Global Positioning System (GPS) receiver and a clock source for providing a common clock signal to the GPS receiver and the telecommunications unit. The<patcit><text>US 5,481,396</text></patcit> disclosed in <figref>6B</figref> and the corresponding description in column 14, beginning at line 10, that a common clock signal from the clock source as a reference frequency to a frequency synthesizer in &lt;?page 3?&gt;a GPS downconverter sent in GPS receiver is. The frequency synthesizer produces inputs for two local oscillators in GPS system. The output of one of these two local oscillators is in the first stage of an RF / intermediate frequency downconversion input, and is in a feedback loop also the frequency synthesizer supplied.

It An object of the invention to provide an improved personal to provide telecommunications device that both Global Positioning System (GPS) - as has also telecommunications equipment.

These Task is to by an apparatus and a method, respectively to claims 1 and 8 reached.

More Developments of the invention are given in the subclaims.

More Systems, methods, features and advantages of the invention will be or be the skilled worker after examination the following figures and detailed description.

The Invention will be better understood by reference to the following figures. The components in the figures are not necessarily to scale, but it is instead a value has been placed on the principles of Invention clearly present. In the figures, identical reference numerals the different views corresponding parts.

<figref idrefs="S16">1</figref> is a block diagram of a typical personal communications device;

<figref idrefs="S17">2</figref> is a schematic diagram of a GPS receiver;

<figref idrefs="S18">3</figref> is a block diagram of the invention;

<figref idrefs="S19">4</figref> is a schematic diagram of a personal communication device according to the invention;

<figref idrefs="S20">5</figref> is a schematic diagram of a Fractional-N synthesizer;

<figref idrefs="S21">6</figref> is a detailed description of an embodiment of a phase compensation circuit and an on-chip tuning circuit;

<figref idrefs="S22">7</figref> is a timing diagram, the relationship the between signals of the frequency synthesizer in relation to the signals represents the compensation circuit; and

<figref idrefs="S23">8th</figref> is a diagram showing a further embodiment of the invention.

The Invention is a personal communication device <figref>10</figref> With Global Positioning System (GPS) -Tauglichkeit create. The invention is a personal communication device<figref>10</figref> create, in which a single oscillator <figref>201</figref> as the clock source both for a Mobiltelephonschaltung <figref>200</figref> and a Global Positioning System (GPS) circuit <figref>100</figref> acts. The GPS circuit <figref>100</figref> contains fractional synthesizer means for controlling the generation of the frequency of signals based on the oscillator <figref>201</figref>,

<figref idrefs="S18">3</figref> shows a block diagram of a personal communications device according to the invention <figref>10</figref>, It is a Global Positioning System (GPS) receiver <figref>100</figref> and a CDMA-based telecommunication unit <figref>200</figref> provided. The GPS receiver <figref>100</figref> contains a GPS radio receiver <figref>102</figref> and a GPS baseband unit <figref>103</figref>, The GPS radio receiver<figref>102</figref> receives and processes GPS signals and provides them to the baseband unit <figref>103</figref>. for more data from a received GPS signal to extract can. It is also a CDMA radio unit <figref>202</figref> for receiving, processing and transmitting CDMA-based radio signals and a CDMA baseband unit <figref>203</figref> for further Processing received or further conducting CDMA radio signals given. The CDMA telecommunications unit<figref>200</figref> includes an oscillator <figref>201</figref> to the Providing a clock signal to the circuitry of the CDMA-telecommunication unit <figref>200</figref> and to the GPS receiver <figref>100</figref>, Specifically, the CDMA oscillator <figref>201</figref> provides a clock signal to the CDMA radio unit <figref>202</figref>, The CDMA baseband unit <figref>203</figref> and the GPS receiver <figref>102</figref> and the GPS baseband unit <figref>103</figref>,

<figref idrefs="S19">4</figref> shows a diagram of the GPS receiver <figref>100</figref> in the Detail. There is a voltage controlled oscillator (VOC)<figref>115</figref> given which generates a GPS system clock signal Z whose frequency by the voltage input from the loop filter <figref>145</figref> is caused. The output from the VOC<figref>115</figref> becomes to the mixer <figref>110</figref> delivered, where he received a Radio frequency (RF) input signal from the amplifier with low noise (LNA) <figref>105</figref> is combined to a first intermediate frequency signal (IF) to produce S1. This first intermediate frequency signal S1 is at the amplifier <figref>112</figref> and then to the mixer <figref>120</figref> and the mixer <figref>121</figref> delivered. In mixer <figref>120</figref> is it with a signal S2 from frequency divider <figref>130</figref> combined to a second intermediate frequency output signal to produce (IF) S3. In mixer <figref>121</figref> is the second intermediate frequency output signal S1 combined with a signal S4 also from frequency divider <figref>130</figref> comes, to another intermediate frequency output signal to produce (IF) S5. The signal S4 is also applied to the frequency divider <figref>135</figref> LOVED&lt;?page 4?&gt;fert, where it is converted into a signal with an alternative frequency and S6 to the GPS base band unit <figref>150</figref> is output.

the Signal S3 is in the comparator and A / D processor <figref>125</figref> entered, where it is processed and in a digital output signal I for input the GPS baseband unit <figref>150</figref> converted is. In the same manner, the signal S5 to the comparator and A / D processor <figref>126</figref> input, where it is processed and in a digital output signal Q is converted the to the GPS base band unit <figref>150</figref> supplied is.

Of the Output of the GPS system clock signal Z from VOC <figref>115</figref> will also be to the frequency divider <figref>130</figref> and a frequency synthesizer <figref>116</figref> delivered. The frequency divider <figref>116</figref> converts the signal Z from VCO <figref>115</figref> in a feedback signal S7 by that to a phase comparator <figref>146</figref> is supplied, a control signal S9 to the loop filter <figref>145</figref> in reaction to the input of the feedback signal S7 and the clock signal S8 from oscillator <figref>201</figref> outputs. the Control signal S9 is then provided to the VCO <figref>115</figref> provided that the Frequency of the output signal Z in accordance with the control signal S9 adjusts. In this illustration it can be seen that a feedback loop is formed from the frequency synthesizer <figref>116</figref>, The phase comparator <figref>146</figref> and the loop filter <figref>145</figref> composed.

<figref idrefs="S20">5</figref> is a block diagram of the phase interpolated fractional N frequency synthesizer <figref>116</figref>, The synthesizer <figref>116</figref> may be accomplished using known CMOS fabrication methods or other compatible semiconductor chip technologies as an integrated Circuit can be implemented. In<figref idrefs="S20">5</figref> becomes a Reference signal Z from VCO <figref>115</figref> to an input of the phase detector <figref>322</figref> delivered. The output of the phase detector <figref>322</figref> becomes a loop filter <figref>324</figref> delivered. The output of the loop filter <figref>324</figref> is controlled to a oscillator <figref>326</figref>As a VCO, delivered, the output a S7 (feedback signal S7) which the output of the synthesizer <figref>116</figref> is. The signal S7 is supplied to a fractional-N divider <figref>328</figref> supplied. A control word K is the fractional-N divider <figref>328</figref> delivered to the value the divider N set.

Of the Output of the fractional-N divider <figref>328</figref> is supplied to a phase compensation circuit <figref>330</figref> and a chip tuning circuit <figref>332</figref> provided that in combination be referred to as a phase compensator. The output (fcomp) the phase compensation circuit <figref>330</figref> is used as a second input to the phase detector <figref>322</figref> delivered. an accumulator<figref>334</figref> also receives the control word K and the signal Z. The output for the carry (the carry signal S10) from the accumulator <figref>334</figref> also serves as an input to the Fractional-N divider <figref>328</figref>, The signal Z serves as a clock signal for the accumulator <figref>334</figref>, The signal S10 from the output of the carry the accumulator <figref>334</figref> triggers the division of the N-1 function of the fractional-N divider.

Of the phase detector <figref>322</figref>, The loop filter <figref>324</figref> and the VCO <figref>326</figref> can of any suitable type to be associated with those average Expertise are known. The commonly used in fractional-N synthesizers Types of phase detectors, loop filters, VCOs and fractional-N dividers can as Synthesizer <figref>320</figref> ver be used as voltage or current controlled oscillators, phase or phase / frequency detectors, active or passive loop filter and loop filter with charge pumps.

<figref idrefs="S21">6</figref> shows a more detailed description of an embodiment of a phase compensation circuit <figref>330</figref> and On-chip tuning circuit <figref>332</figref>, Phase compensation circuit<figref>330</figref> and on-chip tuning circuit <figref>332</figref> may under Using an array of voltage controlled delay elements (D) are implemented, wherein the amount of the delay elements D signal delay creates by TVCO / 4, where TVCO the period of the frequency of the output S10 of the VCO <figref>326</figref> balances.

Of the Output of the fractional-N divider <figref>328</figref> is applied to the series of the delay lines applied, the outputs as φ1-φ4 are identified. It should be noted that φ1 no delay elements having, whereas φ2 a single delay element which φ3 two delay elements having and having φ4 three delay elements. The Signals φ1-φ4 are applied to the control circuit <figref>339</figref> provided that fcomp an output comprises that to one input of the phase detector <figref>322</figref> created , as in <figref idrefs="S20">5</figref> shown. The output fcomp the control circuit <figref>339</figref> selectively with inputs φ1-φ4 according to the output the accumulator <figref>334</figref> and connected to the control circuit <figref>339</figref> delivered.

The On-chip tuning circuit <figref>332</figref> includes four voltage-controlled delay elements D, a phase detector <figref>336</figref> and a loop filter <figref>338</figref>, In the on-chip tuning circuit <figref>332</figref> is a delay locked loop implemented. The signal S10 from the VCO<figref>326</figref> happened the four delay elements (D) of the on-chip tuning circuit <figref>332</figref> and then to the phase detector <figref>336</figref> delivered. The phase detector<figref>336</figref> gives a signal proportional to the phase difference between the two Input signals. The output of the phase detector<figref>336</figref> happens then a loop filter <figref>338</figref>, The output Vc of the loop filter<figref>338</figref> becomes as a control voltage for each of the delay elements D of the on-chip tuning circuit <figref>332</figref> used. The CON&lt;?page 5?&gt;erspannung Vc is also applied to each of the delay elements (D) of the tuning circuit <figref>332</figref> created ¼ of Frequency period of the input signal to the delay locked loop. The tuning circuit<figref>332</figref> certainly or adjusts the value of the delay elements according to the input frequency at.

<figref idrefs="S22">7</figref> shows a timing diagram, the relationship the between various signals of the synthesizer <figref>116</figref> in Relation to the signals of the compensation circuit <figref>330</figref> and the on-chip tuning circuit <figref>332</figref> represents. More specifically,<figref idrefs="S22">7</figref> shows an example in the S10 = 4.25 (Z). In this example, the divider <figref>328</figref> at N = 4 (via the control word K) programmed. The accumulator<figref>334</figref> is (about the Control word K) programmed to a carry signal at every fourth generating cycle of the signal Z. Each of the time intervals T equals a cycle of Z. While of the time interval T1-T4 S10 has 17 cycles and Z 4 cycles. During the time interval T1 shares of fractional-N divider <figref>328</figref> the signal S10 4. In the second time period T2, and the third time period T3 notify the divider <figref>328</figref> turn to the signal S10 by 4. Beginning of the fourth period, T4, produced the accumulator <figref>334</figref> the carry signal, which causes the divider divides by N + 1, in this example N + 1 = 5. Therefore, the signal Z is divided during T4 by five.

During the Time period T1 supplies the phase compensation circuit <figref>330</figref>. more specifically, the control circuit <figref>339</figref>, The signal φ1 to the phase detector <figref>322</figref>, At the beginning of the time period T1 is the signal φ1 to the signal Z phase. At the start the time period T2 on the output of the phase compensation circuit <figref>330</figref> on φ2. The switching of the output of the control circuit <figref>339</figref> becomes by the output of the accumulator <figref>334</figref> controlled by the the signal Z is clocked. It should be noted that φ2 at the output of the phase compensation circuit <figref>330</figref> phase with Z is. equally switches at the beginning of the time period T3, the output of the phase compensation circuit <figref>330</figref> to φ3, and then turned on at the beginning of the time period T4, the output of the phase compensation circuit <figref>330</figref> to φ4. Then the pattern repeats. In this manner, the compensation the phase lag of the divider <figref>328</figref> reached.

<figref idrefs="S23">8th</figref> shows an alternative embodiment, in facilities selective feedback to phase <figref>146</figref> via the fractional-N synthesizer <figref>116</figref> or a frequency divider <figref>136</figref> have been provided. at this embodiment is a switch <figref>250</figref> for switching between the output the fractional-N synthesizer <figref>116</figref> or frequency divider <figref>136</figref> for the input to the phase comparator <figref>146</figref> provided. Of the switch <figref>250</figref> , a multiplexer or another logical Gat ter be. Further, the switch can<figref>250</figref> permanently to a desired position while be set manufacture or could be achieved by applying a suitable be switching signal selectively switchable and controllable.

FURTHER EMBODIMENTS

The present invention can be in the United States in the the <patcit><text>US Patent Nos. 5,874,914</text></patcit> for "GPS Receiver Utilizing a Communication Link "and <patcit><text>US Pat. No. 5,841,396</text></patcit> also for "GPS Receiver Utilizing a Communication Link "implemented will. Here is a receiver a global positioning system (GPS) discloses a first antenna for receiving a GPS signal, and a with the first antenna coupled downconverter includes. The first antenna provides the GPS signal to the down converter. A local oscillator is connected to the downconverter coupled and provides a reference signal to the down-converter, to the GPS signals from a first frequency to a second frequency convert. A second antenna is for receiving a precision carrier frequency signal from a source of the precision carrier frequency signal provided. An automatic frequency control circuit (AFC) is coupled to the second antenna. The AFC circuit provides a second reference signal to the local oscillator to the first reference signal from the local oscillator to calibrate. The local oscillator used to detect the GPS signals.

Also described is a mobile GPS receiver to a first antenna for receiving GPS signals and to the first antenna coupled buck converter. The first antenna provides the GPS signals to the downconverter. The down-converter has an input for receiving a signal of the local oscillator, to the GPS signals from a first frequency to a second frequency convert. The second antenna is provided to a precision carrier frequency signal from a source, the precision carrier frequency signal, the returns to receive. An automatic frequency control circuit (AFC) is coupled to the second antenna. The AFC circuit is also the downconverter coupled to provide the signal of the local oscillator is used for collecting the GPS signals.

Further the present invention in the in <patcit><text>US Pat. No. 6,002,363</text></patcit> for "Combined GPS Positioning Systems and Communication System Utilizing Shard Circuitry "implemented will. the<patcit><text>US Pat. No. 6,002,363</text></patcit> disclosed among other things a GPS receiver, the a GPS antenna for receiving data containing the GPS signals from at least one satellite represent; Einein digital processor, coupled to the GPS antenna, wherein the digital processor data verar&lt;?page 6?&gt;processed, which the GPS signals represent at least one satellite, including the implementation of a matched filter process of determining a pseudo range based on the GPS signals representing the Data. The digital processor also processes communication signals, which are received by a communication link, where processing communication signals, the demodulation of communication signals includes that on the GPS receiver have been sent.

Further the present invention in the in <patcit><text>US Pat. No. 5,734,966</text></patcit> for "Wireless Communications System For Adapting to Frequency Drift "are implemented. the <patcit><text>US Patent 5,734,966</text></patcit> disclosed among other things, a frequency tolerant wireless transceiver to Receiving and forwarding the wireless signal energy on the same frequency and to automatically adjust to that frequency, wherein the transceiver includes: an antenna for receiving a wireless data signal, including application data of one or more remote transceivers, at an actual Frequency, and outputting this signal as a supplied radio frequency (RF) data and for forwarding a wireless return signal in the actual Frequency to the remote transceiver in response to the supplied RF return signal; a synthesizer for sequentially generating a signal of a local oscillator (LO) in response to a first and a second frequency control signal, and to generate the RF return signal in the actual Frequency in response to the second frequency control signal and with a modulation in response to a digital return signal; a direct conversion receiver for Receiving the LO signal to the RF data signal to a baseband data signal down to convert; a Frequen discriminator for receiving the baseband data signal, a frequency difference signal for the instantaneous frequency difference between the expected frequency and the actual provide frequency and to demodulate the baseband data signal, and a demodulated data signal output; and a micro-controller system a reception setting mode to the first frequency control signal provide that predicts an expected frequency and to the Frequency difference signal to receive, with a receive data mode, to process the frequency difference signal to the second frequency control signal, the actual predicting frequency, supply, and the demodulated data signal to receive, including the application data, and to provide the digital return signal.

Further disclosed is a frequency-tolerant transceivers for automatic Adjustment to a radio frequency (RF) data on an actual receive frequency and an RF return signal on the same pass frequency, wherein the transceiver includes: a Synthesizer for sequentially generating a signal of a local Oscillator (LO) and the RF return signal, wherein the LO signal sequentially a first frequency, the expected one Frequency of the RF signal corresponds to data, and a second frequency having the actual Frequency of the RF data signal in response to a first and a second frequency control signal corresponds in each case, the RF return signal, the second frequency comprising in response to said second frequency control signal; and a Microcontroller system with a reception setting mode for providing the first frequency control signal, which predicts the expected frequency, and providing the second frequency control signal for the actual frequency, on a frequency difference between the actual Frequency and the expected frequency based.

The personal communication device of the invention, in Hardware, software, firmware or a combination thereof implemented will. When / the preferred embodiment / s is the personal communication device implemented in software or firmware that is stored in a memory and by a suitable instruction execution system is delivered. When implemented in hardware, as in a alternative embodiment the personal communication device of the invention with implemented any or a combination of the following technologies are all well known in the art: discrete logic circuit / s with logic gates for implementing logic functions due data signals, an application specific integrated circuit with appropriate logic gates, a PGA (Programmable Gate Array / Programmable Gate Arrays), an FPGA (completely Programmable Gate Array / programmable gate arrays), etc.. more.

It should be emphasized that the embodiments described above, the invention, particularly any "preferred" embodiment, only possible constitute examples of implementation which the only for a clear understanding Principles of the invention have been demonstrated. There are many variations and modifications of the above-described embodiment / s of the invention may be made without substantially from the scope of the invention as defined in the following claims is departing.