Cpu accessing an extended register set in an extended register mode and corresponding method

Background of the Invention

Technical field

The Invention relates to microprocessors, and in particular mechanisms to extend the register address space in an existing microprocessor architecture.

State of technology

microprocessor Manufacturer constantly developing new products that run 86 × commands compatibility with the large Amount for previous 80 × 86 Generations of software - the 8086/8, 80286, 80386 and 80486 - for true. Defining software compatibility has many newer products architectural compromises demanded. To use the functions of previous products preserve the microprocessor hardware was often modified easily or extended to the skills and to increase performance.

The x86 instruction set variable is relatively complex and through a plurality of instructions Byte length in. <figref idrefs="S28">1</figref> shows a generic format of a 86 × command <figref>10</figref>, at a 86 × command <figref>10</figref> can several optional prefix bytes <figref>12</figref> 1-2 opcode byte (Opcode) in an opcode <figref>14</figref> precede. an optional Adressiermodusbyte (Mod R / M) <figref>16</figref> can the opcode <figref>14</figref> consequences. An optional scale-index byte (SIB) <figref>18</figref> can on the optional Mod R / M byte <figref>16</figref> consequences. An optional displacement field<figref>20</figref> can to the optional SIB byte <figref>18</figref> follow, and an optional Direct data field <figref>22</figref> may tender box on the optional displacement <figref>20</figref> consequences. The optional displacement field <figref>20</figref> contains an in address calculations used constant and optional immediate data field <figref>22</figref> contains a used as constant instruction operand.

The 1-2 Opcodebytes the opcode <figref>14</figref> define the basic operation of × 86 command <figref>10</figref>, the basic operation typically includes at least one operand. Because the x86 architecture no transfers enables from memory to memory, is at least one of the operands is always a register (ie, Register operand). The three least significant bits of a Opcodebytes can specify a register operand. The shortest x86 instructions are only one byte long and comprise a single opcode byte. It should be noted, that 80286 a maximum for a × 86 Command of 10 bytes pretending while 80386 and 80486 × 86 instruction lengths Allow up to 15 bytes.

The Operation of a 86 × Command, by prefix bytes <figref>12</figref> modified will. A prefix byte<figref>12</figref> can For example, the size of the address or the operands of 86 × change command, the default segment used in memory addressing disable, or the x86 executing instruction Processor instruct to repeat a string operation several times. It should be noted that the size of a Instruction operands the number he bits in the operands, or the "width" of the operand in Bits concerns.

The optional Mod R / M byte <figref>16</figref> Register specified used and Speicheradressiermodi. <figref idrefs="S28">2</figref> shows The fields of the Mod R / M byte <figref>16</figref>, As in<figref idrefs="S28">2</figref> shown, the Mod R / M byte <figref>16</figref> divided into three fields: a Mode Field (MOD), a register / opcode (REG / OP) and a register / memory array (R / M). the content of the MOD field determines how the R / M field and the displacement field <figref>20</figref> be interpreted. The REG / OP field serving either specifying a register operands or holding additional Opcode bits. The R / M field specifies either a register operands or a memory operand, depending on the content of the MOD field.

The optional SIB byte <figref>18</figref> is related basis only when the 32-bit Addressing using scale and index factors used. <figref idrefs="S28">3</figref> shows the fields of SIB bytes <figref>18</figref>, As in <figref idrefs="S28">3</figref> represented that SIB is Byte <figref>18</figref> in three Fel divided of: a SCALE field, an INDEX field and a field BASIS. The BASE field specifies which register a basic value for an address calculation contains. The INDEX field specifies which register an index value for the address calculation contains, and the SCALE field specifies the square, with the multiplying the index value is before it for along with any displacement underlying is added.

in the least significant three bits of Opcodebytes can Movie a certain registers × 86 Architecture occur, for example, the REG / OP field optional Mod R / M byte <figref>16</figref>, The R / M field of optional Mod R / M byte <figref>16</figref> or BASE and INDEX fields of optional SIB byte <figref>18</figref>, it So are four references to a register in a 86 × Instruction possible. As described above, can the three least significant bits of a Opcodebytes a register operands specify. The REG / OP and R / M fields of Mod R / M byte<figref>16</figref> can source specify and destination registers. The BASE and INDEX fields of SIB bytes<figref>18</figref> can specify registers containing base and index values ​​in the operand address calculation for memory accesses be used. It should be noted that only three of the four registers covers in a certain × 86 may occur command.

On considerable disadvantage of × 86 Architecture is the relatively small number of general purpose registers. The&lt;?page 3?&gt;X86 architecture currently defined eight 32-bit general-purpose registers: EAX, EBX, ECX, EDX, ESP, EDP, EBP, ESI and EDI. By contrast, typical RISC processors least 32 general purpose registers. A large register set allows Storing more operands in register file with relatively fast Access, rather than in a memory with a relatively slow access. Modern compilers are also capable of a greater number use of registers to a higher command level parallelism for increased superscalar Exemplary performance to accomplish. In addition to the limited number of registers is 86 × their use characterized often complicated by the compiler that most have special uses implicit in various commands.

EP-A-0942357 discloses a data processor with multiple instruction formats is compatible. A first instruction format defines a register-a predetermined size, while a second instruction format, a larger register- defined. If a received command as the first command format is detected, performs the processor the instruction using data from that in a first register file are kept. If the command as in the second instruction format is recognized presently, leads the Processor command using data from the second in a are register file contained, said first register file more includes registers than the second register file.

US-A-6014739 the applicant discloses a microprocessor having a register file, the a standard register set and an extended register set contains. A command decoder circuit receives a command extension register key field contains, which serves as a standard register field when the extension register key field a other than the extension registry key value contains.

US-A-5935240 discloses a command to transfer packed data from an extended register file and either an integer register file or a memory. The command has an opcode to which the direction of transfer with respect to extended register file specifies.

it is a central processing unit (CPU) with a register file and one connected to the register file execution core described. The Register file has a standard register set and an extended Register set. The default register set includes several standard tabs on and the extended register set includes a plurality of extended register on. Execution core fetches instructions and guides it receives and a signal indicative of an operating mode of the CPU. Execution core responding to a command by accessing at least one extended Register when the signal indicates that the CPU in an extended register mode works and the command a prefix portion has that to access the at least one extended register is required. There is a computer system will be further described, containing the CPU.

The Standard Register can its general purpose registers with a CPU architecture in conjunction defined the command. The Standard Register can in example be general purpose registers defined by the x86 architecture, and the command may be a command of the x86 instruction set. The Number of Standard Register may be less than or equal to the number of general-purpose registers to be that defined by the CPU architecture are, and the number of extended registers is greater than be the number of defined by the CPU architecture general-purpose register. In this case, the command can without the prefix area register identification information exhibit sufficient to provide a selected Standard Register. However, since the number of extended registers the number of the CPU architecture defined purpose register exceeds, can Register identification information may be insufficient to a elected extended register identify. contains the prefix portion of the command additional Register identification information for identifying a selected are extended register required. The encoding of the command, including the Präfixbereichs, can thus identify the at least one extended register, on the execution core accesses.

in one embodiment, , the standard register set on eight 32-bit general purpose registers, by the × 86 Architecture are defined. The eight 32-bit general purpose registers, for example, EAX, EBX, ECX, EDX, ESP, EDP, EBP, ESI and its EDI. Of the advanced register set, the eight 32-bit general-purpose registers of Standard set of registers and eight additional 32-bit registers that not covered by the 86 × Structure are defined. The execution core can fetch and Run × 86 commands variable length be configured.

Of the prefix area , a prefix byte for extended Register and the prefix byte can be a key field for extended comprise registers. The contents of the key field for extended register can indicate whether the prefix byte for extended Register contains the information, the need for access to the at least one extended register are. The prefix byte for the Advanced tab, the information on how to access the at least one extended register is required; only contain if the key field for extended register &lt;?page 4?&gt;a predetermined key value for extended register contains (for example, the binary Value "0100").

The CPU may include a control register for storing information, indicating whether the extended register mode generally activated is, as well as a flag register for storing information specify whether the extended register mode is activated by a current process , and generating means for generating the signal representing the Operating mode of the CPU indicates. The signal may indicate that the CPU operates in the extended register mode when the Advanced Mode tab is enabled in general and of a current process.

Of the Standard register set may have more general purpose registers by the CPU architecture (eg, x86 architecture) are defined, and the width of the extended register of extended registers set may be greater than be the width of the default tab. The width of a register the total number of bits in the register. The execution core can access the command respond by the entire contents of it at least one extended register accesses, when: (i) indicates the signal that the CPU operates in an extended register mode, (ii) the instruction a prefix area which of the access to the at least one extended register contains required information, and (iii) the prefix portion an indication of contains, that on the accessed entire contents of the at least one extended register shall be. In this way, the instruction operand sizes selectively be enlarged if the CPU is operating in the extended mode register. The standard set of registers may be a sub-set be the extended register set and the standard registers areas lower order (geringstwertig) be the extended registers.

In addition to the above-described key field the extended register, the prefix byte for extended register a Operandengrößendeaktivierungsbit exhibit. The value of Operandengrößendeaktivierungsbits specify whether the entire contents of the at least one extended Register to be accessed. It should be noted that the size of a Instruction operands the number of bits in the operand or the "width" of the operand in Bits concerns.

BRIEF DESCRIPTION OF THE drawings

<figref idrefs="S28">1</figref> is a generic format of a 86 × instruction, said × 86 Command an optional Adressiermodusbyte (Mod R / M) and an optional Scale-Index-based byte (SIB) has;

<figref idrefs="S28">2</figref> shows The fields of the Mod R / M byte of the x86 instruction from <figref idrefs="S28">1</figref>;

<figref idrefs="S28">3</figref> shows The fields of the SIB byte of the x86 instruction from <figref idrefs="S28">1</figref>;

<figref idrefs="S29">4</figref> is a diagram of an exemplary embodiment a computer system having a central processing unit (CPU);

<figref idrefs="S30">5</figref> is a diagram of an exemplary embodiment the CPUI of <figref idrefs="S29">4</figref>Wherein the CPU with a a Register file associated execution core comprising;

<figref idrefs="S31">6</figref> is a diagram illustrating the transitions between a "32-Bit Compatibility Mode" of the CPU of <figref idrefs="S30">5</figref> and a "32-bit register extension mode" (REX32) of the CPU;

<figref idrefs="S32">7</figref> is a diagram of exemplary embodiments the execution core and the register file of <figref idrefs="S30">5</figref>, in which execution core a comprising decoding unit with an execution unit and register file is connected, and wherein the register file a standard register set and has an extended register set, and the decoding unit a representative command receives, and wherein the command may contain an optional prefix portion;

<figref idrefs="S33">8</figref> is a diagram of an exemplary embodiment the optional Präfixbereichs the command from <figref idrefs="S32">7</figref>Wherein the prefix portion a prefix byte for extended Register is the key field for extended Register, a 64-bit Operandengrößedeaktivierungsbit and having three Felderweiterungsbits;

<figref idrefs="S34">9</figref> is a diagram of an exemplary embodiment the register file of <figref idrefs="S32">7</figref>Wherein the standard register set a subset of the extended register set is;

<figref idrefs="S35">10</figref> is a diagram of another embodiment the register file of <figref idrefs="S32">7</figref>Wherein the register file to Standard register set and the extended set of registers which and also a standard multimedia extension register set (MMX) an extended MMX register set, a standard streaming single-instruction multiple-data (SIMD) -Erweiterungs- or SSE register set, and an extended SSE register set comprises; and

<figref idrefs="S36">11</figref> is a diagram of an exemplary embodiment the data structure formed in the memory, the storing of Register contents during a context switch is used, whereby the data structure of the Storing the contents of the standard MMX register set, the extended MMX Re&lt;?page 5?&gt;gistersatzes, and the standard SSE register set and the extended SSE register set is used, a previously unused area of Data structure for storing the content of the extended register set is used.

indeed the invention can in various modifications and alternative embodiments be formed, however, are specific embodiments thereof in the drawings shown as examples, which described in detail below will. It should be noted, however, that the drawings and detailed Description thereof is not to limit the invention to the particular form disclosed serve, but on the contrary, it is intended all Modifications, equivalents, and cover alternatives that the spirit and scope of the present The invention according to the appended claims correspond.

Type (s) of execution of the invention

<figref idrefs="S29">4</figref> is a diagram of an exemplary embodiment a computer system <figref>30</figref> with a central processing unit (CPU) <figref>32</figref>, A North bridge <figref>34</figref>, Memory <figref>36</figref>. a Peripheriekomponentenverbindungsbus (PCI) <figref>38</figref>, A South bridge <figref>40</figref> and a Industriestandardarchitekturbus (ISA) <figref>42</figref>, The CPU <figref>32</figref> leads in the memory <figref>36</figref> Commands (for example, x86 instructions) contained. The Northbridge <figref>34</figref> provides an interface between the CPU <figref>32</figref>. the memory <figref>36</figref> and the PCI bus <figref>38</figref>, the memory<figref>36</figref> can For example, a semiconductor memory (ROM) and / or a semiconductor random access memory (RAM). The Southbridge<figref>40</figref> provides an interface between the PCI bus <figref>38</figref> and the ISA bus <figref>42</figref>,

The computer system <figref>30</figref> further comprises a first device <figref>44A</figref>. with the PCI bus <figref>38</figref> is connected, and a second device <figref>44B</figref> on, the ISA bus <figref>42</figref> connected is. The device<figref>44A</figref> can For example, an input / output device (I / O) such as a modem, be a sound card, network adapter, etc.. As in<figref idrefs="S29">4</figref> shown, , the device <figref>44A</figref> with the ISA bus <figref>42</figref> instead the PCI bus <figref>38</figref> be connected. The device<figref>44B</figref> can For example, a peripheral device such as a hard disk, Floppy disk drive, a compact disc-read only memory (CD-ROM) drive, etc.. As in<figref idrefs="S29">4</figref> shown, the apparatus may <figref>44B</figref> With the PCI bus <figref>38</figref> instead of the ISA bus <figref>42</figref> coupled be.

The CPU <figref>32</figref> obsolete (or transfers) commands from memory <figref>36</figref> about Northbridge <figref>34</figref> and executes the instructions. In the storage room<figref>36</figref> saved data can be processed by the commands. Commands and data to Addresses in memory <figref>36</figref>Wherein an address is a value of a memory location or locations in memory <figref>36</figref> identified. The addresses of instructions and data from the CPU <figref>32</figref> in front delivering to the Northbridge <figref>34</figref> be implemented. in this case, the CPU <figref>32</figref> include Adressenumsetzhardware and the memory <figref>36</figref> can store address translation information, by the CPU <figref>32</figref> virtual address translation in physical addresses are used.

how hereinafter described, the CPU <figref>32</figref> an internal Cache memory (ie, an internal cache), which for storing is formed of commands and data to which the CPU <figref>32</figref> before accessed. The computer system<figref>30</figref> may further include a have external cache for storing instructions and data is formed, to which the CPU <figref>32</figref> previously accessed has.

it is self-evident, that information as in memory <figref>36</figref> be referred stored in internal Cache of the CPU <figref>32</figref> or an external cache of the computer system <figref>30</figref> be saved can.

<figref idrefs="S30">5</figref> is a diagram of an exemplary embodiment the CPU <figref>32</figref> from <figref idrefs="S29">4</figref>, Other embodiments the CPU <figref>32</figref> are possible and intended. In the embodiment from <figref idrefs="S30">5</figref> , the CPU <figref>32</figref> an instruction cache <figref>50</figref>. an execution core <figref>52</figref>. a data cache <figref>54</figref>, An interface unit <figref>56</figref>. a decoding control unit <figref>58</figref> and a register file <figref>60</figref> on. The instruction cache <figref>50</figref> is the execution core <figref>52</figref>, of the Decoding control unit <figref>58</figref> and the interface unit <figref>56</figref> connected. Execution core <figref>52</figref> is the decoding control unit <figref>58</figref>, The register file <figref>60</figref> and the data cache <figref>54</figref> connected. The data cache<figref>54</figref> is the execution core <figref>52</figref>. the decoding control unit <figref>58</figref> and the interface unit <figref>56</figref> connected. The interface unit <figref>56</figref> is connected to the instruction cache <figref>50</figref>. the data cache <figref>54</figref>, The decoding control unit <figref>58</figref> and Northbridge <figref>34</figref> connected (<figref idrefs="S29">4</figref>).

The Decoding control unit <figref>58</figref> has a control register <figref>62</figref> on. The decoding control unit <figref>58</figref> further includes a flag register <figref>64</figref> on, the status of the CPU <figref>32</figref> reports and controls. The flag register<figref>64</figref> can a × 86 his flag register. Modern × 86 Processors have a 32-bit extended flag or "EFLAGS" register. The flag register<figref>34</figref> is Therefore, preferably, the 32-bit EFLAGS Register modern x86 processors.

General specifically, the CPU used <figref>32</figref> a processor architecture, with the × 86 Architecture is compatible, and has additional architectural features for support the 64-bit processing. The CPU<figref>32</figref> created a operation mode &lt;?page 6?&gt;in response to released information that in the control register <figref>62</figref> and in the flag register <figref>64</figref> stored.

in this connection specifies a "mode" of CPU <figref>32</figref> Default values ​​for different programmable selectable Processor attributes. specified in the embodiments described, the operating mode of the CPU <figref>32</figref> a default operand size. It should Note that the size of a Instruction operands to the number of bits in the operand or the "width" of the operand in Bits relates. In more detail below describes the coding of a command, the preset disable operand size.

at the embodiment from <figref idrefs="S30">5</figref> generates the decoding control unit <figref>58</figref> on Operation mode signal indicating an operation mode of the CPU <figref>32</figref> indicates and supplies the operation mode signal to the execution core <figref>52</figref>, the execution core <figref>52</figref> executes commands dependent on the operating mode signal (ie, the operation mode of the CPU <figref>32</figref>). The operation modes of the CPU <figref>32</figref> have a "32-Bit Compatibility Mode" and a "32-bit Registererweiterungs-" or "REX32" mode. In both amounts modes the default operand size <figref>32</figref> Bits. IM REX32 mode can Commands the preset 32-bit operand size accordingly by a 64-bit operand size change the coding of the commands as described below. how described further below, can in Felderweiterungsbits Codings of commands in REX32 mode <figref>74</figref> be provided, in order to increase the number of registers, can be referenced in the command.

Of the REX32 mode is a bit REX32 <figref>63</figref> in control register <figref>62</figref> and a "RX" bit <figref>66</figref> in the flag register <figref>64</figref> released. The REX32 bit <figref>63</figref> caused global release of REX32 Mode. The REX32 mode can for example be released when a logical value "1" in bit REX32 <figref>63</figref> saved is un dder REX32 mode can be disabled if a logical Value "0" in the bit REX32 <figref>63</figref> saved is. The REX32 bit<figref>63</figref> is preferably a code with posted a relatively high access or privilege level (eg "privileged code" as an operating system, a basic input / output system, or BIOS or Supervisor mode application).

it it should be noted that the control register <figref>62</figref> may be one of the control registers by the current state of × 86 Architecture are defined, and access can thus by known Procedures carried out. The REX32 bit<figref>63</figref> For example, a bit in one of the currently defined 32-bit control register CRO-CR4 be. Alternatively, the control register<figref>62</figref> one of the model specific registers be defined by the current state of the x86 architecture, and access can thus specific model using the existing mo Leseregister- (RDMSR) and the model-specific write register commands (WRMSR) done.

The RX bit <figref>66</figref> causes a process-specific release of REX32 Mode. One of the CPU<figref>32</figref> currently running application program (Ie, a current process) can the REX32 mode by setting the RX bits <figref>66</figref> activate. The REX32 mode must by the REX32 bit <figref>63</figref> be activated before the process by Setting the RX bits <figref>66</figref> pass into the REX32 mode can. If the REX32 mode by REX32 bit<figref>63</figref> activated is the current operation in the REX32 mode may occur by it has a logic value "1" in bit RX <figref>66</figref> stores. Only when the bit REX32 <figref>64</figref> and the RX bit <figref>66</figref> both are set, generates the decoding control unit <figref>58</figref> the the REX32 mode indicating operation mode signal. The current operation can leave the REX32 mode by a logic value "0" in the RX Bit <figref>66</figref> stores.

Two introduced here new × 86 commands be used by application programs to the RX Bit <figref>66</figref> in to set the flag register and delete. A new "STX" command stores a logic value "1" in the bit REX32 <figref>63</figref> and a new "CLX" stores command a logic value "0" in the bit REX32 <figref>63</figref>, The STX and CLX command preferably act immediately after execution of the command. The use of STX and CLX commands when not the REX32 bit <figref>63</figref> Shared (ie activate) REX32 Mode can not become a " defined opcode "exception to lead.

how described above, the mode of operation defines a preset Operand size. If the encoding of a particular instruction is not the default operand size disabled, leads execution core <figref>52</figref> operations with of operands having the default operand size. On the other hand the coding of the command, the preset Operand size deactivated leads the execution core <figref>52</figref> operations with from operand having the disable operand size.

Of the execution core <figref>52</figref> get Register operands from the register file <figref>60</figref> and fetches memory operands from the data cache <figref>54</figref>, If the memory operand in the cache can be stored and the data cache <figref>54</figref> present, supplies the Datenca che <figref>54</figref> the memory operand to the execution core <figref>52</figref>, if the memory operand are not stored in the cache and not in the data cache <figref>54</figref> present, receives the data cache <figref>54</figref> the Memory operand from memory <figref>36</figref> via the interface unit <figref>56</figref> and the Northbridge <figref>34</figref> (<figref idrefs="S29">4</figref>) And supplies the memory&lt;?page 7?&gt;operands to the execution core <figref>52</figref>,

<figref idrefs="S31">6</figref> is a graph <figref>70</figref> showing the transitions between the 32-bit compatibility mode, the one with <figref>72</figref> is designated, and with <figref>74</figref> designated REX32 the CPU mode <figref>32</figref> from <figref idrefs="S30">5</figref>, As previously described, is the default operand size both in 32-Bit Compatibility Mode <figref>72</figref>. and in REX32 mode <figref>74</figref> 32 bits. In REX32 mode but can Commands the preset 32-bit operand size by a 64-bit operand size in accordance with the codes disable the commands. As described in more detail below, may in the codes of the commands in REX32 mode <figref>74</figref> Felderweiterungsbits be provided in order to increase the number of registers on referenced in the instructions.

how in <figref idrefs="S31">6</figref> indicated, the CPU <figref>32</figref> in the REX32 mode <figref>74</figref> about, when the CPU <figref>32</figref> in 32-Bit Compatibility Mode <figref>72</figref> is working, if the general enable bit REX32 <figref>63</figref> and the process-specific enable bit RX <figref>66</figref> both having the logical value "1". As described above, may a privileged code, such as "privileged code" as an operating system, a basic input / output system, or BIOS or a supervisor mode application, a logical "1" in general enable bit REX32 <figref>63</figref> save. One of the CPU <figref>32</figref> currently running application program (ie a current process) wherein the CPU <figref>32</figref> in 32-Bit Compatibility Mode <figref>72</figref> is working, can be a logic "1" bit in the RX <figref>66</figref> save, to the REX32 mode <figref>74</figref> enter. The CPU<figref>32</figref> going from REX32 mode <figref>74</figref> in the 32 bit compatibility mode <figref>72</figref> over when either the general enable bit REX32 <figref>63</figref> or process-specific enable bit RX <figref>66</figref> logic "0". For example, the current process with the mode REX32 <figref>74</figref> working CPU <figref>32</figref> a logic "0" bit in the RX <figref>66</figref> save, to the REX32 mode <figref>74</figref> to leave and in the 32-bit compatibility mode <figref>72</figref> to return.

how turn from the <figref idrefs="S30">5</figref> be seen, the CPU can <figref>32</figref> also having a memory management unit with paging hardware to a paging address translation of virtual addresses into physical addresses to implement. A "virtual Address "is a before the reaction by an address translation mechanism (for example, a Paging mechanism) generated in a "physical address" address, which for the access to a memory address is actually used. The paging hardware may include a Umysetzungs lookaside buffer (TLB) have to save Page conversions.

Of the instruction cache <figref>50</figref> is a high speed memory for Storing instructions. Execution core<figref>52</figref> get Instructions from the instruction cache <figref>50</figref> for execution. Of the instruction cache <figref>50</figref> may use any suitable cache organization, including direct mapped, set associative and fully associative configurations. If not a requested instruction in the instruction cache <figref>50</figref> present, can the instruction cache <figref>50</figref> with the interface unit <figref>56</figref> communicate, to obtain the requested command. Such communication can fill / Replace a Cachetzeile in the instruction cache <figref>50</figref> to lead. Moreover, the instruction cache<figref>50</figref> with the Memory management unit communicate to physical address translations virtual to get addresses from the instruction cache <figref>50</figref> were brought.

Of the execution core <figref>52</figref> executes the instruction cache <figref>50</figref> Brought from commands. Execution core<figref>52</figref> receives register operands from the register file <figref>60</figref> and stores register values ​​result in the register file <figref>60</figref>, the size of the operands depends on the Operating mode of the CPU <figref>32</figref> and can as described by Commands are disabled. Execution core<figref>52</figref> obtained from memory operand the data cache <figref>54</figref> and provides memory result values the data cache <figref>54</figref>As described in the following.

Of the execution core <figref>52</figref> can have any suitable construction. For example, the execution core<figref>52</figref> a "super pipeline" core, a superscalar Core or a combination thereof. Execution core<figref>52</figref> can depending on the choice of design a carrying out of order or use according to the order.

Of the data cache <figref>54</figref> is a high speed memory for storing of data. The data cache<figref>54</figref> may use any suitable cache organization, including direct mapped, set associative and fully associative configurations. If the value of a memory operand is not in the data cache <figref>54</figref> available is the data cache can <figref>54</figref> with the interface unit <figref>56</figref> communicate to accessing the memory operand. Such communication can for filling / Replace Cache line in the data cache <figref>54</figref> to lead. If the data cache<figref>54</figref> a Writeback cache Procedure pursued, can superseded updated cache lines of the interface unit <figref>56</figref> to the write back fed into the memory will. The data cache<figref>54</figref> can communicate with the memory management unit, to physical address translations for the data cache <figref>54</figref> delivered obtain virtual addresses.

The interface unit <figref>56</figref> communicates with the Northbridge <figref>34</figref> (<figref idrefs="S29">4</figref>). In response to requests from the instruction cache <figref>50</figref>. receives the instructions from the memory interface unit <figref>36</figref> (<figref idrefs="S29">4</figref>) On the North bridge <figref>34</figref> and supplies the commands to the Be&lt;?page 8?&gt;lack cache <figref>50</figref>, the interface unit <figref>56</figref> also transmits memory operand between the Northbridge <figref>34</figref> and the data cache <figref>54</figref>. Like previously described.

<figref idrefs="S32">7</figref> is a diagram of exemplary embodiments the execution core <figref>52</figref> and the register file <figref>60</figref> the <figref idrefs="S30">5</figref>, in which embodiment the <figref idrefs="S30">5</figref> , the execution core <figref>52</figref> a decoding unit <figref>76</figref> on, with an execution unit <figref>78</figref> and the register file <figref>60</figref> connected is. in<figref idrefs="S32">7</figref> is the decoding unit <figref>76</figref> as a representative command <figref>80</figref> receiving shown. The command<figref>80</figref> is preferably a 86 × command and may include an optional prefix portion <figref>82</figref> exhibit. As described below, the prefix portion includes information that for the Access to the at least one extended register required are.

The Decoding unit <figref>76</figref> recognizes each register source operand reference in commands and calls on the operand values ​​from the register file <figref>60</figref>, the register file <figref>60</figref> transmits the requested Source operand values ​​to the execution unit <figref>78</figref>, simultaneously (For example, during the same clock cycle), the decoded instruction by the decoding unit <figref>76</figref> to execution unit <figref>78</figref> be transmitted. In this way, the decoded instruction and the operands are usually to the execution unit <figref>78</figref> to same time (for example during the same clock cycle) transfer.

The execution unit <figref>78</figref> resulting decoded instructions from that of the decoding unit <figref>76</figref> to be delivered. The execution unit <figref>78</figref> can to the formation of addresses for Memory operands are used and the memory operand address to the data cache <figref>54</figref> supply (<figref idrefs="S30">5</figref>). As previously described above, the data cache can <figref>54</figref> for delivering memory operand to the execution unit <figref>78</figref> responsible be. The data cache<figref>54</figref> the memory operand address to deliver paging hardware in the memory management unit to implement these virtual addresses into physical addresses to leave. If the value of a memory operand is not in the data cache<figref>54</figref> available is the data cache can <figref>54</figref> the memory operand address to the interface unit <figref>56</figref> transmitted to them via the Northbridge <figref>34</figref> (<figref idrefs="S29">4</figref>) In the storage room (<figref idrefs="S29">4</figref>find permit).

The execution unit <figref>78</figref> provides each result of the instruction execution either to the register file <figref>60</figref> or to the data cache <figref>54</figref> (<figref idrefs="S30">5</figref>). If the result is a tab to be stored value, provides the execution unit <figref>78</figref> the Result to the register file <figref>60</figref>, if the result of is a memory location to be stored value, provides the execution unit <figref>78</figref> the Result and the corresponding address of the storage location to the data cache <figref>54</figref>, if the contents of the storage location is not in the data cache <figref>54</figref> available is the data cache can <figref>54</figref> the result and the corresponding address the location of the interface unit <figref>56</figref> supply. The interface unit <figref>56</figref> can have the value at the corresponding Memory location of the memory <figref>36</figref> (<figref idrefs="S29">4</figref>) about the Northbridge <figref>34</figref> (<figref idrefs="S29">4</figref>) Store.

at the embodiment after <figref idrefs="S32">7</figref> , the register file <figref>60</figref> a standard set of registers <figref>84</figref> and an extended register set <figref>86</figref> on. The standard set of registers<figref>84</figref> comprises eight 32-bit general-purpose registers EAX, EBX, ECX, EDX, ESP, EDP, EBP, ESI and EDI represented by the × 86 Architecture are defined. The extended register set<figref>86</figref> can For example, eight additional or Advanced Regi art exhibit. As described below, can they extended registers of extended register set <figref>86</figref> 64-bit its register.

Of the command <figref>80</figref> an × 86 his command of 3 bits register operands identifying information has to each of which it refers only eight × identify 86 general-purpose registers. The number of extended registers in the extended register set <figref>86</figref> exceeds However, the eight general purpose registers defined by the x86 architecture. Therefore, the 3 bits of register operands identifying information the command <figref>80</figref> for identifying a selected one of the eight × 86 General purpose registers are used, insufficient to a selected one of the extended registers identify. The prefix portion<figref>82</figref> of command <figref>80</figref> therefore serves to provide an additional register identification information, the need for identifying a selected extended register are. The coding of the command,<figref>80</figref>, Including Präfixbereichs <figref>82</figref>. can thus identify each specified therein extended register.

If the CPU <figref>32</figref> (<figref idrefs="S30">5</figref>) Operates in mode and REX32 the command <figref>80</figref> a register source operands identified However, no optional prefix portion <figref>82</figref> having, Calls for the decoding unit <figref>76</figref> the content of a corresponding Standard register set <figref>84</figref> from the register file <figref>60</figref>, the execution of command <figref>80</figref> then takes place using the standard register the standard register set <figref>84</figref> the register file <figref>60</figref>, On the other hand, the CPU <figref>32</figref> works in REX32 mode and the command <figref>80</figref> the optional prefix portion <figref>82</figref> having and refers to a register source operands, calls the decoding unit <figref>76</figref> the Content of a corresponding extended register the extended register set <figref>86</figref> from the register file <figref>60</figref>, the execution the command <figref>80</figref> is carried out using the extended Register of register set <figref>86</figref> the register file <figref>60</figref>,

The Decoding unit <figref>76</figref> may generate an operand size signal and the execution unit <figref>78</figref> supply, the operand size of the instruction <figref>80</figref> indicates. The decoding unit <figref>76</figref> can do that from &lt;?page 9?&gt;Decoding control unit <figref>58</figref> generated and the operation mode of the CPU <figref>32</figref> received indicating operation mode signal. When the operation mode signal indicates that the CPU <figref>32</figref> in REX32 Mode, and the command <figref>80</figref> a prefix portion <figref>82</figref> having, , the decoding unit <figref>76</figref> For example, the operand size signal activate, indicating that the operand size for instruction <figref>80</figref> 64 Bit is. When the operation mode signal indicates that the CPU <figref>32</figref> in REX32 Mode, and the command <figref>80</figref> no prefix area <figref>82</figref> having, , the decoding unit <figref>76</figref> For example, the operand size signal disable, indicating that the operand size for instruction <figref>80</figref> 32 Bit.

If the operand size signal is enabled, the execution unit <figref>78</figref> operations perform 64-bit operands. The execution unit <figref>78</figref> can 64-bit extended register operands from the register file <figref>60</figref> receive and 64-bit extended register result values ​​in the register file <figref>60</figref> save. Alternatively, if the operand size signal is disabled, the execution unit <figref>78</figref> operations run with 32-bit operands. The execution unit <figref>74</figref> can 32-bit register operands from the register file <figref>60</figref> receive and 32-bit register result values in the register file <figref>60</figref> save.

The execution unit <figref>78</figref> can the 32-bit memory operand values ​​that distinguish them from the data cache <figref>54</figref> receive has, with leading zeros "cushion" to 64-bit operands to build. The execution unit<figref>78</figref> can Further, the lower order (ie, the geringswertigen) 32 bits of the 64-bit memory result values ​​for storing the data cache <figref>54</figref> supply. Alternatively, the execution unit <figref>78</figref> the Operand size signal to the data cache <figref>54</figref> supply, and the sizes of the Memory operand, the execution core between the <figref>52</figref> and the data cache <figref>54</figref> transfer be able of the operand size signal depend. For example, if the operand size signal is activated, the execution unit <figref>78</figref> 64-bit Memory operands from data cache <figref>54</figref> receive and can 64-bit memory result values to the data cache <figref>54</figref> transfer. Alternatively, if the operand size signal is disabled, the execution unit <figref>78</figref> 32-bit Memory operands from data cache <figref>54</figref> receive and can 32-bit Memory result values ​​to the data cache <figref>54</figref> supply.

The Decoding unit <figref>76</figref> may further include an exception signal in response to the operating mode signal and the presence or absence of the Präfixbereichs <figref>82</figref> in the command <figref>80</figref> produce. If the command<figref>80</figref> a prefix portion <figref>82</figref> having, and the operation mode signal indicates that the CPU <figref>32</figref> not works in REX32 mode, the decoding unit <figref>76</figref> for example activate the exception signal. The activated exception signal can an exception "device unavailable "lead.

<figref idrefs="S33">8</figref> is a diagram of an exemplary embodiment the optional Präfixbereichs <figref>82</figref> of command <figref>80</figref> from <figref idrefs="S32">7</figref>, In the embodiment the <figref idrefs="S33">8</figref> is the prefix portion an expanded Registerpräfixbyte <figref>90</figref> With an extended register key field <figref>92</figref>. a 64-bit Operandengrößendeaktivierungsbit <figref>94</figref> and three Felderweiterungsbits <figref>96</figref>. <figref>98</figref> and <figref>100</figref>, The extended register key field <figref>92</figref> takes the bits 4-7 the extended Registerpräfixbytes <figref>90</figref> on, and a binary Enhanced registry key value "0100" in the extended register key field <figref>92</figref>. as in <figref idrefs="S33">8</figref> illustrated, the identification of the extended serving Registerpräfixbytes <figref>90</figref>, the decoding unit <figref>76</figref> recognizes the advanced Registerpräfixbyte <figref>92</figref> on the extended register key value "0100" in the extended register key field <figref>92</figref>, when the extended register key field <figref>92</figref> no extended register key value "0100" which recognizes the decoding unit <figref>76</figref> the prefix byte not as advanced Registerpräfixbyte.

The 64-bit Operandengrößendeaktivierungsbit <figref>94</figref> has 3 bits of the extended Registerpräfixbytes <figref>90</figref> on. The 64-bit Operandengrößendeaktivierungsbit <figref>94</figref> can For example, to disable the default 32-bit operand size of the instruction <figref>80</figref>. of the extended Registerpräfixbyte <figref>90</figref> contains, used will (<figref idrefs="S32">7</figref>), So that 64-bit register operand in the register file <figref>60</figref> is accessed (<figref idrefs="S32">7</figref>). The Felderweiterungsbits <figref>96</figref>. <figref>98</figref> and <figref>100</figref> can to Extending 3-bit fields in an opcode, a Mod R / M byte and / or an SIB byte of the instruction <figref>80</figref> serve on 4 bits, whereby it can be accessed 16 registers instead. 8 The Felderweiterungsbits<figref>96</figref>. <figref>98</figref> and <figref>100</figref> can thus to increase the number of general-purpose register in the CPU <figref>32</figref> serve (<figref idrefs="S29">4</figref> and <figref idrefs="S30">5</figref>).

If the CPU <figref>32</figref> located in REX32 mode, the command <figref>80</figref> the having erweitete Registerpräfixbyte, the extended register key field <figref>92</figref> the extended Registerpräfixbytes <figref>90</figref> the extended register key value "0100", and said 64-bit Operandengrößendeaktivierungsbit <figref>94</figref> of advanced Registerpräfixbytes <figref>90</figref> logic "0", it is assumed that the register operand in the instruction sizes <figref>80</figref> the have preset 32 ​​bits, and there are 32-bit register operands for the command <figref>80</figref> from the register file <figref>60</figref> fetched. If on the other hand the value of the 64-bit Operandengrößendeaktivierungsbit <figref>94</figref> logic "1", is the pre-set 32-bit Operand size for instruction <figref>80</figref> disabled and there are 64-bit operands the command <figref>80</figref> from the register file <figref>60</figref> fetched.

The Felderweiterungsbits <figref>96</figref>. <figref>98</figref> and <figref>100</figref> to take respectively, the bits 2, 1 and 0 of the extended &lt;?page 10?&gt;Registerpräfixbytes <figref>90</figref> on. The Felderweiterungsbit <figref>96</figref> For example, use are to the Mod R / M byte REG field from three to four bytes expand, whereby an expanded REG field is formed. The Felderweiterungsbit<figref>96</figref> can the most his bit of the extended REG field. During the 3-bit field to REG Access to one of 8 different registers in the register file <figref>60</figref> used is the 4-bit Advanced REG field can to access a of 16 different registers within the register file <figref>60</figref> used will.

The Felderweiterungsbit <figref>98</figref> For example, to expand the SIB byte IN-DEX Field used by three bits to four, whereby an expanded formed IN-DEX field becomes. The Felderweiterungsbit<figref>98</figref> can the most his bit of the extended INDEX field. During the 3-bit field INDEX to access one of 8 different registers in the register file <figref>60</figref> used is the 4-bit Advanced INDEX field can to access a of 16 different registers within the register file <figref>60</figref> used will.

The Felderweiterungsbit <figref>100</figref> For example, to expand the Mod R / M byte R / M field, the SIB byte BASIS box or Opcoderegisterreferenzfelds three bits are used to four, whereby an extended field is formed. The Felderweiterungsbit<figref>100</figref> can the most his bit of the expanded field. During the 3-bit field to access to one of 8 different registers in the register file <figref>60</figref> used is the 4-bit field is extended to access one of 16 different registers within the register file <figref>60</figref> used will.

<figref idrefs="S34">9</figref> is a diagram of an exemplary embodiment the register file <figref>60</figref> the <figref idrefs="S32">7</figref>, in which the standard register set <figref>84</figref> a subset of the extended register rate <figref>86</figref> is. As described above, includes the standard set of registers<figref>84</figref> the eight 32-bit general-purpose registers EAX, EBX, ECX, EDX, ESP, EDP, EBP, ESI and EDI, the 0-7 are numbered. The extended register set<figref>80</figref> has sixteen 64-bit registers, the 0-15 are numbered. The 32-bit register 0-7 of the standard register set<figref>84</figref> form 32-bit Areas of lower order (ie, least significant areas) of respective 64-bit register 0-7 the extended register set <figref>86</figref>, as in<figref idrefs="S34">9</figref> shown, is the extended register set <figref>86</figref> the standard register set <figref>84</figref> superior.

<figref idrefs="S34">9</figref> shows Further, the effect of the extended Registerpräfixbytes <figref>90</figref> the <figref idrefs="S33">8</figref> on Register within the register file <figref>60</figref>, Bits 0-2 (Felderweiterungsbits<figref>100</figref>. <figref>98</figref> and <figref>96</figref>) the extended Registerpräfixbytes <figref>90</figref> enable it command <figref>80</figref>, The selected tab of the extended register set <figref>86</figref> to identify. If the bit<figref>3</figref> (ie the 64-bit Operandengrößendeaktivierungsbit <figref>94</figref>) the extended Registerpräfixbytes <figref>90</figref> is deleted (Ie, a logic "0"), only on the (Least significant) 32 lower order bits of the extended register in the extended register set <figref>86</figref> accessed. If the bit<figref>3</figref> (Ie 64-bit Operandengrößendeaktivierungsbit <figref>94</figref>) of advanced Registerpräfixbytes <figref>90</figref> however is set (ie, a logic "1"), is applied to the entire 64 bits of the extended registers in the extended register set <figref>86</figref> accessed.

On Problem is when you implement the extended register set <figref>86</figref> the register file <figref>60</figref> (<figref idrefs="S32">7</figref>) To the effect occur that a 32-bit CPU operating system <figref>32</figref> (<figref idrefs="S30">5</figref>) Most likely the extended register does not know and does not attempt to extended registers with context changes to preserve. The<figref idrefs="S35">10</figref> and <figref idrefs="S36">11</figref> serve hereinafter the description of a system and method for preserving the contents of the extended register of the extended register set <figref>86</figref> when context changes when the CPU <figref>32</figref> ( <figref idrefs="S30">5</figref>) comprising a 32-bit operating system. It should be noted that in this Representation of the standard MMX register set <figref>110</figref> and the standard SSE register set <figref>114</figref> similar to Standard register set <figref>84</figref> can be expanded as described above (as well as the extended register sets <figref>112</figref> and or <figref>116</figref>. if available). In a context change causes the operating system that the CPU <figref>32</figref> execution completed the instructions of a first program and the commands of execute second program starts. The operating system spei chert the state of the CPU<figref>32</figref> during the Context change, So that the instruction execution the first program at a later Time can be re-initiated. The 32-bit operating system can, however, in ignorance of the extended registers of register set <figref>86</figref> be, as described previously, and therefore does not attempt the extended register while the context change.

<figref idrefs="S35">10</figref> is a diagram of another embodiment the register file <figref>60</figref> the <figref idrefs="S32">7</figref>, in which the register file <figref>60</figref> as described a standard register set <figref>84</figref> and an extended register set <figref>86</figref> having. In the embodiment of<figref idrefs="S35">10</figref> has the register file <figref>60</figref> also a standard multimedia extension register set (MMX) <figref>110</figref>, An extended MMX register set <figref>112</figref>. a standard streaming single-instruction multiple-data (SIMD) -Erweiterungs- or SSE register set <figref>114</figref>. and an extended SSE register set <figref>116</figref> on.

at a context switch stores a typical 32-bit operating system Status information about the CPU <figref>32</figref>That to restore the interrupted Program or the tasks required in a task state segment (TSS) or the stack of the program, (explicitly) in the memory &lt;?page 11?&gt;<figref>36</figref> educated is (<figref idrefs="S29">4</figref>). The TSS contains the contents of the general-purpose register EAX, EBX, ECX, EDX, ESP, EDP, EBP, ESI and EDI before context switch and contains Thus the content of the standard register of the standard register set <figref>84</figref>, As described above, the 32-bit operating system is probably in ignorance of the extended registers of extended register set <figref>86</figref> (and the extended register sets <figref>112</figref> and <figref>116</figref>) and therefore does not attempt the content of the extended register of register set <figref>86</figref> while to save the context switch.

The 32-bit operating system probably uses the available × 86 "FXSAVE" command to the Context change the content of the standard MMX registers the standard MMX register set <figref>110</figref> and the standard SSE register the standard SSE register set <figref>114</figref> in a specific 512-byte store data structure in memory <figref>36</figref> educated is. The 32-bit operating system probably uses the available × 86 "FXRSTOR" command to the content the standard MMX registers the standard MMX register set <figref>110</figref> and the standard SSE register the standard SSE register set <figref>114</figref> restore, the bytes in a special data structure 512 using the FXSAVE Be command has been saved. Usually, the Commands FXSAVE and FXRSTOR in the CPU <figref>32</figref> by microcode be implemented. In one embodiment, this microcode extended to the content of the extended register sets <figref>86</figref>. <figref>112</figref> and or <figref>114</figref> to Save (and restore). Thus, the 32-bit operating system, the the × 86 Commands FXSAVE and FXRSTOR to save and restore the Content of the standard MMX registers the standard MMX register set <figref>110</figref> and the standard SSE register the standard SSE register set <figref>114</figref> when context changes points out, also storing the content of the extended register set <figref>86</figref>. the extended MMX register set <figref>112</figref> and the extended SSE register set <figref>116</figref> cause.

<figref idrefs="S36">11</figref> is a diagram of an exemplary embodiment one with <figref>120</figref> designated special 512-byte data structure, which formed in the memory and to store register contents serves (conventionally the standard MMX registers and the standard SSE registers in the x86 architecture). The data structure <figref>120</figref> has an unused area <figref>122</figref> and a previously unused area <figref>124</figref> on. The standard MMX registers data area<figref>126</figref> and the standard SSE register data area <figref>130</figref> consist in use Area <figref>122</figref> for storing the contents of the registers of Standard MMX register set <figref>110</figref> and the register of the standard SSE register set <figref>114</figref> (<figref idrefs="S35">10</figref>). As in <figref idrefs="S36">11</figref> illustrated, the above- unused area <figref>124</figref> the data structure 120 for storing the contents of the extended register sets <figref>86</figref>. <figref>112</figref> and <figref>116</figref> at context Switches in storage areas <figref>134</figref>. <figref>135</figref> and <figref>136</figref> serve. In this way, the 32-bit operating system that the 86 × FXSAVE and FXRSTOR commands for saving and cons producing content the standard MMX and SSE registers in executing context switching, also save and restore the contents of the extended register sets.

Industrial applicability

The Invention is generally to integrated circuits and power saving applicable in integrated circuits.