Flat panel display unit having pixel activation by low voltage signals

The invention relates to a device for controlling the current for a field emission display device having a number of Feldemit tern and a method for producing such a field emission Display device.

In a field emission display device, it is a Flat panel display, especially a matrix-Flachtafelan display device, connected in the high pixel activation voltages Need to become. There are row and column signal voltages allowed light, the usual with conventional CMOS, NMOS or other integrated circuits with respect to the logic voltage level kom are compatible with also much higher pixel activation voltages be achieved.

About half a century, the CRT was (CRT) the display device for visualization of information per se. If already CRTs in this period with regard to their specially len properties have been significantly improved, in particular as regards Color, brightness, contrast and resolution, these devices remained after still bulky and power consuming to a great extent. With the advent of portable computers rose accordingly the Bedürf nis, display means to have available not only by itself light weight and compact design are distinguished, but can be also operated at low power. Although currently practically laptop computers anywhere Flüssigkristallanzeigevor devices are used, but these suffer from a low Contrast, compared with cathode ray tubes, a limited Viewing angle range, a considerable power specifically is added at the color versions of these display devices, so that their use for battery operation hardly advisable. Compared to CRTs same screen size, the liquid crystal Color display devices considerably more expensive.

concentrating Because of the disadvantages of liquid crystal display devices the developments in the industry centered heavily on the thin layer-field emission display devices. Flat panel displays, which in this technology are carried out, have a matrix-addressable Field of pointed thin-cold field emission cathodes in Combination with a phosphor screen. The phenomenon of field emission was discovered in the fifties, and considerable For mixtures by many people, for example, Charles A. Spindt SRI International, has improved the technology such that the Prospects, cheap, little power receiving, by high On resolution and high contrast distinguishing flat full color Anzeigevor be able to manufacture devices, are promising. However, it remains yet to do a lot of work to the technology to target kommer promote len readability.

There are a number of problems in connection with the presently verfüg ble matrix-field emission display devices. earlier such display devices were constructed so that a Spaltensig nal a single conductive strip activated within the grid, while a series signal a conductive strip within the emitter Base electrode activated. At the intersection of an activated column an activated row then there is a grid-emitter Spannungsdiffe Renz, sufficient to induce field emission, with the consequence that the associated phosphor in the phosphor screen on shines. In<b>Fig.</b> 1 which is a representative illustration of the construction such a device is, three grid strips (Git Cut ter) <b>11</b>A, <b>11</b>B and <b>11</b>C with a trio of emitter Basiselektroden- (Row) strips <b>12</b>A, <b>12</b>B and <b>12</b>C. In this illustration, each Row-column interface (the equivalent of a single pixel or Pixel within the display device) sixteen field emission cathode (hereinafter "emitter") <b>13</b>, In practice, the number vary greatly from emitter tips per pixel. The tip of each Emitter tip is surrounded by a lattice strip opening <b>14</b>, In order to a field emission takes place, the voltage difference between one must Row conductor and a column conductor to be at least as big as a Voltage corresponding to the acceptable field emission levels. Inten sity of field emission is highly dependent on several factors, of which the most important is the sharpness of the cathode emitter tip and the Strength of the electric field at the tip. Although a for Operation of flat panel display devices suitable level of field emission achieved with emitter-grid voltages of only 80 volts was (it is expected that this number in the coming years by further improvements in the structure of the emitter and Improvements in manufacturing technology reduces), the Emission voltages still substantially greater than in the future be 5 volts, the standard level "1" in the CMOS, NMOS and TTL technology equivalent. Thus, when the field emission thresholds voltage is 80 volts, the row and column lines must are designed to between 0 and either +40 or -40 volts can switch to an interface voltage difference of 80 Volt to come. Consequently, it is necessary to use a high voltage in order turn elicit these row and column lines. There are Consequently, not only the problem suitable driver for switching in such a way to develop high voltages, but one must also use the Problem of excessive power consumption concerned, caused by the capacitive coupling of row and column conductors. That is, the higher the voltage on the lines, the greater the power to Driving the display device is required.

An example in which the light emission to achieve a Benö preferential voltage must be switched by means of switching transistors, is made DE 27 56 354 C2, there, however, for a gas-discharge display device having arrayed gas discharge cells.

What is needed is a type of Feldemissionsanzeige- Architecture, the überwin the problems of switching high voltages det and significantly alleviates the problem of emitter mesh shorts and moreover, the power consumption of the display device decreased puts.

From DE 41 12 078 A1 discloses a field emission display device is known in which between the field emitter of each pixel and Mass a drive transistor is connected, the function of controlled charging voltage of a capacitor conductive or non-conductive becomes. Here, the capacitor between the gate and source of the drive and transistor switched by means of a charging transistor, with which it in Series is connected, open and discharged. The gate terminal of Ladetran sistor is connected to the column conductor and whose drain terminal is connected to the connected row conductor of the associated pixel. The source of the Charging transistor is verbun to the gate terminal of the driver transistor the. The two transistors do not need the relatively high Feldemis sion to switch voltage only column and row conductor signals which may be much lower than the field emission voltage.

The invention is based on the object at a field emission Display device of the type mentioned to provide a stable stream of pixels.

This object is achieved according to a device according to claim 1 and treated with a method for producing a field emission display device according to claim 4, further developments are in the dependent claims.

According to the invention, a Stromregulierwiderstand a Transistor channel controllably coupled with at least one field emitter. The transistor channel can be part of two series-connected Niedrigvolt- be switching MOSFETs. The resistor is connected directly to a negative coupled power supply terminal as a ground rail. one achieved stable current values ​​regardless of the cathode voltage within a wide range of cathode voltages.

in one embodiment, a field emission display device switched the channels of the two transistors of each pixel in row and the control electrodes of the two transistors of the respective verbun pixel with the Reihenadreßleiter or the column address the.

That the channels of two transistors of a pixel are connected in series are, opens the possibility of both transistors in common with a seed channel produce. Therefore it is much chip space can be saved connected in comparison with a control circuit comprising two cascaded Transistors (DE 41 12 078 A1), the only two separate channels can be produced. For a display device having a very large number pixels and a correspondingly large number Transisto ren is such a saving in chip space is of great importance. With the series circuit of the invention of the two transistors of a each pixel, therefore, the distance between the individual pixels significantly reduced and corre the resolution of the display device accordingly be increased.

In one embodiment, the column address and Rei are henadreßleiter used at least one pair of wired in series to control connected field effect transistors (FETs), each pair in conducting state, the base electrode of a single emitter node with a potiential couples, which is sufficiently low with respect to a constant, applied to the grid potential to field emission to induce. Each row / column interface (ie each pixel) internal half of the display device may include a plurality of emitter node to improve the production yield and product reliability. In a preferred embodiment, the grid the field is on a constant potential (V_FE) Held, which is consistent with reliable field emission when the emitter to ground potential lie. Individual bases can via a pair of series connected FETs are thereby connected to ground, that a signal voltage to both the row and to the Column lines sets that belong to this emitter node. One of the in Series connected FETs is indicated by a signal on the row line controlled, the other FET is controlled by a signal on the column line controlled. For the avoidance of doubt, that in a preferred Ausfüh ment of the invention, each pixel multiple emitter node contains and each emitter node having a plurality of cathode emitter. For each row / column interface controls several pairs of in Series connected FETs and each pair controls a single emitter node that contains multiple emitters.

In one embodiment, the grid of each emitter base is isolated. A pixel is turned off (ie, in a non-emitting state accommodated) by connected either or both in series FETs are turned off. From the moment in which at least one of the FETs is non-conductive (that is, the gate voltage V_GS under the Component-threshold voltage V_T drops), electrons are injected from the this pixel derived corresponding emitter tips or discharged until the voltage difference between the base and the lattice just un is below the emission threshold voltage.

In another embodiment of the invention, each emitter base node via a current limiting field effect transistor with coupled grating, wherein the transistor comprises a continuous low- and current path represents a threshold voltage of V_T owns. While the base usually at a potential of V_GRID - V_T lies, enough the voltage difference between the grid and each emitter (in generally below one volt) of not hervorzuru a field emission fen. However, when the emitter-base through a ground path formed by the two series-connected FETs on a row and column section spot is controlled, is connected to ground, field emission occurs. So that the ground path is active, both row and column must switched FETs at the same time (ie, the gate voltage at each Field effect transistor must be greater than the component threshold tension Regulation). The use of current-limiting transistors for coupling each emitter base node to the grid on demand, provides a precise switching timing.

A brightness control can be achieved by mixing the Gate voltages of each FET varies in the ground path, which in turn, the emission current is set.

In all embodiments of the invention the current is for each pixel via the series-connected FETs in at least one Emitter electrode ground path regulated. This feature improves in strong measure the uniformity of brightness over the entire On display surface away. Control of the brightness level is carried out in a fold manner by varying the gate voltage of each of FETs. In addition, the low-voltage switching improves the pixel-level Operating speed of the display devices. If one uses the Architecture, in which a display row line is activated and all Columns are activated simultaneously, so can be a shade of gray achieved by that the duty ratio in each column signal during the period of activation of the row line varied.

Embodiments of the invention using the be Drawing explained. Show it:

<b>Fig.</b> 1 is a simplified perspective view of the structure the grid and emitter base electrodes in a conven union flat panel field emission display device;

<b>Fig.</b> 2 is a schematic representation of a first embodiment form a single emitter node of a field emission Display device without resistance invention, wherein the emitter-base electrode separated from the grating is;

<b>Fig.</b> 3 is a schematic diagram of a second embodiment, a single emitter node of a field emission Ad vortexed direction without resistance invention, wherein a current-limiting transistor, the Emitterbasiselek electrode connects to the grid;

<b>Fig.</b> 4 is a schematic representation of a third embodiment form a single emitter node of a field emission display device with a current according to the invention regulating resistance;

<b>Fig.</b> 5 is a plan view of a possible layout for a flat panel display architecture barbless invention stand, which is apparent from the illustration, as a plurality of Emitter node in a single row-column interface (Ie, a single pixel) can be installed; and

<b>Fig.</b> 6 is a plan view of a possible layout for a field emission display device according to the invention with Stromregulierwiderstand.

According to <b>Fig.</b> 2, an embodiment of a field emission display device without resistance according to the invention, is a single Emitter node with a (first as a pixel element designated) conductive grid <b>21</b> provided, which extends over the entire field kon extends continuously and at a constant potential V_GRID kept becomes. Each pixel element within the field is determined by an emitter group is lighted. To ensure that product reliability and to improve production yields, each emitter group of several ren emitter nodes, each node in turn several Feldemis contains sion cathode (also known as "field emitter" or "emitter" be draws). Although the single emitter node according<b>Fig.</b> 1 only three emitters <b>22</b>A, <b>22</b>B, <b>22</b>C, the number may in practice much be higher. Each of the emitter<b>22</b> is connected to a base electrode <b>23</b> is closed, together for only the emitter of an individual Emit is terknotens. The combination of emitters and base electrode also referred to herein as a second pixel element.

In the in <b>Fig.</b> 2 illustrated embodiment, the Basiselek electrode <b>23</b> from the grating <b>21</b> separated. To induzie a field emission ren, the base electrode <b>23</b> via a pair of transistors connected in series (Field effect transistors) Q_C and Q_R grounded. The transistor Q_C is a column line signal S_C open controlled while the transistor Q_R by a row line signal S_R is piloted open. The usual logic signal voltages for CMOS, NMOS, TTL and other technologies integrated circuits be consistently 5 Volts or less and can find both the column and the be hergenommen row line signal. It should be noted that the transistor Q_C may be replaced by two or more wired in series switched FETs that all controlled by the same column line will. Similarly, the transistor Q_R by two or more FETs connected in series to be replaced, all of which, of dersel ben row line are controlled. Similarly, other can controlled by control logic FETs in series within the grounding path be arranged. A pixel (picture element) is characterized off (d. h. accommodated in the non-emitting state), that either one or both of the series connected FETs (Q_C and Q_R) turned off.

From the moment at which at least one of the non-conductive FETs (that is, the gate voltage V_GS among the structural thresholds voltage value V_T drops), electrons from the emitter tips, the pixels that correspond, exhausted to the point until the Spannungsdiffe difference between the base and the grid just below the emission Threshold voltage value is.

<b>Fig.</b> 3 shows a further embodiment of an emitter node without Resistance according to the invention, the emitter node operatively and from the structure according to the first embodiment of the emitter node <b>Fig.</b> 2 is similar. The main difference is that the base electrode <b>23</b> to the grid <b>21</b> via a current limiting n-channel Field effect transistor Q_L, The threshold voltage V_T has, gekop pelt is. Both the drain and the gate of the transistor Q_L are directly connected to the grid <b>21</b> coupled. The channel of the transistor Q_L is dimensioned such that the current is only at such a value be is limited, which is required to the base electrode <b>23</b> and delivered impaired emitter <b>22</b>A, <b>22</b>B and <b>22</b>C reset to a potential, substantially equivalent to a value V_GRID - V_T is similar, with a Rate sufficient, adequate gray gradation on to ensure solution.

<b>Fig.</b> 4 shows a single emitter node similar to the first Ausfüh embodiment according <b>Fig.</b> 2, but here with the emitter node via a pair of series-connected field effect transistors Q_C and Q_R and also has a current regulating resistor invention R is grounded. The resistor R is connected between the source of transistor Q_R and mass. In the likely event that the Grid voltage is greater than 20 volts, it is necessary that the grating <b>21</b> at night vi lying first MOSFET device (in this case, the MOSFET Q_C) be a high-voltage device, a cathode-substrate to prevent breakthrough. The breakdown of such security High voltage transistor depends on the voltage range of the emitter knot.

As in the <b>Fig.</b> 2, 3 and 4, situated in series with the lowering Current path from the base electrode <b>23</b> via the transistors Q_C and Q_R leading to mass, a fusible link FL. These fusible Connection (fuse) may FL Runaway during testing of the device be burned when a grid-emitter short-circuit within this Emitter group is present, so the shorted group from the rest to separate the field and so raise the device yield and to reduce power consumption of the display panel. It should noted that the position of the fuse within the power FL path without impact, as far as it concerns the circuit technology. That is, the purpose of separating a shorted node, is achieved regardless of whether the fuse between the transistors Q_C and Q_R, Between the base electrode <b>23</b> and on Mass leading transistor pair, as in <b>Fig.</b> 2 is shown, or located between ground and the transistor pair to ground.

Referring again to <b>Fig.</b> 2, 3 and 4 it should be noted that the Gray scale (ie varying the pixel lights) in a working display device thereby can take place, that the Duty cycle or the duty cycle (the time period in which the emitter within a pixel actually emit, expressed as a percentage the frame time) varies. The brightness control can suc gene by varying the emitter current, for example the changing the gate voltages of either of the transistor Q_C or transistor Q_R or both transistors.

<b>Fig.</b> 5 shows a simplified layout for multi-emitter node each row-column interface of the display panel without erfindungsge Maessen resistance. A pair of polysilicon row lines (Reihenadreßleiter) R₀ and R₁ perpendicularly intersects with metal column lines (column address) C₀ and C₁ as with a pair of metal ground lines GND₀ and GND₁, The Masselei tion GND₀ belongs to a column line C₀While the ground line GND₁ the column line C₁ belongs. For each port of rows and column (row and column line), ie for each individually addressable pixels within the Display device, there is at least one row line stub E₀₀ ... e₁₁. which the gates and the gate connection points for multiple-emitter node within this pixel forms. For example, part of the stub e₀₀ the intersection of row R₀ with the C column₀, the Stub e₀₁ belongs to the intersection of the row R₀ with the column C₁; stub e₁₀ belongs to the intersection of the row R₁ with the column C₀; and the stub E₁₁ belongs to the intersection of row R₁ with the C column₁, All of these interfaces operate in identi an operational manner, so that here only the components in the interface Stel lenzone R₀-C₀ be explained in detail.

After <b>Fig.</b> 5 carries the cutting zone R₀-C₀ three emitter node EN₁, EN₂ and EN₃, Each of these emitter node EN₁, EN₂, EN₃ includes a first active region (transistor channel) AA₁ and a second active region AA₂, A metal ground line GND contact simply one end of a first active region AA₁ at one first contact CT₁ ago. In combination with the first active region AA₁ forming a first L-shaped polysilicon strips S₁ the gate of the Field effect transistor Q_C (see. <b>Fig.</b> 2). The metal column line C₀ provides contact to the polysilicon strips S₁ at a second contact stelle CT₂ ago. Polysilicon stub E₀₀ forms the gate of Field effect transistor Q_R (Again, see <b>Fig.</b> 2 and 3). A first Metal strip MS₁ connects the first active region AA₁ with the second active region AA₂ by Kotaktgabe a third Kon Diplomatic CT₃ and a fourth contact CT₄,

The portion of the metal strip MS₁, Between the third Kon Diplomatic CT₃ and the fourth contact CT₄ lies, forms the Schmelzverbin tion FL. The emitter base electrode (see position<b>23</b> in <b>Fig.</b> 2 and 3, as the emitter base electrode is not shown in this layout) is provided with the metal strip MS₁ coupled. A second L-shaped polysilicon strip S₂ forms the gate of the current limiting transistor Q_L, and a second metal strip MS₂ is at a fifth contact CT₅ with the second polysilicon strips S₂ connected, and over a third Kon Diplomatic CT₆ with the second active region AA₂ connected. The grid plate (see position <b>21</b> in <b>Fig.</b> 2 and 3, since the grid plate in this not shown layout) with the second metal strip MSZ connected. It must be emphasized that the layout by<b>Fig.</b> 5 only is exemplary.

<b>Fig.</b> 6 shows a possible layout for an embodiment of the Emit terknotens with a current regulating resistor invention the ground path. Although the layout by<b>Fig.</b> 5 very similar, there a difference so far as no current limiting transistor Q_L by the second active region AA₂ and the strip S₂ (<b>Fig.</b> 5) is formed of a gate of the current limiting transistor Q_L acts. In the case of this layout, the emitter points E₁ and e₂ directly on the second active region AA₂ educated. Another difference is the presence of the Stromregulierwiderstands R, which in here the form of a C-shaped Polysili zium strip P_R is trained. One end of the C-shaped polysilicon strip P_R has direct contact with the first active region AA₁While the other contact with a metallic ground line or rail GND at a first contact point CT₁ Has. If already most of the C-shaped polysilicon strip slightly is doped with a level that the resistance value for the resistor R adjusts appropriately, its ends are endowed strengthens, so that an effective ohmic contact exists.

Equivalent layouts are possible, and there are other resistive and Conductor materials instead of polysilicon and metal structures in the <b>Fig.</b> 5 and 6 are possible.