Method for forming self-aligning gate structure around cold-cathode emitter end using chemical and mechanical polishing method

The present invention relates to field emission devices and more particularly relates to a method for forming a self-out directed gate structure around a cathode emitter tip.

CRT display of the type as used in screens Desktop computers are generally used to work on the Based on an output from an electron beam scanning elec tronenstrahls, the relatively distant on phosphors on a Screen incident. increase the electron energy level of the light substances. When the phosphors to their normal energy level back return, they put the energy of the electrons released as a light photon, the transmitted through the glass pane of the screen to the viewer becomes.

Flat screen displays always find more important with units on are those lightweight portable screens required. Currently USAGE to those screens the electroluminescence or liquid technology. One promising technology is the USAGE formation of a matrix moderately controllable field of Kaltkathodenemis sion devices for exciting phosphor on a screen.

The document US 3,875,442, entitled "Display Panel" of Wasa et al. discloses a display panel with a transparent gas up th enclosure, two major planar electrodes parallel to each other are arranged inside the gas-tight enclosure, and a Ka thodenluminiszenz panel. When one of the two main electrodes If it is a cold cathode, while it at the other an anode, a gate or a grating having in each case a low potential concerns. The cathode luminescence panel may consist of a transparent Glass plate, a formed on the transparent glass plate trans -transparent electrode, and a vapor on the transparent electrode brought consist phosphor layer. The phosphor layer is z. B. of zinc oxide, which can be excited with low energy electrons.

The field emission cathode structures are described in the documents US 3,665,241, US 3,755,704, US 3,812,559 and US 4,874,981 of Spindt et al. described. To generate the desired field emission a potential source is provided, the positive connection with the Gate or grating and whose negative connection with the Emitter electrode (cathode conductor substrate) is connected. The potential source, for the purpose of control of the electron emission current be made variable. Upon application of a potential between the Electrodes, an electric field between the emitter tips and made the low potential having anode grid where by an emission of electrons from the cathode through the tips Holes in the grid electrode caused therethrough.

An array of points in alignment with holes in anode grids low potential can be adapted for the production of cathodes, The compound containing in one or more peaks areas are divided, to which in separate manner appropriate emissions by applying Potentials can be triggered at this.

The resolution of a field emission display is a radio tion of several factors such as emitter tip sharpness, orientation and Spacing of the gates or grating openings that surround the tips, Picture element (pixel) size and cathode-gate voltage and Katho the screen voltage. These factors are also in change mutual relationship. For example, the electron emission for a of the emitter tips voltage required is a function of both the Cathode-gate spacing and the tip sharpness. An advantage the disclosed method is that a very narrow cathode Gate spacing is possible, whereby threshold voltages can be used that at least one order of magnitude lower than the to be found in previous reports are threshold voltages. Since the emitted current at a given emitter-gate voltage proportio nal to the difference from the applied emitter-gate voltage and the Emission threshold voltage, performs a lower threshold tension tion to a higher power.

The gate etch masks earlier field emission displays were hand with brought the emitter tips in alignment. Manual alignment performs a variability into the process, which often leads to low ren leads as optimal electron emission patterns. The document US 3,970,887, entitled "Micro-Structure Field Emission Elec tron Source "teaches a self-alignment of emitter tips. The self aligned formation of emitter tips and gates leading to a considerable reduction in the Verfahrensveränderlichkeit reduced the production costs and also results in a display with RESIZE ßerer sharpness. Other structures are relevant in tech. Digest IEDM, 1990, pages 7.4.1 to 7.4.4, and in the publications US 4,943,343, US 3,921,022 and US 5,057,047 discloses.

From the document: Sokolich, M. et al .: "Field emission from Sub micron emitter arrays ", Proc. Int. Electron Devices, 1990, is a A method for forming a gate structure for an electron emission lace around known. In this known method, the upper is surface of each with at least an insulating and conductive. Layer provided substrate not using a chemical- leveled mechanical planarization, but it is a photoreactive sist layer deposited as an etch mask, which is afterwards removed. On Plasma etching is used, this photoresist mask under USAGE prepare training of oxygen electrons.

The publication US 5,057,047 discloses a method for forming a gate structure known to an electron emission peak around.

In this method, a planarization layer is etched away to expose a part of a conductive layer. This is done by Using a conventional etching technique, such as Plas maätzen, wet etching or reactive ion etching (comp. ibid, column <b>5</b>. row <b>35-47</b>).

An object of the present invention is to provide a improved self-aligned method for forming a Self-timer directional gate structure is a cathode emitter tip around which is used for the production of field emission displays and the ge mentioned disadvantages of the prior art avoids.

The object is achieved by the in claim 1 Method specified.

According to one aspect, a method employs a plurality of selectively etchable dielectric layers in combination with a chemical mechanical planarization process for producing an extremely fine Gate-to-peak spacing, which leads to emission threshold voltages, the at least one order of magnitude lower than those previously in Litera tur emission threshold voltages described are. Since, in a given emitter-gate voltage of the emitted current is proportional to the difference from the applied emitter-gate voltage and the emis sion threshold voltage, leads to a lower threshold voltage a höhereren power.

Preferred embodiments of the invention result from the sub claims <b>2</b> to <b>15</b>,

The invention and further developments are in reference to the graphic representations of an embodiment with reference acquisition described in greater detail to the accompanying drawings. In the drawing calculations show:

<b>Fig.</b> 1 is a schematic cross-sectional view a flat panel display showing an electron emission tip or Field emission cathode, surrounded by the self-aligned gate structures at Training in accordance with the procedure of prior invention;

<b>Fig.</b> 2 is an electron emitter according to the invention top, on the conformal insulating layer and a flowable insulating layer are applied;

<b>Fig.</b> 3 is a view of the electron emitter top of <b>Fig.</b> 2 after a REUSE flüssigungs-heating of the flowable Insulating layer at about 1000 ° C;

<b>Fig.</b> 4 is a view of the electron emitter top of <b>Fig.</b> 3 after application of the gate conductive layer on this;

<b>Fig.</b> 5 is a view of the electron emitter top of <b>Fig.</b> 4 according to a chemical- mechanical Planarisierschritt;

<b>Fig.</b> 6A and 6B are a representation of the electron emitter pointed to <b>Fig.</b> 5 after the insulating layer a wet etching to expose the emitter tip has been subjected, in which <b>Fig.</b> 6A shows the result when it located in insulation layer is an oxide acts and <b>Fig.</b> 6B shows the result, if it is in the insulating layer a nitride-treated;

<b>Fig.</b> 7 is a flowchart for explaining the Steps of the invention in which Gate training methods are used.

With reference to <b>Fig.</b> 1 is a field emission display shown, the else use a cold cathode det. substrate<b>11</b> z can. B. Glass or ir quietly another of many geeigne th materials. In the preferred From leadership example is a monocrystalline Sili ziumschicht as substrate <b>11</b>, On which a layer <b>12</b> doped conductive material such. B. polycrystalline silicon is deposited. At a Field emission body is a micro cathode <b>13</b> above on the substrate <b>11</b> been trained. In the microcathode <b>13</b> is it a collection, the many different shapes, such as pyramidal, conical or a different geometry with a fine Microtip for the emission of electrons aufwei sen can. The micro cathode<b>13</b> surrounding a Anode-gate structure <b>15</b> low-potential provided. When a voltage difference by a source <b>20</b> between the cathode <b>13</b> and the gate <b>15</b> is applied, an electron flow <b>17</b> in Towards a phosphor coated screen <b>16</b> emitted. When the screen<b>16</b> If it is an anode. The electrons emission peak <b>13</b> is monocrystalline with the Semiconductor substrate <b>11</b> integral and serves as a cathode conductor. The gate<b>15</b> serves as a a low potential anode comprising or Grid structure for its associated cathode <b>13</b>, A dielectric insulating layer <b>14</b> is on the leit enabled cathode layer <b>12</b> applied. also has the insulator <b>14</b> an opening in the box, emission spot.

The invention is best understood with reference to the <b>Fig.</b> 2 to 7 to understand where through a series of inventive manufacturing steps formed initially during manufacture formed and ultimately devoted structures shown are.

There are various methods by which the ver in the inventive process blank form used electron emission tips. Examples of such procedures are found in U.S. 3,970,887 entitled "Micro-structure Field Emission Electron Source ".

Preferably, one uses a single-crystal p- type silicon wafer in which geeigne by te known Dotiervorbehandlung Läng a number Licher, mutually parallel and Einan the opposite n-type regions or Trays are formed. Each n-type strips has a width of about 10 microns and a depth of about 3 microns. The spacing of the stripes freely selectable and can for accommodating a desired number of on a Siliziumwafersub strat certain size trainee field emission cathode filters are fixed. The Processing of the substrate to create the p-lei border and the n-type regions can be obtained by well-known semiconductor processing techniques done such. as by growing by diffusion and / or epitaxial growth. If desired, can the p-type and n-type regions Of course by using a geeigne th output substrate and corresponding doping materials with respect to their conductivity type to be formed swept.

The ion implanted wells form the Stel le the emitter tips. A Feldemissionskathoden- Microstructure can including using a lying semiconductor substrate are prepared. The semiconductor substrate may be either p-type or be n-type and is at one of its Oberflä chen there masked where field emission cathodes points are to be formed. Masking is carried out such that said masked regions on the islands Surface of the underlying Halbleitersub strats form. Then performs a selective since Liche removal of the underlying surrounding Edge regions of the semiconductor substrate under the Edges of the masked island regions to produce a centrally located, elevated semiconductor Field emitter tip in the area immediately below each field emission cathode site forming masked island region. It is preferred that the Removing the underlying surrounding Randbe rich of the semiconductor substrate by oxidation of the masked island areas surrounding surface the semiconductor substrate is tightly controlled, the oxidation phase carried out long enough is to a lateral growth of the resulting Oxide layer under the edges of the masked Be rich in an amount to produce as neces is sary to ensure that only a non-oxidized peak of the underlying substrate under the island mask remains. Thereafter, the oxide layer is little least in the masked island areas immediacy bar surrounding regions differentially etched, so that desired at each field emission cathode constitutes an integral with the underlying Semiconductor substrate formed centrally angeord designated, semiconductor field emitter tip increased ent stands.

Before the gate formation process, the tip <b>13</b> the electron emitter by a Oxi dationsvorgang be sharpened, as in <b>Fig.</b> 7 is indicated. The surface of the silicon wafer (Si) <b>11</b> and the emitter tip <b>13</b> are to form an oxide layer, not shown, of SiO₂ oxi diert which then sharpening the tip <b>13</b> etched becomes. To form the SiO₂Layer and etching the top <b>13</b> can be any conventional, well ter oxidation process are used.

In the next step, in accordance with <b>Fig.</b> 7 a layer <b>18</b> of a selectively etchable material applied. In the method according to the Favor th embodiment is down a compliant whipped silicon <b>18</b> used. Although other materials are used can (z. B. SiO₂ and silicon oxynitride), which in respect to the other insulating layers <b>14</b> selectively are etched, is a nitride layer <b>18</b> especially effective against oxygen diffusion and can thus be used for layers 100 nm are thin, but preferably more than 100 nm. This is particularly advantageous since small distances from the gate <b>15</b> to the cathode <b>13</b> to lower emitter driving voltages lead. The Thickness of the insulating dielectric layer <b>18</b> determines the distance from the gate <b>15</b> to the cathode <b>13</b>, When in <b>Fig.</b> 2 insulating nitride shown layer <b>18</b> it is preferably a compliant insulation. The nitride layer is on the emitter tip <b>13</b> deposited such that the nitride layer <b>18</b> the shape of the cathode emitter great <b>13</b> equivalent.

Next, the application of a further carried insulating layer <b>14</b>As shown in <b>Fig.</b> 2 is shown.

This further insulating layer is preferably a flowable layer <b>14</b>, the may be formed of spin-on, Borophos phosilikatglas or a polyimide or at whose suitable material such. B. In other spin dielectrics or flowable dielectrics, these materials, however, not as from finally understand usable materials are. Under certain conditions, such flow Materials easily over the surface of the wafer, arises whereby a planar layer formed.

The thickness of the insulating layer <b>14</b> together with the layer <b>18</b> determines the distance between the gate <b>15</b> and the substrate <b>11</b>; the conformal layer<b>18</b> alone essentially determines the distance between tween the gate <b>15</b> and the cathode <b>13</b>, The depth of insulating layer <b>14</b> is thus dependent on the amount the space between the tip <b>13</b> and the substrate <b>11</b>, If the layer<b>18</b> is very thick, the insulating layer <b>14</b> be superfluous. For before the However ferred embodiment are both layers <b>14</b> and <b>18</b> available. The insulating layer<b>14</b> is preferably at a level above the tip <b>13</b> dejected, but they can also deposited a level below the top will. In the latter case, the flow step would optionally done.

In the preferred embodiment, is Boro phosphosilicate glass to form the layer <b>14</b> ver turns. The Borophosphosilikatglasschicht<b>14</b> can at the beginning by a technique such as chemical Abschei formation from the vapor phase or vapor phase deposition are deposited, in a Phosphorquel le such. as phosphine (PH₃-) Gas is used. The Wafer surface can also a source of boron such. B. Diborane (B₂H₆be exposed) gas. The resultie Rende Borophosphosilikatglasschicht <b>14</b> covered to Beginning substantially the cathode tip <b>13</b> and can then be liquefied.

In general, the Borophosphosilikatglas- done Liquefying at a temperature in the range of 700 ° C to 1100 ° C. In practice, the upper limit the reflow temperature by the effec te the reflow on the substrate and other associated structures controlled. Alterna tively this re-liquefaction can also rapid thermal processing take place.

In the preferred embodiment, the Borophosphosilikatglasschicht <b>14</b> a tempera tur heated from about 1000 ° C to a liquefaction the flowable insulating material <b>14</b> elicit, this preferably on a substantially uniform level below the emitter tip <b>13</b> takes place, as shown in <b>Fig.</b> is shown 3rd

A technique described in US 4,732,658 illustrates the use of a chemical vapor phase deposition method. A Silkatglas how z. B. borophosphosilicate glass is, on a Be rich of a semiconductor wafer as a layer having a approximately uniform thickness deposited. The Glass is doing by a chemical Dampfphasenab dejected divorce in an atmospheric system beat. An overview of atmospheric chemical cal vapor deposition systems can be found in the RCA Review of W. Kern, GL Schnable, band <b>43</b>, Pages 423-457, September 1982nd

A variation in atmospheric chemical Vapor deposition systems is also in the Signature of W. Kern stated, this font by reference to a part of vorliege ligands application is made. For depositing the Silicate glass could also be a plasma enhanced used chemical vapor deposition (PECVD) will. The plasma enhanced chemical vapor phase deposition is described in more detail in:"Process and Film Characterization of PECVD Borophosphosilicate film for VLSI Applications " JE Tong, K. Schertenleib and RA in Carpio Solid State Technology, pages 161-170, January 1984. For deposition of silica glass can Other precipitation methods, as in niedri gem pressure takes place chemical Dampfphasenabschei tion, are used.

As in <b>Fig.</b> 7 is shown, a further layer <b>18</b> of insulating nitride material on top the flowable insulating material <b>14</b> upset be to change the distance between the gate <b>15</b> and the tip <b>13</b> further adjust.

In an alternative embodiment, the Application of conformal dielectric layer <b>18</b> up to this stage of the gate forming process delayed, ie it only takes place after the Aufbrin gene and the re-liquefaction of the flowable insulating layer <b>14</b>, In other words, the flowable insulating <b>14</b> first downcast gen, after which the conformal insulating layer <b>18</b> is deposited. After reflow is the emitter tip <b>13</b> exposed, thereby an opportunity arises, a conformal insulating layer <b>18</b> before depositing the layer <b>15</b> knock down of conductive gate material.

The next step is carried out in accordance <b>Fig.</b> 7 On the affix the conductive gate material <b>15</b>, The gate<b>15</b> is formed of a conductive layer. at the conductive layer <b>15</b> may involve a Metal such as chromium or molybdenum act, where However doped polysilicon as the preferred Material is considered for this procedure.

can at this stage of the manufacturing process according to <b>Fig.</b> 7 an unshown buffer material be applied to the underlying preparation che the gate conductive layer <b>15</b> during the subsequent chemical-mechanical polishing process to protect. It should be emphasized that at the Applying a buffer layer to an optional occurring step is. The buffer layer may then remain or removed, depending after, as desired.

A suitable buffer material is a thin Layer of Si₃N₄, This nitride buffer layer has the effect of the tip <b>13</b> to protect, and this is a when performing this optional step occurring advantage. delayed The buffer layer essentially the penetration of the chemical-mechanical African Planarisiervorgangs in the layer on which the buffer material is deposited, and is as artificial layer. Alternatively, also a photoresist material used as the buffer layer will.

At the next step in the Gatebildungsverfah reindeer is in accordance <b>Fig.</b> 7 to the chemical- mechanical planarization, which is also called as che mixing mechanical polishing, respectively. By the use of chemical engineering and grinding technology are the buffer material and any other than the emitter tip <b>13</b> extending Layers (z. B. the conductive layer <b>15</b>, the compliant insulation <b>18</b>) "Polished off".

In general, the chemical mechanical includes Planarization or polishing the holding or turning a wafer of semiconductor material against a wetted polishing surface under controlled Bedin conditions in chemical slurry pressure and temperature. A chemical slurry, which a polishing agent such as alumina or silicon oxide contains, can be used as an abrasive medium will. In addition, the chemical slurry chemical etchant contained. The preferred pH Value of the slurry is in excess of 7.5, the preferred embodiment, a pH of 12 owns.

This method can be used for producing an upper surface to a desired end point or a desired thickness are used, these is polished and planarized surface. Such Devices for polishing are described in US 4,193,226 and US 4,811,522 discloses. Another sol Che device is manufactured by Westech En neering under the designation Model <b>372</b> Polisher produced.

The chemical-mechanical planarization is in substantially over the entire wafer surface, and wherein a high pressure. takes place at the beginning chemical mechanical planarization at Ent distant peaks of a very high Geschwin speed, and after the tips of substantially have been removed, the speed is drastically reduced. The removal rate the chemical mechanical planarization is on Proportion to the pressure and hardness of the planari ized surface.

<b>Fig.</b> 5 shows an intermediate step in the gate education process, after the chemically-me chanical planarization. It is an in wesent union planar surface available, and the con forme insulating <b>18</b> is thus exposed. <b>Fig.</b> 5 shows the means by which the conformal insulating layer <b>18</b> the distance between the gate <b>15</b> and the cathode <b>13</b> defined, as well as the means by which the gate <b>15</b> is self-aligned.

The next step is according to <b>Fig.</b> 7 by a wet etching of the layer <b>18</b> of selectively etchable material to expose the emitter tip <b>13</b>, The insulating layer<b>18</b> is in with respect to the layer <b>14</b> of flowable material etched selectively. The<b>Fig.</b> 6A and 6B show the Field emitter device according to this way performed etching of Isolierhohlraums. <b>Fig.</b> 6A shows while the resultant structure when it is at the insulating layer <b>18</b> an oxide, while <b>Fig.</b> 6B shows the resulting structure, which when using a nitride as an insulating layer <b>18</b> results.

If desired, the cathode tip <b>13</b> choice as a material with low leakage work to be coated, as in <b>Fig.</b> 7 is is indicated. Materials with low leakage work include cermet (Cr₃Si + SiO₂), Cesium, Rubidium, tantalum nitride, barium, chromium silicide, Titanium carbide, molybdenum and niobium, said Materials but not exclusively to ver are available.

A coating of the emitter tips can in many different ways done. The low Work function containing material or its Precursor may by sputtering or other suitable means to the tips <b>13</b> downcast be gen, certain metals (eg., titanium or Chromium) can be in the formation of silicide during a rapid thermal processing step react with the silicon of the tips. After the RTP is jegli Ches unreacted metal from the top <b>13</b> away. In a nitrogen environment, applied Tantalum during rapid thermal machining tion in tantalum, a material with particularly low work function, are converted. The Coating process variations are almost end los. This leads to an emitter tip<b>13</b>, the not only sharper than a simple silicon tip may be, but also a higher resistance ability to erosion and less from work function has. The silicide is represented by the Reaction of the refractory metal with the shows underlying polysilicon in a heat treat treatment step formed.

are all above-mentioned US patents in their entirety by reference herein to a constituent of this application ge power.