Manufacture of semiconductor device

The invention relates to a semiconductor device according to the preamble of claim 1 and to a manufacturing method therefor according to the preamble of patent claim 9th

The basic arrangement of a MOS-type Feldeffekttransi stors has a carrier-supplying source and a Abziehendes charge carriers to the drain, which on both sides are a so-called MOS capacitor is provided, which a Silicon substrate and a metal electrode disposed above , wherein a thin oxide film between these two is provided. Since the metal electrode on the oxide film, the Function for controlling conduction between the source and exerts the drain, it is as a transfer gate electrode designated. As materials for the transfer gate electrode are often doped with impurity atoms and a polysilicon used metal silicide obtained by applying a heat treat treatment in an inert gas to a polysilicon to abgeschie Misc, heat-resistant metal such as tungsten, is formed.

If the voltage of the transfer gate electrode (gate clamping voltage) lower than the inverting the conductivity type the surface adjacent to the silicon substrate surface between tween a source and a drain (channel) required smoldering lenspannung V_th is the source and the drain are voneinan the isolated by a pn junction, and current does not flow. When a gate voltage higher than V_th is applied, the Line type of the channel surface inverted, a layer of the same conductivity type as that of the source and drain is formed in this area, and current flows between the source and the drain.

If variations in the impurity concentration distribution large at the boundary between the source and drain and the channel are, the electric field strength is great in this area. Because the electric field received the carrier Energy, and so-called hot carriers are generated. The Charge carriers are then into the insulating transfer gate movie injected, sometimes they form a boundary layer state at a boundary layer of insulating About tragungsgatefilmes and a semiconductor substrate, or Sometimes they are in the insulating film transfer gate caught. Thus, the threshold voltage and the transfer be transmission line of the MOS transistor during operation deteriorated. This is the MOS Transistorverschlechte approximately phenomenon due to hot carriers. The breakdown voltage also falls due to the hot carrier. Therefore, the electric field strength by reducing the n-type impurity concentration in the vicinity of the source and drain reduced so that only a small variation in the Konzentra tion distribution is achieved. In a transistor of the MOS type and the LDD arrangement suppresses this the MOS transistor deterioration due to the hot carrier and increases Breakdown voltage of the source and drain.

A manufacturing method of a transistor of the MOS type having an LDD arrangement is in the <b>Fig.</b> 15A to 15H are posed. First, in this method, a transmission gate oxide film <b>3</b> in one of a component separated insulating <b>2</b> surrounding component forming on field a p-type semiconductor substrate <b>1</b> by so-called LOCOS (Local Oxidation of Sillcon) method formed (<b>Fig.</b> 15A). Next, for controlling the threshold voltage p-type Impurities such as boron ions, across the Halbleitersub strat <b>1</b> for forming ion-implanted regions <b>4</b> on out (<b>Fig.</b> 15B). Subsequently, a polysilicon film on the entire Übertragungsgateoxidfilm <b>3</b> by Lower pressure CVD (Chemical Vapor Deposition) process deposited and a transfer gate electrode <b>5</b> by photolitho graphic technique and reactive ion formed (<b>Fig.</b> 15C). Alternatively, the transfer gate electrode <b>5</b> a two-layer film of a heat-resistant metal, such as tungsten, molybdenum, and titanium or their Silizidverbindun gene and polysilicon used in place of the polysilicon will. Phosphorus ions are in the transfer gate electrode<b>5</b> doped for increasing its conductivity. In this Case, the transfer gate electrode <b>5</b> the n-type, the the same as that of the channel or the source and Drains is. Therefore, even when a gate voltage is not applied the transfer gate electrode <b>5</b> is applied, the p-type Channel surface in such a state as if a posi tive gate voltage would be applied, because of the difference between the work functions of the n-type transfer gate electrode <b>5</b> and the p-type channel surface.

This will be described in the following with the band theory. When no n-type transfer gate electrode <b>5</b> in the channel surface is formed, are first bands of transmis supply gate electrode <b>5</b>, The Übertragungsgateoxidfilmes <b>3</b> and the p-type semiconductor substrate <b>1</b> as in <b>Fig.</b> 15G shown. If a transfer gate electrode <b>5</b> on the channel surface is formed, a Übertragungsgateoxidfilm <b>3</b> in between the two is provided, the bands change, such as in <b>Fig.</b> 15H is shown. The change of the bands occurs, since the Fermi level E_FG the transfer gate electrode <b>5</b> and the Fermi level E_FS the semiconductor substrate is equal be such that a balanced state is generated, and the tape in the vicinity of the surface of the semiconductor substrate <b>1</b> is under the effect of the electric field by the Transfer gate electrode <b>5</b> bent down. After forming the transfer gates <b>5</b> becoming like <b>Fig.</b> shown 15H, free electrons in the vicinity of the surface of the Semiconductor substrate <b>1</b> injected. Thus to the delegation is supply gate electrode <b>5</b> in a state in which an effective positive potential is applied to it.

The n-type impurity doping in the transfer gate electrode <b>5</b> can also in the p-type channel surface due to the following heat treatment to diffuse. For these reasons, decreases V_th, And it can happen possibly that a inverted layer already in the channel in some cases is generated. The ranges described above<b>4</b>That with ion are implanted, are used to overcome the effect, the is produced by the implantation of p-type impurities Impurity ions in the transfer gate electrode <b>5</b> doped be so sure the desired V_thachieved -Voltage becomes.

Next, under the use of the gate electrode <b>5</b> as a mask n-type impurities such as phosphorus ions and arsenic ion vertically into the semiconductor substrate surface to form of layers <b>6</b>Implanted with ions of n-type, implanted (<b>Fig.</b> 15D). Subsequently, an insulating Film of silicon dioxide or the like over the entire Surface of the semiconductor substrate <b>1</b> by the low pressure CVD method or the CVD method at atmos Shem pressure deposited, these are the anisotropic etching to form sidewall spacers <b>7</b> subject (<b>Fig.</b> 15E). Next, using the transmission gate electrode <b>5</b> and the sidewall spacers <b>7</b> as masks n-type impurities such as phosphorus ions and arsenic ions perpendicularly in the surface of the semiconductor substrate <b>1</b> to form layers <b>8th</b> with n-type Ionenimplantierungen of higher Kon concentration than that of the layers <b>6</b> with Ionenimplantierungen introduced (<b>Fig.</b> 15F). Thus, after the heat treatment for activating the implanted impurity ions Transi stor completed with LDD arrangement of the MOS type.

While in the embodiment described above, a p-type Semiconductor substrate is used, may also be a sub strat be used with a p-well or a region, in which at least near the substrate surface impurity implants are made of p-type. Also, as a substrate, an n-type semiconductor substrate or a substrate with an n-type well or a region with Fremdatomimplan tierungen n-type used at least near the surface will. In this case, then the transfer gate electrode<b>5</b> p-type, the areas <b>4</b> with Ionenimplantierungen to Controlling the threshold voltage are n-type, and layers <b>6</b> and <b>8th</b> be with Ionenimplantierungen p-type as the source landscape and formed drain region.

Since the above embodiment is based on that the ions implanting only in a direction perpendicular to the upper surface of the semiconductor substrate <b>1</b> is carried out, must the areas <b>4</b> with Ionenimplantierungen for controlling the Threshold voltage prior to forming the Übertragungsgateelek electrode <b>5</b> are formed. On the other hand, the Japanese Offenlegungsschrift reference 61-226968 taken on a Ver go to form the corresponding ion-implanted layers after forming the transfer gate electrode <b>5</b>By a The method is applied to the oblique ion implantation. As in the <b>Fig.</b> 16A to 16D, in which A method of manufacturing a MOS type semiconductor device, which is described in the cited document, using one on a p-type semiconductor substrate <b>11</b> formed box oxide film <b>12</b> and Gates <b>14</b> n-type regions <b>18</b> by implant animals of phosphorus ions with an accelerating voltage formed by 20 keV (<b>Fig.</b> 16A). be Subsequently, by Boron ions, using the gate electrode <b>14</b> as a mask at an incident angle of 30 ° and with a Accelerat nigungsspannung be addressed from 30 keV to the substrate, p-type regions <b>19</b>a formed (<b>Fig.</b> 16B). After not a similar Liche oblique ion implantation from the opposite Side is performed, are p-type regions <b>19</b>a and <b>19</b>b ge forms, the total of the sides and the bottom of the n-type areas <b>18</b> surround (<b>Fig.</b> 16C).

Next, a photoresist <b>20</b> to the gate <b>14</b> around ge forming, and by setting this as a mask, are Arsenic ions implanted at a high concentration, so that n-type regions <b>21</b> are formed as source and drain (<b>Fig.</b> 16D).

Finally, a silicon oxide film <b>22</b> over the entire Surface deposited by the CVD method, contact holes are at prescribed locations in the corre relevant areas of the gate, source and drain through the reak tive ion etching or the like are formed, and aluminum is switched off by the spray method or the CVD method eliminated and patterned, then the n-channel semiconductor single direction ends of the MOS type.

According to the above embodiment, corresponding Schich th formed with Ionenimplantierungen after the Gateelek electrode <b>14</b> is formed as the p-type regions <b>19</b>a and <b>19</b>b are formed by oblique ion implantation.

Among the above-described manufacturing method for semiconductor devices is carried in the first embodiment vertical implanting ions over the entire surface of the semiconductor substrate prior to forming the transfer gate electrode <b>5</b> the area <b>4</b> with ion implantation or diffused layer for controlling the threshold voltage ge forms. Consequently, the concentration distribution of the p-type is Impurity ions fairly uniform over the entire channel region as shown in by the dashed line <b>Fig.</b> 17 shown is. This behavior does not change much after ther mixing diffusion, as shown by the two-dot chain line in <b>Fig.</b> is shown 17th Since the threshold voltage corresponding to a pretty average value of the channel potential is determined over the channel region, is by setting a predetermined threshold voltage the average value of Concentration distribution of on-forming regions <b>4</b> With Ionenimplantierungen determined accordingly. In the first Example, the concentration distribution in the region <b>4</b> the Ionenimplantierungen in the vicinity of the channel range or the distribution of the channel potential rather uniform, and the channel potential in the neighborhood the source region and the drain region takes a rela tively low value, the rather the potential in the central region of the channel is equal. Thus, in the vicinity of the source and drain region on both Ends of the channel region a sufficient potential barrier educated. Therefore, the extension of the depletion layer increases in the direction of the semiconductor substrate in the neighborhood the source and drain to. Since the establishment of high inte grated and the length of the transfer gate electrode or are the effective channel length is shorter, takes a short circuit between the source and the drain more easily, since the Depletion layer expands, and the breakdown voltage between tween the source and the drain decreases. When the concentration of ions in the channel region to suppress the expansion of the depletion layer is increased, the threshold voltage is higher than a desired value.

Similarly, the probability increases that the so-called Alpine (Alpha Particle source / drain penetration) effect occurs, in which or by radioactive isotopes such as uranium Thorium radiated in Gießharzpackung α-particles by the source and drain regions go. Because of this Alpine Effect occurs a so-called "soft error" when an α-ray hits a memory cell, thereby the infor mation of a memory cell destroyed, whereby a faulty radio tion occurs. In the case where the information "H" ge is stored, in which electrons are not in the capacitor are collected of a memory cell will, if α-particles take this memory cell, electron-hole pairs by the Current effect produced by the energy of the α-particles, and the electrons are collected in a depletion zone so, that the condition of the information "L" is reached. If go the α-particles through the source and drain, are Electron-hole pairs are generated along the path of the α-particles. The electron-hole pairs by the electric field of the depletion region between the source or the drain and separate the semiconductor substrate, and a new temporary Depletion layer is generated along the path of α-particles. The phenomenon that a temporary depletion layer ent long of the path of α-particles is generated, as "Funneled" phenomenon (channeling phenomenon) refers. currency ing operation of a transistor enters pass the breakthrough in between the source and drain when a temporary depletion region due to the funneling-phe Agreement between the depletion regions near the source and the drain is produced, whereby a soft error of New style ( "L → &lt;H" soft error) is generated.

If in the first manufacturing method described above the device is highly integrated, the source / sinks By breakdown voltage and the soft error is more likely on, and there is the problem that both the initial Property and the long-term reliability of the Einrich direction is deteriorated.

The p-type regions <b>19</b>a, <b>19</b>b, in the second embodiment are dimensionally formed, serve as barriers for preventing Breakthrough at both ends of the channel region. This p- Type regions <b>19</b>a, <b>19</b>b are independently of the control the threshold voltage of the channel region is formed. Therefore in addition to the increase in the number of the steps in Manufacturing method, the predetermined threshold voltage affected.

It is therefore an object of the invention to provide a semiconductor single-Rich device with characteristics of the source / drain breakdown voltage or the like be provided, which does not decrease even if the Device is highly integrated.

furthermore to a method of manufacturing a semiconductor memory device to be created.

According to the invention a semiconductor device is provided with a MOS-type field effect transistor having the features of Claim 1.

Preferred embodiments of the semiconductor device are in the associated Subclaims.

According to the semiconductor device is the Kanalpotentialvertei ment in the channel region near the central Abschnit tes of the channel region is low and corresponds to the impurity ion concentration distribution, and it is significantly high at both ends. Consequently, a high-potential barrier formed at both ends of the channel region so that the off expansion of the depletion layer between the source-drain is confined areas. As a result, a short circuit occurs the depletion layer between the source region and the Drain region does not easily occur, and the breakdown voltage increases between the source and the drain.

Even if the α-particles in the source and drain regions penetrate the funneling phenomenon because this is by the high potential barrier at both ends of the channel region limited, and the temporary breakdown between the Source and the drain due to the ALPS-effect is just if avoided.

This invention is particularly effectively applicable to a MOS-type LDD arrangement with a source region and a Drain region with impurity diffusion regions of low Concentration of the second conductive type included in the neighbor Community of the sections directly below both sides of the About tragungsgateelektrode are formed and with Fremdatomdiffu sion areas of higher concentration outside the impurity diffusion areas of low concentration.

The inventive production process of a semiconductor device has the features of claim. 9

A composition prepared according to the above production method Semiconductor device with the effects described above can be very effective produced.

Preferred embodiments of the method are disclosed in the accompanying dependent claims indicated.

It can work effects in this Herstellungsverfah Ren be achieved similarly to the case in which the areas with implanted ions for threshold voltage control by the ion implantation is formed with oblique rotation who the. Screaming In this ion implantation with fixed tilt tet diffusion rapidly forward when the Einrich tion necessary thermal treatment is applied thereafter, since the impurity concentration distribution in front of the diffusion strode through the thermal treatment changes sharply, so that the effect of forming a potential barrier at both ends of the channel region is reduced in comparison with the case where the ion implantation variable Orientation is carried out.

Below is a description of embodiments with reference of the figures. Of the figures:

<b>Fig.</b> 1A-1F are sequential sectional views that systematically the manufacturing steps according the first embodiment;

<b>Fig.</b> 2 is a diagram schematically showing the profile the ion-implanted layers in After bourhood of the channel of the transistor by MOS type LDD arrangement, in accordance with the Method of the embodiment according to <b>Fig.</b> 1 is formed, and the respective foreign atom ion concentration distribution shows;

<b>Fig.</b> 3 is a diagram schematically showing the profile the ion-implanted layers in After bourhood of the channel of the transistor by MOS type LDD arrangement for the case the ion-implanted layers for the threshold voltage control in accordance with a similar arrangements are formed, in which the inclination of the ion implantation is determined instead of the inclination of the ion implantation rotates, and the corresponding impurity ion concentration distribution shows;

<b>Fig.</b> 4 is a diagram showing the ion range and the system of coordinates for describing the theory of numerical analysis for on Find the impurity concentration in the respective embodiments;

<b>Fig.</b> 5A-5C are diagrams for describing three factors the effect of shielding the transmis transmission gate electrode in the ion implantation;

<b>Fig.</b> 6 is a diagram for describing the system coordinates in the analysis of ions implantation with tilt rotation;

<b>Fig.</b> 7A is a diagram of the distribution of the weight function W (X), W_mod (X), taking into tion of Abschattungseffektes and throughput dringungseffektes the Übertragungsgateelek electrode, and <b>Fig.</b> 7B is a graph of the distribu ment of the distribution function in the direction the depth P (Z), P_mod (Z);

<b>Fig.</b> 8A-8F sequential sectional diagrams The manufacturing method of systematically a second embodiment;

<b>Fig.</b> 9A-9C are sequential sectional views that schematically the basic principles of manufacturing method according to a third embodiment show;

<b>Fig.</b> 10A-10D are sequential sectional views that schematically the basic principles of manufacturing procedure according to a fourth embodiment show;

<b>Fig.</b> 11A-11D are sequential sectional views that systematically the fundamentals of manufacturing procedure according to a fifth embodiment form show;

<b>Fig.</b> 12A-12D are sequential sectional views that schematically the basic principles of manufacturing procedure according to a sixth embodiment form show;

<b>Fig.</b> 13A-13D are sequential sectional views that schematically the basic principles of manufacturing procedure according to a seventh embodiment form show;

<b>Fig.</b> 14A-14D are sequential sectional views that schematically the basic principles of manufacturing procedure according to an eighth embodiment show;

<b>Fig.</b> 15A-15F are sequential sectional views that schematically illustrates the production method of a Show example, and

<b>Fig.</b> 15G and 15H are diagrams of the conditions of the changes of the energy band before and after forming the Transfer gate electrode on the semicon tersubstratoberfläche;

<b>Fig.</b> 16A-16D are sequential sectional views that schematically the basic principles of manufacturing procedure of a second example showing; and

<b>Fig.</b> 17 is a diagram schematically showing a profile of ion-implanted layers in the neighboring Community of the channel of a transistor from MOS type LDD arrangement, in accordance with the the first example is formed, and the this corresponding impurity ions Konzen tration shows.

Referring to <b>Fig.</b> 1, the Herstellungsver drive described in a first embodiment. First is an insulating gate film transfer <b>3</b> on a Element-forming region, the element of a divisive area <b>2</b> is surrounded by the LOCOS method on a p-type semiconductor substrate <b>1</b> educated (<b>Fig.</b> 1A). Next is a polysilicon film over the entire surface of insulating film transfer gate <b>3</b> by the low pressure CVD method for forming a transfer gate electrode <b>5</b> deposited by photolithography and reactive ion etching (<b>Fig.</b> 1B). This transfer gate electrode<b>5</b> may instead, that they formed from a single polysilicon layer is also formed by depositing a double layer of a heat-resistant metal such as tungsten, molybdenum or titanium and Polysilicon by low pressure CVD method or the Spraying and applying photolithography and reactive ion etching are formed. It may also by depositing a suicided heat-resistant metal, ie a heat-resistant metal silicide, and applying the Photolithography and reactive ion etching formed will.

Impurity ions such as phosphorus ions, are in the transmis supply gate electrode <b>5</b> doped to increase its conductivity, and the conductivity type is opposite to that of the semicon tersubstrates or the same as that of the channel. by virtue of the positive difference between the work function of the n-type transfer gate electrode and the p-type channel region and due to the phosphorus ion diffusion in the channel due to Consequently, the following heat treatment takes, the thresholds voltage from. It is necessary, therefore, the threshold voltage by forming the ion-implanted regions <b>4</b> to increase, as will be described below.

Next, boron ions, the impurity ions of p-type and thus the same as those for the semiconductor substrate <b>1</b> are, in an oblique direction at a predetermined Tilt angle θ relative to the normal direction on the entire surface of the semiconductor substrate <b>1</b> implanted. The ion implantation is in this case in the range Runaway acceleration voltage of 80 keV to 180 keV leads, and the dose of boron is 4 × 10¹² / cm² to 8 × 10¹² / cm². At the same time, the semiconductor substrate<b>1</b> an arbitrary normal axis of the main surface of the The semiconductor substrate is rotated. By this ion implantation with tilt and rotation, the ion-implanted layers <b>4</b> ge p-type for controlling the threshold voltage forms (<b>Fig.</b> 1C).

When the inclination angle θ of the ion implantation is less than about 10 °, the so-called channeling effect occurs one in which the ion unusually low in the direction the crystal axis penetrate because they only weakly with the Atoms interact; this is not preferred. Even is when the angle θ is greater than about 10 °, but if it is is less than about 15 °, the ion implantation is in the section directly below the transfer gate electrode <b>5</b> not running well enough so that the control of the Threshold voltage is difficult. If the angle θ about exceeds 60 °, there arises the problem that the amount of Ion implantation in the section directly below the transmis supply gate electrode <b>5</b> increases so that the threshold voltage is too high. Therefore, the inclination angle θ of Ionenim is plantation preferably greater than 15 ° and smaller than 60 ° ge chooses. Usually, it is greater than 30 ° and less than about 45 °.

Thereafter, phosphorus ions or arsenic ions, which are foreign atom ions of n-type, of the opposite conductivity type to that of the semiconductor substrate <b>1</b> represents, in the normal direction over the entire surface of the semiconductor substrate <b>1</b> implanted. Thus ion implanted layers<b>6</b> n-type using the transfer gate electrode <b>5</b> as a mask (<b>Fig.</b> 1D). Next, an oxide film of silicon by the CVD method or the like over the entire surface of the semiconductor substrate <b>1</b> from divorced, then applied to the anisotropic etching so is that sidewall spacers <b>7</b> are formed.

Next, n-type impurity ions, phosphorus ions or Arsenic ions in the normal direction over the entire surface of the semiconductor substrate <b>1</b> implanted. Thus, ion implanted layers <b>8th</b> n-type using the gate electrode <b>5</b> and the sidewall spacers <b>7</b> as masks educated.

In this case, for forming the LDD arrangement, the amount of the ion implantation in the ion-implanted layers <b>6</b> so is notes that the implanted concentration much lower than that of the ion-implanted layers <b>8th</b>,

Then, by performing the heat treatment, the corre relevant ion-implanted layers <b>6</b> and <b>8th</b> to form Impurity ion diffusion layers activated.

While in this embodiment, a p-type Halbleitersub strat <b>1</b> as a substrate for forming a transistor of the MOS Type is used with LDD arrangement may also one that with a p-well, a p-type region having at least one predetermined depth from the substrate surface used to will.

The conductivity type of the substrate not be on p-type limited, and the ion-implanted layers <b>6</b> and <b>8th</b> can as p-type ion-implanted in an n-type substrate and layers <b>4</b> are formed.

The impurity ion concentration distribution of the transistor MOS-type LDD arrangement, which is formed as above, is in <b>Fig.</b> 2 is shown.

The profile and the channel potential distribution of ionenimplan oriented areas <b>4</b> in the case of application of Implanta tion procedure with oblique incidence and rotation can by numerical analysis are calculated, in addition to the later described LSS theory, a theory of vertical ion implantation in an amorphous target, and a Weight function are used, the shading effect the and the gate indentation into the surface of the transfer gate electrode <b>5</b> account. The impurity ion concentration distribution in <b>Fig.</b> 2 schematically shows the distribution over the channel landscape surface due to the calculated result.

A summary of the theory of the numerical analysis to achieve the impurity concentration distribution in accordance with <b>Fig.</b> 2 will be described in the following.

The distribution of the semiconductor substrate in <b>1</b> implanted Impurities is first passed through the dose, the acceleration voltage and the implantation direction determined. The rela Hung can be prepared by the mechanism of analyze impact of the implanted ion and target atom becomes. The essence of the thermal treatment after the implant tion can be used as the second factor for determining the impurity distribution are used. That is, by the shock with the goal of nuclear certain distribution may by Diffu sion be changed during the thermal treatment.

First, the first part is without the thermal treatment described. Even if the target substance (target substance) crystalline, it can in the case of ion implantation, in random directions for preventing Channelling- Effect are considered amorphous. Therefore, the theory the ion implantation used in amorphous substances.

The implanted ions penetrate into the substrate of the sub stratoberfläche ago, and then to its direction of movement bent obligations of the location in the substrate, as in <b>Fig.</b> 4 is shown. The total length R of the place of the ion in the Substrate is referred to as total area. The whole Area R does not always match the depth R_p of the Ions from the substrate surface coincide. This penetration R_p is carried on an axis perpendicular to the substrate surface projected distance designated or in Projection range R_p, as in <b>Fig.</b> 4 is shown.

The range of the implanted ions contains a directional component R_xy in the xy plane. These respective areas are about the average value with a certain distribution yet because of the shock and the incidence statistically or is random. Lindhard among others led an integral sliding Chung, which indicates the distribution of these areas, wherein the term for the implanted ion distribution rather good agreement with the experimental values ​​indicated. This is referred to as the LSS theory (see for In play "(KK) Kogyochosa-kai, electronics Zenshu (8) Ion Implantation Technique, page 29 to page 40 ").

The expression of the three-dimensional concentration distribution N (X, Y, Z) of the impurity ions through the LSS theory is obtained, is shown below.

in which.DELTA.R_p the standard deviation of R_p is,ΔX², ΔY² the mean square standard deviation is in the X-direction and Y-direction, the incidence of .DELTA.X = R_p in the X direction is undΔY = the extension of R_p in the Y-direction is.

Next, in addition to the above LSS theory is the described numerical analysis, in which a weight function in terms of the shading effect and the gate penetrant effect of the transfer gate electrode <b>5</b> is introduced.

Implantation with oblique angles of inclination and rotation contains three factors, such as in <b>Fig.</b> 5A, 5B and 5C is. The first is a factor of the shadowing of implantable th tons at the end of the transfer gate electrode <b>5</b> (please refer <b>Fig.</b> 5A), which is herein referred to as the factor "A". Of the second factor is a factor due to the direct Eindrin gene of the ions from the semiconductor substrate surface in a Section under the transfer gate electrode <b>5</b> (please refer <b>Fig.</b> 5B), which is hereinafter referred to as the factor "B". The third factor is based on the Ioneneindringung by polysilicon gate <b>5</b>b on the side of Übertragungsgateelek electrode <b>5</b> (please refer <b>Fig.</b> 8C), this is called the factor "C" here designated.

All of these three factors "A", "B" and "C" act to Reduzie tion of the number of ions in the in the semiconductor substrate are implanted, compared with the case of absence the transfer gate electrode <b>5</b>, Therefore, their effect with the concept of probability are described. In In other words, the implant, the ratio in the substrate oriented ions in the case where the Übertragungsgateelek electrode <b>5</b> actually exists, to the number of the half in conductor substrate <b>1</b> the implanted ions in the case where the transfer gate electrode <b>5</b> does not exist, a out. This ratio depends pretty obvious of the distance from the transfer gate electrode <b>5</b> from.

Roughly itself constitutes impurity distribution specified by produces ion implantation with skewness and rotation is composed of two components. One is from the half conductor substrate surface implanted, this contains the Fak tors "A" and "B". The other is from the side of the poly silicon gates implanted, this contains the factor "C". If the factors "A", "B" and "C" taken as weights are, the impurity distribution N (X, Z), which by implantation with skewness and rotation is generated, shown below are presented:

N (X, Z) = N_Ocos {w (x) · P (z) + W_mod (X) · P_mod (Z)},

in which:N_O the irradiated amount of impurity ions per Unit area,θ the inclination angle of the ion implantation direction relative to the vertical to the substrate, W (X) is the weight function in the X-direction by the factors of "A" and "B" isW_mod (X) is the weight function in the X-direction by the factor "C",P (X), the concentration distribution in the Z-direction for the case where W (X) = 1.0, W_mod (X) = 0,P_mod (Z), the concentration distribution in the Z-Rich device for the case of W (X) = 0, W_mod (X) = 1.0.

The first term in the above equation, "N_Ocos W (X) P (Z) " shows one of the surface of the semiconductor substrate in the plan oriented component, and the second term "N_Ocos W_mod (X) P_mod (Z) ", shows a from the side of the polysilicon gate <b>5</b>b implanted component.

In this system of coordinates, the origin 0 on the Semiconductor substrate surface at the side of the transmis supply gate electrode <b>5</b> disposed, and the X-, Y- and Z-axis are as in <b>Fig.</b> arranged as shown. 6

As a specific example of the distribution of the weight function for θ = 45 °, energy of the implanted ION BEAM ment e_imp = 42 keV and N_O = 2.8 × 10¹³cm^-2 the Resul tate for the calculation of W (X), W_mod (X), P (Z) and P_mod (Z) in the <b>Fig.</b> 7A and 7B.

From the obtained as described above function values ​​and the above equation for N (X, Y, Z), the calculated Values ​​for the impurity ion concentration distribution in the Vicinity of the channel surface by the curve of the ge dashed line in the <b>Fig.</b> 2 is shown.

The ion implantation method with oblique implantation, used to form the p-type regions <b>19</b>a and <b>19</b>b in the second- Example was used, allows for the formation of ionenim -implanted regions <b>4</b> in the steps of fabricating the Transistor of the MOS type having LDD structure according to the above Embodiments instead of the implantation with sloping Incidence and rotation to form the ion-implanted areas <b>4</b> are used, whereby effects similar to the above embodiment can be obtained. In<b>Fig.</b> 3 are the profile of the ion-implanted regions <b>4</b>immediately after the ion implantation is completed, and the corre sponding impurity concentration distribution in the neighborhood the substrate surface in the case shown in which the ion implanted regions <b>4</b> in the above first Ausfüh ment of by the ion implantation method with oblique Incidence (hereinafter referred to as "ion implantation with solid Nei of inclination ") is formed, said the incident symmetrically in two directions with a given slope angle is executed, and the transfer gate electrode <b>5</b> is used as a mask. This is by dashed Li Britain in <b>Fig.</b> 3 is shown. Further, the impurity Konzen tration after the heat treatment under Be conditions is applied as after the establishment are needed by the double-dashed line in <b>Fig.</b> 3 shown.

By the curves in the <b>Fig.</b> 2 and 3 are compared, it can be seen that the impurity ions profile directly after completion of the ion implantation, the ion- implantation is formed with oblique incidence and rotation, the tendency that the p-type ion concentration in the Vicinity of the two ends of the channel is higher. It varies however, to a lesser extent compared to the Ionenimplanta tion with fixed angle of incidence, as from <b>Fig.</b> can be seen. 3 As already described in the introduction, happens for the following reasons. When Ionenimplan tation with fixed inclination angle, due to the selective screening flow through the transfer gate electrode <b>5</b> and sides wall distance pieces <b>7</b> the irradiated ion whose Konzen tration largely at the edges of the shadow varied with the same angle of inclination and for a fixed irradiated period of time so that the concentration distribution significantly immediately after the ion implantation be influenced by the effects of the shadow, so that it varies greatly. On the other hand alter the Shadow of the shield through the transfer gate electrode <b>5</b> and the sidewall spacers <b>7</b> continuously their position in which ion implantation method with oblique incidence and rotation, since the irradiated ion and the semiconductor substratum <b>1</b> rotate relative to each other. The effect on the variation of the impurity ion concentration distribution based because of the shadow, is averaged and ge smoothes out such that the concentration distribution of small Varia having functions.

As described above, the varied by the ion implantation Impurity profile generated with oblique incidence and rotation even immediately after the ion implantation little, so that it is not greatly influenced by the thermal treat- then required treatment is affected. Since the diffusion of impurities by the thermal or heat treatment is proportional to the spatial is union gradient of the impurity profile, vary the by the ion implantation with oblique incidence and rotation Impurity profile generated is not as strong in the Heat Treatment ment. This means that the most appropriate distribution the impurity profile after the heat treatment under the Condition of the heat treatment can be realized, the to maintain the properties of a device are needed, such as the suitable heat treatment condition for achieving the refresh characteristics in a DRAM (Dynamic Random Access Memory) for example. This means, as represented by the implantation with oblique incidence and Rota tion formed impurity ions profile not so much by the Diffusion due to the following heat treatment at the most suitable conditions for the establishment impressed is enced, the most appropriate impurity ions can profile practically independent of the heat treatment conditions be determined.

On the other hand, for example, by varying the Ionenimplan tation impurity profile generated with a fixed angle of inclination strongly immediately after implantation, so that it clearly is affected by the subsequently required heat treatment. Therefore, the heat treatment condition, the most appropriate Distribution of impurity ions Profiles maintains, not the most suitable condition for the heat treatment for the device in many cases. On the contrary, if Runaway the appropriate heat treatment for the device leads is, it is not possible, the most suitable impurity to achieve ion profile after the heat treatment.

The smaller the variation of the impurity ions Profiles immediacy bar after completion of the ion implantation, the appropriate impurity ions profiles among the most appro Neten heat treatment conditions for the device can be achieved, as described above. In this regard, it can be said that the implantation with oblique incidence and a better rotation ion implantation method for the device design is as implanting fixed Tilt angle.

The threshold voltage corresponds to almost the middle Value of the channel potential on the channel region. It will given below is the qualitative summary. If the p-type impurity ion concentration in the longitudinal section L (in <b>Fig.</b> 2 shown) in the vicinity of the source Region and the drain region is higher, the smoldering is lenspannung in this section is higher, and a decrease in Drift velocity is proportional to the mobility of the Carrier or the strength of the electric field on due to the impurity scattering in this section is Doomed gently. Consequently, the threshold voltage V_th about Tran transistor higher. Thus taking by reducing the p-type ion concentration in the central portion of the channel in comparison equal to that of a conventional transistor thresholds voltage in this section, in contrast decreases, and the Move sensitivity at this portion increases. Consequently, the Threshold voltage V_th be reduced through the channel. As described above, the threshold voltage V_th over the ge entire channel determined according to the average value of p-type impurity concentration over the entire channel length (The length L in <b>Fig.</b> 2).

Because of the distribution of the channel potential to achieve predetermined threshold voltage is obtained by applying Implantation with oblique incidence and rotating the channel potential near the source region and the drain Area in comparison with the implantation procedure with solid angle of inclination greater. As a result of these forms Section a potential barrier to limit the off expansion of the depletion layer between the source region and the drain region, so that the breakdown voltage between Source and drain for the case that no voltage to the Transfer gate electrode <b>5</b> is applied increases. Even if the α-particles in the channel region by the source penetration region and the drain region, the Funneling phenomenon of generating a depletion layer temporarily by along the Eindringweges of α-particles this potential barrier will be limited. Consequently, or temporary breakdown between the source and the Drain due to the ALPS-effect and the soft error due the ( "L" → "H" error) are also limited.

As described above, good original features be achieved by in this embodiment a high Potential barrier in the vicinity of the source and drain to both ends of the channel region are formed, even if the device is highly integrated, with the effective Channel length is shortened. What the temporary self-sheep As th, reliable operation can also be achieved.

The manufacturing method of the in <b>Fig.</b> 8A to 8F ge showed embodiment, as the in the <b>Fig.</b> 1A to 1F shown embodiment, the steps of Bil dens of an insulating film transfer gate <b>3</b> in which the Element-forming region, the element through which the iso lierenden area <b>2</b> is surrounded, on the p-type Halbleitersub strat <b>1</b> by the LOCOS method (<b>Fig.</b> 8A) and forming a transfer gate electrode <b>5</b> (<b>Fig.</b> 8B) on.

In contrast to the above embodiment, the p-type Ion implantation region <b>4</b> for controlling the threshold voltage by ion implantation with oblique incidence and rotation formed after the ion implantation layers <b>6</b> and <b>8th</b> are formed from the n-type in this embodiment. The is, in this embodiment, a Seitenwandab standing piece <b>7</b> educated (<b>Fig.</b> 8D) after the ionenimplan oriented layers <b>6</b> n-type by ion implantation with oblique incidence using the Übertragungsgateelek electrode <b>5</b> as a mask (<b>Fig.</b> 8C) are formed.

Next, using the transmission gate electrode <b>5</b> and the side spacers <b>7</b> ion as masks implanted layers <b>8th</b> n-type by vertical ion implantation formed (<b>Fig.</b> 8E). Thereafter ionenimplan oriented areas <b>4</b> p-type for controlling the threshold voltage educated (<b>Fig.</b> 8F) wherein the semiconductor substrate <b>1</b> to the mean normal axis of the transfer gate electrode <b>5</b> rotates is and the ion implantation with a predetermined A is incidence angle θ performed, the transmission gate electrode <b>5</b> and the sidewall spacers <b>7</b> as masks to be used. Thereafter, a heat treatment is to Diffun decoding the implanted ions.

By performing the steps of this embodiment is virtually the same profile of the corresponding ion implanted layers and the channel potential distribution obtained as in <b>Fig.</b> 2 shown.

In the first and second embodiment described above is the semiconductor device with a transistor of the MOS Type LDD arrangement applied, but the idea can also be applied to a MOS-type transistor, the no having LDD arrangement. Below is a description of Off embodiments of manufacturing processes for MOS type Tran transistors, the arrangements other than the LDD arrangement point.

The in <b>Fig.</b> 9A to 9C shown embodiment a method for producing a transistor of the MOS type represents, at which no side wall spacers on the sides walls of a transfer gate electrode <b>5</b> are formed. at this embodiment, the transfer gate electrode <b>5</b> by photolithography and reactive ion etching on a insulating film transfer gate <b>3</b> on a p-type semiconductor conductor substrate surface <b>1</b> (<b>Fig.</b> 9A) formed. Next is using this transfer gate electrode <b>5</b> as Mask, an n-type impurity beam of phosphorous or arsenic senk quite on the substrate surface for forming ionenimplan oriented layers <b>6</b> directed that and the source region the drain region (<b>Fig.</b> 9B) represent. Next, while rotating the semiconductor substrate <b>1</b> in a horizon talen level p-type boron in an oblique direction with a predetermined inclination angle to form ionenim plan oriented units <b>4</b> for controlling the threshold voltage the channel region (<b>Fig.</b> 9C) irradiated.

In this way the method can also at steps for forming a field effect transistor of the MOS type having a single source / drain type are applied.

When the <b>Fig.</b> 10A to 10D illustrated embodiment is, as in the above third embodiment, first the transfer gate electrode <b>5</b> educated (<b>Fig.</b> 10A), then be the ion-implanted layers <b>6</b> as source region and drain region by implanting n-type ions Use of the transfer gate electrode <b>5</b> gebil as a mask det (<b>Fig.</b> 10B). In this embodiment, however, after forming the ion-implanted layers <b>6</b> Side wall distance pieces <b>7</b> on a side wall of the transfer gate electrode <b>5</b> educated (<b>Fig.</b> 10C), and then be ionenim plan oriented areas <b>4</b> by ion implantation at an oblique formed incidence and with rotation (<b>Fig.</b> 10D). Since in this Embodiment, the sidewall spacer <b>7</b> for controlling to form the steps for the ion-implanted regions <b>4</b> is used, but not for the formation of LDD, the Fine adjustment of the concentration distribution of ionenim -implanted regions <b>4</b> by changing the sidewall widths independent of LDD possible.

When the <b>Fig.</b> 11A to 11D shown embodiment after forming a transfer gate electrode <b>5</b> on the insulating film transfer gate <b>3</b> (<b>Fig.</b> 11A), wherein this is used as a mask, ion-implanted regions <b>4</b> by ion implantation with oblique incidence and rotation educated (<b>Fig.</b> 11B). After next, a sidewall distance pieces (<b>Fig.</b> 11C) is formed, are ionenimplan oriented layers <b>6</b> by the vertical ion implantation educated. In this embodiment, the side wall serves distance piece <b>7</b> for expanding the mask width in the case of forming the ion-implanted layers <b>6</b>Because the Dif fusion rate of phosphorus is greater than that of Boron.

When the <b>Fig.</b> 12A to 12D shown embodiment be immediately after the gate electrode <b>5</b> is formed (<b>Fig.</b> 12A), sidewall spacers <b>7</b> deposited (<b>Fig.</b> 12B), ion-implanted regions <b>4</b> be Ionenimplan tation with oblique incidence and rotation in this state educated (<b>Fig.</b> 12C), and then ion-implanted Be rich <b>6</b> formed by the vertical ion implantation (<b>Fig.</b> 12D).

When the <b>Fig.</b> 13A to 13D shown embodiment are to form an ion implanted layer <b>4</b> by Ion implantation of boron at oblique incidence and rotation under the use of a transfer gate electrode <b>5</b> as mask (<b>Fig.</b> 13A) sidewall spacers <b>7</b> secluded (<b>Fig.</b> 13B). Thereafter, phosphorus ions are through the vertical Ion implanting to form ion-implanted layers <b>6</b> implanted by a relatively low concentration (<b>Fig.</b> 13C) Moreover, arsenic ions with a smaller thermal Diffusion coefficient than that of the phosphorus ions through the vertical ion implantation for forming ion-implanted layers <b>9</b> implanted with a relatively high concentration (<b>Fig.</b> 13D). This is based on the idea that the electrical Field intensity in the channel portion by the double ion-implanted layers <b>6</b> and <b>9</b> is decreased, the formed with different concentrations in this way are, making a breakthrough in the channel prevents becomes. This idea is similar to that in the LDD arrangement. This arrangement will double as a transistor of the MOS type with diffused drain (DDD), respectively.

The in <b>Fig.</b> 14A to 14D eighth embodiment shown is the same as the above-described seventh Ausfüh bodiment, namely by the method of forming a Tran sistor is used MOS type with DDD arrangement. at this embodiment, after the deposition of pages wall distance pieces <b>7</b> (<b>Fig.</b> 14A) boron ions through Ionenimplan tation with oblique incidence and rotation for forming ion implanted areas <b>4</b> implanted p-type (<b>Fig.</b> 14B). Phosphorus ions are by vertical ion implantation then implanted (<b>Fig.</b> 14C), and arsenic ions are further towards implanted (<b>Fig.</b> 14D), so that a DDD arrangement ge forms, is the same as in the seventh Ausfüh bodiment is.

In the third to eighth embodiments described above, , the ion-implanted regions <b>4</b> for adjusting the Threshold voltage of the channel practically the same distri Assembly at as in the first embodiment. Consequently, the impurity concentration distribution, as determined by the doubly dotted line in <b>Fig.</b> 2 is shown, according to the heat treatment achieved, and the electrical barrier is formed, the source-drain breakdown voltage can be increased will.