Configuration and control unit

30

The invention relates to a data processing system of variable configuration having at least one central processor having a plurality of data channels, a number of input / output units, including peripheral memory, and control stations.

Data processing systems with variable configuration are known in various designs. U.S. Patent 3,812,468 describes a multiprocessor data processing system whose functional units are grouped into subsystems. Each subsystem has a central processing unit, a memory unit, a plurality of input / output units and possibly other terminal units. Furthermore, each subsystem is connected to a configuration change circuit which detects fault conditions in the functional units of the subsystem concerned. The configuration change circuits are coupled to a higher-level configuration control circuit having a configuration data memory. When one of the configuration change circuits has detected a fault condition in one of the subsystems and reported it to the control circuit, it selects from the configuration data store a set of configuration data that ensures the operability of the system by reconfiguring the functional units within that subsystem. These data will then be transferred to the relevant configuration change circuit which makes the necessary switches. This known data processing system has the disadvantage that the existing input / output units can not be arbitrarily connected to the existing central processing units. Reconfiguration is only possible within the given subsystems, which can only be separated from the system as a whole.

Similar data processing systems capable of reconfiguring subsystems are described in US Pat. Nos. 2,353,262 and 3,413,613.

There are also known data processing systems, which consist of groups of identical functional units, which can be interconnected to different configurations (US Pat. No. 3,641,505). These systems can be advantageously adapted to the execution of certain data processing tasks in which a plurality of similar basic operations are to be performed simultaneously. Their use as general-purpose computers, however, is limited because the functional units are not set up to perform the various special processing operations that a general-purpose computer must be capable of executing.

In US Patent 38 28 321 a data processing system is described with multiple switchable input / output channels. The configuration or reconfiguration of this system is done under the control of a stored program, which is previously determined according to all possible configuration changes and change criteria. A disadvantage of this system is its sensitivity to program errors and program execution errors. Any errors in the program or its execution can have far-reaching consequences for the functioning of the entire system and lead to its complete failure.

There is also a multiprocessor data processing system with decentralized configuration Steuemng known (DE-PS 12 79 980). In this system, each data processing unit is assigned a configuration control register that contains a copy of the configuration information. If one of the data processing units fails, the configuration information is still available. This is only lost if the power supply fails throughout the system

Numerous arrangements are also known in which the defective device is switched off and a similar replacement device is switched on within a data processing system in the event of a device error (eg, US Patents 33 03 473, 34 09 877, 35 62 716, 36 23 014). , However, these arrangements require a high degree of device redundancy.

The object of the invention is to specify, while avoiding the above-mentioned disadvantages, a power failure insensitive configuration control, which is largely system independent, that is used for data processing systems consisting of different central units and different exclusion units (heterogeneous system).

This object is achieved by the measures indicated in the characterizing part of claim 1. Various advantageous embodiments and development of the invention are apparent from the other claims.

In the data processing system according to the invention, a configuration control can be initiated from any computer or from any connected console. There is no common bus netwendig which connects the processors or computers with each other. All computers in the system can work independently without having to stand by as a backup unit. In addition, no connected input / output control unit (EA control unit) must be firmly associated with a computer, so

that in the interconnection is very flexible. Moreover, the devices according to the invention allow further functional units such as computers or input / output units (EA units) to be added to the system without complicated changes. After a power outage that has lost the contents of volatile memory, the contents of the long-term configuration memory can be used to restore the most recent configuration. Finally, the initialization of the system, ι ο ie initial program loading with adjustment of the initial configuration, facilitated by the inventive devices.

An embodiment of the invention is illustrated in the drawings and will be described in more detail below. It shows

F i g. 1 shows an exemplary embodiment of a data processing system with a plurality of processors,

F i g. 2 shows an embodiment of the configuration and control unit (KST unit) of the F i g. 1, 2α

F i g. 3 shows an exemplary embodiment of the PWL adapter in the KST unit in FIG. 2 with a configuration memory for persistent storage,

F i g. 4A shows an embodiment of an external modem adapter RM which is connected to a time-division multiplex line TML from the TML adapter of the KST unit in FIG.

4B shows another embodiment of an external modem adapter with a persistent configuration register for permanent storage,

F i g. FIG. 5 shows the internal structure of a conventional channel coordinate switch as used in the system according to FIG. 1 can be used

F i g. 5A shows the connection of the channel coordinate switch K 1 according to FIG. 1 with the PWL-M output is the PWL adapter according to F i g. 3 and

F i g. 5B shows the connection of the outer modem adapter RM with the coordinate switch M according to FIG. 1 (via the RM adapter output 441 according to FIG. 4A or 4B),

F i g. 6A or 6B on parallel lines PWL connectable two-channel or four-channel control unit switches for an EA control unit,

F i g. 7A and 7B, a two-channel and four-channel control unit switch with external modem adapter,

F i g. Figure 8 shows a control processor memory directory of the blocks and control processor programs used to operate the KST unit.

F i g. 9 processor instructions in the processor main memory with which each processor in the multiple system of the KST unit can give signals for controlling the configuration of the system or a part thereof,

F i g. 10 the format of the outdoor modem adapter commands and

F i g. 11A, 11B, and 1C show formats for an extension of the RM instruction format shown in Fig. 10 for communicating the configuration information or control signals to an outdoor modem adapter RM from the KST unit. bo

F i g. Fig. 1 shows a multiprocessor system or multi-computer system including a plurality of processors (or CPUs) Pi to PN, each having one or more dedicated input / output channels, hereafter called channels. The b5 processors do not need to be identical , and it is assumed in the exemplary embodiment that they are different from each other. The processor P 1 has the channels A, C, the processor P2 the channels A and B, and the processor N has the channels A and B. The processors Pi and PI have local operation consoles 101 and 102, but the processor PN is assumed that he does not have these. In addition, the processor P2 includes a service processor 103, which is also connected to the processor P 1 via the line 104.

A configuration and control unit KST (KST unit) is connected to a channel of each processor so that exchange of system configuration information and commands between all processors and the KST unit is possible. For reasons of reliability, two or more channels of each processor (not shown) can also be connected to the channel adapter 201 of the KST unit, so that each processor can still exchange information with the KST unit if one of its channels fails. The channel adapter 201 is connected to the interface of the respective channels, which leads to the EA units 15 This can, for. B. the interface between channel and I / O control unit, which can be found in commercially available systems. The KST unit has a unique address, which appears to the processors as the address of an I / O control unit

Furthermore, several coordinate switches K 1 to KN are provided, whose inputs are also connected to the channels of the processors. The coordinate switches Ki to KN need not have a uniform size. For example, the switch K 1 has three inputs and four outputs, while the coordinate switch KM has four inputs and four outputs. The channel inputs of each coordinate switch can therefore be connected to each channel of each processor. Each coordinate switch can connect each of its channel inputs to each of its outputs, which can be connected like channel outputs, e.g. B. to an EA Steuei unit or to a control unit switch 10 to 13, (through which a plurality of channels can be connected to a control unit). For example, the coordinate switch Ki can switch each of the three connected channels to the input C of a four channel control unit switch 12. Similarly, the output L 2 of the coordinate switch K 1 is connected both to the input B of the two-channel control unit switch 11 and to the EA control units 53 and 55. The output L 3 of the coordinate switch K 1 is connected to the input D of the four-channel control unit switch 12, and the output L 4 of the coordinate switch K 1 to the input A of the two-channel control unit switch 13 Thus, the three channels connected to the input of the coordinate switch K 1 are connected simultaneously to each of three of the following units: (1) EA control unit 56, (2) one of the EA control units 53, 54 or 55 and (3) EA control unit 57. If one channel is connected to multiple I / O controllers, only one I / O controller can be selected by the channel at any given time by sending an I / O controller address to that channel.

Similarly, each of the four channels connected to the coordinate switch KN can be simultaneously connected to: (1) I / O control unit 57 via two-channel control unit switch 13 at (2) I / O control unit SK, output L 1 de: coordinate switch K Λ / is not connected and standing

available for a future connection. The configuration and control unit KST has two types of output connections, the parallel lines PWL from a parallel line adapter 230 (PL adapter) and the time-division multiplex lines TML from a ■, time-division multiplex adapter 240 (ZM ​​adapter). The parallel lines PiVLl, PWL-2, ..., PWL-M are connected to the control inputs of the coordinate switches Ki to KN, the four-channel control unit switches 10, 12 and the two-channel control unit switches 11, 13. The control input to the coordinate switch K 1 in F i g. 1 is connected to the parallel lines PWL-M of the adapter 230, while the control input to the coordinate switch RM is connected to the time-division multiplex line of the time-division-multiplexing adapter 240. The ι * -,

Time division multiplex lines TML-i, 7ML-2 TML-Psind

each connected to an outdoor modem adapter AM, which is connected to the unit to be controlled.

Overview of the configuration and control unit (KST unit)

20

The KST unit is connected to each processor in the multiple system from which it can receive configuration and control commands as well as data. The KST unit has two types of outputs: (1) Parallel Line (PL) Adapters and (2) Time Division Line (ZM) Adapters, which are connected to other units in the multiprocessor system. When a unit is connected to the ZM adapter 240, an outdoor modem adapter, ÄM, is provided on the unit.

A unit connected to the PL adapter 230 receives only switching signals but no data from the KST unit. A device connected to the ZM adapter 240 can also receive data as switching or control signals as j5 and transmit maintenance information to the ZM adapter 240. Devices with high data transmission speeds can be controlled by the PL adapter 230 or the ZM adapter 240 via coordinate switches Ki to KW 4-channel control unit switches, 2-channel control unit switches, etc., which receive data and control commands directly from the channels, which are primarily intended for the system I / O devices.

The time division operations and the control processor operations in the KST unit may limit the data transfer rates through this unit. Low data rate devices can therefore be connected directly to the ZM adapter 240 with data inputs / outputs without the need to use a channel switch for such devices so that they can communicate with each processor in the multiple system.

The PL adapter 230 can therefore only output configuration switching signals. The ZM adapter 240 may transmit both configuration signals, maintenance signals or control signals, and data to and from the configuration and control unit / CST.

Thus, the KST unit acts as a channel switch for all units that receive their data through the ZM adapter 240 because the KST unit can switch the data from each connected channel to each ZM adapter output and vice versa. In this way, the KST unit can establish a data connection between a b5 external device connected via a time division multiplex line TML and each processor. For example, the remote control console 105 may be connected to each processor, as well as the service processor 103 and the local service console 102.

Details of configuration and control unit (KST unit)

In F i g. 2, an embodiment of the KST unit is shown. The KST unit contains a channel adapter 201 consisting of several channel interface ports KANAL-ANSi, 2 ... N, which can connect the KST unit with up to N processors via their channels. Each channel interface port includes a connector to which the controller interface of a channel is connected in a known manner. The terminals of the interface plugs are connected to the inputs of a conventional channel multiplexer 210, which outputs the signals of a selected channel on the lines of a bus 211, which is a branch of a data bus 212 of a control processor 216 which is designed as a microprocessor The bus 212 and all its branches lie completely within the KST unit. The bus 212 connects all the signal processing devices in the KST unit to the control processor 218 and a memory unit 217 connected thereto, which may be arranged on a common chip with the microprocessor-based control processor 216. The PL adapter 230 is connected via the bus branch 221, the ZM adapter 240 via the bus branch 22, a magnetic recording memory 223 and a configuration check timer 224 via a bus branch 225. A configuration recovery signal encoder 250 is connected via the bus branch 251 and Maintenance field 270 connected via the manifold branch 271.

The processor control of the KST unit is accomplished by processor instructions to the KST unit via a processor channel and the channel adapter 201 as well as the buses 211 and 212 leading to the control processor 216. The format of these commands is shown in FIG. These processor instructions show the KST unit the necessary switching and control operations in FIG. 1 shown multiple system.

All devices connected to the outputs of the KST unit can be driven by each processor to form a desired system configuration, but do not receive all data through the KST unit. Each to an EA control unit 51, 52, ... SKm F i g. 1 connected MA unit 15 can be connected to each processor Pi, P2, ... PN within the available connection arrangement shown. The processor 1 can thus to all in F i g. 1 shown EA devices are connected for the purpose of data transmission, ie the channel A can be connected to the EA control units 51 and 52. The channel B can be connected to the control via the ZM adapter with the EA control units 52, 53, 54, 57 and SK and can be connected to the control consoles 105 and 102 and to the service processor 103 for data transmission. The channel Cist for data transmission connectable via the coordinate switches K i and KN with the EA control units 53, 54, 55, 56, 57 and SK. The processor P 2 is connectable for data transmission with the devices on the EA control units 5 2.5 3.5 4.5 5.5 6.5 7 and 5 K, the control panels 102 and 105 and the service processor 103. In the same way is the processor N for data transmission

Connectable via the coordinate switch K 1 or KN with the devices to the EA control units 53, 54, 55, 56, 57 and SK and the control panels 102 and 105 and the service processor 103rd

Due to processor commands, the control processor 216 provides configuration switching control signals over the bus branches 221 or 222 to the PL adapter 230 or the ZM adapter 240 to select particular outputs of the KST unit. A selected PL output provides a DC voltage configuration signal to a coordinate switch or channel control unit switch to control the connections within the switch. A selected ZM adapter output transmits a serial pulse train to an outdoor modem adapter RM, which picks up the pulses and provides the signals to all connected switch units, (1) to control the connections to channels through the switch unit, and (2) the transmission of To control unit maintenance information from the RM to the KST unit, (3) to transmit processor data between the data devices connected to the RM and the KST unit; or (4) to send control signals to the I / O controllers 51 to SKöder control panels 102, 105.

Connected to the busbar branch 271 of the KST unit is a conventional maintenance panel 270 containing the standard switches and indicators used with a processor or microprocessor.

In fig. 2, floppy disks are recorded in microprograms which are loaded into the memory unit 217 for operation of the control processor 216. Configuration check timer 224 periodically sends signals to magnetic recording memory 223 and control processor 216 via bus line 225 to write the contents of memory unit 217 to a designated area of ​​magnetic recording memory 223 that may be overwritten during each periodic checkpoint. Thus, the magnetic recording memory 223 holds as stream independent existing records the entire system configurations at each checkpoint in blocks in the storage unit 217. If the multiple system or part of it fails due to power cut or for other reasons, you can recover the system configuration that existed and was saved at the time of the last checkpoint. However, this configuration information does not necessarily correspond to the configuration that exists at a later time, namely in the event of system failure, since configuration changes may have been made between the failure time and the previous checkpoint. However, the exact system configuration existing at the time of failure can be determined from the content of a configuration memory 227 in the PL adapter and from the content of an additional configuration memory 427 in the RM in FIG. Recover 4B. The two configuration memories 227 and 427 are designed as "stable" memories, ie they have a structure such that the stored information is retained even in the event of a power failure (current-independent memory function). In any case, an accurate b5 recording of future usable configuration information, ie an entry in the blocks BL 1 and BL 3 in FIG. 8, is possible through the checkpoints.

A configuration recovery signal decoder 250 in the KST unit (Fig. 2) may be connected to provide signals to the system to establish its last commanded configuration. This happens:

a) On power up, when a Power Start signal is given from power supply controller 260/261 to line 262;

b) upon the occurrence of a restore command 917 (Fig. 9) by a processor which activates a restore command signal on line 251; and

c) Machine malfunction interruption in the KST unit.

The configuration recovery signal encoder 250 provides an IPL start signal (/ PL = initial program load) on line 252 to the magnetic recording memory 223 to return the contents of the memory unit 217 to the last checkpoint state. The configuration recovery signal encoder 250 issues a configuration recovery signal on the line 253 to the PL adapter 230 and the ZM adapter 240 to restore the configuration, the acute configuration information in the persistent memory of the PL adapter and the RM adapter equivalent. For example, during the initial program load (IPL) in the morning, the channel switching connections and the coordinate switch connections may be restored to the state that existed at the previous day system shutdown, regardless of the elapsed time between the system shutdown and the initial program load.

ZM Adapter 240 (Time-Division Multiplex Adapter)

The ZM adapter 240 in FIG. 2 consists of several conventional modulator / demodulator units (modems) M \ to MP, which are connected to the bus branch 222 via the external modem multiplexer (transmit / receive time multiplexer) 241. Also, the out-of-the-box multipiece 241 is a conventional device that converts parallel signals from and to the trunk line 22 into serial signals to and from a TNT line connected to the selected KST modem.

PL adapter 230 (parallel line adapter)

F i g. 3 shows an exact embodiment of the PL adapter 230 in the KST unit. The PL adapter 230 includes a read / write multiplexer 226 which includes a plurality of read / write registers 320 each having 16 bit positions corresponding to 16 data lines on the bus branch 221 of the control processor 216. There are / read / write registers 320 corresponding to J times (in time multiplexed) for a set of parallel line configuration data (PWL) from the control processor 216 corresponding to a bit cell in Table 1 in FIG. 8 and to be transmitted to the configuration memory 227 whose memory function is current-independent.

The read / write multiplexer 226 further includes a time division control decoder 301 connected to a bus 221 for controlling time division multiplexing in the write / read registers 320 in a conventional manner. The decoder 301 may consist of a counter which is incremented at each received bus clock signal

Unit continues to drive to the next read / write register 320 until the counter has completed a full cycle when all read / write registers 320 have been allocated a PWL configuration set. The decoder output line 302 indicates the end of the reception of the configuration record to a decoder 311 which causes the data received in the read / write registers 320 to be transmitted and written to the configuration memory 227. The configuration memory 1 "227 has a current-dependent memory function; in this embodiment, it is assumed that it consists of conventional mechanical bistable relay switches, which retain their last setting as soon as the power is turned off. Each bit in the configuration memory 227 is stored in a corresponding relay, referred to as PSD. Each PSD is switched to the ON state by actuation of an AND gate 312 or to the zero state (AB) by operation of an AND gate 313 to represent the binary value of the corresponding bit in read / write registers. Each pair of AND gates 312 and 313 is thus connected with its inputs to the true or complement output (via the inverter I) for a bit position in the write / read register 320 whose position reference number is taken up to the AND gate reference number. The other input of the AND gates 312 and 313 is connected to the output of the decoder 311 to clock the transmission of bits from the read / write registers to the configuration memory 227. Once the units in the configuration memory 227 are switched to a particular state representing a particular configuration for the devices connected via parallel lines PWL, this configuration is continuously indicated by closed contacts on the output lines from the configuration memory 227 (DC signals).

The bit positions in the configuration memory 227 are grouped by the switch unit that controls them. Two bit positions are used for a two-channel switch, such as PSD 1-1 and 2-1 in Fig. 3, which can be connected to the two-channel switch shown in Fig. 3A. For a four-channel switch four bit positions are used, such. PSD 1-2, 2-2, 3-2 and 4-2, which can be connected to the four-channel switch shown in Fig. 6B. Eight bit positions such as PSD 1-M to 8-M that can be connected to the coordinate switch shown in Fig. 5A are used for a coordinate switch.

Each PSD has multiple outputs, one of which is fed back, while the others provide the signals N / O, C and N / C to the respective switch unit, as shown in FIG. 6A and 6B can be seen.

Coordinate switch according to F i g. 5 are known. The decoder 301 is additionally incorporated to receive the control signals from the KST unit. The fi g. 5A shows the connection of the coordinate switch Ki in FIG. I to the in F i g. 3 output PWL-M of the configuration and control unit KST.

FIGS. 6A and 6B show the two-channel switches or four-channel switches 11 and 10 and their connections to the designated PWL connectors in the KST unit.

For the PSD feedback signals, a set of ir, restore gates 321 is provided at the respective read / write register bit positions. Restore gating circuits are actuated by a restore signal on line 253 from configuration restore signal encoder 250, which resets volatile read / write registers 320 to the state found in configuration memory 227.

Outdoor Modem Aaapter (RM)

FIGS. 4A and 4B each show a different type of outer modem adapter (RM). An RM is part of each external system unit connected to the ZM adapter 240 of the KST unit.

The in F i g. 4B has another basis for the reconfiguration of the switch units it controls than the one shown in FIG. 4A, which does not have the configuration memory 427, which is shown in FIG. 4B /? Mfindet.

The RM in Fig. 4A is for increasing the reliability when it is fed from a source other than the KST unit, so that it does not fail when the power supply of the KST unit fails. In this case, the current (acute) configuration becomes from the non-failed unit, ie the RM, to the other unit to restore this system configuration. (In the opposite case, ie If the KST unit fails and the RM does not, then the current (acute) configuration stored in the configuration register 420 of the RM becomes the KST via bus 434. If the "AM" fails, but the KST unit fails Unit to restore the configuration. By / PL (initial program load) of the memory unit 217, the control processor programs and blocks are restored in the form in which they existed at the last checkpoint before the standstill or the failure of the KST unit.

The configuration stored in the configuration register 420 (Fig. 4A) is provided to support switchable units as needed, such as the connection to the service processor 103 in Fig. 1, which is switchable to the processor Pi or P 2, even if it spatially located at the processor P 2.

Each AM includes an external modem 411, which is a conventional modulator / demodulator, which transmits data on the output lines 431 through a bidirectional gate circuit 430 from and to an external unit such as a control unit, a service processor, a remote control station, and so forth can. The outer modem 411 also has inputs 434, 435 and outputs 432, 433 connected to a maintenance register 416, a control register 425, the configuration register 420, or a control processor command decoder 412. The output 431 transmits data to and from certain units connected via time-division multiplex lines 7ML. The output 432 provides command signals to a control processor command decoder 412 which controls the transfers to and from the registers 416, 425 and 420 via their respective input port circuits 417, 415, 413, 422 and 421 and the corresponding output port circuits 418, 414, 423 and 424 , In addition, in FIG. 4B, an input gate 428 is provided for the register 420 to place the existing configuration information from the additional configuration memory 427 into the configuration register 420. All modem inputs and outputs converge conventionally in outer modem 411 to a bus

An RM command is sent from the control processor 216 to a selected outside modem adapter RM when the control processor 216 initiates an operation on the data output lines 431 or a :; the register wants to have 416,425 or 420 executed in the RM. The RM instruction format is shown in Fig. 10 where bit positions 4 through 7 contain the RM instruction operation code.

The control processor command decoder 412 includes a clock (not shown) that starts one cycle on each byte received by the modem except upon detection of a command code by the control processor command decoder 412. In this case, it starts an extra cycle for each of the control commands B1 to B10 listed in the subsequent RM command bar, but two extra cycles after the data command 11 of the table below has been detected. The combination of bits 4, 5, 6 and 7 received from the control processor command decoder 412 activates the decoder outputs B 1 to B 10 in the F i g. 4A and the decoder outputs B 1 to B 11 in FIG. 4B corresponding to the similarly numbered instruction codes according to the following table:

<p><tgroup cols="6"><tbody><row><entry>command</entry><entry>Code-op</entry><entry>0</entry><entry>Bits of</entry><entry>1</entry><entry>RM-operation</entry></row><row><entry>No.</entry><entry>command</entry><entry></entry><entry></entry><entry></entry><entry></entry></row><row><entry>sl</entry><entry>0</entry><entry>0</entry><entry>0</entry><entry>0</entry><entry>From maintenance reg. at</entry></row><row><entry></entry><entry></entry><entry></entry><entry></entry><entry></entry><entry>Modem,</entry></row><row><entry>S2</entry><entry>0</entry><entry>0</entry><entry>1</entry><entry>1</entry><entry>to maintenance reg. from</entry></row><row><entry></entry><entry></entry><entry></entry><entry></entry><entry></entry><entry>EA-control unit,</entry></row><row><entry>S3</entry><entry>0</entry><entry>1</entry><entry>1</entry><entry>0</entry><entry>at configuration</entry></row><row><entry></entry><entry></entry><entry></entry><entry></entry><entry></entry><entry>reg. from modem,</entry></row><row><entry>S4</entry><entry>0</entry><entry></entry><entry>0</entry><entry></entry><entry>at configuration</entry></row><row><entry></entry><entry></entry><entry>1</entry><entry></entry><entry>1</entry><entry>reg. from tax</entry></row><row><entry></entry><entry></entry><entry></entry><entry></entry><entry></entry><entry>switches,</entry></row><row><entry> B5 </entry><entry>0</entry><entry>1</entry><entry>0</entry><entry>0</entry><entry>from configuration</entry></row><row><entry></entry><entry></entry><entry></entry><entry></entry><entry></entry><entry>reg. to channel switch,</entry></row><row><entry>S6</entry><entry>0</entry><entry>1</entry><entry>1</entry><entry>1</entry><entry>from configuration</entry></row><row><entry></entry><entry></entry><entry></entry><entry></entry><entry></entry><entry>reg. to modem,</entry></row><row><entry> bl </entry><entry>0</entry><entry>0</entry><entry>1</entry><entry>0</entry><entry>to tax reg, from</entry></row><row><entry></entry><entry></entry><entry></entry><entry></entry><entry></entry><entry>Modem,</entry></row><row><entry> BS </entry><entry>1</entry><entry>0</entry><entry>0</entry><entry>1</entry><entry>from Steuerreg, to</entry></row><row><entry></entry><entry></entry><entry></entry><entry></entry><entry></entry><entry>EA-control unit,</entry></row><row><entry>59</entry><entry>1</entry><entry>0</entry><entry>0</entry><entry>0</entry><entry>to tax reg, from</entry></row><row><entry></entry><entry></entry><entry>0</entry><entry></entry><entry>1</entry><entry>Control switches,</entry></row><row><entry>ßlO</entry><entry>1</entry><entry></entry><entry>1</entry><entry></entry><entry>Pass data,</entry></row><row><entry>SIl</entry><entry>1</entry><entry>1</entry><entry>at configuration</entry></row><row><entry></entry><entry></entry><entry></entry><entry>reg. from PSD.</entry></row><row><entry></entry></row><row><entry></entry></row></tbody></tgroup></p>

20

40

45

50

55

If one of the RM control commands Bi to β9 or SIl is detected during an RM cycle, the command is extended during the next cycle by transferring a byte of configuration, control or maintenance information from block BL3 to t> o the RM or from the RM to block BL 4 as shown in Figures 11A, B and C. The configuration or control bit (KF / ST) in block BL3 is not transmitted to the RM. When the data command 610 is asserted, transmission of the command to b5 immediately follows the RM's transfer of two bytes of data between the RM and the KST unit during the following two cycles (ie, one byte per cycle).

A row of the bits received by the KST unit, which represent either configuration information for a channel switch unit or control information for an I / O control unit or a processor console, appears at the output 433. A previous instruction on the output line 432 activates the line S3 if it is configuration information for the configuration register 420, or the line 7 if it is control information (to an I / O controller or a processor console) for the control register 425. The input 434 transmits the configuration information of the configuration register 420 to the external modem 411 for retransmission to the KST unit in response to a command 6. The input 435 transmits the contents of the maintenance register 416 to the external modem 411 for transmission to the KST unit. The outer modem 411 may thus return the contents of the register 416 or 420 to the memory unit 217 on command of the control processor 216.

With the control register 425, commands such as IPL (initial program load) or reset (normally called by push buttons on the processor or controllers) may also be initiated under the control of the KST unit. When switch 451 is in the local control position, control processor command decoder 412 gates gates 415 and 414 to output the position of control switches 455 to EA controller 15 or console 102 on lines 46M to 4617V. When the switch 451 is in the remote control position, the control processor command decoder 412 effects transfer of the control data from the external modem 411 to the control register 425, thereby electronically controlling the same control switch functions by a sequence: RM command S7 / data / RM command S8 (see above RM command table) sent from the KST unit to the outmodem 411.

According to F i g. 4A, the configuration register 420 has an eight-wire output bus 426 which connects the eight outputs from the register 420 to the three RM output groups 441, 442 and 443. The output group 441 (which may be a plug) is connected to all eight wires of the bus 426 and can be connected to a coordinate switch, as in F i g. 5B is shown. F i g. 5B shows the eight input connections to the channel coker switch M with the eight-wire output of the adapter! RM in the Fi g. 4A or 4B. The output group 442 is intended for a four-channel switch and connected to the four wires A, B, C and D of the bus 426. The output group 442 can ar a four-channel control unit switch of the in Fig. G. 7E type are connected. Similarly, the output group 443 may be connected to a two-channel controller switch of the type shown in Fig. 7A. The fi g. 7A and 7B thus show the connection possibilities one; Two-channel control unit switch and a four-channel control unit switch with external modem adapter RM to the time-division multiplex lines 77WL of the configuration and control unit KST and also internal design.

The maintenance register 416 receives maintenance information from one or more connected external devices such as an EA control unit 51 to SK of a remote control console 10;

or a service microprocessor 103. The bits in the register represent the condition of abnormal operating conditions such as I / O overtemperature, Ea machine error, I / O power failure, etc., and are separate from the normal status bits transmitted from an I / O controller to a conventional data processing system become.

In Fig. 4A, the external modem adapter RM also has a local control panel containing a plurality of maintenance indicators 456 which indicate the contents of the bit positions in the maintenance register 416. In addition, the local control panel includes a plurality of configuration switches and control switches 455, the settings of which may be entered into registers 420 and 425 when a switch 451 is manually set to Local Control, whereby the control processor command decoder 412 activates its outputs 4 and 9 for opening the gate circuits 422 and 415 for transmitting the positions of the configuration and control switches 453 and 455.

In F i g. 4B is an additional persistent configuration memory 427 of FIG. 4A basic structure of an outer modem adapter RM added. The configuration memory 427 includes eight persistent storage units PSD-i ... PSD-S corresponding to the eight bit positions in the configuration register 420. The same elements can be used as the stable memory as in the configuration memory 227 in the PL adapter 230 in FIG. Third In this case, the configuration memory 427 consists of eight bistable relays. Likewise, however, for each PSD element, other nonvolatile memory elements such as ferrite cores may be used.

In F i g. 4B are the output lines of the configuration register 420 (corresponding to the bus 426 in FIG. 4A) connected to the inputs of the configuration memory 427. Each bit in the configuration memory 427 is fed back to the corresponding inputs of the configuration register 420 via an input gate 428 due to the modem command 11 (see table above) which can be issued by the KST unit each time it reads the contents of the volatile configuration register 420 the configuration currently stored in the configuration memory 427. Then command 6 (see table above) may be issued by the KST unit to pass the contents of the configuration register 420 to the modem for transmission to the KST unit so that it can reconstruct the system configuration that existed at the time, where the contents of the memory unit 217 or the configuration register 420 were lost.

Processor control of the configuration and control unit KST

55

The KST unit is replaced by the one shown in FIG. 9, which may be delivered by any of the processors Pi through PN, but the system may exclude particular processors as needed by means not part of this invention.

The processor instructions used in the embodiment are conventional channel instructions whose format is tailored for use by the KST unit. The write command 911 and the read command 915 in FIG. 9 may be known commands of a commercially available central processing unit, while all other instructions in FIG. 9 are also known control commands which differ by different modifier bits in the opcode. Only bits 0 to 31 of the instructions are in F i g. 9, since bits 32 through 63 represent the usual tag and byte count field.

The processor instructions control the control processor 216, which in turn controls blocks and programs in the memory unit 217 shown in FIG. The microprograms and blocks may be inserted into the memory unit 217 by initial program loading (IPL) from the magnetic recording memory 223. The circuitry in the time division multiplexers 210, 266 and 241 (Figs. 2) and the control processor programs 801 (FIG. 8) control transfers of control signals and data by the KST unit which are buffered in the blocks BL 1 and BL 3 in the storage unit 217 as shown in FIG. These control processor programs are initiated by command signals transmitted by a processor via its channel connected to an interface connector of the KST unit. Each processor command in F i g. 9 contains an address of processor main memory 901 at which an address of memory unit 217 is found. The processor instruction activates conventional channel lines to the associated interface connector.

The write control command 910 is used together with a subsequent write command 911 by a processor Pi to PN to set up or modify the blocks or microprograms shown in FIG. 8, or to write to another field of the memory unit 217. The write control command 910 is executed by the processor Pl to PN by driving the addressed location in the processor main memory 901 shown in Fig. 9 and transmitting the content as a control signal to the interface connector for that processor.

The control signal generated by the code in one of the instructions 910 through 917 is sent from the interface connector as an address to the control processor 216 to activate an execution microprogram in the memory unit 217 that uses the control signal to drive a row in block BL 2, to start a microprogram, which corresponds to the received processor command The signals provided, for example, by the processor write command activate a write program in the memory unit 217, which is then executed by the microprocessor to write the received data to the indicated location. In this way, the data transferred from the addressed processor main memory in the subsequent write command 711 is brought to the control memory address transmitted by the write control command 910. The lines in block BL 2 in FIG. 8 contain addresses of entry points of the microprograms 8iO in the memory unit 217.

Each line (KONF) in block BL 1 in F i g. 8 may contain the information for a particular configuration via parallel lines PWL connected units (PL units), and the different rows then store various available configurations. A line with a desired configuration is selected by transferring the contents of this line to block BL 1 of the configuration mapper 227 in FIG. 2, in which a processor P 1 to P N controls the command 912 »configure PL devices« in FIG. 9 delivers. Instruction 912 transfers from the processor main memory 901 the address of the requested line

in the block SL1 in the memory unit 217. The line content is then transferred to the configuration memory 227 in Fig.2 via the bus 212 and its branch 221. The PL unit configuration is changed by selecting and transmitting another row of the BL1 block containing the next required configuration. The ZL1 block is initially set up and can later be changed by the 410 and 911 commands for all PL system switchable configurations , In addition, if a PL unit configuration is not found in block BL 1, a new configuration may be entered at a later time into a selected row in block BL 1 with instructions 910 and 911. So there are S different PL configurations, which can be specified in block 5Ll.

Similarly, command 913 »Configuring or Controlling RM Units« can be used to configure or control RM units. The main memory address of the instruction 913 contains the address of a line in the block BL 3 of the memory unit 217. The lines in the block BLZ contain either one

RM coordinate switch configuration signal (Fig. 1IA or RM-EA switch configuration signal, Fig. 1 IB) for a specified outdoor modem adapter RM or a control signal for the RM units corresponding to the respective rows. The channel signals output for the command codes are interpreted by the control processor 216 in a conventional manner to invoke corresponding microprograms by the control processor 216, using the channel command code signals, to drive corresponding lines in block BL2 to initialize microprograms selected therefrom.

The channel signals output for the instruction codes of instructions 913 and 914 control the rows in block BL 2 to initiate execution of the microprograms that read rows from blocks BL 1 and BL 3.

A control processor instruction of the type shown in FIG. 10 is issued by the microprogram "control or configure RM units" to select a particular outmodem adapter RM whose units are to be configured, or to issue a control signal through a command 913 which RM is indicated by the address in a selected row in block BL 3.

The read maintenance register instruction 914 from a processor indicates to the control processor 216 that it must execute a microprogram that issues the instruction Bi (see microprocessor instruction table above) to transfer the contents of the RM maintenance register 416 to the control processor via time division multiplex lines TML To direct 216 Then, a control processor issues instruction 914 "Read Maintenance Register", and then reads command 915, with which the channel sends the TMl index for the requested state to block BL 4 in block BL 4 KST unit transmits. The KST unit responds by driving the relevant TML index in block BL 4 and transmitting the maintenance data to the main memory location specified in read command 915. In this way, the external maintenance state is set in block BL 4 and then transferred to the processor main memory under the control of the bs processor.

Restore command 917 is used by each processor after a suspected multisystem failure. Command 916 signals the initial program load IPL to the KST unit and restores the last specified overall system configuration by reloading memory unit 217 with the version of the blocks and programs at the last checkpoint stored on the disk file 223. Then, the control processor issues commands to the configuration entries in the blocks BLi and BL3 from the existing settings to the configuration memory 227 in the PL adapter and the configuration memories 427 in the out-of-state adapters AM Thus, the acute configuration entry in the block BL 1 is issued by a command returned to the configuration recovery signal encoder 250 in FIG. and entries in block BL 3 are retrieved by querying all outboard modem adapters AM with control processor commands BIO and B6 (for each RM unit). A completion signal is set to the main memory address for instruction 917 when checkpoint recovery is complete. Block 4 is retrieved by issuing an instruction read maintenance register 914 and a read instruction 915 (from a processor) for each time division multiplex line TML.

Multiplexing operations in the configuration and control unit KST

Each processor Pl to PN is connected to an associated interface connector in the channel adapter 201 of the KST unit (Figure 2). The KST unit therefore identifies a particular processor by its unique association with an interface connector. In the case of FIG. The channel multiplexer 210 shown in FIG. 2 is a conventional device.

Each processor Pi through PN may connect itself to the KST unit by issuing a dial instruction in which the KST unit is addressed by a unique address (in the instruction box of the instruction). The connection is then made between the KST unit and the processor in a conventional manner (if the KST unit is not busy, ie not currently connected to another processor).

Meanwhile, when the KST unit is busy, the processor P1 through PN can do something else and at a later time resend the dialing instruction until it finds the KST unit unoccupied and the connection is made. Once the processor is connected, it transmits its commands and / or data to the KST unit where it is either executed or forwarded to the addressed outdoor units. When the processor completes the transmission or expands its transmission beyond a predetermined period, the connection is terminated and the KST unit becomes free and can then be dialed again by a processor P1 to P TV, which provides a dial instruction to the KST unit releases

When the processor P1 to PTV transmits control information for a KST-controlled coordinate switch Ki to KN or a control unit switch 10 to 13, the KST unit sets the control unit switch for the required I / O connections and disconnects from the processor. All subsequent transfers between the accepted

closed units and the processor then bypass the KST unit, which is free to service other processors

In this way, one processor's data can be transferred to and from each outmoded adapter. The KST unit can connect each processor to each outdoor modem adapter RM by simple connection.

An operator on a control panel connected via the ZM adapter 240 may therefore control the connection of the control panel (eg, 102) with each of the processors P1 through PN to send messages to or receive messages from the processor. For this purpose, the operator writes a command in the conventional manner on the control panel, which is then sent to the currently connected to the control panel processor Pl to PN. The console command may designate any processor P1 through PN to which the console is to be connected. The KST unit establishes the connection between the console and the requested processor.

By way of example, suppose an operator console has an outdoor modem adapter RM connected to line 77 "ίΖ ^ 2, currently connected to the processor PN. Thus, at the moment the control panel is connected only to the processor PN. When the operator types in a command, eg "Connect TML-2 with Channel Interfaces", which requires the console to be connected to the P 1 processor, this command is received by the KST unit which then establishes the connection between the control panel and the requested processor Pl, which then acts as the single processor can exchange messages with the control panel. In this way, the operator console can be connected to any processor on demand from the control panel.

For this 9 sheets of drawings