Semiconductor die package and method for making the same

REFERENCES TO RELATED APPLICATIONS

0001These Patent application is for a subsequent application and claims priority to the following provisional U.S. applications: 60 / 701.781, filed on 22 July 2005; 60 / 696.320, filed June 30, 2005; 60 / 696.027, filed June 30, 2005; 60 / 696.350, filed June 30, 2005; 60 / 702.076, filed on 22 July 2005; 60 / 696.305, filed June 30, 2005 and 60 / 753.040, be filed on 21 December 2005. This provisional US applications hereby incorporated by reference in their entirety for all purposes.

BACKGROUND OF THE INVENTION

0002Various Semiconductor chip package or wraps known.

0003While such housing useful are able they can be improved. For example, many of the above-described housing difficult and / or expensive to manufacture.

0004consequently would it be desirable, improved semiconductor chip package, A process for the production of semiconductor chip packages, components for such chip package and electrical assemblies which utilize such a semiconductor chip package, provide. Such improved semiconductor chip package preferably would be less expensive to manufacture and / or would have a better functionality.

SUMMARY OF THE INVENTION

0005embodiments of the invention are directed to semiconductor chip packages, methods for making of semiconductor chip packages and electrical components that include the semiconductor chip package, addressed.

0006A embodiment the invention is directed to a method comprising providing a preformed substrate with a leadframe structure and a molding material, wherein the leadframe structure includes a first conductive portion, a second conductive portion and a Intermediate portion between the first conductive portion and the second conductive portion includes; Separating the intermediate portion, to the first conductive portion of the second conductive portion electrically isolate; Attaching a semiconductor chip to the substrate; and electrically coupling the first and second conductive Part areas to the semiconductor chip.

0007A another embodiment the invention is directed to a semiconductor die package directed, comprising: a premolded substrate comprising a leadframe structure and a molding material, wherein the leadframe structure includes a first conductive portion, a second conductive portion and Recess between the first conductive portion and the two th conductive portion includes; a semiconductor die on the premolded substrate; and an encapsulating material covering the semiconductor chip and the recess between the first conductive portion and the second conductive portion fills.

0008A another embodiment the invention is directed to a method comprising: providing a pre-formed substrate having a first surface and a second surface, wherein the preformed substrate includes a leadframe structure and a molding material includes, wherein the leadframe structure a field region and includes field region, wherein an outer surface of the Field region and an outer surface of the Molding material are substantially coplanar or coplanar with the second surface of the preformed substrate coincide; and attaching at least two semiconductor chips on the first surface of the preformed substrate.

0009A another embodiment the invention is directed to a semiconductor die package directed, comprising: a premolded substrate including a first surface and a second surface, wherein the preformed substrate comprises a leadframe structure and a Molding material contains, the leadframe structure, a field area , wherein an outer surface of the Field region and an outer surface of the Molding material are substantially coplanar and with the second surface the preformed substrate coincide; and at least two semiconductor chips to the first surface are coupled to the preformed substrate.

0010A another embodiment the invention is directed to a method of forming a semiconductordirected chip package, the method comprising: forming a substrate, forming a Substrate comprising (i) placing a leadframe structure between a first and a second Ausformform Ausformform, (ii) contacting the leadframe structure with the first and second Ausformformen, and (iii) molding a molding material around the leadframe structure; Attaching a semiconductor die to the substrate; and encapsulating of the semiconductor chips in an encapsulation material.

0011A another embodiment the invention is directed to a semiconductor die package directed, comprising: a substrate, wherein forming a substrate a leadframe structure and a molding material, wherein the Substrate forms at least one concave structure; and a semiconductor chip on the substrate.

0012A another embodiment the invention is directed to a method comprising: providing a Substrate including a leadframe structure and a molding material, wherein a surface the molding material and the leadframe structure is substantially coplanar , and wherein the substrate is a first die attach region and a second die attach region includes; fix a first semiconductor chip to the first chip mounting area; and securing a second semiconductor die to the second die attach region.

0013A another embodiment the invention is directed to a semiconductor die package directed, comprising: a substrate including a leadframe structure and a molding material, wherein a surface of the molding material and the Leadframe structure are substantially coplanar, and wherein the substrate is a first die attach region and a second Die attach area includes; a first semiconductor chip on the first die attach region; and a second semiconductor chip on the second die attach region.

0014A another embodiment the invention is directed to a method for producing a substrate for a Semiconductor chip package addressed, the method comprising: providing a first leadframe structure and a second leadframe structure; Securing the first and second leadframe structure together using an adhesive layer; and applying the molding material to the first leadframe structure, the second leadframe structure, or the adhesive layer.

0015A another embodiment the invention is directed to a semiconductor die package directed, comprising: a premolded substrate comprising a leadframe structure and a molding material, wherein an outer surface of the leadframe structure and an outer surface of the Molding material in union Wesent coplanar are; and a semiconductor chip on the preformed substrate; to the preformed substrate mounted ladder wherein the conductors are individually formed from the preformed substrate

0016A another embodiment the invention is directed to a method comprising: providing a Substrate comprising a conductive die attach surface; Securing a high side Transistor including a high side transistor input to the substrate, wherein the high side transistor input to the conductive Die attach surface coupled; and attaching a low-side transistor including a low-side transistor output to the substrate, wherein the low side transistor input to the conductive die attach surface coupled is.

0017A another embodiment the invention is directed to a semiconductor die package directed, comprising: a substrate comprising a conductive die attach surface; a high side transistor comprising a high side transistor input, wherein the high side transistor input to the conductive die attach surface coupled is; and a low-side transistor including a low side Transistor output, the low side transistor input is coupled to the conductive die attach surface.

0018These and other embodiments of the invention are described below in further detail.

BRIEF DESCRIPTION OF THE DRAWINGS

0019<figref idrefs="S95">1A</figref>-<figref idrefs="S96">1H</figref> show Cross sections of components during of forming a semiconductor chip package according to an embodiment the invention.

0020<figref idrefs="S96">1I</figref> shows a bottom view of a semiconductor chip package according to an embodiment the invention.

0021<figref idrefs="S97">1y</figref> is a plan view of an arrangement of substrates during Production.

0022<figref idrefs="S97">1K</figref> is a cross-sectional side view of a strip including a Reference notch.

0023<figref idrefs="S97">1L</figref> shows a plan view of a substrate having dividing lines.

0024<figref idrefs="S98">2A</figref> shows a bottom view of another semiconductor die package according to a embodiment the invention.

0025<figref idrefs="S98">2 B</figref> shows a cross-sectional side view of the in <figref idrefs="S98">2A</figref> shown Semiconductor chip package.

0026<figref idrefs="S98">2C</figref> shows a bottom view of a lead frame structure according to a embodiment the invention.

0027<figref idrefs="S99">2D</figref> shows a bottom view of a semiconductor chip package according to another embodiment the invention.

0028<figref idrefs="S99">2E</figref> shows a cross sectional side view of another semiconductor die package according to an Alternatively, the invention.

0029<figref idrefs="S100">3A</figref>-<figref idrefs="S100">3C</figref> show a plan view of a semiconductor chip package while it is established.

0030<figref idrefs="S100">3D</figref> shows a bottom view of a semiconductor chip package.

0031<figref idrefs="S100">3E</figref> shows a cross-sectional side view of a Substrate according to a embodiment the invention.

0032<figref idrefs="S101">4A</figref>-<figref idrefs="S101">4C</figref> are plan views of a other semiconductor chip package according to an embodiment the invention.

0033<figref idrefs="S101">4D</figref> shows a bottom view of a substrate according to a embodiment the invention.

0034<figref idrefs="S101">4E</figref> shows a cross-sectional side view of a Substrate according to a embodiment the invention.

0035<figref idrefs="S102">5</figref> shows a perspective view of a leadframe structure array.

0036<figref idrefs="S103">6A</figref>-<figref idrefs="S106">6I</figref> show perspective views die packages while they are formed.

0037<figref idrefs="S107">7A</figref>-<figref idrefs="S107">7C</figref> show side cross-sections of another semiconductor die package as it is formed.

0038<figref idrefs="S107">7D</figref> shows a perspective view of a semiconductor chip package, formed by means of in <figref idrefs="S107">7A</figref>-<figref idrefs="S107">7C</figref> shown Process.

0039<figref idrefs="S108">8A</figref>-<figref idrefs="S108">8D</figref> show side cross-sections of another semiconductor die package as it is formed.

0040<figref idrefs="S108">8E</figref> shows a perspective view of the semiconductor chip package, formed by means of in <figref idrefs="S108">8A</figref>-<figref idrefs="S108">8D</figref> shown Process.

0041<figref idrefs="S109">9A</figref>-<figref idrefs="S109">9D</figref> show cross-sections of a other semiconductor chip package while it is formed.

0042<figref idrefs="S109">9E</figref> shows a perspective view of another Semiconductor chip package according to a embodiment the invention.

0043<figref idrefs="S110">10A</figref>-<figref idrefs="S110">10D</figref> show Cross-sections of another semiconductor chip package while it is formed.

0044<figref idrefs="S110">10E</figref> shows a perspective view of another Semiconductor chip package according to a embodiment the invention.

0045<figref idrefs="S111">11A</figref>-<figref idrefs="S111">11D</figref> show Cross-sections of another semiconductor chip package while it is formed.

0046<figref idrefs="S111">11E</figref> shows a perspective view from below of the semiconductor chip package.

0047<figref idrefs="S112">12A</figref>-<figref idrefs="S112">12D</figref> show Cross-sections of another semiconductor chip package while it is formed.

0048<figref idrefs="S112">12E</figref> shows a perspective view from below of this in <figref idrefs="S112">12D</figref> shown semiconductor chip package.

0049<figref idrefs="S113">13A</figref>-<figref idrefs="S113">13D</figref> show Cross-sections of another semiconductor chip package while it is formed.

0050<figref idrefs="S113">13E</figref> shows a perspective bottom view of the in <figref idrefs="S113">13D</figref> shown semiconductor chip package.

0051<figref idrefs="S114">14A</figref>-<figref idrefs="S114">14D</figref> show Cross-sections of other semiconductor chip package, while it is formed.

0052<figref idrefs="S114">14E</figref> shows a perspective view of the in <figref idrefs="S114">14D</figref> shown semiconductor chip package.

0053<figref idrefs="S115">15A</figref>-<figref idrefs="S115">15D</figref> show Cross-sections of other semiconductor chip package, while it is formed.

0054<figref idrefs="S115">15E</figref> shows a perspective bottom view of the in <figref idrefs="S115">15D</figref> shown semiconductor chip package.

0055<figref idrefs="S116">16A</figref>-<figref idrefs="S116">16D</figref> show Cross-sections of other semiconductor chip package, while it is formed.

0056<figref idrefs="S116">16E</figref> shows a perspective bottom view of the in <figref idrefs="S116">16D</figref> shown semiconductor chip package.

0057<figref idrefs="S117">17A</figref>-<figref idrefs="S117">17D</figref> show Cross-sections of other semiconductor chip package, while it is formed.

0058<figref idrefs="S117">17E</figref> shows a perspective bottom view of the in <figref idrefs="S117">17D</figref> shown semiconductor chip package.

0059<figref idrefs="S118">18A-1</figref> is a bottom perspective view of a Leadframe structure.

0060<figref idrefs="S118">18A-2</figref> is a top perspective view of a Leadframe structure was partially etched.

0061<figref idrefs="S118">18B-1</figref> is a bottom perspective view of a preformed substrate.

0062<figref idrefs="S118">18B-2</figref> is a top perspective view of a preformed substrate.

0063<figref idrefs="S118">18C</figref> is a top perspective view of a preformed substrate with a mounted thereon semiconductor chip.

0064<figref idrefs="S118">18D</figref> is a top perspective view of a Semiconductor chip package comprising a preformed substrate.

0065<figref idrefs="S119">19A</figref> is a top perspective view of preformed leadframe substrate including a mounted thereon Semiconductor chip.

0066<figref idrefs="S119">19B</figref> shows a perspective bottom view of the in <figref>18A</figref> shown preformed leadframe substrate.

0067<figref idrefs="S120">20A</figref> is a plan view of a premolded substrate according to a embodiment the invention.

0068<figref idrefs="S120">20B</figref> shows a perspective top view of a pre-formed substrate according to a embodiment the invention.

0069<figref idrefs="S120">20C</figref> shows a cross-sectional side view a pre-formed substrate according to a embodiment the invention.

0070<figref idrefs="S120">20D</figref> shows a perspective bottom view of a preformed substrate according to a embodiment the invention.

0071<figref idrefs="S121">20E</figref> shows a plan view of a preformed Substrate according to a embodiment the invention.

0072<figref idrefs="S121">20F</figref> shows a cross-sectional side view a pre-formed substrate according to a embodiment the invention.

0073<figref idrefs="S121">20G</figref> is a top perspective view of preformed substrate according to a embodiment the invention.

0074<figref idrefs="S121">20H</figref> is a perspective view from below of a pre-formed substrate according to a embodiment the invention.

0075<figref idrefs="S122">21A</figref> is a top perspective view of a Frame structure.

0076<figref idrefs="S122">21B</figref>-<figref idrefs="S122">21C</figref> are perspective views of preformed substrates according to embodiments the invention.

0077<figref idrefs="S122">21D</figref> and <figref idrefs="S122">21E</figref> show perspective plan views in frame mounted preformed substrates. Semiconductor chips are mounted on the preformed substrates.

0078<figref idrefs="S122">21F</figref> shows a perspective bottom view of a preformed, mounted in a frame substrate.

0079<figref idrefs="S122">21G</figref> shows a side view of a preformed, mounted on a frame substrate.

0080<figref idrefs="S123">22A</figref>-<figref idrefs="S123">22D</figref> show each side sections, rear perspective views, plan views and front perspective views of a molded chip package according to an embodiment the invention.

0081<figref idrefs="S124">23</figref> is a circuit diagram for a synchronous buck converter (Buck-converter), which in the <figref idrefs="S125">24C</figref> shown housing equivalent.

0082<figref idrefs="S125">24A</figref> shows a side view of a semiconductor chip package in accordance with one embodiment the invention.

0083<figref idrefs="S125">24B</figref> shows a plan view of a semiconductor chip package according to a embodiment the invention.

0084<figref idrefs="S125">24C</figref> shows a perspective view of a semiconductor chip package according to an embodiment the invention.

0085<figref idrefs="S126">24D</figref> shows a perspective bottom view of a Leadframe structure.

0086<figref idrefs="S126">24E</figref> is a side perspective view of a Semiconductor chip package according to a embodiment the invention.

0087<figref idrefs="S127">25</figref> shows a side view of another embodiment the invention. In this embodiment, is a form of material deposited and isolated in a lead frame a chip of conductive areas on the leadframe structure.

DETAILED DESCRIPTION

0088embodiments of the invention are directed to semiconductor chip packages and processes for preparing of semiconductor chip packages addressed.

0089On Semiconductor chip package according to a embodiment of the invention includes a substrate and a substrate on the mounted semiconductor chip. The semiconductor chip can be connected to the substrate by an adhesive or any other suitable bonding material be attached. In the semiconductor chip package may the lower surface and / or the upper surface of the semiconductor chip to electrically conductive regions of the substrate be coupled. An encapsulating material may encapsulate the semiconductor chip. As will be described in more detail below, the substrate may according to embodiments the invention, various configurations, in various embodiments have.

0090the Substrate may have any suitable configuration. In preferred embodiments However, the invention includes the substrate is a leadframe structure and a molding material. Usually is at least one surface the leadframe structure is substantially coplanar with an outer surface of the Molding material. In some embodiments, are both opposed major surfaces the leadframe structure is substantially coplanar with the opposite outer surfaces of the Molding material in the substrate. In other embodiments, only one main surface of the Leadframe structure is substantially coplanar with an outer surface of the Molding material.

0091Of the Term "leadframe structure" can refer to a Refer structure which is derived from a leadframe. Leadframe structures For example, be molded by known stamping processes. An exemplary Leadframe structure can also by etching a continuous conductive Sheet to form a predetermined pattern are formed. Therefore in embodiments the invention, the lead frame structure in a semiconductor die package, a continuous metallic structure or a discontinuous its metallic structure.

0092A Leadframe structure according to a embodiment the invention may initially one of many leadframe structures in an array of leadframe structures, which are interconnected by webs to be. During the Manufacturing process of a semiconductor chip package, the leadframe structure array be separated to separate individual leadframe structures from each other. As a Result of this separation, can Parts of a leadframe structure (such as a source lead and a gate conductor) in a final Semiconductor chip package be electrically and mechanically decoupled from each other. In other embodiments an array of leadframe structures is not used, when semiconductor chip package according to embodiments of the invention are prepared.

0093A Leadframe structure according to a embodiment of the invention may comprise any suitable material, any have suitable shape and may have any suitable thickness. exemplary Leadframe structure materials include metals such as copper, aluminum, gold, etc., and alloys thereof. The leadframe structures may also coated layers such as coated gold, chrome, silver, Palladium, nickel layers etc. contain.

0094A Leadframe structure according to an embodiment the invention may also have any suitable configuration. For example, the lead frame structure also any suitable having thickness, including a thickness of less than about 1 mm (Eg, less than about 0.5 mm). In addition, the leadframe structure have a chip mounting area that a chip-connection-box (The Attach Pad DAP) can form. Head to the side away from the die attach region extend. You can also have surfaces which are plane-parallel and / or non-parallel to the surface the die attach area formed. For example, the Head down, in some instances be bent with respect to the die attach region.

0095If the head of the leadframe structure not laterally beyond the Mold material extend beyond, the substrate can be regarded as a "conductor-free" substrate be and a housing including the substrate could regarded as a "conductor-free" housing will. When the head of the leadframe structures beyond the molding material extend, then the substrate may be a "conductor casing" a "conductor substrate" and the housing.

0096the Molding material which is used in the substrate may be any suitable materials include. Suitable materials include shape biphenylbasierte materials and multifunctional epoxy crosslinkedresin composite materials. Suitable mold materials are in liquid or semisolid form stacked on a lead frame structure and are subsequently cured to to solidify it.

0097Of the Semiconductor chip, which is mounted on the substrate, may be any suitable semiconductor device include. Suitable components can vertical or horizontal components include. Vertical components have at least one entrance on one side of the chip and a Output on the other side of the chip, so that current flows vertically through the die can. Horizontal devices include at least one input on one side of the chip and an output on the same side of the chip, so that current flows horizontally through the chip. exemplary Semiconductor devices are also described in US patent application Ser. 11 / 026,276, filed on December 29, 2004, described herein in their entirety for all purposes is incorporated by reference.

0098vertical Power transistors include VDMOS transistors and vertical bipolar transistors. A VDMOS transistor is a MOSFET, the two or more semiconductor regions has which are formed by diffusion. He has a source region, a drain region and a gate. The component vertically by the source region and the drain region on opposite surfaces of the semiconductor chip are. The gate of a buried gate structure or a planar gate structure and be on the same surface as the source region is formed. Buried gate structures are preferred, since dug gate structures are narrower and occupy less space as a planar gate structures. In operation, the current flow from the Source region to the drain region in a VDMOS device is substantially perpendicular to the chip surfaces.

0099On Encapsulating material can be used to the semiconductor chip encapsulate. The encapsulating material may the same or another Type of material as the molding material described previously include. In some embodiments, covered or at least partially covers the encapsulating material, the substrate and one or more semiconductor chips on the substrate. The encapsulating material can be used to the one or more semiconductor chips from possible damage to protect because of the suspension of the surrounding environment.

0100Any suitable process can be used to control the / the semiconductor chip (s) and / or the substrate that supports the / the semiconductor chip (s) encapsulate. For example, placing a semiconductor chip and a substrate in a Ausformform be and an encapsulating material can have at least a portion of the The semiconductor chip and / or the substrate are formed. Specific Molding conditions are known to the skilled in the art.

I. chip package comprising substrates separate isolation areas

0101While the characteristic quantities of Micro wire housing (Micro Lead Package MLP) components become smaller and smaller, the designs are by Metal-to-metal distances and the performance of dimensional tolerances etched and half-etched Frame technology limited. embodiments the invention disclose a preformed frame layout, which in is capable of double rows for denuded record fields. A double row MLP has a smaller case size compared a-row MLP for the same number of conductors. In embodiments of the invention is preformed a leadframe structure and then cut to two isolate conductive fields.

0102A embodiment the invention is directed to a method comprising providing a preformed substrate including a leadframe structure and a Molding material contains, wherein the leadframe structure includes a first conductive portion, a second conductive portion and a Intermediate portion between the first conductive portion and the second conductive portion includes. The molding material in the substrate can have a thickness which is substantially equal to a Thickness of the leadframe structure. For example, the thickness of the molded material is substantially equal to the thickness of the first conductive be part region and / or the second conductive portion.

0103Of the Intermediate portion is then separated to the first conductive Portion of the second conductive portion to electrically isolate. The first and second conductive portions may have different connections in a chip housing represent. For example, the first and second conductive portions from the group consisting a gate conductor, a source lead and a drain conductor, be selected, wherein the first and second conductive portions of different are. A plurality of first and second conductive portions can form rows of conductive portions.

0104After disconnecting the lead frame structure, at least a semiconductor chip attached to the substrate. A suitable adhesive or solder can are used to fix the semiconductor chip to the substrate. The semiconductor chip may be of the type described above. For example , the leadframe structure, a semiconductor chip comprising a his power MOSFET.

0105After this the semiconductor chip is attached to the substrate, the semiconductor chip may electrically to the first and second conductive portions are coupled. For example, the semiconductor chip and the first and second conductive portions to be interconnected by wires. Alternatively, conductive Terminals are used to the semiconductor chip to the first and second conductive portions to couple.

0106After this the semiconductor chip electrically to the first and second conductive Partial regions is coupled in the preformed substrate, a Encapsulating material over be coated the semiconductor chip in order to encapsulate it. the Encapsulating material may by the same or a different his type of material as the molding material described above.

0107the molded semiconductor chip package may have conductors who do not have an outer surface of the molding material addition, extend. In some embodiments, , the semiconductor chip package called "micro-conductor housing" or MLP housing will.

0108exemplary Process and chip package can with reference to the <figref idrefs="S95">1A</figref>-<figref idrefs="S97">1L</figref> described will.

0109<figref idrefs="S95">1A</figref> shows a leadframe structure <figref>14</figref> according to one embodiment the invention. The leadframe structure<figref>14</figref> in this example has no chip terminal field (Die attach pad DAP) on. As will be described further below, is the substrate having the ladder-type structure <figref>14</figref> includes, a die attach area have, which is formed of the molding material. The leadframe structure<figref>14</figref> Has a first surface <figref>14 (e)</figref> the a second surface <figref>14 (f)</figref> the Leadframe structure <figref>14</figref> opposes.

0110The Leadframe structure <figref>14</figref> includes a first conductive subregion <figref>14 (a)</figref>, A second conductive portion <figref>14 (b)</figref>. and an intermediate portion <figref>14 (c)</figref> between the first conductive portion <figref>14 (a)</figref> and the second conductive portion <figref>14 (b)</figref>, As shown, the thicknesses of the first and second conductive portions <figref>14 (a)</figref>. <figref>14 (b)</figref> in the Essentially the same, but the thickness of the intermediate portion <figref>14 (c)</figref> is less than the thicknesses of the first and second conductive portions <figref>14 (a)</figref>. <figref>14 (b)</figref>, As a result of these different thicknesses, is a recess <figref>16</figref> defined through the first conductive portion <figref>14 (a)</figref>, the second conductive portion <figref>14 (b)</figref> and the intermediate portion <figref>14 (c)</figref>,

0111The Leadframe structure <figref>14</figref> can by any suitable Process are formed. For example, the leadframe structure<figref>14</figref> by means of Photoresist and etching or embossing process be formed. These methods and other methods are known to those of ordinary skill known. For example, in<figref idrefs="S95">1A</figref> shown recess <figref>16</figref> using known photolithography and etching be formed. In an exemplary photolithography and etching process, may be a raw metal structure (not shown) coated with a layer of photoresist will. This photoresist layer can be exposed and developed. Exposed areas of the metal structure can be prepared by a wet or dry etching process etched will. recess<figref>16</figref> can by means of a wet or dry etching process be formed.

0112As in <figref idrefs="S95">1A</figref> shown, after the leadframe structure <figref>14</figref> shaped is a piece tape <figref>12</figref> at the first surface <figref>14 (e)</figref> the leadframe structure <figref>14</figref> secured will. The piece tape <figref>12</figref> covers the first surface <figref>14 (e)</figref> the leadframe structure <figref>14</figref>. so that the molding material that is used to the substrate to be shapes, not the first surface <figref>14 (e)</figref> covered.

0113As in <figref idrefs="S95">1B</figref> shown, after the tape <figref>12</figref> at the first surface <figref>14 (e)</figref> the Leadframe structure <figref>14</figref> is attached, a molding material <figref>18</figref>. as an epoxy molding material on the leadframe structure <figref>14</figref> coated and solidified. The mold material<figref>18</figref> fills the recess <figref>16</figref> the men Leiterrah structure <figref>14</figref> and the joints between the various first and second conductive subregions <figref>14 (a)</figref>. <figref>14 (b)</figref>, Excess molding material can be removed , so that the second surface <figref>14 (f)</figref> not with is the form of material covered. The area between the first and second surfaces <figref>14 (e)</figref>. <figref>14 (f)</figref> the Leadframe structure <figref>14</figref> However, in this example with the molding material <figref>18</figref> filled.

0114As in <figref idrefs="S95">1B</figref> shown, an outer surface <figref>18 (a)</figref> of the molding material <figref>18</figref> in the essentially coplanar with the outer surfaces <figref>14 (a) -1</figref>. <figref>14 (b) -1</figref> the first and second conductive portions <figref>14 (a)</figref>. <figref>14 (b)</figref> be. As shown, the thickness of the molding material <figref>18</figref> at specific Provide substantially equal to the thickness of the first and second conductive portions <figref>14 (a)</figref>. <figref>14 (b)</figref>,

0115As in <figref idrefs="S95">1C</figref> shown, separates a first partition member <figref>20</figref> the Intermediate portion <figref>14 (c)</figref> the Leadframe structure <figref>14</figref> after the molding, to thereby obtain a or more recesses <figref>24</figref> in the substrate <figref>22</figref> to to form. The one or more recesses<figref>24</figref> can altogether through the intermediate portion <figref>14 (c)</figref> extend and may be partially in the form of material <figref>18</figref> extend. recesses <figref>24</figref> can than half of the Thickness (or less) of the thickness of the substrate <figref>22</figref> shaped be. By separating the intermediate portions<figref>14 (c)</figref> can they first and second conductive portions <figref>14 (a)</figref>. <figref>14 (b)</figref> electric and are mechanically isolated from each other. In more detail below declared is, can the isolated first and second conductive portions <figref>14 (a)</figref>. <figref>14 (b)</figref> after that as separate electrical connections (Eg electrical connection boxes) are used in the resulting semiconductor die package.

0116any suitable first separator <figref>20</figref> can be used, to the intermediate portion <figref>14 (c)</figref> to separate. For example , the first separating element <figref>20</figref> a water jet, a saw, corrosive be material or a laser.

0117As in <figref idrefs="S95">1D</figref> shown, after separating a preformed substratum <figref>22</figref> shaped. substrate<figref>22</figref> has recesses <figref>24</figref>. where the separation performed has been. recesses<figref>24</figref> decoupling the first and second conductive portions <figref>14 (a)</figref>. <figref>14 (b)</figref>, so that you are mechanically and electrically isolated from each other.

0118the shaped preformed substrate <figref>22</figref> may conductors on the lateral edges of the molding material <figref>18</figref> also extend, have or not. In the specific substrate<figref>22</figref> correspond the head of the leadframe structure <figref>14</figref> with the first and second conductive portions <figref>14 (a)</figref>. <figref>14 (b)</figref>, In other embodiments, the substrate may <figref>22</figref> have conductors which laterally beyond the lateral edges of the leadframe structure <figref>14</figref> extend beyond and which may be bent downward to connections to form, or not.

0119As in <figref idrefs="S95">1E</figref> shown, can one or more semiconductor chips <figref>25</figref> then on the substrate <figref>22</figref> to be assembled. substrate <figref>22</figref> , a first surface <figref>22 (a)</figref> and a the first surface <figref>22 (a)</figref> opposed second surface <figref>22 (b)</figref> include. In this example, at least two semiconductor chips <figref>25</figref> directly on the molding material <figref>18</figref> assembled. A plurality of semiconductor chips<figref>25</figref> can on the substrate <figref>22</figref> be mounted, when a plurality of Semiconductor chip packages to forms are. As will be explained further below, can be related housing are formed and this can after all are separated in a singulation process.

0120any suitable material may be used to the one or more Semiconductor chips <figref>25</figref> on the substrate <figref>22</figref> to assemble. For example, solder or a conductive or non-conductive Adhesive can be used to the one or more semiconductor chips <figref>25</figref> on the substrate <figref>22</figref> to assemble. Suitable adhesives include filled or unfilled Epoxy adhesives.

0121Of the one or more semiconductor chips <figref>25</figref> can at any appropriate Location on the substrate <figref>22</figref> be mounted. As in<figref idrefs="S95">1E</figref> shown, the one or more semiconductor chips <figref>25</figref> on a insulating material as the molding material <figref>18</figref> assembled. In other embodiments, , the leadframe structure <figref>14</figref> on include or more conductive die attach fields (not shown) and the one or more semiconductor chips <figref>25</figref> can to the one or more die attach areas be mounted.

0122The Semiconductor chips <figref>25</figref> can be any of the semiconductor chip described above. For example, each chip <figref>25</figref> a first surface <figref>25 (a)</figref> and a second surface <figref>25 (b)</figref> have, wherein the second surface <figref>25 (b)</figref> closer to the substratum <figref>22</figref> than the first surface <figref>25 (a)</figref>, In some embodiments may the first surface <figref>25 (a)</figref> a , A gate terminal and a drain terminal have source terminal, while the second surface <figref>25 (b)</figref> no connections has. In other embodiments, , the first surface <figref>25 (a)</figref> a Source and / or gate terminal have, while the second surface <figref>25 (b)</figref> a Has drain terminal (or vice versa). In this case, the one or more semiconductor chips <figref>25</figref> on conducting chip connection fields (Not shown) in place on the molding material <figref>18</figref> assembled be.

0123After mounting the one or more semiconductor chips <figref>25</figref> can wires <figref>30</figref> at the electrical terminals at the first surface <figref>25 (a)</figref> the Semiconductor chips <figref>25</figref> and directing the first and secondthe subregions <figref>14 (a)</figref>. <figref>14 (b)</figref> fixed (and thus electrically coupled to). The wires<figref>30</figref> alternatively are referred to as "wire connection". The wires can formed of a noble metal such as gold, silver, platinum, etc. be, or may a transition material, such as copper, aluminum, etc. contain. In some embodiments, can the wires the form of coated wires (For example, a plated with a noble metal such as gold or platinum have copper wire). Alternatively or additionally, conductive terminals can be used are to the electrical connections on the first surface <figref>25 (a)</figref> of Semiconductor chips <figref>25</figref> to the first and second conductive subregions <figref>14 (a)</figref>. <figref>14 (b)</figref> to couple.

0124With in reference to <figref idrefs="S95">1F</figref> then an encapsulating material <figref>32</figref> on the first surface <figref>22 (a)</figref> of substrate <figref>22</figref> and the first on the surface <figref>22 (a)</figref> of substrate <figref>22</figref> mounted semiconductor chips <figref>25</figref> coated will. The encapsulating material<figref>32</figref> fills the previously formed recesses <figref>24</figref> in the substrate <figref>22</figref>, filling the recesses <figref>24</figref> in the substrate <figref>22</figref> by the Einkapsel- material <figref>32</figref> "Locked" preferably the Encapsulating material <figref>32</figref> with the substrate <figref>22</figref>, the Encapsulating material <figref>32</figref> can also be shaped so that it is not over the lateral edges of the substrate <figref>22</figref> extends past.

0125reference Referring to <figref idrefs="S96">1G</figref> may, after coating the encapsulating material <figref>32</figref>. a second separating element <figref>42</figref> (Which is the same or a other than the first separation element described above <figref>20</figref> be can) be used to the shaped housing <figref>40 (a)</figref>. <figref>40 (b)</figref> from one another to separate. The second separating element<figref>42</figref> , the encapsulating material <figref>32</figref> and the substrate <figref>22</figref> sever. This process can be referred to as "singulation".

0126<figref idrefs="S96">1H</figref> shows a cross sectional side view of a semiconductor chip package <figref>40 (a)</figref> according to one embodiment the invention after singling. As in<figref idrefs="S96">1H</figref> shown, the sides of the encapsulating material <figref>32</figref> coextensive with the sides of the substrate <figref>22</figref>, The encapsulating material<figref>32</figref> covers both the semiconductor chip <figref>25</figref> and the wires <figref>30</figref>, The first and second conductive portions <figref>14 (a)</figref>. <figref>14 (b)</figref> are electrically insulated from one another and form electrical connections the underside of the housing <figref>40 (a)</figref>,

0127As in <figref idrefs="S96">1I</figref> shown, can the first and second conductive portions <figref>14 (a)</figref>. <figref>14 (b)</figref> electrical connections the underside of the housing <figref>40 (a)</figref> to form. The connections corresponding to the first and second conductive portions <figref>14 (a)</figref>. <figref>14 (b)</figref> can conductive Contact pads on a printed circuit board (not shown) correspond.

0128the in <figref idrefs="S96">1I</figref> Semiconductor chip package shown <figref>40 (a)</figref> can easily on the circuit board (not shown) can be mounted to a to form electrical assembly. Lot can on the bare surfaces of first and second conductive portions <figref>14 (a)</figref>. <figref>14 (b)</figref> and or to the corresponding conductive pads on the circuit board be coated. The semiconductor chip package<figref>40 (a)</figref> can then be mounted on the circuit board as a flip chip.

0129<figref idrefs="S97">1y</figref> shows a bar structure <figref>50</figref>That a plurality of substrates <figref>22</figref> during the Case Shape Process can absorb. The strips structure<figref>50</figref> includes several Reference separating notches <figref>50 (a)</figref>, notches<figref>50 (a)</figref> can use are to the Run to support the above-mentioned first partition member, so that the optimum cutting depth can be determined before the intermediate portion separated between the first and second conductive portions is. notches<figref>50 (a)</figref> can be described as "saw streets references" in some cases.

0130<figref idrefs="S97">1K</figref> shows a side view of a reference notch <figref>50 (a)</figref> in a strips structure <figref>50</figref>, As shown extending notch<figref>50 (a)</figref> by part of the thickness of the frame structure <figref>50</figref>,

0131<figref idrefs="S97">1L</figref> shows horizontal and vertical separators. These lines<figref>62</figref> define Separating paths the first separating element, while it the intermediate portion, of the first and second conductive portions of the leadframe structure in the substrate <figref>22</figref> isolated, separates.

0132If the separation is performed by the dividing lines, a saw blade For example, only a portion of the strip structures <figref>50</figref> separate, so that they can remain intact and the various substrates <figref>22</figref> be published can. As an alternative to using a saw and reference notches <figref>50 (a)</figref> can to use a laser to the previously described intermediate portions to separate, extending between the first and second conductive portions . are A laser beam can be used to specifically the to distinguish between sub-areas, without using reference notches.

0133The Embodiments described above, have a number of advantages. As mentioned above,by providing a recess between first and second conductive portions a leadframe structure and then filling the recess with a Encapsulating material encapsulating material to the preformed Substrate are "locked". This helps to ensure that the molded chip package is stable and robust. can also Chip package with a plurality of electrical terminals fast and efficient means of the embodiments the invention are formed. In addition, embodiments of the invention can at least two rows of MLP packages with minimized housing dimensions shapes and without merely lying Chip terminal fields (DAPs).

0134In the on related <figref idrefs="S95">1A</figref>-<figref idrefs="S97">1L</figref> described embodiments is the semiconductor chip within an interior of the Portions of the conductors defined area. In other embodiments, of the invention, it is possible a semiconductor chip package provide that has a configuration in which the semiconductor chip Portions of the conductor overlaps. This type of semiconductor chip package may also be a two-row MLP package. The improved two-row MLP housing allows a higher pin count in the same package size, without thermal performance to sacrifice. The improved two-row MLP housing is also smaller than comparable housing with the same number of pins or pins, without thermal performance to sacrifice. These additional embodiments are with reference to the <figref idrefs="S98">2A</figref>-<figref idrefs="S99">2E</figref> described.

0135<figref idrefs="S98">2A</figref> shows a bottom view of a semiconductor chip package <figref>700</figref> according to a embodiment the invention. The semiconductor chip package<figref>700</figref> includes a leadframe structure <figref>720</figref> including a plurality of inner first conductive portions <figref>702 (a)</figref> and a Plurality of outer second conductive portions <figref>702 (b)</figref>, As shown, surrounded the second conductive portions <figref>702 (b)</figref> the first conductive subregions <figref>702 (a)</figref>, As in the preceding embodiments, formed a molding material <figref>704</figref> a substrate <figref>721</figref> With a leadframe structure <figref>720</figref>, Outer surfaces of the molding material<figref>704</figref> are substantially coplanar with the outer surfaces of the first and second conductive portions <figref>702 (a)</figref>. <figref>702 (b)</figref> the Leadframe structure <figref>720</figref>,

0136A cross-sectional side view of the semiconductor chip package <figref>700</figref> is in <figref idrefs="S98">2 B</figref> shown. <figref idrefs="S98">2 B</figref> is a cross-section along the line 2B-2B in <figref idrefs="S98">2A</figref>, the Semiconductor chip package <figref>700</figref> includes a semiconductor chip <figref>710</figref>, On a substrate <figref>721</figref> by means of a die attach material <figref>712</figref> as solder or not conductive adhesive is mounted. In this example, the bottom of the semiconductor chip <figref>710</figref> not electrically to the first conductive inner portion <figref>70 (a)</figref> coupled. As in the aforementioned embodiments includes the substrate <figref>721</figref> the molding material <figref>704</figref> and the leadframe structure <figref>720</figref> and there are recesses <figref>703</figref>. in the substrate <figref>721</figref> are formed. recesses<figref>703</figref> are between respective first and second conductive portions <figref>702 (a)</figref>. <figref>702 (b)</figref> and are by separating the intermediate portions the leadframe structure <figref>720</figref>, Extending between the first and second conductive portions <figref>702 (a)</figref>. <figref>702 (b)</figref> are, shaped. Separation processes are earlier in<figref idrefs="S95">1C</figref> and <figref idrefs="S95">1D</figref> described and all the separation processes described above can be used herein.

0137Then can steps including die attach, wire bonding, encapsulation and isolation accomplished will. Such steps are described above with respect to<figref idrefs="S95">1E</figref>-<figref idrefs="S96">1H</figref> described. These descriptions are incorporated herein.

0138otherwise as in the above case, this in <figref idrefs="S96">1G</figref> is shown, the semiconductor chip <figref>710</figref> in this embodiment on the substrate <figref>721</figref> mounted so that it is about the inner first conductive portions <figref>702 (a)</figref> and a etched region <figref>720 (a)</figref> the leadframe structure <figref>720</figref> is and these overlaps. wires<figref>711</figref> couple the semiconductor chip <figref>710</figref> electrically to the upper surfaces of first and second conductive portions <figref>702 (a)</figref>. <figref>702 (b)</figref>,

0139<figref idrefs="S98">2C</figref> is a bottom view of the lead frame structure <figref>720</figref>, the in the substrate <figref>721</figref> is used. As shown, the first and second conductive portions <figref>702 (a)</figref>. <figref>702 (b)</figref> formed by etching. Intermediate portions <figref>702 (c)</figref> located between the first and second conductive portions <figref>702 (a)</figref>. <figref>702 (b)</figref>, Together can a first and second conductive portion <figref>702 (a)</figref>. <figref>702 (b)</figref> and an intermediate portion <figref>702 (c)</figref> between the first and second subregions <figref>702 (a)</figref>. <figref>702 (b)</figref> a recess to form. As noted above, the intermediate portion is<figref>702 (c)</figref> finally separated and is filled with an encapsulating material. The leadframe structure<figref>720</figref> includes also etched areas <figref>720 (a)</figref>Where material from the leadframe structure <figref>720</figref> away is.

0140<figref idrefs="S99">2D</figref> shows a bottom view of a semiconductor chip package <figref>730</figref> according to a Alternatively, the invention. As in the previous embodiments includes the Semiconductor chip Gehousing <figref>730</figref> a Leadframe structure <figref>740</figref> and a molding material <figref>746</figref>, Together, these components a substrate <figref>741</figref> to form. The leadframe structure<figref>740</figref> includes a central portion <figref>736</figref>, Both a die attach area including a chip connecting field (DAP) and inner first conductive portions <figref>732 (a)</figref> and outer second conductive portions <figref>732 (b)</figref> contain can. The second conductive portions<figref>732 (b)</figref> can they inner first conductive portions <figref>732 (a)</figref> surrounded, and the first and second conductive portions <figref>732 (a)</figref>. <figref>732 (b)</figref> may like described above may be electrically isolated from each other.

0141As in <figref idrefs="S99">2E</figref> shown, a semiconductor chip <figref>752</figref> at the die attach area the central portion <figref>736</figref> by means of a die attach material or similar assembled. The semiconductor chip<figref>752</figref> overlaps both many of the first conductive portions <figref>732 (a)</figref> and the central portion <figref>736</figref>, Each of the second conductive portion areas in the plurality of second conductive portions <figref>732 (b)</figref> electrically by a respective first conductive portion in the plurality of first conductive portions <figref>732 (b)</figref> isolated. <figref idrefs="S99">2E</figref> is a cross-section along the line 2E-2E in <figref idrefs="S99">2D</figref>, The Wires previously described are made <figref idrefs="S99">2E</figref> omitted for clarity.

0142The regarding <figref idrefs="S98">2A</figref>-<figref idrefs="S99">2E</figref> described embodiments have a number of advantages. Embodiments of the invention enable higher Pin number, without sacrificing thermal performance. embodiments the invention can alternatively be smaller than comparable housing with the same number of pins, without sacrificing thermal performance. For example can a small housing by means of such embodiments be formed, even though the chip used in the housing is relatively large. Other Designs are unable to include a large semiconductor chip in a housing without the size of the housing to enlarge. the is that in other designs of the semiconductor chip on a DAP (chip-connection-box) placed of comparable size is. In the embodiments described above, the semiconductor chip but have lateral dimensions that are greater than a DAP or even no DAP have while the semiconductor chip at least some of the conductive portions (conductor) the leadframe structure overlaps. Thermal performance is not sacrificed and may be improved because heat is not discharged only by a DAP is, but also by the conductor (conductive portions) of the Leadframe structure.

0143table 1 illustrates the to of the specific, with reference <figref idrefs="S98">2A</figref>-<figref idrefs="S99">2E</figref> described embodiments provided advantages in comparison to the above specific in the <figref idrefs="S95">1A</figref>-<figref idrefs="S97">1L</figref> (embodiment 1) described embodiments Can. As shown in Table 1 the embodiments with respect to the <figref idrefs="S98">2A</figref>-<figref idrefs="S99">2E</figref> specific described are (embodiment 2) be smaller, higher have pin numbers and have better thermal properties as the embodiments specifically in the <figref idrefs="S95">1A</figref>-<figref idrefs="S97">1L</figref> described are. <tables><table frame="all"><tgroup cols="3" colsep="1" rowsep="1"><colspec colnum="1" colname="1" colwidth="1*" /><colspec colnum="2" colname="2" colwidth="1*" /><colspec colnum="3" colname="3" colwidth="1*" /><tbody><row><entry namest="1" nameend="3">table 1</entry></row><row><entry colname="1">property</entry><entry colname="2">embodiment 1</entry><entry colname="3">embodiment 2</entry></row><row><entry colname="1">Size (pitch)</entry><entry colname="2">7 mm.times.6 mm (0.65 mm pitch)</entry><entry colname="3">6 mm × 5 mm (0.4 mm-0.5 mm pitch)</entry></row><row><entry colname="1">pin number</entry><entry colname="2">56 Pin code</entry><entry colname="3">80 Pin code</entry></row><row><entry colname="1">Division limit</entry><entry colname="2">min 0.5 mm</entry><entry colname="3">min 0.4 mm</entry></row><row><entry colname="1">Thermal Resistance single plate (Degrees C / W)</entry><entry colname="2">DAP not soldered with 56 pins - 82.6</entry><entry colname="3">DAP not soldered with 80 pins - 78.7 DAP not soldered with 64 pins - 72.1</entry></row><row><entry colname="1">Thermal Resistance multidisk (Degrees C / W)</entry><entry colname="2">DAP not soldered with 56 pins - 45.1</entry><entry colname="3">DAP not soldered with 80 pins - 35.3 DAP not soldered with 64 pins - 32.8</entry></row></tbody></tgroup></table></tables>

II. Chip package comprising a plurality of semiconductor chips

0144While the characteristic quantities of Micro conductor housing (Micro Lead Package MLP) components become smaller and smaller, are the designs by metal-to-metal distances and performance dimensional tolerances etched and half-etched Frame technology limited. This prompted the introduction of the Bump chip carrier (bump chip carrier BCC) technology, currently has no layout restrictions, but usually wet etching would use. The use of wet etching not preferred.

0145embodiments the invention utilize preformed substrates that include leadframe structures. The substrates may record multiple semiconductor chips. Usually a requires Multichip housing the use of a specific substrate layout. A certain Substrate layout is usually for the certain multichip housing specific. embodiments of the invention are able to overcome this limitation by the Enable of reusing the same design of a preformed substrate, to accommodate a plurality of semiconductor chip layouts. A recited field layout can also make are used, the thermal efficiency of the semiconductor chip package in embodiments to improve the invention. Other layout concepts include the ability the semiconductor chip housing, access to provide to a drain contact of a semiconductor chip (for example, if the semiconductor chip is a vertical power MOSFET includes).

0146In one embodiment of the invention is a pre-formed substrate comprising a first surface and a second surface provided. The preformed substrate includes a leadframe structure and a molding material. The leadframe structure includes a field area. An outer upper surface of the field area and an outer surface of the Mold material are We sentlichen coplanar and coincide with the second surface the preformed substrate together. At least two semiconductor chips are attached to the substrate. Preferably, the at least two semiconductor chips attached to the molding material of the substrate and conductors at the lateral edges of the substrate by means of connecting wires and / or conductive terminals connected.

0147<figref idrefs="S100">3A</figref>-<figref idrefs="S100">3E</figref> show steps in training a semiconductor chip package comprising a preformed substrate and a plurality of semiconductor chips.

0148<figref idrefs="S100">3A</figref> shows a plan view of a preformed substratum <figref>100</figref> according to a embodiment the invention. The preformed substrate<figref>100</figref> includes a mold material <figref>102</figref> and a leadframe structure <figref>104</figref>, At least one outer surface of the molding material <figref>102</figref> and an outer surface of the leadframe structure <figref>104</figref> are substantially coplanar. The leadframe structure<figref>104</figref> includes a number of conductors <figref>104 (a)</figref>Which at the outer side edge areas the substrate <figref>100</figref> are and end there. The ladder<figref>104 (a)</figref> in this sample are located at each of the four side edges regions the substrate <figref>100</figref> and exposed through a molding material <figref>102</figref> and not extend to this addition. Outer surfaces of the ladder <figref>104a</figref> can substantially plane-parallel with the outer surface of the molding material <figref>102</figref> be.

0149As in <figref idrefs="S100">3A</figref> shown by the dotted lines, includes the leadframe structure a lowered central area which inside the conductor <figref>104 (a)</figref> is. The guide set central area may be formed by a partial etching process. The top surface the royalty set central region is connected to the molding material <figref>102</figref> covered.

0150The top surface of the molding material <figref>102</figref> , a die attach area <figref>100 (a)</figref> forming, on are two or more semiconductor chips (not shown) mounted can. Since the upper surface of the molding material <figref>102</figref> as die attach area <figref>106</figref> used is and not conducting chip connection fields as Anbringungs surfaces of the illustrated embodiment are used, the preformed substrate <figref>100</figref> a based plurality of semiconductor chips without requiring that these chips arranged in a particular layout are. Several multi-chip configurations may be used without to change the external conductor layout.

0151reference Referring to <figref idrefs="S100">3B</figref> are after the substrate is formed, the semiconductor chip <figref>110</figref>. <figref>112</figref>. <figref>114</figref> on the die attach area <figref>106</figref> on the substrate <figref>100</figref> assembled. A non-conductive (or conductive) adhesive can be used, to the semiconductor chips <figref>110</figref>. <figref>112</figref>. <figref>114</figref> at the die attach area <figref>106</figref> to fix. The semiconductor chips can be any of the above-described semiconductor chips. Preferably can the chips <figref>110</figref>. <figref>112</figref>. <figref>114</figref> in the form of material <figref>102</figref> of be placed substrate in any suitable arrangement.

0152reference Referring to <figref idrefs="S100">3C</figref>, Can, after the semiconductor chips <figref>110</figref>. <figref>112</figref>. <figref>114</figref> on the substrate <figref>100</figref> are mounted, the upper surfaces of Semiconductor chips <figref>110</figref>. <figref>112</figref>. <figref>114</figref> electric to the conductors <figref>104 (a)</figref> be coupled to a semiconductor chip package <figref>121</figref> to to form. If desired, an optional encapsulating material on both the semiconductor chips <figref>110</figref>. <figref>112</figref>. <figref>114</figref> as the conductive structures (such as wires, terminals, etc.) which uses be to the Head <figref>104 (a)</figref> to the upper surfaces of Semiconductor chips <figref>110</figref>. <figref>112</figref>. <figref>114</figref> couple, coated and cured will.

0153<figref idrefs="S100">3C</figref> specifically shows a number of wire connections <figref>118</figref>. the electrical connections (not shown) on the upper surfaces the semiconductor chips <figref>110</figref>. <figref>112</figref>. <figref>114</figref> to the lateral guides <figref>104 (a)</figref> the leadframe structure <figref>104</figref> electric couple. The wire connections<figref>118</figref> can wirebond process are formed, which are known in the art. alternative can conductive terminals and solder are used to the electrical connections the upper surface the semiconductor chips <figref>110</figref>. <figref>112</figref>. <figref>114</figref> to the conductors <figref>104 (a)</figref> to couple.

0154<figref idrefs="S100">3D</figref> shows a bottom view of the substrate <figref>100</figref>, The bottom of the substrate <figref>100</figref> and the lead frame structure <figref>104</figref> includes a field area <figref>104 (b)</figref>Which is opposite the die attach area <figref>106</figref> is. The field area <figref>104 (b)</figref> is large and takes a significant Portion of the second surface <figref>100 (b)</figref> of substrate <figref>100</figref> and is lowered with respect to the ladder <figref>104 (a)</figref> at the edges of the substrate <figref>100</figref>, In this example, the bare lying Field area <figref>104 (b)</figref> at least about 50% of the lateral surface of the substrate <figref>100</figref> take advantage of. The large field area<figref>104 (b)</figref> Feathers the shaped housing with good heat transfer properties, since the large Field area <figref>104 (b)</figref> the Ladder frame structure as a heat sink acts.

0155<figref idrefs="S100">3E</figref> shows a cross-sectional side view of the substrate <figref>100</figref> along line 3E-3E in <figref idrefs="S100">3A</figref>, The field area<figref>104 (b)</figref> has an outer surface <figref>104 (b) -1</figref>. which an extensive portion of the bottom surface of the substrate <figref>100</figref> occupies. The outer surface<figref>104 (b) -1</figref> the field area <figref>104 (b)</figref> is exposed from and substantially coplanar with an outer surface <figref>102 (a)</figref> of Molding material in the substrate <figref>100</figref>, In this example, isolated the molding material <figref>102</figref> the semiconductor chips <figref>110</figref>. <figref>112</figref>. <figref>114</figref> electrically from the field area <figref>104 (b)</figref>, The exposed field region<figref>104 (b)</figref> can on a circuit board (not shown) may be soldered, if desired, a thermal path from the semiconductor chip <figref>110</figref>. <figref>112</figref>. <figref>114</figref> to the circuit board provide.

0156As in <figref idrefs="S100">3E</figref> shown, the conductor <figref>104 (a)</figref> thicknesses, substantially equal to the maximum thickness of the molding material <figref>102</figref> are. additionally is in the substrate <figref>100</figref> an inner surface of the Field area <figref>104 (b)</figref> the leadframe structure <figref>104</figref> by the molding material covered. The mold material<figref>102</figref> has a Thickness "T" and in this example corresponds to the combined thickness T and the thickness of the field area <figref>104 (b)</figref> the Thickness of the substrate <figref>100</figref>,

0157The regarding <figref idrefs="S100">3A</figref>-<figref idrefs="S100">3E</figref> described embodiments have a number of advantages. First, the large exposed improves Field area <figref>104 (b)</figref> the thermal performance the molded semiconductor chip package through Providing a large Heat-conduction path of the semiconductor chips <figref>110</figref>. <figref>112</figref>. <figref>114</figref>, additionally has the great Chip mounting area <figref>106</figref> of substrate <figref>100</figref> no conductive pads so that different Multi-chip layout in a housing can be provided, although only a substrate design is used.

0158<figref idrefs="S101">4A</figref>-<figref>4F</figref> make a A method of forming another embodiment of the invention.

0159<figref idrefs="S101">4A</figref> shows another molded substrate <figref>100</figref> according to a embodiment the invention. substrate<figref>100</figref> includes a leadframe structure <figref>104</figref> including a field area <figref>104 (b)</figref> and Head <figref>104 (a)</figref> and a mold material <figref>102</figref>, A die attach area<figref>106</figref> at an upper surface <figref>100 (a)</figref> the preformed substrate <figref>100</figref> a surface of the field area <figref>104 (b)</figref> contain and (not shown) supporting a plurality of semiconductor chips. The dotted lines in <figref idrefs="S101">4B</figref> show the contour of the leadframe structure <figref>104</figref>. and the leadframe structure <figref>104</figref> can by a partial etching process be formed.

0160otherwise as the above with respect to <figref idrefs="S100">3A</figref> described substratum <figref>100</figref>, Has the field area <figref>104 (b)</figref> in this Example opposite Surfaces, with the opposite surfaces the substrate <figref>100</figref> coincide. In this embodiment, includes the die attach area <figref>106</figref> both an outer surface of the Field area <figref>104 (b)</figref> and an outer surface of the molding material <figref>102</figref>,

0161In This example extends the field area <figref>104 (b)</figref> by the entire thickness of the substrate <figref>100</figref> and may include a conductive and / or thermal path for a semiconductor chip (not shown) on the field area <figref>104 (b)</figref> by the substrate <figref>100</figref> and to an underlying circuit board (Not shown) represent. In some embodiments, the field area<figref>104 (b)</figref> electric to an input or output terminal of an electrical component in a semiconductor chip (in <figref idrefs="S101">4A</figref> not shown) may be coupled. For example, the field area<figref>104 (b)</figref> electric coupled to the drain region of a MOSFET in a semiconductor chip be.

0162As in <figref idrefs="S101">4B</figref> shown, a number of semiconductor chips <figref>110</figref>. <figref>112</figref>. <figref>114</figref> on fastening the chip-gungs area <figref>106</figref> be placed. one of the semiconductor chips, semiconductor chip <figref>112</figref>, May at the field area <figref>104 (b)</figref> secured his while the other semiconductor chips <figref>110</figref>. <figref>114</figref> to the molding material may be attached. The semiconductor chip <figref>112</figref> , a vertical component as be a vertical MOSFET. As described above, such have vertical Components an input to a surface of the chip and an output at another opposite surface of the chip. The other semiconductor chip<figref>110</figref>. <figref>114</figref> can horizontal components include. As described above, has a horizontal component an input and an output on the same surface of the Crisps.

0163reference Referring to <figref idrefs="S101">4C</figref> , after the semiconductor chip <figref>110</figref>. <figref>112</figref>. <figref>114</figref> on are mounted to the substrate, a number of wire connections <figref>118</figref> shaped, to the Head <figref>104 (a)</figref> with the upper surfaces of Semiconductor chips <figref>110</figref>. <figref>114</figref>. <figref>112</figref> connect to. A semiconductor chip package <figref>121</figref> is then formed.

0164<figref idrefs="S101">4D</figref> shows a bottom view of the substrate <figref>100</figref>, As in <figref idrefs="S101">4D</figref> shown is exposed surface of Field area <figref>104</figref> greater at the lower surface <figref>100 (b)</figref> of substrate <figref>100</figref> as to the exposed surface of the Field area <figref>104 (b)</figref> on the upper surface <figref>100 (a)</figref> of substrate <figref>100</figref>, In other embodiments, the exposed surface the field area <figref>104 (b)</figref> on the upper surface <figref>100 (a)</figref> of substrate <figref>100</figref> to be taller have or the same size as the exposed surface the field area <figref>104 (b)</figref> on the lower surface of the substrate <figref>100</figref>,

0165<figref idrefs="S101">4E</figref> shows a side view of the <figref idrefs="S101">4A</figref> shown substrate <figref>100</figref>, As in<figref idrefs="S101">4E</figref> shown, the first and second opposing surfaces <figref>104 (b) -1</figref>. <figref>104 (b) -2</figref> of Field area <figref>104 (b)</figref> substantially coplanar with the outer surfaces of the molding material <figref>102</figref>, The mold material<figref>102</figref> can a Thickness "T" of an etched portion the field area <figref>104 (b)</figref> have. Therefore, the molding material<figref>102</figref> a thickness have, the same as the thickness of the substrate <figref>100</figref> on some Ask, and it may have a thickness "T" on the other have bodies.

0166The regarding <figref idrefs="S101">4A</figref>-<figref idrefs="S101">4E</figref> described embodiments have a number of advantages. First, the large exposed improves Field area <figref>104 (b)</figref> the thermal performance the molded semiconductor chip package through Providing a large Heat-routing path of the semiconductor chips <figref>110</figref>. <figref>112</figref>. <figref>114</figref>, additionally , the great Die attach area <figref>106</figref> the substrate <figref>100</figref> as conductive and thermal path one or more semiconductor chips on the substrate <figref>100</figref> assembled are serving.

0167The in <figref idrefs="S100">3A</figref>-<figref idrefs="S100">3E</figref> and <figref idrefs="S101">4A</figref>-<figref idrefs="S101">4E</figref> shown embodiments still have other advantages in addition to those already mentioned. First, since no DAP is required, many different semiconductor die configurations can be used are, without altering the external conductor configurations. Of the Distance between chips on the substrate may be minimized, since a DAP is not required, whereby a more compact housing provided is. Second, since a DAP is not required, is a latch, which is used during the DAP to connect the processing is not required. This can reduce the processing simplify. Third, a one of a bared Field related field unutilized area in a substrate according to a embodiment the invention can be maximized. As shown above, the exposed Field almost the entire back the substrate that supports the semiconductor chip, to complete. Fourth , as shown above, the lead frame structure an exposed surface have in the substrate to the drain or other terminal in a electrical component in a semiconductor chip on the substrate is mounted to connect. This can be achieved, while the exposed field area on the opposite Side of the substrate, which eventually suitable to a circuit board soldered is is maximized.

III. A method for producing a semiconductor chip package under Using a printed leadframe structure

0168Some the preformed substrate embodiments, which were described above, using an etched leadframe structure (For example, with respect to the <figref idrefs="S95">1A</figref>-<figref idrefs="S96">1H</figref> described Embodiments) and be formed using expensive cover tape. the Using etched Lead frame and cover is expensive. Band is a relatively expensive increasing component in the manufacturing process and the masking and etching process which Manufacturing time, complexity and the cost of a preformed substrate. It would be desirable, provide a method for making a pre-formed substrate, which is not on the use of masking tape or etched leadframe structures recourse.

0169Around tackle this problem, embodiments the invention comprises a printed circuitframe apparatus use to form a premolded substrate. Masking tape and etched leadframe are not required, to the preformed substrate to be formed, so that the final Housing, which is produced, less expensive than a housing which is formed using an etched Lead frame and cover tape. Due to the process efficiency, which using embodiments the invention is achieved, can the resulting semiconductor chip package, which according to embodiments the invention are prepared, cost about 42% less than similar Semiconductor chip package, which preformed substrates with etched leadframe structures use.

0170In addition to the illustrated addressing previously would trouble it is also desirable the thermal characteristics of semiconductor chip packages including improve preformed substrates. In embodiments of the invention is the thermal property good, because heat of a semiconductor chip can be transmitted to the conductors of a leadframe structure.

0171It would also desirable, in some cases, the area of ​​a soldering point, is used, a semiconductor chip package to a circuit board to connect, to enlarge. Among Using embodiments of the invention may be a concave structure formed in the substrate. With a concave structure, it is possible, the size of a soldering point to increase and an abandoned field can from potential protected electrical short will. This is explained below in more detail.

0172embodiments the invention can also flip-chip mounting methods using which a non-conductive adhesive or a Lötbuckel and a liquefaction process use. The leadframe structure design is relatively simple and it is also possible, the pin number for to increase a given case size. It is possible, too, a larger chip in the semiconductor chip package to use because a DAP (die attach pad, chip terminal box) do not is required in the embodiments the invention.

0173In one embodiment the method comprises forming a pre-shaped substrate. The step of forming of the preformed substrate comprises (i) placing a leadframe structure between at least one first and second Ausformform Ausformform, (ii) contacting the leadframe structure with the first and second Ausformform, and (iii) forming a molding material around the leadframe structure. The leadframe structure may be a non-etched leadframe structure and the first and second part of a Ausformformen can Ausformapparats his or tool. After the preformed substrate formed is, a semiconductor chip is attached to the premolded substrate. Wire connections, conductive clips, solder structures (for example, solder balls) or similar can be used to the semiconductor chip to conductors in the preformed to couple substrate. After the semiconductor chip is electrically and mechanically is coupled to the preformed substrate, the semiconductor chip is then encapsulated in a capsule material to form a semiconductor die package. The capsule material may be the same or a different to the above-described molding material. For example, the capsule material be different than the molding material described above, to the thermal properties of the molded chip package to improve and to reduce the manufacturing cost.

0174In a specific embodiment, , the method for producing a semiconductor chip package the following process using: a) a first molding process to to form a premolded substrate, b) a substrate cleaning process, which a plasma, a laser, or chemical etching and / or can use a deflash process, c) a die attach process, d) a plasma cleaning process, e) a wire bonding process, e) a second Ausform- or capsule process, and f) a singulation process. Each of these specific processes in more detail further described below.

0175<figref idrefs="S102">5</figref> shows a leadframe structure array <figref>201</figref>Which a number of associated leadframe structures <figref>200</figref> includes. Each leadframe structure <figref>200</figref> in the leadframe structure array <figref>201</figref> includes uncut cables <figref>200 (b)</figref> and a larger main portion <figref>200 (a)</figref>, The uncut cables <figref>200 (b)</figref> relate to: opposing Sides of the main portion <figref>200 (a)</figref>, The leadframe structures<figref>200</figref> in the leadframe structure array <figref>201</figref> optionally used in individual semiconductor chip packages and, if necessary separated from each other. The leadframe structures<figref>200</figref> and the leadframe structure array <figref>201</figref> can any characteristics or properties of any of the leadframe structures described above exhibit.

0176<figref idrefs="S103">6A</figref> shows a perspective view of a molded Leadframe structure array <figref>206</figref>. after a Ausformwerkzeug <figref>202</figref> has been formed. The Ausformwerkzeug<figref>202</figref> includes a first Ausformform <figref>202 (a)</figref> and a second Ausformform <figref>202 (b)</figref>, An inlet for introducing an uncured Molding material and a fluid outlet for excess molding material can in the Ausformwerkzeug <figref>202</figref> be provided. In some make can and heating elements (not shown) provided to the to heat molding material, so that it can flow. In general, Shaping tools known in the art.

0177Around the molded leadframe structure array <figref>206</figref> train, , the leadframe structure arrangement described above <figref>201</figref> in between the first and second Ausformformen <figref>202 (a)</figref>. <figref>202 (b)</figref> used will. A molding material<figref>204</figref> is around the leadframe structure array <figref>200</figref> formed and hardens, a molded leadframe structure array <figref>206</figref> form. The molding material <figref>204</figref> exposed outer surfaces of the pipes <figref>200 (b)</figref> and of the main portion <figref>200 (a)</figref>, A slightly raised rim structure<figref>204 (a)</figref> can to each main area <figref>200 (a)</figref> to be available. Some exterior surfaces of molding material <figref>204</figref> and the leadframe structures in the leadframe structure array <figref>200</figref> are essentially coplanar with each other.

0178the Ausformwerkzeug <figref>202</figref> has two Ausformformen <figref>202 (a)</figref>. <figref>202 (b)</figref>. which corresponding configurations may have to the molding material <figref>204</figref> in a desired Way to form. The upper mold<figref>202 (b)</figref> may have surfaces which are in direct contact with the main areas <figref>200 (a)</figref> are surfaces of uncut cables <figref>200 (b)</figref> and any other surfaces which are not intended to be covered with the molding material. By using the Ausformformen <figref>202 (a)</figref>. <figref>202 (b)</figref> is it does not require expensive cover tape or etched leadframe structures to be used when a pre-shaped substrate is formed. This reduces the cost of the preformed substrate and therefore the semiconductor mold housing, which formed from the preformed substrate. This also reduces the Number of steps which are needed to the molded forming portion of the preformed substrate, thus process time and expense einsparend. After all is using Ausformformen <figref>202 (a)</figref>. <figref>202 (b)</figref> possible a Edge of the molding material to a main area <figref>200 (a)</figref> form, thereby a concave structure ausbildend.

0179As in <figref idrefs="S104">6B</figref> shown, a cleaning process may be used are, the adhesion a capsule material to the molding material <figref>204</figref> and the exposed conductors <figref>200 (b)</figref> to increase. Any suitable cleaning process can be used. For example, a plasma cleaning process, a Laser cleaning process, a chemical etching process, a mechanical Deflash- process, etc. can be used. Suitable purification process parameters from Skilled are determined. <figref idrefs="S104">6B</figref> shows specifically a purifier <figref>216</figref>As the upper surface the molded leadframe assembly <figref>206</figref> cleans.

0180As in <figref idrefs="S104">6C</figref> shown, after the molded lead frame assembly <figref>206</figref> With the Purifier <figref>216</figref> is cleaned, an adhesive <figref>218</figref> (or Solder or the like.) On the outer surfaces of the main areas <figref>200 (a)</figref> be coated using an adhesive coating apparatus <figref>217</figref>, The adhesive<figref>218</figref> can any suitable adhesive commercially available include, including an epoxy adhesive. The adhesive<figref>218</figref> can filled or unfilled and may or may not include a conductive material.

0181As in <figref idrefs="S105">6D</figref> shown, after the adhesive <figref>218</figref> on the main areas <figref>208 (a)</figref> is coated, or a More numerous semiconductor dies <figref>226</figref> on the main areas <figref>200 (a)</figref> assembled. The semiconductor chip <figref>226</figref>Which electrically connected to each main area <figref>200 (a)</figref> coupled is, can the lines <figref>200 (b)</figref> can be positioned to overlap and. However, the semiconductor chip <figref>226</figref> electrically from the lines <figref>200 (b)</figref> isolated be due to the presence of the edge of the molding <figref>204 (a)</figref>, Because the semiconductor form <figref>226</figref> actually a portion of the conductor <figref>200 (b)</figref> positioned may be, is the size of the semiconductor form <figref>226</figref> not on the size of the main portions <figref>200 (a)</figref> limited. This allows the inclusion of larger semiconductor chips in the semiconductor chip package according to the embodiments the invention.

0182As also in <figref idrefs="S105">6D</figref> shown, then wire terminals (wire bonds) <figref>228</figref> in between electrical connections (Not shown) on the upper side of the semiconductor chip <figref>226</figref> and the conductors <figref>200 (b)</figref> formed. In other embodiments, can, instead of wire bonds <figref>228</figref>. conductive clips are used to the conductors <figref>200 (b)</figref> electric and mechanically connected to the upper surfaces of the semiconductor chips <figref>226</figref> to couple.

0183As in <figref idrefs="S105">6E</figref> shown, the resulting assembly is then with a capsule material <figref>230</figref> overmolded to an overmolded arrangement <figref>232</figref> form. <figref idrefs="S105">6E</figref> shows a top perspective view of the over-molded assembly <figref>232</figref>,

0184Any suitable molding process may be used to treat the over-molded arrangement <figref>232</figref> form. For example, a Ausformwerkzeug be used with Ausformformen to form the overmolded assembly. As in previous embodiments can the capsule material <figref>230</figref> be the same or different as the molding material, which is used to the preformed form substrate in the semiconductor chip package.

0185<figref idrefs="S105">6F</figref> shows a perspective bottom view of the opposing Side of the over-molded arrangement <figref>232</figref>, what a <figref idrefs="S105">6E</figref> shown is. As shown, can second edges <figref>204 (b)</figref> of Molding material around the lower surfaces of the main portions <figref>208 (a)</figref> the be leadframe structures available. As hereinafter in further Detail is described, this concave structures formed.

0186<figref idrefs="S106">6G</figref> shows the overmolded arrangement <figref>232</figref> comprising a molding <figref>230</figref>. as with a laser <figref>238</figref> is marked or any other suitable marker. The overmolded assembly<figref>232</figref> includes a number of associated semiconductor form enclosures. After labeling, the connected housing are separated by a respective separating element (not shown) the molded housing inseparable. Suitable separators include laser, saws, Punching apparatus or the like.

0187<figref idrefs="S106">6H</figref> shows a top perspective view of a shaped housing <figref>246</figref>. while <figref idrefs="S105">6E</figref> a bottom perspective view of the molded housing <figref>246</figref> shows. As in <figref idrefs="S106">6I</figref> shown, the second edge <figref>204 (b)</figref> and the exposed surface of the main area <figref>208 (b)</figref> a concave structure forming. The concave structure can include solder (not shown) and can be flipped and then be mounted on a printed circuit board. The concave structure can be used to solder particular at a connecting body and the second edge <figref>204 (d)</figref> the molding material can be a barrier between the to the main area <figref>204 (b)</figref> and the conductors <figref>200 (b)</figref> attached Lot train. As shown the lateral edges of the circuit <figref>200 (b)</figref> essentially coplanar with the side surfaces of the molding material <figref>204</figref> and not extend to these. The lower surfaces the Head <figref>200 (b)</figref> are also substantially coplanar with the surfaces the molding material <figref>204</figref>That between the conductors <figref>200 (b)</figref> is.

0188The <figref idrefs="S107">7A</figref>-<figref idrefs="S107">7D</figref> show side views of a Semiconductor mold package, as it is produced. The in<figref idrefs="S107">7A</figref>-<figref idrefs="S107">7D</figref> shown The method is similar to that in the <figref idrefs="S103">6A</figref>-<figref idrefs="S106">6I</figref> shown Process.

0189<figref idrefs="S107">7A</figref> shows a leadframe structure <figref>302</figref>. comprising a first surface <figref>302 (a)</figref> and a second surface <figref>302 (b)</figref> opposite the first surface <figref>302 (a)</figref>, In this example, the leadframe structure <figref>302</figref> a Number of rooms <figref>303</figref>. which between the conductors <figref>305</figref> are present, and a central main section <figref>333</figref> the leadframe structure <figref>302</figref>, The central main portion <figref>333</figref> between sets of ladders <figref>305</figref> available. The leadframe structure<figref>302</figref> can the same or different characteristics as the previously have leadframe structures described. For example, the leadframe structure<figref>302</figref> on include material such as copper and may be plated.

0190<figref idrefs="S107">7B</figref> shows a leadframe structure <figref>302</figref>. after a molding <figref>302</figref> been formed thereon is. This may constitute a first molding process. A preformed substratum <figref>301</figref> is then formed following. The molding material<figref>302</figref> Has two sections <figref>304 (a)</figref>. <figref>304 (b)</figref>Which an edge the molding material <figref>304</figref> can form. As in<figref idrefs="S107">7B</figref> shown, a concave structure <figref>307</figref> by the Ausformmaterialabschnitte <figref>304 (a)</figref>. <figref>304 (b)</figref> educated and the lower surface the central main portion <figref>333</figref> of the leadframe structure.

0191As in <figref idrefs="S107">7C</figref> shown, after the preformed substrate <figref>301</figref> educated is a semiconductor chip <figref>310</figref> to the preformed substrate <figref>301</figref> among Using an adhesive <figref>308</figref> fixed, the conducting a may or may not include conductive adhesive, solder, etc.. The semiconductor chip<figref>310</figref> can a horizontal or a vertical device include, as previously described. If a vertical device is present, the adhesive <figref>308</figref> be conductive, so that current from or to the lower surface of chips <figref>310</figref> to the adhesive <figref>308</figref>, The central main section <figref>333</figref> the leadframe structure <figref>302</figref> and to a corresponding field on a circuit board not ( shown) flow can.

0192Then are wire connections <figref>314</figref> between the conductors <figref>305</figref> the Leadframe structure <figref>302</figref> and electrical connections (not shown) on the upper surface of the semiconductor chip <figref>310</figref> formed. The upper surface of the Semiconductor chips <figref>310</figref> can be further from the preformed substrate <figref>301</figref> be as the opposite surface of the semiconductor chip <figref>310</figref>, A capsule material<figref>318</figref> becomes then over the semiconductor chip <figref>310</figref> and the wire connections <figref>314</figref> formed. As in <figref idrefs="S107">7C</figref> shown, the lateral surfaces of capsule material <figref>318</figref> coplanar with the side surfaces of the ladder <figref>305</figref> be the leadframe structure.

0193A perspective view of the resulting semiconductor chip package <figref>330</figref> is in <figref idrefs="S107">7D</figref> shown. The semiconductor chip package<figref>330</figref> includes a capsule material <figref>318</figref> and a leadframe structure <figref>302</figref>, An edge of the molding <figref>304</figref> is around the central main section <figref>333</figref> the leadframe structure <figref>302</figref> arranged, a concave structure <figref>301</figref> form. are as shown the regions between the conductors of the leadframe structure <figref>302</figref> With the molding material <figref>304</figref> filled and the surfaces of the molding material <figref>304</figref> at these points are substantially coplanar with the surfaces the ladder.

0194Other Semiconductor chip package according to the embodiments the invention can preformed substrates without concave structures include. Such embodiments can with reference to the <figref idrefs="S108">8A</figref>-<figref idrefs="S108">8E</figref> described will.

0195<figref idrefs="S108">8A</figref> shows another cross-sectional side view a leadframe structure <figref>320</figref> including a gap <figref>321</figref>, The leadframe structure <figref>320</figref> also includes a first surface <figref>320 (a)</figref> and a second surface <figref>320 (b)</figref> and ladder <figref>324</figref> on opposite Sides of the gap <figref>321</figref>,

0196<figref idrefs="S108">8B</figref> shows the leadframe structure <figref>320</figref>. after a molding process is performed has been. This may constitute a first molding process. As in <figref idrefs="S108">8B</figref> shown is a molding <figref>322</figref> within the gap <figref>321</figref> arranged and outer surfaces of the molding <figref>322</figref> are substantially coplanar with the first and second surfaces <figref>320 (a)</figref>. <figref>320 (b)</figref> the Leadframe structure <figref>320</figref>, The resulting preformed substratum <figref>363</figref> has first and second opposing surfaces <figref>363 (a)</figref>. <figref>363 (b)</figref>. which with the outer surfaces of the molding material <figref>322</figref> and the first and second surfaces <figref>320 (a)</figref>. <figref>320 (b)</figref> the leadframe structure <figref>320</figref> coincide. In contrast to the in <figref idrefs="S107">7B</figref> shown Substrate is not a concave structure formed in the preformed substratum <figref>363</figref>Which in <figref idrefs="S108">8B</figref> shown is.

0197As in <figref idrefs="S108">8C</figref> shown, a semiconductor chip <figref>328</figref> on the substrate <figref>363</figref> assembled using an adhesive <figref>344</figref>. after the substrate <figref>363</figref> is trained. In this example the semiconductor chip <figref>328</figref> an upper surface with electrical connections comprise the electrical connections a part of a horizontal Device in the semiconductor chip <figref>328</figref> form. The adhesive<figref>344</figref> can be an epoxy adhesive or any other suitable type of adhesive and can be filled or unfilled be.

0198After mounting the semiconductor chip <figref>328</figref> on the substrate <figref>363</figref> will wire connections <figref>329</figref> between the conductors <figref>324</figref> of substrate <figref>363</figref> and the upper surfaces of the semiconductor mold <figref>328</figref> formed. alternative could conductive clips are used in other embodiments of the invention.

0199As in <figref idrefs="S108">8D</figref> is shown after the wire connections <figref>329</figref> in between the upper surface of Semiconductor chips <figref>328</figref> and the conductors <figref>324</figref> educated are, a capsule material <figref>332</figref> over the semiconductor chip <figref>328</figref> adapted to a semiconductor chip package <figref>330</figref> form. This can be a second molding process. In this example extends the capsule material <figref>332</figref> does not have the outer edges the substrate <figref>363</figref>, As in previous embodiments can the capsule material <figref>332</figref> the same or a different be to the molding material <figref>322</figref>,

0200<figref idrefs="S108">8E</figref> shows a perspective bottom view of the Semiconductor chip package <figref>330</figref>. what a <figref idrefs="S108">8D</figref> is shown. As in<figref idrefs="S108">8E</figref> shown, the lower surface of the Semiconductor shape housing <figref>330</figref> flat. The lower surfaces the Head <figref>324</figref> are substantially coplanar with the lower surfaces the molding material <figref>322</figref>,

0201<figref idrefs="S109">9A</figref> shows another cross-sectional side view a leadframe structure <figref>320</figref> including a gap <figref>321</figref>, The leadframe structure <figref>320</figref> also includes a first surface <figref>320 (a)</figref> and a second surface <figref>320 (b)</figref> and ladder <figref>324</figref> on opposite Side of the gap <figref>321</figref>,

0202<figref idrefs="S109">9B</figref> shows the leadframe structure <figref>320</figref>. after a molding process has been executed. As shown, fills the shaped molding material <figref>322</figref> the gap <figref>321</figref> and covered parts of the second surface <figref>320 (b)</figref> the Leadframe structure <figref>320</figref> to a substrate <figref>363</figref> form. However, the molding material covered <figref>322</figref> in this example not the first surface <figref>320 (a)</figref> the Leadframe structure <figref>320</figref>,

0203reference Referring to <figref idrefs="S109">9C</figref> , after the substrate <figref>363</figref> educated is a semiconductor chip <figref>328</figref> to the substrate <figref>363</figref> among Using an adhesive <figref>344</figref> attached. wire connections<figref>329</figref> will between the upper surface of the semiconductor chip <figref>328</figref> and the conductors <figref>324</figref> the Leadframe structure <figref>320</figref> in the substratum <figref>363</figref> formed. As in previous embodiments could conductive clips instead of wire bonds <figref>329</figref> used will.

0204reference Referring to <figref idrefs="S109">9D</figref> , after the semiconductor chip <figref>328</figref> at the substrate <figref>363</figref> is attached, a capsule material <figref>332</figref> about the substratum <figref>363</figref> and the semiconductor chip <figref>328</figref> formed, a semiconductor chip package <figref>330</figref> to form. As shown, the conductors extend<figref>324</figref> the Leadframe structure <figref>320</figref> not on the capsule material <figref>332</figref> addition.

0205<figref idrefs="S109">9E</figref> shows a perspective bottom view of a Semiconductor chip package <figref>330</figref> in <figref idrefs="S109">9D</figref>, As shown, the molding material is<figref>320</figref> from the second surface <figref>320 (b)</figref> the Leadframe structure <figref>320</figref> in front.

0206<figref idrefs="S110">10A</figref> shows another cross-sectional side view a leadframe structure <figref>320</figref> including a gap <figref>321</figref>, The leadframe structure <figref>320</figref> also includes a first surface <figref>320 (a)</figref> and a second surface <figref>320 (b)</figref> and ladder <figref>324</figref> on opposite Sides of the gap <figref>321</figref>,

0207As in <figref idrefs="S110">10B</figref> shown, a filled molding material <figref>320</figref> the gap <figref>321</figref> the leadframe structure <figref>320</figref> and covered also a portion of the first surface <figref>320 (a)</figref> the leadframe structure <figref>320</figref>. to a preformed substrate <figref>363</figref> form. The molding material<figref>320</figref> covered not the second surface <figref>320 (b)</figref> the Leadframe structure <figref>320</figref> in this example.

0208As in <figref idrefs="S110">10C</figref> shown, a semiconductor chip <figref>328</figref> on the substrate <figref>363</figref> using an adhesive <figref>344</figref> assembled. wire connections <figref>320</figref> or the like. can be formed to electrical connections (Not shown) on the upper surface of the semiconductor chip <figref>328</figref> With the conductors <figref>324</figref> the leadframe structure <figref>320</figref> of substrate <figref>363</figref> to couple.

0209As in <figref idrefs="S110">10D</figref> shown covered a capsule material <figref>332</figref> the Semiconductor chip <figref>328</figref> to the conductors of the substrate <figref>363</figref>. a semiconductor chip package <figref>330</figref> form. As shown, the lower surface of the semiconductor chip package <figref>330</figref> flat.

0210<figref idrefs="S110">10E</figref> shows a perspective bottom view of the Semiconductor chip package <figref>330</figref>. which in <figref idrefs="S110">10D</figref> is shown.

0211<figref idrefs="S111">11A</figref> shows another cross-sectional side view a leadframe structure <figref>320</figref> including a gap <figref>321</figref>, The lead frame structure also includes a first surface <figref>320 (a)</figref> and a second surface <figref>320 (b)</figref> and ladder <figref>324</figref> on opposite Sides of the gap <figref>321</figref>,

0212<figref idrefs="S111">11B</figref> shows a cross-sectional side view a substrate <figref>363</figref> after exposure of the leadframe structure <figref>320</figref> to a molding process. substrate<figref>363</figref> includes a molding <figref>322</figref>. that the gap <figref>321</figref> crowded and a portion of the first and second surfaces <figref>320 (a)</figref>. <figref>320 (b)</figref> the Leadframe structure <figref>320</figref> covered.

0213<figref idrefs="S111">11C</figref> shows the mounting of a semiconductor chip <figref>328</figref> on the substrate <figref>363</figref> using an adhesive <figref>344</figref>, wire connections <figref>329</figref> . Be or the like between the upper surface of the semiconductor chip <figref>328</figref> and the conductors <figref>324</figref> of substrate <figref>363</figref> formed.

0214As shown in <figref idrefs="S111">11D</figref>, Then a capsule material is <figref>320</figref> about the substratum <figref>363</figref> and the semiconductor chip <figref>328</figref> shaped, a semiconductor chip package <figref>330</figref> form. As shown, the molding material is <figref>320</figref> about the lower surfaces the Head <figref>324</figref> in front.

0215<figref idrefs="S111">11E</figref> shows a perspective bottom view of the Semiconductor chip package <figref>330</figref>. which in <figref idrefs="S111">11D</figref> is shown. As shown, the outer surface of the molding material <figref>322</figref>That between the conductors <figref>324</figref> is and the outer surfaces of ladder <figref>320</figref> substantially coplanar. However, the central Section of the molding <figref>322</figref> between the opposite records the Head <figref>324</figref> charged in relation to the outer surfaces of ladder <figref>320</figref>,

0216<figref idrefs="S112">12A</figref> shows another cross-sectional side view a leadframe structure <figref>320</figref> including columns <figref>321</figref>, The leadframe structure <figref>320</figref> also includes a first surface <figref>320 (a)</figref> and a second surface <figref>320 (b)</figref>, ladder<figref>324</figref> are on opposite Sides of the columns <figref>321</figref> arranged. A central body portion<figref>330</figref> is between columns <figref>321</figref>,

0217<figref idrefs="S112">12B</figref> shows the leadframe structure <figref>320</figref> in <figref idrefs="S112">12A</figref>been after a molding process carried out is. As shown, a molding material<figref>322</figref> in between the columns <figref>321</figref> and on at least a portion of the second surface <figref>320 (b)</figref> the Leiterrrahmenstruktur <figref>320</figref> shaped to a pre-formed substratum <figref>363</figref> according to a embodiment the invention form. The molding material<figref>322</figref> includes a first portion <figref>322 (a)</figref> and a second portion <figref>322 (b)</figref>, The first paragraph <figref>322 (a)</figref>, The second section <figref>322 (b)</figref> and the central body portion <figref>333</figref> the leadframe structure <figref>320</figref> in between the first and second sections <figref>322 (a)</figref>. <figref>322 (b)</figref> can a concave structure <figref>337</figref> form.

0218As in <figref idrefs="S112">12C</figref> shown, a semiconductor chip <figref>328</figref> on the substrate <figref>363</figref> using an adhesive <figref>344</figref> assembled. The surface the substrate <figref>363</figref>On which the semiconductor chip <figref>328</figref> assembled is, is flat. Then wire connections<figref>329</figref> (Or the like.) between the conductors <figref>324</figref> the substrate <figref>363</figref> and all electrical connections on the upper surface of the semiconductor chip <figref>328</figref> formed.

0219As in <figref idrefs="S112">12D</figref> shown, after the semiconductor chip <figref>328</figref> on the substrate <figref>363</figref> mounted, is a capsule material <figref>332</figref> on the substrate <figref>363</figref> and over the semiconductor chip <figref>328</figref> shaped to a semiconductor chip package <figref>330</figref> form.

0220<figref idrefs="S112">12E</figref> shows a perspective bottom view of the Semiconductor chip package <figref>330</figref>. which in <figref idrefs="S112">12D</figref> is shown. As in<figref idrefs="S112">12E</figref> shown, includes the molding material <figref>322</figref> a Edge of the molding <figref>322</figref>Which has a concave structure with the main portion <figref>333</figref> the leadframe structure <figref>320</figref> surrounds and forms.

0221The with respect to the <figref>6</figref>-<figref>12</figref> described embodiments have wire bonds or the like., to provide electrical connections to a Surface of the semiconductor chip, opposite to the preformed substrate mounting surface to conductors in the preformed connect substrate. <figref>13</figref>-<figref>17</figref> illustrate that embodiments the invention can be used with one form of the flip chip type can, a semiconductor chip package the flip-chip-type train.

0222<figref idrefs="S113">13A</figref> shows another cross-sectional side view a leadframe structure <figref>340</figref> including a gap <figref>339</figref>, The leadframe structure <figref>340</figref> also includes a first surface <figref>340 (a)</figref> and a second surface <figref>340 (b)</figref>, ladder <figref>326</figref> are on opposite sides of the gap <figref>339</figref>,

0223<figref idrefs="S113">13B</figref> shows the leadframe structure <figref>340</figref> in <figref idrefs="S113">13A</figref>After being exposed to a molding process has been to a preformed substrate <figref>349</figref> form. As shown therein, fills the molding material <figref>342</figref> the gap <figref>339</figref>But extends not over the first and second surfaces <figref>340 (a)</figref>. <figref>340 (b)</figref> the Leadframe structure <figref>340</figref>, The resulting preformed substratum <figref>349</figref> has opposite planar surfaces.

0224<figref idrefs="S113">13C</figref> shows a semiconductor chip <figref>346</figref> including a number of solder bumps <figref>348</figref>, The solder bumps <figref>348</figref> can electrical connections in a semiconductor device in the semiconductor chip <figref>346</figref> coupled will.

0225The solder bumps <figref>348</figref> can any include suitable solder material including Pb-Sn solder, Pb-free solder, etc.. Alternatively, conductive columns, which conductive a comprise materials such as copper, instead of or in addition to the solder bumps <figref>348</figref> used will.

0226As in <figref idrefs="S113">13C</figref> shown, the semiconductor chip <figref>346</figref> on the preformed substrate <figref>349</figref> using an adhesive <figref>344</figref> assembled. The adhesive <figref>346</figref> can on the substrate <figref>349</figref> filed are including using any suitable process Laminating, roll coating, doctor blade coating, etc. Any suitable Adhesive including an epoxy adhesive may be used.

0227<figref idrefs="S113">13D</figref> shows the molded semiconductor chip package <figref>350</figref>. after the semiconductor chip <figref>346</figref> on the surface <figref>349</figref> assembled is. As shown, fills the adhesive <figref>340</figref> the space between the semiconductor chip <figref>346</figref> and the preformed substrate <figref>349</figref> and may partially outside of the periphery of the semiconductor chip <figref>346</figref> lie. In the semiconductor chip package<figref>350</figref> couple the solder bumps <figref>348</figref> Ports (not shown) in the semiconductor chip <figref>346</figref> with the heads <figref>366</figref> the Leadframe structure <figref>340</figref> electrically.

0228Although the <figref idrefs="S113">13C</figref> and <figref idrefs="S113">13D</figref> a Show adhesive deposited onto a substrate first is and then a semiconductor chip <figref>346</figref> on the substrate <figref>349</figref> assembled has been is to be understood that other embodiments are possible. For example, it is possible to the semiconductor chip <figref>346</figref> first on the substrate <figref>349</figref>to assemble and then the space between the semiconductor chip <figref>346</figref> and the substrate <figref>349</figref> to fill with an underfill material. underfill are commercially available. In other embodiments, an underfill material or an additional Adhesive is not required, since the solder <figref>348</figref> the semiconductor chip <figref>346</figref> With the preformed substrate <figref>349</figref> coupled.

0229<figref idrefs="S113">13E</figref> shows a perspective bottom view of the Semiconductor chip package <figref>350</figref>. which in <figref idrefs="S113">13D</figref> is shown. As shown, covered the lower surface of the semiconductor chip package <figref>350</figref> With the second surface <figref>340 (b)</figref> the Leadframe structure <figref>340</figref> together. On the underside of Semiconductor chip package <figref>350</figref> is the outer surface of Leadframe structure <figref>340</figref> substantially coplanar with the outer surface of molding material <figref>342</figref>,

0230<figref idrefs="S114">14A</figref> shows another cross-sectional side view a leadframe structure <figref>340</figref>, Including a gap <figref>339</figref>, The leadframe structure <figref>340</figref> also includes a first surface <figref>340 (a)</figref> and a second surface <figref>340 (b)</figref>, ladder <figref>366</figref> are on opposite sides of the gap <figref>339</figref> arranged.

0231<figref idrefs="S114">14B</figref> shows the leadframe structure <figref>340</figref>. after it has been subjected to a molding process. The molding material<figref>342</figref> fills the gap <figref>339</figref> and covers at least a portion of the second surface <figref>340 (b)</figref> the Head frame structure <figref>340</figref>To a preformed substrate <figref>349</figref> form. The first surface <figref>340 (a)</figref> is not with the molding material <figref>342</figref> in this embodiment covered.

0232<figref idrefs="S114">14C</figref> shows a semiconductor chip <figref>346</figref> including solder bumps <figref>348</figref>. that on the substrate <figref>349</figref> with adhesive <figref>344</figref> assembled are. As in the previous embodiment penetrate the solder bumps <figref>348</figref> the adhesive layer <figref>344</figref>To the leadframe structure <figref>340</figref> to to contact. As in the previous embodiments, the solder bumps <figref>348</figref> any suitable solder including Pb-Sn, Pb-free solder, etc. include. Conductive columns could additionally are or used in place of the solder.

0233<figref idrefs="S114">14D</figref> shows the semiconductor die package <figref>350</figref>. after the semiconductor chip <figref>346</figref> on the substrate <figref>349</figref> assembled is. <figref idrefs="S114">14E</figref> shows a perspective Bottom view of the semiconductor chip package <figref>350</figref>which in <figref idrefs="S114">14D</figref> is shown. As in the<figref idrefs="S114">14D</figref> and <figref idrefs="S114">14E</figref> shown, is the molding material <figref>342</figref> downward from the second surface <figref>340 (b)</figref> the Leadframe structure <figref>343</figref> in front. As in<figref idrefs="S114">14E</figref> shown that A is usformmaterial<figref>342</figref>. which between adjacent conductors <figref>366</figref> is essentially coplanar with the outer surfaces of ladder <figref>366</figref>,

0234<figref idrefs="S115">15A</figref> shows another cross-sectional side view a leadframe structure <figref>340</figref> including a gap <figref>339</figref>, The leadframe structure <figref>340</figref> also includes a first surface <figref>340 (a)</figref> and a second surface <figref>340 (b)</figref>, ladder <figref>366</figref> are on opposite sides of the gap <figref>339</figref>,

0235<figref idrefs="S115">15B</figref> shows the leadframe structure <figref>340</figref>. after it has been subjected to a molding process. The molding material<figref>342</figref> fills the gap <figref>339</figref> and does not cover the first surface <figref>340 (a)</figref> or the second surface <figref>340 (b)</figref> the Leadframe structure <figref>340</figref>,

0236<figref idrefs="S115">15C</figref> shows the semiconductor chip <figref>346</figref>, as it on the substrate <figref>349</figref> is mounted. Like the previous Embodiments, has the semiconductor chip <figref>346</figref> a number of solder bumps <figref>348</figref>. which at terminals not ( shown) in the semiconductor chip <figref>346</figref> are connected.

0237As in <figref idrefs="S115">15D</figref> shown, after the semiconductor chip <figref>346</figref> on the preformed substrate <figref>349</figref> assembled is a capsule material <figref>352</figref> above and below the semiconductor chip <figref>346</figref> shaped be a semiconductor chip package <figref>350</figref> form. The capsule material <figref>352</figref> may be the same or different Type of material used as the molding material described above <figref>342</figref>,

0238<figref idrefs="S115">15E</figref> shows a perspective bottom view of the Semiconductor chip package <figref>350</figref>, As shown, the outer surface of the molding material <figref>342</figref> substantially coplanar with the outer, lower surfaces the Head <figref>366</figref>,

0239the Semiconductor chip package <figref>350</figref> can be reversed and mounted on a circuit board. If desired, Lot can on the exposed surfaces of the conductors <figref>366</figref> in front mounting the semiconductor chip package <figref>350</figref> on the circuit board can be formed.

0240deviant of the preceding embodiments, on the substrate <figref>349</figref> prior to the mounting of semiconductor chips <figref>346</figref> on the substrate <figref>349</figref> an adhesive layer does not exist. Instead covers the capsule material <figref>350</figref> both the upper and the lower surfaces of the semiconductor chip <figref>346</figref>,

0241<figref idrefs="S116">16A</figref> shows another cross-sectional side view a leadframe structure <figref>340</figref> including a gap <figref>339</figref>, The leadframe structure <figref>340</figref> also includes a first surface <figref>340 (a)</figref> and a second surface <figref>340 (b)</figref>, ladder <figref>366</figref> are on opposite sides of the gap <figref>339</figref>,

0242<figref idrefs="S116">16B</figref> shows the leadframe structure <figref>340</figref>. after it has been subjected to a molding process. The molding material<figref>342</figref> fills the gap <figref>339</figref> and covers at least a portion of the second page <figref>340 (b)</figref>To a preformed substrate <figref>349</figref> form.

0243<figref idrefs="S116">16C</figref> shows the semiconductor chip <figref>346</figref>, as it on the preformed substrate <figref>349</figref> is mounted. The semiconductor chip<figref>346</figref> includes a plurality of solder bumps <figref>348</figref>, The solder bumps <figref>348</figref> to contact the ladder <figref>366</figref> after mounting.

0244As in <figref idrefs="S116">16D</figref> shown, after the semiconductor chip <figref>346</figref> on the substrate <figref>349</figref> assembled is a capsule material <figref>352</figref> above and below the semiconductor chip <figref>346</figref> shaped be a semiconductor chip package <figref>350</figref> form.

0245<figref idrefs="S116">16E</figref> shows a perspective bottom view of the Semiconductor chip package <figref>350</figref>. which in <figref idrefs="S116">16D</figref> is shown. As shown, is the molding material <figref>342</figref>Which between adjacent ladders <figref>366</figref> is substantially coplanar with outer surfaces of these conductors <figref>366</figref>, A larger portion of the molding<figref>342</figref> stands by the heads <figref>366</figref> in front.

0246<figref idrefs="S117">17A</figref> shows another cross-sectional side view a leadframe structure <figref>340</figref>Including at least two columns <figref>339</figref>, The leadframe structure<figref>340</figref> includes also a first surface <figref>340 (a)</figref> and a second surface <figref>340 (b)</figref>, A central body portion <figref>333</figref> is between the columns <figref>339</figref>, ladder <figref>366</figref> extending outwardly from the columns <figref>339</figref>,

0247<figref idrefs="S117">17B</figref> shows the leadframe structure <figref>340</figref>. after it has been subjected to a molding process. As in<figref idrefs="S117">17B</figref> shown, filled the molding material <figref>342</figref> the columns <figref>339</figref> and covered at least a portion of the second surface <figref>340 (b)</figref>To a preformed substrate <figref>349</figref> form. The molding material<figref>342</figref> includes a first portion <figref>342 (a)</figref> and a second portion <figref>342 (b)</figref>. which along with a second of the central main portion <figref>333</figref> the Leadframe structure <figref>340</figref> a concave structure <figref>351</figref> form.

0248<figref idrefs="S117">17C</figref> shows the semiconductor chip <figref>346</figref>, as it on the substrate <figref>349</figref> is mounted. The semiconductor chip<figref>346</figref> includes a number of solder structures <figref>348</figref>, Which on its underside are attached. The solder structures<figref>348</figref> coupling electrical connections in the semiconductor chip <figref>348</figref> with the heads <figref>366</figref> the Leadframe structure <figref>340</figref> electrically.

0249As in <figref idrefs="S117">17D</figref> shown, the semiconductor chip <figref>346</figref> on the substrate <figref>349</figref> mounted, a capsule material <figref>352</figref> can and under the semiconductor chip <figref>346</figref> be shaped to a semiconductor chip package <figref>350</figref> form.

0250<figref idrefs="S117">17E</figref> shows a perspective bottom view of the Semiconductor chip package <figref>350</figref>. which in <figref idrefs="S117">17D</figref> is shown. As in<figref idrefs="S117">17E</figref> shown, an edge of a molding material <figref>342</figref> around the central body portion <figref>333</figref> formed. Together can they form a concave structure.

0251The with reference to the <figref idrefs="S102">5</figref>-<figref>17</figref> described embodiments provide a variety of benefits. First, can the Semiconductor chip package less are produced costly because costly masking and etched not needed leadframe structures be to produce a semiconductor chip package. In these embodiments be an etched Leadframe structure and the cover is not required to a preformed substrate form as a Ausformwerkzeug used with Ausformformen is to form the preformed substrate. In some cases, this reduce the cost of a semiconductor chip package by 42%, when with semiconductor chip packages compared, which produced using expensive cover tape will. Second, as shown by many of the foregoing embodiments shown, can the semiconductor chip package more semiconductor chips use. As previously illustrated, the size of the semiconductor chip does not need by the size of the chip mounting boxes in the leadframe structures that used in the substrates be limited to become. Third, it is in the embodiments of the invention possible, the pin number of conductors to increase, without increasing the size of the semiconductor chip package to enlarge. As Fourth, it is, when a concave pattern is formed, it is possible that Lötverbindungsverlässlichkeit to increase. The concave structures can containing solder, which is used the molded semiconductor chip package with printed circuit boards or the like. connect.

IV. A process for the preparation and of high-performance modules

0252High Power Modules be used in a variety of electronic applications. Some high-performance modules are "Smart" -Leistungsmodule. These power modules include at least one power semiconductor chip and at least one control semiconductor chip. The control semiconductor chip (Eg, an integrated driver circuit or driver chip) can be used to at least partially the operation of the power semiconductor chips control.

0253additional embodiments of the invention are high power modules and methods for preparing directed by high-performance modules. In one embodiment, a substrate including a leadframe structure and a obtained molding material. A surface of the molding and the leadframe structure are substantially coplanar. substrate includes a first die attach region and a second die attach region. A first semiconductor chip is mounted on the die attach region and a second semiconductor chip is attached to the second die attach region attached. The first semiconductor chip may be a power transistor include. The second semiconductor chip may comprise a control chip (Or driver IC or driver IC). additional Power transistors and additional electronic elements also be present in the high-performance module.

0254<figref idrefs="S118">18A-1</figref> shows a leadframe structure <figref>402</figref> including a first die attach region <figref>402 (b) -1</figref>, a second Chip mounting region <figref>402 (b) -2</figref> and a third die attach region <figref>402 (b) -3</figref>, The rooms between the various die attach regions <figref>402 (b) -1</figref>. <figref>402 (b) -2</figref>. <figref>402 (b) -3</figref> can by voltage requirements the trainee housing be defined.

0255The Leadframe structure <figref>402</figref> also includes a number of ladders <figref>402 (a)</figref>Which differs from the first, second and third die attach regions <figref>402 (b) -1</figref>. <figref>402 (b) -2</figref>. <figref>402 (b) -3</figref> away extend. In these examples, the conductors extend<figref>402 (a)</figref> away of the first, second and third die attach regions <figref>402 (b) -1</figref>. <figref>402 (b) -2</figref>. <figref>402 (b) -3</figref> in a single direction. In other instances, they may away from the various die attach regions in more extend than one direction. In this example, the third Chip mounting region <figref>402 (b) -3</figref> a chip paddle for a Driver semiconductor chip correspond, whereas the other die attach regions <figref>402 (b) -1</figref>. <figref>402 (b) -2</figref> to Chip paddle for may correspond power semiconductor chips.

0256<figref idrefs="S118">18A-2</figref> shows the reverse side of the leadframe structure <figref>402</figref>, The leadframe structure <figref>402</figref> includes a first half-etched region <figref>402 (c) -1</figref> and a second half-etched region <figref>402 (c) -2</figref>, In embodiments of the invention can etched Regions by partially etching are formed through the thickness of a leadframe structure. A "half-etched" structure can be refer to a portion of a leadframe structure, which has been formed after about half of the thickness of the leadframe structure is removed.

0257The half-etched Regions <figref>402 (c) -1</figref>. <figref>402 (c) -2</figref> be able formed under Using a Standardätzprozesses. For example, the surfaces which to the half-etched Regions <figref>402 (c) -1</figref>. <figref>402 (c) -2</figref> correspond, before etching with a material such as a photoresist or tape (polyimide) be covered. Then, an etching material (For example, a liquid etchant or a dry etchant) be used to the regions of the leadframe structure <figref>402</figref>. which are not covered by the masking material to be etched. reference Referring to both <figref idrefs="S118">18A-1</figref> as also <figref idrefs="S118">18A-2</figref> can in this example, the first half-etched region <figref>402 (c) -1</figref> and the first die attach region <figref>402 (b) -1</figref> on be part of the same structure. Also in this example, the second half-etched region <figref>402 (c) -2</figref> and the second die attach region <figref>402 (b) -2</figref> also be part of the same structure.

0258<figref idrefs="S118">18B-1</figref> shows the leadframe structure <figref>402</figref>. after a molding process has been executed. After a been molding process performed (eg a Transferausformprozess) is, is a molding <figref>402</figref> the leadframe structure <figref>402</figref> shaped, characterized a preformed substrate <figref>405</figref> ausbildend. In a exemplary Transferausformprozess can surface of the leadframe structure <figref>402</figref>. which are not intended to form material covered with an off to be, be covered with a band (eg, polyimide) to to prevent that during of forming mold material penetrates. After the leadframe structure<figref>402</figref> With Band is covered, a molding material on the leadframe structure <figref>402</figref> are stored. The tape is then removed following, hence the previously covered Portions of the leadframe structure <figref>402</figref> by the molded Molding material free radically. In other embodiments, as previouslydescribed, can preformed substrates are used, without using Ausformwerkzeugen Using the masking tape.

0259As shown, the molding material <figref>404</figref> formed so that outer surfaces of the molding material <figref>404</figref> substantially coplanar with the outer surfaces of first, second and third conductive die attach regions <figref>402 (b) -1</figref>. <figref>402 (b) -2</figref>. <figref>402 (b) -3</figref> are. As <figref idrefs="S118">18B-1</figref> shown, extend ladder <figref>402 (a)</figref> away from a lateral edge of the molding <figref>404</figref>, In other embodiments, can the conductors extending from the conductive die attach regions <figref>402 (b) -1</figref>. <figref>402 (b) -2</figref>. <figref>402 (b) -3</figref> extend, of two or more lateral edges of the molding material <figref>404</figref> away extend.

0260<figref idrefs="S118">18B-2</figref> shows a perspective bottom view the preformed substrate <figref>405</figref>, As shown, the outer surfaces of the first and second half-etched Regions <figref>402 (c) -1</figref>. <figref>402 (c) -2</figref> by the molded material <figref>404</figref> released.

0261The pre-formed integrated leadframe structure according to the embodiments the invention have a lower deflection and a higher strength, when compared with some conventional substrates. As from the following description will be appreciated, consists in embodiments the invention as SIP (System In Package A, Housing System) modules no need for one Extra heat swamp or a substrate such as a direct bonded copper or insulated metal substrate. The thermal properties of Semiconductor chip package can by using leadframe structures with respective thicknesses be achieved. The electrical circuits of the preformed substrate can while the molding operation are defined.

0262As in <figref idrefs="S118">18C</figref> shown, first, second and third semiconductor chips <figref>408 (a)</figref>. <figref>408 (b)</figref>. <figref>408 (c)</figref> at the substrate <figref>405</figref> attached using an adhesive or other suitable material. As in previous embodiments, an adhesive from Epoxidtypus or any other suitable commercially available Adhesive can be used to the semiconductor chips <figref>408 (a)</figref>. <figref>408 (b)</figref>. <figref>408 (c)</figref> at the preformed substrate <figref>405</figref> to fix.

0263As in the embodiments described above can Wire connections (not shown) between the conductors <figref>402 (a)</figref> and the terminals on the upper surfaces the semiconductor chips <figref>408 (a)</figref>. <figref>408 (b)</figref>. <figref>408 (c)</figref> educated are, if desired. Wire connections can also be used to meet the different semiconductor chips together. For example, the semiconductor chip<figref>408 (b)</figref> on his driver IC chip, while the semiconductor chips <figref>408 (a)</figref>. <figref>408 (c)</figref> Power IC chips could be. The driver IC chip may be electrically coupled to the power IC chip via wires can control them about his and. In other embodiments, can other conductive Structures such as conductive Clips can be used instead of wire bonds.

0264As in <figref idrefs="S118">18D</figref> shown, a capsule material <figref>410</figref> about the first, second and third semiconductor chips <figref>408 (a)</figref>. <figref>408 (b)</figref>. <figref>408 (c)</figref> formed, a semiconductor chip package <figref>400</figref> form. The capsule material <figref>410</figref> can be then formed under Using a Standardausformprozesses. In the exemplary semiconductor chip package<figref>400</figref> extend up lines <figref>402 (a)</figref> away from one side of the capsule material <figref>410</figref>,

0265After performing the encapsulation process can trim the formed housing and formed into appropriate dimensions.

0266<figref idrefs="S119">19A</figref> and <figref idrefs="S119">19B</figref> show Views of an SPM (Smart Power Module, smart power module) -Typgehäuses which can be prepared using the same general Process flow, which in terms of <figref>18A</figref>-D has been described.

0267<figref idrefs="S119">19A</figref> shows a perspective view of a frame structure <figref>502</figref>. which as a framework for a substrate <figref>504</figref> is used, which includes a leadframe structure. <figref idrefs="S119">19B</figref> shows a bottom view of the frame structure <figref>502</figref> and the substrate <figref>504</figref>, First and second semiconductor chips<figref>506 (a)</figref>. <figref>506 (b)</figref> are on the substrate <figref>504</figref>, As described above, the substrate is<figref>504</figref> formed using a leadframe structure <figref>504 (a)</figref> and a molding material <figref>504 (b)</figref>, As in the preceding embodiments can Portions of the leadframe structure <figref>504 (a)</figref> be partially etched and the molding material <figref>504 (a)</figref> may have outer surfaces that are substantially coplanar with the outer surfaces of molding material <figref>504 (a)</figref> are.

0268As described above, can embodiments the invention half or partially etched leadframe structures have what predefined chip paddle for power and driver IC semiconductor chips exhibit. The Isolationsbeabstandung between the die attach paddle can controlled by the voltage requirements of the semiconductor chip package will. additionally can be preformed the leadframe structures and leadframe structures can back coated be with tape to form and Materialdurchdringungen during Mold stripping to prevent. Also, the outer surface of the molding material may be in the Substantially coplanar with the outer surfaces of Die attach paddle to be in the pre-formed substrate.

0269As described above, which has pre-formed integrated lead frame substrate a less deflection and a higher overall plate strength than other substrates. additionally there is no need for an extra heat swamp or a substrate such as a directly bonded Copper or insulated metal substrate since the thermal properties the housing can be achieved using leadframe structures with different Thicknesses. Thicker lead-frame structures can be used if better heat conduction required is. In embodiments the invention, a sub-assembly board be formed to an eventual housing dimensions and the final housing can be trimmed and shaped.

0270The Semiconductor chip package, which are described above, thermally highly efficient housing and be able in housings such as LCD (Liquid Crystal Display) TV module housings are used.

V. substrates for high power modules

0271Other embodiments The invention onto preformed substrates for semiconductor chip package, method including for producing the preformed substrates and semiconductor chip package the preformed substrates directed.

0272In one embodiment be a first leadframe structure and a second leadframe structure receive. Then the first and second leadframe structures are secured together using an adhesive layer. Than it will be a molding material to the first leadframe structure, the second Leadframe structure or the adhesive layer applied.

0273<figref idrefs="S120">20A</figref> shows a plan view of a substrate <figref>700</figref> according to a embodiment the invention. <figref idrefs="S120">20B</figref> shows a perspective Top view of the substrate <figref>700</figref>Which in <figref idrefs="S120">20A</figref> is shown. In this example includes the upper surface the substrate <figref>700</figref> four conductive regions <figref>752</figref>. are what separated and delineated by insulating areas <figref>754</figref>, The insulating regions <figref>754</figref> include a molding material, which columns <figref>758</figref> between the conductive areas <figref>752</figref> filled. The conductive areas <figref>752</figref> can as conductive Chip mounting areas are used. The four conductive regions<figref>752</figref> can be part be a single leadframe structure. If the gaps between the four conductive areas <figref>752</figref> are filled with a molding material, the molding material has an outer surface which substantially coplanar with the outer surfaces of conductive areas <figref>752</figref> is. This combination can a preformed Substrate, as described above, form.

0274<figref idrefs="S120">20C</figref> shows a cross-sectional side view the substrate <figref>700</figref>Which in the <figref idrefs="S120">20A</figref>. <figref idrefs="S120">20B</figref> is shown. As shown in<figref idrefs="S120">20C</figref>, Includes the substrate <figref>700</figref> two half-etched Leadframe structures <figref>702</figref>Which face one another. The two, half-etched Leadframe structures <figref>702</figref> can copper, a copper alloy, include or any other suitable conductive material. The two half-etched (Or partially etched) Leadframe structures <figref>702</figref> can thick of two 10-20 mil be formed leadframe structures, each of which partially etched are to a thickness of about 5-10 mils at certain locations. In other embodiments can the leadframe structures <figref>702</figref> Thicknesses of about 20-40 mils have and can half-etched be to thicknesses of about 10-20 mils at certain locations. The leadframe structures<figref>702</figref> have preferably the same thicknesses and configurations. However, this does not in all cases required.

0275Each Leadframe structure <figref>702</figref> can in a preformed substrate to be available. The preformed substrates and their corresponding Leadframe structures <figref>702</figref> are on an adhesive layer <figref>704</figref> laminated and contact them, which between the leadframe structures <figref>702</figref> arranged is. After lamination, a sandwich composite is formed.

0276The adhesive layer <figref>704</figref> may have any suitable shape and can aufwei any suitable thicknesssen. For example, the thickness of the adhesive layer <figref>704</figref> about 1-3 mils in some embodiments be. Also, the adhesive layer<figref>704</figref> in the form of a continuous or a discontinuous layer.

0277The adhesive layer <figref>704</figref> may comprise any suitable material, which the substrates and leadframe structures described above, pre-formed <figref>702</figref> together can bond. For example, the adhesive layer<figref>704</figref> a polymer layer include as a polyimide film (polyimide). In other embodiments, it is possible to to use an FR4 laminate or high-K-adhesive film to any CTE (coefficient of thermal expansion, thermal expansion coefficient) Difference between the adhesive layer <figref>704</figref> and the leadframe structures <figref>702</figref> and to reduce any boundary layer shear stress when the trained, preformed Substrate is particularly large.

0278the Leadframe substrate <figref>702</figref> and the adhesive layer laminate comprising is formed may be symmetrical, in order to reduce potential deflection states. For example, as shown in <figref idrefs="S120">20C</figref>. can the regions <figref>702 (a)</figref>Represented by the above-described partial etching process are formed inwardly on each other in the formed substrate <figref>700</figref> point. The two leadframe substrates<figref>702</figref> can also symmetrically etched Samples and similar have geometry so that it symmetrically in the substrate <figref>700</figref> arranged are.

0279the Sandwich laminate is further molded with a molding material pre- <figref>706</figref>. which at the edges of the leadframe structures <figref>702</figref> educated is. The molding material<figref>706</figref> an Epoxyausformmaterial include or any other suitable type of molding material. A Transferausformprozess or other process can be used, to the molding material <figref>706</figref> around the edges of the leadframe structures <figref>702</figref> and form the corresponding preformed substrates. For example, may arranged the sandwich laminate between two Ausformformen be and the molding material can be formed as shown, using known Ausformprozesse. The molding material<figref>706</figref> reduced the free edge stress at the boundary surfaces of the formed laminate.

0280After the overmolding the sandwich laminate to the molding material <figref>706</figref> can they surfaces of conductive areas <figref>752</figref> be further processed, if desired. For example, can, if the exposed conductive areas <figref>752</figref> at the top of the substrate <figref>724</figref> as conductive Chip mounting areas for Power IC semiconductor chips are used, the exposed surfaces the conductive areas <figref>752</figref> are plated or otherwise coated be a Unterhügelkomposit such as Ni / Pd / Au, or other metallic layers. Such additional layers a solderable Field for soldering of semiconductor chips to the conductive areas <figref>752</figref> form. In other examples, if the exposed surfaces the conductive areas <figref>752</figref> are intended to be isolated, then can the exposed upper surfaces the conductive areas <figref>752</figref> be anodized. Any suitable, known Anodizing process may be used.

0281<figref idrefs="S120">20D</figref> is a bottom perspective view of the substrate <figref>700</figref>That described in the previous figures is.

0282The substrates <figref>700</figref> and <figref>710</figref> may be in a plate form as in MLP-like housings be prepared, then be separated using, for example, a wafer saw, and then used in subsequent arrangements. As in the other Detail will be described below, can such embodiments be constructed using common leadframe structures for flexible module assembly. SIP (Single In Line Package) can also be formed using such embodiments.

0283Other embodiments are possible. In the embodiments described above in the <figref idrefs="S120">20A</figref>-<figref idrefs="S120">20D</figref> are Leadframe structures partially etched and then Ausformprozesse executed to form the preformed substrates. The preformed substrates have leadframe structures with outer surfaces which is substantially coplanar with the outer surfaces of the Molding material is. The preformed substrates are then laminated with an adhesive layer to form a sandwich composite. The resulting sandwich composite is then edge-formed, in order to form a substrate.

0284however is it in other embodiments possible, two partially etched obtain leadframe structures and then the laminating together with an adhesive layer without first form the preformed substrates. Then can the laminated leadframe structures are formed with a molding material, to a substrate to form that the principle same configuration having, as previously described.

0285Although the use of two partially etched leadframe structures has been described in detail, it is to be understood that two or more etched Leadframe structures can be combined to a combination substrate according to a embodiment the invention form.

0286<figref idrefs="S121">20E</figref>-<figref idrefs="S121">20H</figref> illustrate other substrates according to other embodiments the invention.

0287<figref idrefs="S121">20E</figref> shows a plan view of a substrate <figref>710</figref> according to a embodiment the invention. substrate<figref>710</figref> includes a leadframe structure <figref>712</figref> (eg a copper leadframe structure) and a molding <figref>714</figref>. which the joints of the leadframe structure <figref>712</figref> filled. consequently a thick copper leadframe structure are preformed with a molding material, such as a Epoxyausformmaterial to metal boxes in the substrate <figref>712</figref> electrically isolate.

0288<figref idrefs="S121">20F</figref>. <figref idrefs="S121">20G</figref> and <figref idrefs="S121">20H</figref> show corresponding cross-sectional side view, Top view and bottom perspective views of the substrate <figref>710</figref>, As in <figref idrefs="S121">20F</figref> shown, the thickness the molding material <figref>714</figref> substantially equal to the thickness the leadframe structure <figref>712</figref>, The edges of the leadframe structure<figref>712</figref> will also limited by the molding material <figref>714</figref>So that the Molding material, the outer edge of the substrate <figref>710</figref> forms.

0289In embodiments the invention can the substrates described above <figref>700</figref>. <figref>710</figref> independently in Semiconductor chip packages be used. As in other embodiments, semiconductor chips may be on Substrates are mounted. If desired, input and output connections between the mounted semiconductor chip and the substrate and / or external inputs and / or Output sources are formed. The formed body can then are mounted on a circuit board.

0290In other embodiments can However, substrates <figref>700</figref>. <figref>702</figref> of the previously described Type are mounted on frame structures to the Sub strate <figref>700</figref>. <figref>702</figref> with external lines to provide. These embodiments are in the <figref>21</figref> and <figref>22</figref> shown and will be described in further detail in the following.

0291<figref idrefs="S122">21A</figref> shows a frame structure <figref>550</figref> including a frame portion <figref>550 (a)</figref> and a number of conductors <figref>550 (b)</figref>, A central region <figref>550 (c)</figref> a substrate according to a embodiment Record of the invention.

0292any suitable substrate may be in the central region <figref>550 (c)</figref> placed be. For example, the substrates, which in the central region <figref>550 (c)</figref> recorded be, the substrate <figref>710</figref>Which in <figref idrefs="S121">20E</figref> is shown or the substrate <figref>700</figref>. which in <figref idrefs="S120">20C</figref> is shown to be. <figref idrefs="S122">21B</figref> shows a top view of a specific substrate <figref>552</figref>. which in the central region <figref>550 (c)</figref> the frame structure <figref>550</figref> placed can be. <figref idrefs="S122">21C</figref> shows a perspective Bottom view of the substrate <figref>552</figref>Which in <figref idrefs="S122">21B</figref> is shown.

0293As in the <figref idrefs="S122">21D</figref> and <figref idrefs="S122">21E</figref> shown, a number of semiconductor chips <figref>554</figref> on the substrate <figref>552</figref> assembled be before or after the substrate <figref>552</figref> to the frame structure <figref>550</figref> secured is. As described above, may be any suitable conductive adhesive material be used to the semiconductor chips <figref>554</figref> to the substrate <figref>552</figref> to fasten. additionally can the semiconductor chips any of the characteristics previously described exhibit. For example, at least one of the semiconductor chips<figref>554</figref> a Driver IC semiconductor chip includes, during at least one of Semiconductor chips <figref>554</figref> may include a power IC semiconductor chip. After this the semiconductor chips <figref>554</figref> to the substrate <figref>554</figref> secured are, then the following is a semiconductor chip assembly <figref>560</figref> formed.

0294As shown, the substrate may <figref>552</figref>Which semiconductor chips <figref>554</figref> includes, on the conductors <figref>550 (b)</figref> the frame structure <figref>550</figref> secured will. The lower surfaces the Head <figref>550 (b)</figref> can soldered or in any other way to the upper surfaces of the conductive substrate <figref>552</figref> be attached.

0295In an alternative embodiment, the substrate may <figref>552</figref> on the conductors <figref>550 (b)</figref> the frame structure <figref>550</figref> without the semiconductor chips <figref>554</figref> secured will. After the substrate<figref>552</figref> on the conductors <figref>550 (b)</figref> the frame structure <figref>550</figref> secured is, can the semiconductor chips <figref>554</figref> on the substrate <figref>552</figref> assembled will.

0296<figref idrefs="S122">21F</figref> shows a perspective bottom view of the Semiconductor chip system <figref>560</figref>, <figref idrefs="S122">21G</figref> shows a cross-sectional side view of a semiconductor chip assembly <figref>560</figref>,

0297After this the semiconductor chip system <figref>560</figref> is formed, a capsule material <figref>576</figref> about the semiconductor chips <figref>554</figref> be formed. <figref idrefs="S123">22A</figref> shows a cross-sectional side view of the semiconductor chip package <figref>577</figref>, In this example, the semiconductor chip package <figref>577</figref> a single Inreihengehäuse (SIP). <figref idrefs="S123">22B</figref>. <figref idrefs="S123">22C</figref> and <figref idrefs="S123">22D</figref> show perspective top views, top views and top perspective view of the semiconductor package <figref>577</figref>, The resulting housing may be a thermal high-efficiency housing and in a LCD TV module housing be used.

0298It is to be understood that the technology described above used could be, to a dual Inreihengehäuse (DIP, dual in-line package) form as well. To a dual Inreihengehäuse form, would the Frame structure previously described <figref>550</figref> two sets of having conductors which inwardly in direction of the central region <figref>550 (c)</figref> point. Both sets of conductors would are then attached to the substrate (with or without the subsequent mounted semiconductor chips) and then the resulting assembly would encapsulated are as previously described, to form a DIP-type semiconductor die package.

0299The Embodiments described above have a number of advantages over conventional structures. For example, compared with directly bonded copper substrates (DBC) are embodiments of the Invention less costly because DBC substrates using materials of expensive base and require high processing temperatures. Also, in a DBC substrate the thermal mismatch between copper and ceramic in the DBC high interfacial tensions produce and can housing reliability problems produce. additionally can the high process temperatures which are required to DBC substrates form, higher Plate bending produce.

0300Thermal The liner plates are another type of substrate. you use a combination of aluminum (1-1.5 mm), dielectric (50-80 micron) Copper (35-400 micron) and electroless nickel applied (3-5 micron).

0301embodiments of the invention have a variety of advantages over thermal Liner plates. For example, compared to thermal liner plates need embodiments the invention less layers and therefore less costly produce. additionally have thermal liner plates have a higher thermal resistance as embodiments of the invention and can more CTE mismatch problems exhibit. Thermal mismatch can generate high voltage boundary layers and can housing reliability problems entail.

0302Finally, as previously shown embodiments of the invention with a common leadframe structure for flexible Module assembly be constructed.

VI. System comprising in one housing a voltage regulator

0303Lots the above-described embodiments relate to the design and use of preformed substrates in semiconductor chip package. The foregoing semiconductor die package embodiments are directed to specific configurations Power semiconductor chip package addressed. The semiconductor chip package can power supplies Voltage regulators are used and / or. The embodiments which are described below, any of the previously described using preformed substrates or any other suitable Substrate may comprise one or more semiconductor chips are based.

0304There the need for Broadband applications increases, the design requirements are complex microprocessors. This has been followed by that CPU clock frequencies increase and this has in an increase of energy consumption results. in principle voltage regulator are designed in consideration of the following Requirements: (1) the voltage regulator has a high Responsibilität works, at a reduced voltage, and adopts high power level to (eg from a 1.3 V and 70 A output at a 0.8 V and 150 A output); and (2) the voltage regulator has increased efficiency at higher switching frequencies, in order to absorb any potential losses at low levels.

0305Around produce a voltage regulator of a high frequency, and high-efficiency operation are combined, it is desirable each of the individual to improve devices which incorporated into the power MOSFETs and are also the parasitic Inductors the wiring to reduce between the devices. By Integrating a driver IC and high- and low-side power MOSFETs in a single housing , a substantial increase in efficiency can be achieved with significant miniaturization.

0306Conventional housing for synchronous downconverter (Buck-converter) or the like typically have. Three chip paddle, one for each of the driver IC, a high-side MOSFET chip and a low side MOSFET chip. In the conventional case, the high-side MOSFET source connected to a low-side MOSFET drain with bond wires. This creates high parasitic Inductances. additionally is the connection of the driver IC to the high side and low side MOSFET gate -source and drain practiced using bonding wires. the Using individual paddles requires the use of long Bonding wires. Such factors redu adorn the high frequency power efficiency and the thermal properties of conventional casings. have basically Multi-chip paddle housing a lower housing Reliability Level as embodiments the invention.

0307On synchronous buck converter (Buck-converter) may include a driver IC, a high-side power MOSFET and use a low-side power MOSFET. <figref idrefs="S124">23</figref> shows a simplified, schematic diagram a typical synchronous buck converter (Buck-converter). The synchronous buck converter (buck converter) (SBC) <figref>670</figref> includes a high-side metal oxide semiconductor field effect transistor (MOSFET) <figref>672</figref> and a low-side MOSFET <figref>674</figref>, The drain D of low-side MOSFET <figref>674</figref> electrically to the source S of the high-side MOSFET <figref>672</figref> connected. Most commercially produced MOSFETs are vertical devices and packed are such that the external connection points for Gate, the drain and the source at the same geographical level of the device.

0308The Connection between the source S and the drain D of the high and low side MOSFET <figref>672</figref> and <figref>674</figref>, Accordingly, the SBC <figref>670</figref>. preferably have very low inductance so that the SBC <figref>670</figref> at medium to high operating / switching frequencies used. Where MOSFET<figref>672</figref> and <figref>674</figref> as discrete devices are configured, the design of the Circuit interpretation of SBC <figref>670</figref> preferably optimized parasitic Inductors to reduce. Alternatively, the SBC<figref>670</figref> configured be a fully integrated synchronous buck converter (buck converter) in a single converter in a single housing and be configured and arranged to parasitic inductances in the Connection between the source S and the drain D of the high and low side MOSFET <figref>672</figref> and <figref>674</figref>, Accordingly reduce. Such fully integrated devices, however, tend hardly application and / or to be design specific devices, often not compatible with other applications and / or designs are. Furthermore, the paths / conductor of the printed circuit board, which connect the MOSFETs are typically not well suited, at medium to high level currents to conduct.

0309In embodiments the invention, a novel dual common paddle housing (eg a 9 × 5 mm 26-pin dual-sided flat, non-conductive housing) problems of conventional Housings overcome. embodiments the invention can have the following characteristics: <ul><li>• A driver IC, a high-side MOSFET and a low-side MOSFET can share same paddle.</li><li>• The high side MOSFET can be a flip, which attached to the chip paddle , while the low-side MOSFET conventionally a conventional solder die attach material can use.</li><li>• The Source of the high-side MOSFET is thus automatically with the Drain of the low-side MOSFETs on the die attach paddle connected.</li><li>• The Drain the high-side MOSFET can communicate with external pins with a or more metal strips clip bonds or one or more be connected wire bonding.</li><li>• Of the Driver IC can also between the high- and low-side MOSFET be set to lengths of wire to to reduce.</li><li>• Of the Driver IC uses a non-conductive die attach material, to isolate it from the MOSFETs.</li><li>• The housing according to the embodiments the invention have a smaller footprint (for example, 70%) and a smaller pin count (eg, 26), when compared with conventional housings as 8 × 8 QFN packages.</li></ul>

0310On exemplary method according to an embodiment of the invention includes obtaining a substrate having a conductive Chip mounting surface covers and attaching a high side transistor including a high side transistor input to the substrate. The term hochsei Transistor input is coupled to the conductive die attach surface. A low-side transistor including a low side Transistor output is also fixed to the substrate. The low-sided Transistor input is coupled to the conductive die attach surface.

0311<figref idrefs="S125">24A</figref> shows a cross-sectional side view a semiconductor chip package <figref>600</figref> according to a embodiment the invention. The semiconductor chip package<figref>600</figref> Has a low-side transistor <figref>606</figref>, A high-side transistor <figref>602</figref> and a controller chip <figref>604</figref>, the to a substrate <figref>610</figref> are mounted.

0312<figref idrefs="S125">24B</figref> shows a plan view of the semiconductor chip package <figref>600</figref>. which in <figref idrefs="S125">24A</figref> is shown. <figref idrefs="S125">24C</figref> shows a perspective view of the semiconductor chip package <figref>600</figref>. what a <figref idrefs="S125">24A</figref> is shown. Referring both <figref idrefs="S125">24B</figref> as well as <figref idrefs="S125">24C</figref> has the semiconductor chip package <figref>600</figref> a low side transistor chip <figref>606</figref>, A high-side transistor chip <figref>602</figref> and a controller chip <figref>604</figref>, Mounted on a substrate <figref>610</figref>, The high side transistor in the high side transistor chip <figref>602</figref> and the low-side transistor in the low-side transistor chip <figref>606</figref> can power transistors, be as vertical power MOSFETs. Vertical power MOSFET chips are described in further detail above.

0313In This example includes the substrate <figref>610</figref> high side Source lines <figref>610 (c)</figref>. a high-side gate line <figref>610 (h)</figref>, A conductive die attach surface <figref>610 (g)</figref>. low-side source lines <figref>610 (a)</figref> and control lines <figref>610 (b)</figref>, substrate <figref>610</figref> may be a pre-formed substrate, such as described above, a single conductive leadframe structure may be or may be any other suitable structure. The conductive die attach surface<figref>610 (g)</figref> can the part of the surface the substrate <figref>610</figref> occupy or the entire upper surface of the substrate <figref>610</figref>,

0314It can a number of connections to the high side MOSFET die <figref>602</figref> consist. For example, a drain clip <figref>612</figref> with the drain region in the high-side MOSFET chip <figref>602</figref> attached. A number of solder structures<figref>622 (a)</figref> can use are to be electrically and mechanically to the drain region in the high side MOSFET die <figref>602</figref> With the drain clip <figref>612</figref> to couple. One or more drain wires may instead or additionally, to the drain clip <figref>612</figref> are used in this example.

0315As in <figref idrefs="S125">24B</figref> shown, the gate region in the high-side MOSFET chip <figref>602</figref> with a gate line <figref>610 (h)</figref> coupled. A Lotstruktur <figref>622 (b)</figref> , the gate line <figref>610 (h)</figref> With the gate region in the high side MOSFET die <figref>602</figref> couple. The source region in the high side MOSFET die <figref>602</figref> is connected to the conductive die attach surface <figref>610 (g)</figref> coupled. Lot (not shown) can also be used to electrically connect the Source region in the high side MOSFET die <figref>602</figref> With the conductive Chip mounting surface <figref>610 (g)</figref> to couple.

0316It can also a number of compounds with the low side MOSFET die <figref>606</figref> consist. For example, can Source wires <figref>616 (a)</figref> the Source region in the low-side MOSFET chip <figref>606</figref> with the source lines <figref>610 (a)</figref> of Substrate coupling. As an alternative, one or more source clips can be used instead or additionally, to the source wires <figref>616 (a)</figref> used will. The source wires<figref>616 (a)</figref> , copper, include gold or any other suitable material. The gate region the low-side MOSFET chip is connected to the control chip <figref>604</figref> using a wire <figref>616 (c)</figref> coupled.

0317Of the Drain region of the low-side MOSFET chip <figref>606</figref> is with the conductive Chip mounting surface <figref>610 (g)</figref> of substrate <figref>610</figref> coupled by a conductive die attach material as solder or the like. Lead-based or non-lead-based solder can be used to the drain region of the low side MOSFET die <figref>606</figref> at the chip mounting surface <figref>610 (g)</figref> to fasten.

0318Of the control chip <figref>604</figref> is also applicable to the conductive die attach surface <figref>610 (g)</figref> of substrate <figref>610</figref> mounted, but can be electrically separated from the substrate <figref>610</figref> isolated be. A number of bonding wires<figref>616 (e)</figref> can terminals in the control chip <figref>604</figref> with control lines <figref>610 (b)</figref> couple. A wire <figref>602 (d)</figref> may also have a connection to the controller chip <figref>604</figref> With the conductive Chip mounting surface <figref>610 (g)</figref> couple. In some cases could conductive Clips instead of bonding wires be used.

0319<figref idrefs="S126">24D</figref> shows a bottom view of the substrate <figref>610</figref>, As in <figref idrefs="S126">24D</figref> shown, the bottom the substrate <figref>610</figref> a half-etched portion <figref>610 (i)</figref> exhibit.

0320<figref idrefs="S126">24E</figref> shows a perspective view of the semiconductor chip package <figref>600</figref>,

0321<figref idrefs="S127">25</figref> shows a cross-sectional side view of a substrate <figref>610</figref> according to a Alternatively, the invention. substrate<figref>610</figref> includes a recess <figref>690</figref>. which with a molding material <figref>692</figref> is filled. A control chip <figref>604</figref> is on the top of the molding material <figref>692</figref>, The molding material <figref>692</figref> isolates the controller chip <figref>604</figref> electric of the conductive Portions on the substrate <figref>610</figref>, As in previous embodiments are a low-side MOSFET chip <figref>606</figref> and a high-side MOSFET chip <figref>602</figref> on the substrate <figref>610</figref>,

0322The deepening <figref>690</figref> may be formed by etching, milling or the like.. The molding material <figref>692</figref> can be deposited in the recess and then be subsequently cured or be solidified.

0323The in <figref idrefs="S127">25</figref> Embodiment shown has a plurality of advantages. For example, the molding material isolated<figref>692</figref> electric the controller chip <figref>604</figref> of the high- and low-side crisps <figref>602</figref>. <figref>606</figref> without increasing the height of the formed semiconductor die package.

0324The Embodiments, which have been described above, have a variety of advantages. Such benefits include a smaller footprint, and better thermal and electrical properties. Such embodiments can in a variety of housing configurations be used, including single and Inreihengehäuse dual Inreihengehäuse.

0325Any the above-described embodiments and / or any features thereof may with another embodiment / other embodiments and / or other feature / other features are combined, without departing from the scope of the invention. For example, although systems in modules from the housing type have not been described specifically in reference to the embodiments which in the <figref>1</figref>-<figref>2</figref> shown are, is to be understood that such embodiments for systems in modules from the housing type may be used without detracting from the spirit and scope of the invention departing.

0326The foregoing description is illustrative and not restrictive. Lots Variations of the invention will become apparent to those skilled in Review of the disclosure. The scope of the invention should, therefore not determined with reference to the above description has to be, but instead of referring to the appended claims be determined with the involvement of the full screen or equivalents.

0327Any Referring to positions such as "top", "bottom", "upper", "lower", etc. refer used to the figures and, for convenience of illustration and not as a limitation intended. They are not intended to absolute positions to refer.

0328The Semiconductor chip package, which have been previously described, can be used in any suitable electrical Apparatus used. For example, they in personal computers, servers, mobile phones, household appliances, etc. be used.

0329A intends citation of "a", "an" or "the", "the", "the" is one of my "or more "unless not specifically indicated to the contrary.

0330all Patents, patent applications, publications and descriptions, which have been described hereinbefore are incorporated herein by reference in their entirety for all purposes. Nothing is given as prior art.

SUMMARY

0331be semiconductor chip package disclosed. An exemplary semiconductor chip package includes a preformed Substrate. The preformed substrate may attached thereto having semiconductor chip and an encapsulant can the be arranged semiconductor chip.