Field effect transistor

The present invention relates to a field effect transistor with reduced capacitive coupling between the drain and substrate and a semiconductor chip with this field effect transistor.

For many large-signal applications LDMOS transistors or LDMOS FETs are (LDMOS = lateral diffused metal oxide semiconductor = laterally diffused metal oxide field) used for example for power amplifiers for base stations, handsets, mobile phones etc. The output capacity of an LDMOS field-effect transistor of the drain voltage or depending on the voltage between the drain and the drain region on the one hand and the often connected to a reference potential substrate on the other.

<figref>3</figref> is a schematic representation of a vertical section through a conventional LDMOS field effect transistor. A p-doped base substrate<figref>10</figref> has a first, lower surface <figref>12</figref> and a second, upper surface <figref>14</figref> on. On the lower surface<figref>12</figref> , the base substrate <figref>10</figref> a back contact in the form of a metal coating <figref>16</figref> on. On the upper surface<figref>14</figref> the base substrate <figref>10</figref> is by an epitaxial method, for example by CVD epitaxy (CVD = chemical vapor deposition = chemical vapor deposition), a p-doped epitaxial layer <figref>20</figref> generated. The base substrate<figref>10</figref> and the epitaxial layer <figref>20</figref> together form a device substrate <figref>30</figref> with a surface <figref>32</figref>, The same one of the base substrate <figref>10</figref> surface facing away from the epitaxial layer <figref>20</figref> is.

In or on the epitaxial layer <figref>20</figref> the field effect transistor and its semiconductor functional elements are arranged. A source region<figref>40</figref> is characterized by an n⁺-doped region at or just below the surface <figref>32</figref> educated. At one of the surface<figref>32</figref> opposite side of the source region <figref>40</figref> is followed by a p-doped Enhance area <figref>42</figref> at. At one of the source region<figref>40</figref> and the surface <figref>32</figref> Rear facing the Enhance area <figref>42</figref> is followed by a p-doped body region <figref>44</figref> to which, however, unlike the Enhance area <figref>42</figref> at least in one direction has a greater extent than the source region <figref>40</figref> having and thus laterally or laterally to the source region <figref>40</figref> and the Enhance area <figref>42</figref> as well as to the surface <figref>32</figref> adjacent.

Laterally from the source region <figref>40</figref> spaced but laterally to the body region <figref>44</figref> adjacent, at the surface <figref>32</figref> arranged a drain region in this embodiment of three drain subregions <figref>50</figref>. <figref>52</figref>. <figref>54</figref> is formed with different levels of doping concentration. A first drain subregion<figref>50</figref>That the greatest distance to the source region <figref>40</figref> which is n⁺-doped. Toward the source region<figref>40</figref> joins the first drain subregion <figref>50</figref> a second drain subregion <figref>52</figref> , whose doping concentration is lower than that of the first drain portion <figref>50</figref> is. On the second drain subregion<figref>52</figref> closes a third drain subregion <figref>54</figref> in which the body region <figref>44</figref> and adjacent a lower doping concentration than the second drain portion <figref>52</figref>, The second drain subregion<figref>52</figref> and the third drain subregion <figref>54</figref> are collectively referred to as Resurf area (Resurf = reduced surface field = reduced surface field).

At one of the drain region <figref>50</figref>. <figref>52</figref>. <figref>54</figref> Rear facing the source region <figref>40</figref> is followed by a p⁺doped region <figref>60</figref> on the surface <figref>32</figref> at. Between the p⁺doped region <figref>60</figref> and the base substrate <figref>10</figref> or the upper surface thereof <figref>14</figref> extends a p-doped sinker <figref>62</figref>, Of the electric conductivity between the p⁺doped region <figref>60</figref> and the base substrate <figref>10</figref> elevated.

At one of the source region <figref>40</figref>, The Enhance area <figref>42</figref> and the body region <figref>44</figref> opposite side of the p⁺doped region <figref>60</figref> and Sinkers <figref>62</figref> close laterally more structures <figref>40 '</figref>. <figref>42 '</figref>. <figref>44 '</figref> on, which are for example, a further source region, a further Enhance area and another body region or to the form of an open or closed bow or frame around the p⁺doped region <figref>60</figref> and Sinker <figref>62</figref> laterally guided around the source region <figref>40</figref>, Enhance area <figref>42</figref> and body region <figref>44</figref> concerns.

On the epitaxial layer <figref>20</figref> are embedded in a dielectric layer <figref>66</figref> electrically conductive structures made of metals or other electrical conductors arranged. A source metallization<figref>70</figref> adjacent to the source region <figref>40</figref> and the p⁺doped region <figref>60</figref> and contacted the same or connected to the same electrically conductive. Through-hole conductors<figref>72</figref> connect the source metallization <figref>70</figref> electrically conductive with laterally overlapping or partially vertically above the source metallization <figref>70</figref> arranged shielding conductors <figref>74</figref>Which are part of an overlying metallization.

A drain metallization <figref>80</figref> bordering with the highest award the first drain subregion <figref>50</figref> and is connected with this electrically conductive.

About the portion of the body region <figref>44</figref>Which on the surface <figref>32</figref> adjacent, a gate <figref>90</figref> from a doped polysilicon layer <figref>92</figref> and a silicide layer <figref>94</figref> arranged. The gate<figref>90</figref> or polysilicon layer <figref>92</figref> the same is of the surface <figref>32</figref> or from which the gate <figref>90</figref> substantially opposite body region <figref>44</figref> by a thin insulating layer <figref>96</figref> (Gate oxide) spatially separated and electrically insulated.

When a positive voltage to the gate <figref>90</figref> formed in the said gate <figref>90</figref> opposite body region <figref>44</figref> near the surface <figref>32</figref> a thin conductive layer, the so-called channel from. The region in which the channel is formed upon application of the positive voltage is hereinafter referred to as the channel region<figref>98</figref> designated.

Between the drain region <figref>50</figref>. <figref>52</figref>. <figref>54</figref> one hand, and adjacent areas of the epitaxial layer <figref>20</figref> on the other hand there is a pn junction. At this, a space charge zone and a depletion zone is formed, whose thickness or its extension perpendicular to the pn junction of the drain level of the applied voltage or the potential difference between the drain region<figref>50</figref>. <figref>52</figref>. <figref>54</figref> on the one hand and the substrate <figref>10</figref> but dependent. The blocked pn junction between the drain region<figref>50</figref>. <figref>52</figref>. <figref>54</figref> and the substrate <figref>10</figref> simultaneously forming a capacitor, the capacitance of the thickness of the said space charge zone and thus depends on the drain voltage.

As already mentioned above, makes it difficult to drain voltage dependent on the output capacity or capacitance between the drain region <figref>50</figref>. <figref>52</figref>. <figref>54</figref> and the substrate <figref>10</figref> Adjustment of a circuit which is connected to the field effect transistor, to the same. So far this is dependent on the drain voltage output capacitance of the field effect transistor had to be accepted.

The <patcit><text>DE 100 52 170 C2</text></patcit> relates to a semiconductor device having a substrate, in which a MOS transistor is formed. This includes a drain region, two source regions and two gate electrodes. Between the drain region and the channel regions formed under the source and gate regions of a drift region is formed. Further, an n-type epitaxial layer is provided in which a plurality of grooves are formed which are filled with a p-conductive material.

The <patcit><text>DE 101 22 364 A1</text></patcit> and the <patcit><text>DE 100 12 610 A1</text></patcit> describe vertical transistor structures in which a drain region is formed on a back surface of a substrate, laterally or vertically extending semiconductor regions alternating conductivity type between a surface of the substrate in which the source region is formed, and the drain region are arranged.

In the article "High voltage thin layer devices" by JA Appels eg in IEEE, International electronic device meeting 1979, pages 238-241 a Resurf diode is described.

The object of the present invention is to provide a field effect transistor with an independent of the drain voltage capacitance between a drain region and a substrate.

This object is achieved by a field effect transistor according to claim 1 or claim. 2

According to a preferred embodiment, the present invention provides a semiconductor chip with the field effect transistor according to the invention.

The present invention is based on the idea of ​​creating below the drain region a region which causes a complete depletion within a possible thick, but independent of the drain voltage layer due to its three-dimensional structure even at low drain voltages, so that a higher drain voltages no or no substantial varying the thickness of the depletion region occurs more. This is achieved for example in that the area has one or more columns or plates or is in the form of one or more columns or bars with a doping whose charge carrier type is equal to the drain region and is opposite to that of the substrate. The thickness of the columns or fins and the dimensions between these remaining portions of the oppositely doped substrate are (small) chosen so that even at the lowest possible drain voltage space charge zones are created that meet the column or fins and the spaces between them completely ,

A significant advantage of the present invention is that starting from a predetermined minimum drain voltage at which the space-charge zones, as mentioned, both the columns or disks of the region and the substrate material in the vicinity thereof completely satisfy, the spatial extent and particularly the thickness of this depletion region substantially depends only on the geometry of these pillars or fins and not on the drain voltage. The capacitance between the drain region and the substrate is then largely independent of the drain voltage. This allows a simple, inexpensive and efficient adjustment of a high frequency circuit in which the field effect transistor according to the invention is used, the field effect transistor.

Preferred embodiments of the present invention are defined in the dependent claims.

Hereinafter, preferred embodiments of the present invention with reference to the accompanying figures in more detail. Shown are:

<figref>1</figref> a schematic sectional view of a field effect transistor according to a first embodiment of the present invention;

<figref>2</figref> a schematic sectional view of a field effect transistor according to a second embodiment of the present invention; and

<figref>3</figref> is a schematic sectional view of a conventional field effect transistor.

<figref>1</figref> is a schematic representation of a vertical section through a field effect transistor according to a first preferred embodiment of the present invention. This field effect transistor differs from the above with reference to<figref>3</figref> conventional field effect transistor described in that below the drain region <figref>50</figref>. <figref>52</figref>. <figref>54</figref> and in particular under the two highly doped drain subregions <figref>50</figref>. <figref>52</figref> a range of a plurality of columns <figref>102</figref> is arranged, which as the drain region <figref>50</figref>. <figref>52</figref>. <figref>54</figref> is n-doped. The n-doped columns<figref>102</figref> are perpendicular to the surface <figref>32</figref> the epitaxial layer <figref>20</figref> arranged and are directly adjacent to the drain region <figref>50</figref>. <figref>52</figref>. <figref>54</figref> , so that they are electrically conductively connected to the same. The columns<figref>10 2</figref> have a small diameter as possible and as small a mutual or lateral distance or narrowest possible gaps <figref>104</figref>, This causes that during the application of a drain voltage and hence when a voltage between the n-doped columns<figref>102</figref> and the surrounding p-type material of the epitaxial layer <figref>20</figref> in the reverse direction of the boundary surfaces between the columns <figref>102</figref> and the surrounding material of the epitaxial layer outbound space-charge zones as soon as possible and at the lowest possible voltage, the drain columns <figref>102</figref> and spaces <figref>104</figref> between the columns <figref>102</figref> completely fill.

The length of the column <figref>102</figref> is preferably selected so that it has a small vertical distance from the top surface <figref>14</figref> the base substrate <figref>10</figref> have, of approximately the same size as the distance between the columns <figref>102</figref> and the diameter of the column <figref>102</figref>, When creating the minimum drain voltage described above so that the epitaxial layer<figref>20</figref> among the most highly doped drain subregions <figref>50</figref>. <figref>52</figref> completely depleted. When the drain voltage is increased starting from the minimum drain voltage further, the depletion zone grows only minimally in the vertical direction. The dependent of the drain voltage of the depletion zone growth is also severely limited if the base substrate<figref>10</figref> a high doping concentration, or at least a substantially higher doping concentration than the epitaxial layer <figref>20</figref> having. In the in<figref>1</figref> Embodiment of the field effect transistor according to the invention illustrated, the capacitance between the drain region <figref>50</figref>. <figref>52</figref>. <figref>54</figref> and the substrate <figref>10</figref> thus approximate the capacitance of a corresponding capacitor with a plate spacing which is largely independent of the drain voltage constant and the thickness of the epitaxial layer <figref>20</figref> minus the thickness or the vertical dimension of the drain region <figref>50</figref>. <figref>52</figref>. <figref>54</figref> equivalent. The capacitance between the drain region<figref>50</figref>. <figref>52</figref>. <figref>54</figref> and the substrate <figref>10</figref> is thus small and approximately constant.

The present invention thus brings about a leveling of output capacity in the area of ​​the barrier layer and particularly in the barrier layer is formed between the drain and substrate.

According to a variant of the first embodiment of the present invention, instead of the columns <figref>102</figref> Fins or plates below the drain region <figref>50</figref>. <figref>52</figref>. <figref>54</figref> arranged adjacent to the same and in the vertical direction approximately up to the upper surface <figref>14</figref> the base substrate <figref>10</figref> extend. The<figref>1</figref> can also be interpreted so that the visible structures <figref>102</figref> Cross-sectional areas of the fins or plates. Instead of several slats or plates is alternatively only one fin may be provided which laterally has the shape of a spiral.

<figref>2</figref> is a schematic representation of a vertical section through a field effect transistor according to a second embodiment of the present invention. The second embodiment differs from the reference to the<figref>1</figref> illustrated first embodiment in that instead of the vertical pillars or fins or plates <figref>102</figref> horizontal and parallel to the surface <figref>32</figref> the epitaxial layer <figref>20</figref> arranged n-type columns or rods or discs or lamellae <figref>106</figref> are provided, which, rod via a further n-doped, but vertically aligned, column, plate-like or lamella-shaped connecting portion <figref>108</figref> to the drain region <figref>50</figref>. <figref>52</figref>. <figref>54</figref> are geometrically and electrically conductive manner. The rods or plates<figref>106</figref> the second embodiment as well as gaps <figref>110</figref> therebetween are preferably similar or identical dimensions as the pillars or lamellae <figref>102</figref> of the first embodiment and have the same function.

The embodiments from the <figref>1</figref> and <figref>2</figref> It is common that the area formed by the columns, bars, slats or plates <figref>102</figref>. <figref>106</figref>. <figref>108</figref> at least along a section plane having a comb-shaped cross-section. In the vertical alignment of the pillars or fins<figref>102</figref>As reference the the <figref>1</figref> comprises illustrated first embodiment, is preferably a plurality or a multiplicity of columns or slats <figref>102</figref> or a single lateral helical fin <figref>102</figref> provided so that the depletion zone which is produced has the largest possible lateral extent, which is preferably approximately the lateral extent of at least the more heavily doped drain subregions <figref>50</figref>. <figref>52</figref> equivalent. In the case of horizontally aligned structures of the reference to the<figref>2</figref> second embodiment shown is a plate <figref>106</figref> sufficiently with corresponding lateral extent in order to realize the above-described advantages of the present invention. A plurality of parallel plates<figref>106</figref> but is advantageous because it results in a correspondingly thicker depletion zone. A single horizontal or to the surface<figref>32</figref> parallel plate <figref>106</figref> does not comprise a comb-shaped cross-section. Both described embodiments and their variants is however common that they generate an alternating arrangement of regions or alternating regions with opposite conductivity types.

A field effect transistor according to the present invention is preferably produced by a process whose steps partially correspond to a conventional manufacturing method. Specifically, first, a base substrate such as a monocrystalline silicon substrate is produced by, for example, a corresponding disc cut from a pulled silicon single crystal, and their surfaces are polished. Onto the upper surface<figref>14</figref> the base substrate <figref>10</figref> the epitaxial layer <figref>20</figref> grew up. The vertically oriented columns or slats<figref>102</figref> of the first embodiment are preferably produced by the finished epitaxial <figref>20</figref> Holes or trenches are etched which are filled with silicon whose impurity having a conductivity type of the conductivity type of the substrate <figref>10</figref> and in particular the epitaxial layer <figref>20</figref> opposite. Alternatively, first only a part of the epitaxial layer<figref>20</figref> produced that the scope of future columns or lamellae <figref>102</figref> includes. After generating the pillars or fins<figref>102</figref> is a further partial layer of the epitaxial layer <figref>20</figref> applied in the later of the drain region <figref>50</figref>. <figref>52</figref>. <figref>54</figref> will be arranged.

Alternatively, the columns or slats are <figref>102</figref> after the generation of the epitaxial layer <figref>20</figref> produced by implantation of dopants through a corresponding mask.

Alternatively, the epitaxial layer <figref>20</figref> produced in several layers, each of which portions of the columns or lamellae <figref>102</figref> are produced by implantation, and these sections are aligned laterally and along the columns or lamellae <figref>102</figref> form.

Horizontal structures, as described in the reference to the <figref>2</figref> second exemplary embodiment represented present, are preferably produced by the epitaxial layer <figref>20</figref> is applied in several layers, the horizontal rods or bars or plates <figref>106</figref> by implantation of dopants or by etching corresponding trenches or recesses and filling the same are produced with doped silicon.

The generation of the drain region <figref>50</figref>. <figref>52</figref>. <figref>54</figref>, The source region <figref>40</figref>, The Enhance area <figref>42</figref>, The body region <figref>44</figref>, The p⁺doped region <figref>60</figref> and Sinkers <figref>62</figref> also take place preferably as the production of conductor structures <figref>70</figref>. <figref>72</figref>. <figref>74</figref>. <figref>80</figref> and the gate <figref>90</figref> similar to conventional field effect transistors.

The present invention has for an LDMOS field effect transistor having n-doped source and drain regions <figref>40</figref>. <figref>50</figref>. <figref>52</figref>. <figref>54</figref> and a p-doped body region <figref>44</figref> in a p-doped epitaxial layer <figref>20</figref> on a p-doped base substrate <figref>10</figref> described. However, the present invention is suitable for all types of field effect transistors, in particular lateral field-effect transistors are realized in all types of semiconductor substrates with and without epitaxial layer.