DE102015114707B4

Semiconductor device and method for fabricating the same

Abstract

A method of manufacturing a semiconductor comprising: Forming a first III-V interconnect layer (112) on a substrate (110); Forming a second III-V compound layer (114) on the first III-V compound layer (112), a material of the first III-V compound layer (112) being different from that of the second III-V compound layer (114) ; Forming a dielectric layer (122) on the second III-V interconnect layer (114); Forming an ohmic contact (136) that penetrates the dielectric layer (122) and connects to the second III-V interconnect layer (114); Forming an ARC layer (132) on the ohmic contact (136); Forming an etch stop layer (134) on the ARC layer (132); Forming a gate field plate (140) on the dielectric layer (122) using a deposition and etching process; and Forming a further dielectric layer (150) on the dielectric layer (122) using an ALD process, the further dielectric layer (150) also covering the gate field plate (140) and the ohmic contact (136).

DE102015114707B4, drawing sheet 1 — Sheet 1 of 19

Term

8.9 yearsleft in the term

Expires 3 September 2035.

Parties

Owner: TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
Inventors: Jheng-Sheng You, Hsinchu, Taiwan Province of China
Hsin-Chih Lin, Hsinchu, Taiwan Province of China
Shen-Ping Wang, Hsinchu, Taiwan Province of China
Kun-Ming Huang, Hsinchu, Taiwan Province of China
and 3 more inventorsShow fewer
Chien-Li Kuo, Hsinchu, Taiwan Province of China
Po-Tao Chu, Hsinchu, Taiwan Province of China
Lieh-Chuan Chen, Hsinchu, Taiwan Province of China

Examination

Agent: BOEHMERT & BOEHMERT Anwaltspartnerschaft mbB - Patentanwälte Rechtsanwälte
Filing to grant: 4.8 years

Reach

Cites: 8 earlier patents⁠
Family: 20 members in 5 offices⁠US12CN2DE2KR2TW2

Classification

CPC: H10D30/015H10D30/475H10D64/111H10D64/256H10D64/257H10D62/8503+3 more
IPC: H01L21 338H01L29 778H01L29 812H01L29 201H10D30 47H10D30 01+7 more

10 claims: 5 independent, 5 dependent

1
Verfahren zur Herstellung eines Halbleiters, umfassend:Bilden einer ersten III-V-Verbindungsschicht (112) auf einem Substrat (110);Bilden einer zweiten III-V-Verbindungsschicht (114) auf der ersten III-V-Verbindungsschicht (112), wobei sich ein Material der ersten III-V-Verbindungsschicht (112) von dem der zweiten III-V-Verbindungsschicht (114) unterscheidet;Bilden einer Dielektrikumschicht (122) auf der zweiten III-V-Verbindungsschicht (114);Bilden eines ohmschen Kontaktes (136), der die Dielektrikumschicht (122) durchdringt und eine Verbindung zu der zweiten III-V-Verbindungsschicht (114) herstellt;Bilden einer ARC-Schicht (132) auf dem ohmschen Kontakt (136);Bilden einer Ätzstoppschicht (134) auf der ARC-Schicht (132);Bilden einer Gatefeldplatte (140) auf der Dielektrikumschicht (122) unter Verwendung eines Abscheidungs- und Ätzprozesses;und Bilden einer weiteren Dielektrikumschicht (150) auf der Dielektrikumschicht (122) durch einen ALD-Prozess, wobei die weitere Dielektrikumschicht (150) auch die Gatefeldplatte (140) und den ohmschen Kontakt (136) abdeckt.
5
Verfahren nach einem der vorherigen Ansprüche, wobei die Ätzstoppschicht (134) aus Oxid oder Siliziumnitrid hergestellt ist;und/oder die ARC-Schicht (132) aus TiN hergestellt ist;und/oder die Gatefeldplatte aus TiN, Ti, Al, AlCu oder Cu hergestellt ist.
7
Verfahren nach einem der vorherigen Ansprüche, weiterhin umfassend Bilden einer dotierten GaN-Region (120) zwischen dem Gatemetallstapel (160) und der AlGaN-Schicht (114).
8
Verfahren nach einem der vorherigen Ansprüche, wobei eine 2DEG-Region (116) an dem Übergang der AlGaN-Schicht (114) und der GaN-Schicht (112) gebildet wird.
9
Verfahren nach einem der vorherigen Ansprüche, wobei der ohmsche Kontakt (136) einen Sourcekontakt umfasst, wobei die Gatefeldplatte (140) mit dem Sourcekontakt elektrisch verbunden wird.

Independent claims5

45 paragraphs in 2 sections, as filed

GENERAL PRIOR ART

0001The integrated circuit (IC) industry has grown exponentially. Technological advances in IC materials and design have spawned generations of ICs, with each generation having smaller and more complex circuits than the previous generation. In semiconductor technology, gallium nitride (GaN) as the third generation of semiconductor material with a large band gap has a large band gap, a high breakdown voltage, and the two-dimensional electron gas has a high saturation electron velocity at high concentrations. Gallium nitride is used to form various integrated circuits such as high performance field effect transistors, metal insulator semiconductor field effect transistors (MISFETs), high frequency transistors and high electron mobility transistors (HEMTs).

0002<de-docref CY="US" DNUM="8633094" KI="B2">US 8 633 094 B2</de-docref> describes a manufacturing method of a multilayer structure of a semiconductor device, wherein a nitrogen plasma is generated and used to form a nitride layer. A subsequent treatment with a nitrogen-oxygen plasma is an oxynitride layer which comprises a gate dielectric layer.

0003<de-docref CY="US" DNUM="20140203289" KI="A1">US 2014/0 203 289 A1</de-docref> describes a HEMT device with a multilayer structure which has a two-dimensional electron gas layer, an etching stop layer, a P-semiconductor layer and a gate electrode.

0004describes a semiconductor device which has two AlGaN layers of different types, a gate electrode, a source electrode and a drain electrode.

0005<de-docref CY="US" DNUM="20140203289" KI="A1">US 2014/0 203 289 A1</de-docref> describes a HEMT device which has a stack structure with a silicon substrate, an AlN buffer layer, a thermal expansion layer made of AlGaN, a channel layer made of GaN, a mobility-promoting layer made of AlGaN and a resistance-reducing layer made of AlGaN. A gate and source and drain regions are formed on this stack structure.

Figure list

0006Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that various features are not drawn to scale in accordance with industry practice. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.<ul list-style="none" id="ul_0001"><li id="ul_0001_0001"><figref>1</figref> to <figref>16</figref> 14 are sectional views of different steps of a method of manufacturing a semiconductor device in accordance with some embodiments of the disclosure.</li><li id="ul_0001_0002"><figref>17</figref> and <figref>18</figref> 10 are schematic top views of the semiconductor device according to some embodiments of the disclosure.</li></ul>

DETAILED DESCRIPTION

0007The following disclosure provides many different embodiments or examples to implement different features of the article provided. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit them. For example, the formation of a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional functions may be formed between the first and second features so that the first and second features cannot be in direct contact. In addition, the present disclosure may repeat reference numbers and / or symbols in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various described embodiments and / or configurations.

0008Furthermore, spatially relative terms such as "below", "below", "lower", "above", "upper" and the like may be used to facilitate the discussion herein of the relationship of an element or feature to one or other elements or to describe features as illustrated in the figures. The spatially relative terms are intended to encompass, in addition to the orientation shown in the figures, various orientations of the device when using or operating the device. The device can be otherwise oriented (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein can be interpreted accordingly.

0009<figref>1</figref> to <figref>16</figref> 14 are sectional views of different steps of a method of manufacturing a semiconductor device in accordance with some embodiments of the disclosure. In<figref>1</figref> comprises a semiconductor structure 100 a substrate 110, a first III-V connection layer 112that on the substrate 110 is formed, and a second III-V compound layer 114that on the first layer 112 is formed.

0010The substrate 110 is a semiconductor substrate. In some embodiments, the semiconductor substrate is made of silicon, for example; a compound semiconductor such as silicon carbide, indium arsenide or indium phosphide; or an alloy semiconductor such as silicon germanium carbide, gallium arsenic phosphide or gallium indium phosphide. The substrate110 can also comprise different doped regions, dielectric features or multi-stage coupling structures in the semiconductor substrate.

0011The first III-V connection layer 112 and the second III-V compound layer 114 are compounds made from the III-V groups in the Periodic Table of the Elements. However, the first III-V link layer is different112 and the second III-V compound layer 114 of each other in the composition. In some embodiments of the semiconductor structure110 comprises the first III-V connection layer 112 a gallium nitride (GaN) layer (also called the GaN layer 112 referred to as). The GaN layer112 can be epitaxially grown by a number of processes including, but not limited to, organometallic chemical vapor deposition (MOCVD), also known as organometallic gas phase epitaxy (MOVPE), using suitable nitrogen and gallium containing precursors. Exemplary gallium-containing precursors are, for example, trimethyl gallium (TMG), triethyl gallium (TEG) or other suitable chemical precursors. Exemplary nitrogen precursors include, but are not limited to, phenylhydrazine, dimethylhydrazine, tertiary butylamine, ammonia, or other suitable chemical precursors.

0012In some embodiments, the second III-V interconnect layer comprises 114 an aluminum gallium nitride (AlGaN) layer (also called the AlGaN layer 114 referred to as). The AlGaN layer114 can be epitaxially grown by MOCVD using appropriate aluminum, nitrogen and gallium precursors. The aluminum precursor includes trimethyl aluminum (TMA), triethyl aluminum (TEE) or suitable chemical precursors. Exemplary gallium-containing precursors are trimethyl gallium (TMG), triethyl gallium (TEG) or other suitable chemical precursors. Exemplary nitrogen precursors include, but are not limited to, phenylhydrazine, dimethylhydrazine, tertiary butylamine, ammonia, or other suitable chemical precursors. The AlGaN layer114 can also be called a barrier layer. The GaN layer112 and the AlGaN layer 114 contact each other directly. A transition layer, usually between the substrate110 and the GaN layer 112 is present is not shown.

0013Different materials on the semiconductor substrate 110 are formed, cause the layers to have different band gaps. A bandgap discontinuity between the GaN layer112 and the AlGaN layer 114 together with the piezo effect creates a very thin layer 116 of highly mobile conduction electrons in the GaN layer 112. The thin layer116 contributes to a conductive two-dimensional electron gas (2DEG) region near the junction of the two layers. The thin layer116 (which is also called the 2DEG region 116 allows charge to flow through the device. This barrier layer like the AlGaN layer114 can be doped or undoped. Because the 2DEG region under the gate exists at zero gate bias, most nitride devices are self-conducting or depletion devices.

0014The semiconductor structure further comprises a third III-V connection layer 118that are on the AlGaN layer 114 is arranged. In some embodiments, the third III-V interconnect layer118 a doped III-V compound layer, such as a p-doped GaN layer (also called the doped GaN layer 118 referred to as). The doped GaN layer118 can be epitaxially grown by MOCVD using suitable aluminum, nitrogen and gallium precursors. The aluminum precursor includes trimethyl aluminum (TMA), triethyl aluminum (TEE) or suitable chemical precursors. Exemplary gallium-containing precursors are trimethyl gallium (TMG), triethyl gallium (TEG) or other suitable chemical precursors. Exemplary nitrogen precursors include, but are not limited to, phenylhydrazine, dimethylhydrazine, tertiary butylamine, ammonia, or other suitable chemical precursors. The AlGaN layer114 can also be called a barrier layer.

0015With reference to <figref>2</figref> the doped GaN layer is patterned around a doped GaN region 120 on the AlGaN layer 114 define. In some embodiments, a mask layer, such as a photoresist layer, is formed on the doped GaN layer and the mask layer is patterned by a lithography process to form multiple features and multiple openings through the features on the doped GaN layer118 are defined. The structure of the mask layer is formed in accordance with a predetermined IC structure. The lithography process can include photoresist coating, exposure, post exposure curing, and development. An etch process is then performed around the doped GaN region120 define.

0016With reference to <figref>3</figref> is a dielectric layer 122 on the doped GaN region 120 and on the AlGaN layer 114 educated. The dielectric layer122 may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, low dielectric constant dielectric, or a combination thereof. The dielectric layer122 can be formed by a deposition process such as an ALD process, a CVD process or a PVD process. The thickness of the dielectric layer122 ranges from about 300 angstroms to about 3000 angstroms.

0017The dielectric layer 122 is further structured to include several of ohmic contact regions 124 in the dielectric layer 122 define. In some embodiments, the dielectric layer122 selectively etched and cleaned to the ohmic contact regions 124 define. Exemplary etching processes include ion etching, reactive gas etching, chemical etching, and ion etching.

0018With reference to <figref>4</figref> is an ohmic metal layer 130 on the dielectric layer 122 and in the ohmic contact regions 124 educated. The ohmic metal layer130 is on the hallway layer122 and in the ohmic contact regions 124 deposited. The deposition process can be sputter deposition, evaporation or chemical vapor deposition (CVD). Exemplary ohmic metals include, but are not limited to, Ta, TaN, Pd, W, WSi2, Ti, Al, TiN, AlCu, AlSiCu and Cu. The thickness of the ohmic metal layer130 is in the range of 2000 to 5000 angstroms. It then becomes a glow after the deposition of the ohmic metal layer130 performed any desirable reactions between the ohmic metal and the adjacent AlGaN layer 114 to induce. In some embodiments, the ohmic metal layer is130 formed by rapid thermal annealing (RTA) at an annealing temperature in the range of approx. 800 ° C to approx. 900 ° C.

0019An anti-reflective coating (ARC) layer 132 is still on the ohmic metal layer 130 educated. The ARC layer132 is made, for example, of TiN or another suitable material. The ARC layer132 is formed by a deposition process. In some embodiments, the ARC layer is132 deposited by sputtering, evaporation or CVD. The ARC layer132 can have a thickness in the range of about 50 to 500 angstroms.

0020There is also an etch stop layer 134 on the ARC layer 132 educated. The etch stop layer134 can be made of oxide, SiN, or other suitable material. The etch stop layer134 is deposited using suitable vapor deposition processes (e.g. CVD) or another method. Exemplary silicon nitrides (SiN) include amorphous SiN, trisilicon tetranitride, disilicon mononitride, and silicon mononitride. In some embodiments, the etch stop layer is134 deposited to a thickness in the range of approximately 100 to 1000 angstroms.

0021With reference to <figref>5</figref> are the sections of the ohmic metal layer 130, the ARC layer 132 and the etch stop layer 134 removed to ohmic contacts in the contact region 124 define. The ARC layer132 and the etch stop layer 134 are on the ohmic contact 136 educated. The removal process includes performing one or more etching processes. The ohmic contacts136 are with the AlGaN layer 114 connected. In some embodiments, the ohmic contacts connect136 directly with the AlGaN layer 114. The ohmic contacts136 are used as part of a drain electrode and a source electrode.

0022With reference to <figref>6</figref> is a gate field plate 140 on the dielectric layer 122 educated. The processes of forming the gate field plate140 include forming a gate field plate metal layer on the dielectric layer 122 and patterning the gate panel metal layer. The gate field plate metal layer can be formed by a deposition process such as an ALD process, a CVD process or a vacuum deposition process. The structuring process includes performing one or more etching processes. The gate field plate140 can be made from TiN, Ti, Al, AlCu, Cu or any other suitable metal. The thickness of the gate field plate140 is in the range of 100 to 1200 angstroms.

0023The gate field plate 140 is next to the doped GaN region 120 arranged. The gate field plate140 is between the doped GaN region 120 and one of the ohmic contacts 136 educated. The gate field plate140 covers the doped GaN region 120 not starting. The gate field plate140 is to one of the ohmic contacts 136 electric.

0024The etch stop layer 134 is used to the underlying ARC layer 132 and ohmic contact 136 protect from this during the process of etching the gate field plate 140 to be etched. The ARC layer132 is through the etch stop layer 134 protected so that the area of the ARC layer 132 can be kept smooth. The ohmic contact136 is also through the etch stop layer 134 protected so that the profile of the ohmic contact 136 is maintained and the problem of metal loss of ohmic contact 136 during the process of defining the gate field plate 140 can be prevented.

0025With reference to <figref>7</figref> is another dielectric layer 150 on the dielectric layer 122 educated. The dielectric layer150 also covers the gate field plate 140 and the ohmic contacts 136 from. The dielectric layer150 can be made from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, dielectric with low dielectric constant, or a combination thereof. The dielectric layer150 is formed by a deposition process like an ALD process. The thickness of the dielectric layer150 ranges from about 500 angstroms to about 5000 angstroms.

0026With reference to <figref>8</figref> is an opening 152 formed which the dielectric layers 122 and 150 penetrates to at least part of the doped GaN region 120 to expose. The processes of forming the opening152 include forming a mask layer, such as a photoresist layer, in the dielectric layer 150 is formed, and the mask layer is patterned by a lithography process to form multiple features and at least one opening through the features on the dielectric layer 150 is defined. The structure of the mask layer is formed according to a predetermined IC structure in which the position of the opening of the mask layer is substantially the same as the position of the opening152 is. The lithography process can include photoresist coating, exposure, post exposure curing, and development. Then an etching process is performed around the opening152 on the doped GaN region 120 to build.

0027After the opening 152 was formed around the doped GaN region 120 to expose a gate metal stack in the opening 152 formed and with the doped GaN region 120 connected. The gate metal stack is on the doped GaN region120 formed and between the source and drain contacts (e.g. the ohmic contacts 136) inserted. The gate metal stack includes a layer of conductive material, such as a metal layer, that functions as a gate electrode that is configured for voltage matching and electrical coupling to the channel. According to different embodiments, the gate metal stack can have different compositions.<figref>9</figref> to <figref>12</figref> 10 show the variations of the gate metal stack of the semiconductor device according to some embodiments of the disclosure.

0028In <figref>9</figref> includes the gate metal stack 160a one or more transition insulation features under the metal layer 166 are arranged horizontally. The doped GaN region120 is a p-doped GaN region. The transition isolation feature comprises an n-doped semiconductor layer164 and an aluminum nitride (AlN) layer 162that between the n-doped semiconductor layer 164 and the p-doped GaN region 120 is arranged, the layers being configured as a diode. In some embodiments, the AlN layer162 be formed using MOCVD or another suitable technique. The gate metal stack160a results in a device that yields an Enrichment Type (E mode) device. In some embodiments, the n-doped semiconductor layer164 an n-doped III-V compound layer. In some embodiments, the n-doped III-V interconnect layer is an n-doped GaN layer. The n-doped GaN layer164 is by an n-dopant, such as. B., but not limited to, silicon, oxygen, or a combination thereof. In some embodiments, the n-doped GaN layer164 be formed by MOCVD or other suitable technique. The p-doped GaN region120 is by a p-type dopant such. B., but not limited to, magnesium, calcium, zinc, beryllium, carbon, and combinations thereof. In some embodiments, the p-doped GaN region120 be formed by MOCVD or other suitable technique. The metal layer168 includes Ti, Mo, Pt, Cr, W, Ni, Al, AlCu, AlSiCu, Cu or other suitable material. In the in<figref>9</figref> The embodiment shown are the gate metal stack 160a, the source and drain contacts 136 and the 2DEG region 116 (as a channel) in the GaN layer 112 configured as an E-mode transistor, the E-mode transistor being turned on when a positive voltage applied to the gate stack for the forward voltage is large enough. A transistor configured in this way is also referred to as an E-mode transistor with high electron mobility (HEMT).

0029If in <figref>10</figref> the metal layer 166 of the gate metal stack 160b in direct contact with the AIN layer 162 is placed over the p-doped GaN region 120 adjacent to the AlGaN layer 114 the resulting device results in a Schottky diode or an E-mode device with a low threshold voltage. In some embodiments, the AlN layer162 be formed using MOCVD or another suitable technique. In some embodiments, the p-doped GaN region120 by a p-type dopant such as e.g. B., but not limited to, magnesium, calcium, zinc, beryllium, carbon, and combinations thereof. In some embodiments, the p-doped GaN region120 be formed by MOCVD or other suitable technique.

0030In <figref>11</figref> is the p-doped region 120 left out and the metal layer 166 of the gate metal stack 160c in direct contact with the AlGaN layer 114 arranged, the resulting device resulting in a depletion (D mode) device. In some embodiments, the gate metal stack160c, the source and drain contacts (e.g. the ohmic contacts 136) and the 2DEG region 116 in the GaN layer 112 configured as a D-mode transistor, the device being self-conductive at zero gate-source voltage. Therefore, the D-mode transistor can be turned off by pulling the gate with a negative voltage. A transistor configured in this way is also referred to as a D-mode transistor with high electron mobility (HEMT).

0031However, in some embodiments, as shown in FIG <figref>12</figref> the semiconductor device has a plurality of E-mode and / or D-mode HEMTs. In<figref>12</figref> is the E-mode HEMT 100athat the gate metal stack 160a, the source and drain contacts 136 and the 2DEG region 116 (as a channel) in the GaN layer 112 comprises on the substrate 110 educated. The D mode HEMT100bthat the gate metal stack 160c, the source and drain contacts (e.g. the ohmic contacts 136) and the 2DEG region 116 in the GaN layer 112 is on the substrate 110 educated. The E mode HEMT100a and the D mode HEMT 100b can make ohmic contact 136 share.

0032With reference to <figref>13</figref> becomes another ARC layer 170 on the gate metal stack 160 formed after the gate metal stack 160that any or more of the gate metal stacks 160a to 160c which have the compositions and structures previously described, on the semiconductor structure 100 was formed. The ARC layer170 is made, for example, of TiN, SiON or another suitable material. The ARC layer170 is formed by a deposition and etching process. In some embodiments, the ARC layer is170 deposited by sputtering, evaporation or CVD. The ARC layer170 can have a thickness in the range of approximately 50 to 1000 angstroms.

0033With reference to <figref>14</figref> is an interlayer dielectric (ILD) layer 180 on the substrate 110 deposited. The ILD layer180 covers the dielectric layer 150 and the gate metal stack 160 and the ARC layer 170 from. The ILD layer180 is used to isolate and support capacitor features such as parallel conductive metal lines. The ILD layer180 is made of dielectric. In some embodiments, the ILD layer is180 made from materials with low dielectric constant (k) (ie, “low-k” materials) such as oxide, fluorinated silica glass (FSG), SiLK ™, SiN or another suitable dielectric. In some embodiments, an annealing process can be performed to improve the electrical insulation properties of the ILD layer180 to improve. In addition, the ILD layer180 be doped, e.g. B. carbon-doped oxide or boron / phosphorus-doped oxide to improve their step coverage and annealing properties. The area of the ILD layer180 is flattened. The process of flattening the ILD layer180 involves executing a CMP process.

0034With reference to <figref>15</figref> are multiple vias 182 in the ILD layer 180 educated. The vias182 are to the ARC layers 132, 170 guided. The vias182 can be formed by one or more etching processes. Portions of the etch stop layer134 are also removed to the ARC layer 132 to expose. The etchant used in the etching process can have a high selectivity between the ARC layer132 and the other layers such as the etch stop layer 134, the dielectric layer 150 and the ILD layer 180 exhibit.

0035After the vias 182 in the ILD layer 180 are formed around the ARC layers 132 and 170 to expose a metal layer 190 on the ILD layer 180 formed and fills the vias 182. The metal layer190 can be formed by one or more deposition processes. The deposition process can be sputter deposition, evaporation or chemical vapor deposition (CVD). The metal layer190 is made of Ti, Mo, Pt, Cr, W, Ni, Al, AlCu, AlSiCu, Cu or another suitable material.

0036With reference to <figref>16</figref> the metal layer is structured and becomes several metal contacts 192, each electrically with the ohmic contacts 136 are connected. The metal contacts192 penetrate the etch stop layer 134to deal with the ARC layer 132 connect to. In some embodiments, one or more of the ohmic contacts form136 the ARC layer 132 and one or more metal contacts 192 a source electrode 200a; one or more of the ohmic contacts136who have favourited ARC Layer 132 and one or more metal contacts 192 form a drain electrode 200b; one or more of the gate metal stacks160who have favourited ARC Layer 170 and one or more metal contacts 192 form a gate electrode 200c.

0037In some embodiments, the gate field plate 140 between the gate electrode 200c and the drain electrode 200b arranged. The gate field plate140 is with the source electrode 200a electrically connected. The introduction of the gate field plate140 played a role in gate modulation, the effect of leakage current between state trap to limit the current dip effect; simultaneously with the introduction of the gate field plates140 became the electric field between the gate electrode 200c and the drain electrode 200b redistributed. Without a gate field plate, the electric field strength has a tip region between the gate electrode200c and the drain electrode 200b on. However, if the gate field plate140 between the gate electrode 200c and the drain electrode 200b the region with the maximum electric field strength becomes the drain electrode 200b expanded and the tip of the electric field between the gate electrode 200c and the drain electrode 200b reduced, which can greatly improve the breakdown voltage of the device. Furthermore, the gate field plate reduces140 also the gate-to-drain capacitance (Cgd).

0038Reference is now made to <figref>17</figref>10 is a schematic top view of the semiconductor device according to some embodiments of the disclosure. The semiconductor device may include multiple E-mode HEMTs or D-mode HEMTs. The semiconductor device includes a source line210, a gate line 220, a drain line 230 and a gate field plate 240 in a parallel arrangement. The gate line220 includes several of the gate electrodes 200c arranged linearly. The drain line230 includes multiple drain electrodes 200b arranged linearly. In some embodiments, the gate line is220 between the source line 210 and the drain line 230 arranged and the gate field plate 240 is between the gate line 220 and the drain line 230 arranged. The semiconductor device further comprises a first metal line250that with the drain line 230 connected and to the drain line 230 is vertical. The semiconductor device further includes a second metal line260going to the source line 210, the gate line 220, the drain line 230 and the gate field plate 240 is arranged vertically. The source management210 and the gate field plate 240 are with the vias of the second metal line 260 connected in such a way that the gate field plate 240 with the source management 210 through the second metal line 260 is electrically connected. The semiconductor device further includes a third metal line270that with the gate line 220 connected and to the gate line 220 is vertical.

0039Reference is now made to <figref>18</figref>10 is a schematic top view of the semiconductor device according to some embodiments of the disclosure. The semiconductor device can include both E-mode HEMTs and D-mode HEMTs. The semiconductor device includes multiple source lines210, multiple gate lines 220, at least one drain line 230 and several gate field plates 240 in a parallel arrangement. Each of the gate lines220 comprises several of the linearly arranged gate electrodes 200c. The drain line230 comprises several linearly arranged drain electrodes 200b. In some embodiments, E-mode HEMTs and D-mode HEMTs can drain the line230 share. The gate line220 is between the source line 210 and the drain line 230 arranged and the gate field plate 240 between the gate line 220 and the drain line 230 arranged. That is, the gate field plates240 are on opposite sides of the drain line 230 arranged the gate lines 220 are on opposite sides of the gate field plates 240 arranged and the source lines 210 are on opposite sides of the gate lines 240 arranged. The semiconductor device further comprises a first metal250that with the drain line 230 connected and to the drain line 230 is vertical. The semiconductor device further includes a second metal line260that are perpendicular to the source lines 210, the gate lines 220, the drain line 230 and the gate field plates 240 is arranged. The source lines210 and the gate field plates 240 are with vias of the second metal line 260 connected so that the gate field plates 240 with the source lines 210 through the second metal line 260 are electrically connected. The semiconductor device further includes a third metal line270that with the gate lines 220 connected and to the gate lines 220 is vertical.

0040The semiconductor device includes an etch stop layer formed on the ARC layer so that the ARC layer is protected by the etch stop layer during the process of forming the gate field plate. The ohmic contact profile is maintained and the problem of ohmic contact metal loss during the process of defining the gate field plate can be avoided.

0041A semiconductor device may include a gallium nitride (GaN) layer on a substrate, an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer, a gate metal stack disposed on the AlGaN layer, at least one ohmic contact located on the AlGaN layer is arranged, a gate field plate, which is arranged between the ohmic contact and the gate metal stack, an anti-reflection coating (ARC) layer, which is formed on the ohmic contact, and have an etch stop layer which is formed on the ARC layer.

0042A semiconductor device can have a first III-V connection layer on a substrate, a second III-V connection layer on the first III-V connection layer, material of the first III-V connection layer being different from that of the second III-V connection layer a gate metal stack which is arranged on the second III-V connection layer, a source contact and a drain contact which are arranged on opposite sides of the gate metal stack, a gate field plate disposed between the gate metal stack and the drain contact, an anti-reflective coating (ARC) layer formed on the source contact and the drain contact, and an etch stop layer formed on the ARC layer.

0043A method of manufacturing a semiconductor includes forming a first III-V interconnect layer on a substrate, forming a second III-V interconnect layer on the first III-V interconnect layer, wherein a material of the first III-V interconnect layer is different from differs from that of the second III-V connection layer, the formation of a dielectric layer on the second III-V connection layer, the formation of an ohmic contact, that penetrates the dielectric layer and connects to the second III-V interconnect layer, forming an anti-reflective coating (ARC) layer on the ohmic contact, forming an etch stop layer on the ARC layer, and forming a gate plate on the dielectric layer using a Deposition and etching process.

0044The foregoing describes features of multiple embodiments so that those skilled in the art can better understand the aspects of the present disclosure.

Contents2

Every citation, both ways

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US8633094B2	Cites	United States of America	Applicant
US8633094B2	Cites	United States of America	Search report
US20140203289A1	Cites	United States of America	–
US20140252368A1	Cites	United States of America	–

20 members in 5 offices

This recordMember, by publication datePriority claim

Priority claims2

Priority claims
Document	Office	Kind	Date
14839931	United States of America	–	2015-08-29
201514839931	United States of America	A	2015-08-29

Members20

Family members, oldest first
Document	Office	Kind
TW201709419A	Taiwan Province of China	A	2017-03-01
DE102015114707A1	Germany	A1	2017-03-02
US2017062581A1	United States of America	A1	2017-03-02
CN106486543A	China	A	2017-03-08
KR20170026038A	Republic of Korea	A	2017-03-08
KR101716049B1	Republic of Korea	B1	2017-03-13
TWI608568B	Taiwan Province of China	B	2017-12-11
US9941384B2	United States of America	B2	2018-04-10
US2018233577A1	United States of America	A1	2018-08-16
US10134867B2	United States of America	B2	2018-11-20
US2019109210A1	United States of America	A1	2019-04-11
CN106486543B	China	B	2019-12-10
US10686054B2	United States of America	B2	2020-06-16
DE102015114707B4This record	Germany	B4	2020-06-18
US2020312983A1	United States of America	A1	2020-10-01
US2021384319A1	United States of America	A1	2021-12-09
US11374107B2	United States of America	B2	2022-06-28
US2022336631A1	United States of America	A1	2022-10-20
US11901433B2	United States of America	B2	2024-02-13
US12027603B2	United States of America	B2	2024-07-02

7 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2024-11-22	Amendment of ipc main classPREVIOUS MAIN CLASS: H01L0021338000R079	R079
2021-03-19	Patent grant now finalGrantedR020	R020
2020-02-20	Grant decision by examination section/examining divisionR018	R018
2020-02-19	Amendment of ipc main classPREVIOUS MAIN CLASS: H01L0029778000R079	R079
2020-02-12	Response to examination communicationR016	R016
2016-05-31	Response to examination communicationR016	R016
2015-09-03	Request for examination validly filedR012	R012