Substrate with Feedthrough and Method for Producing the Same

0001The present invention relates to a substrate having a carrying as well as to a method for producing a substrate with a passage.

0002Integrated Circuits, sensors or micromechanical devices are usually on applied a substrate or integrated into one. to built Connecting external circuits to be able to it may be helpful if the substrates via electrically conductive feedthroughs feature of the substrate top to bottom substrate.

0003In front this background, a substrate according to claim 14, a semiconductor module according to the claim 25 and a method according to the claim 1 indicated. Other aspects of the substrate, the semiconductor module and Process, and improvements or modifications are defined by the dependent claims, the Figures and the description discloses.

0004Especially providing a substrate provided with a semiconductor substrate a first main surface, a second main surface and at least one of the first main surface to the second major surface of reaching Channel covers. The at least one channel has in a first section a first cross-sectional area and in a second section a second cross-sectional area, wherein the first cross-sectional area greater than the second cross-sectional area is. The channel is introduced into the first section to one of a melt filled electrically conductive first material and the second section with an electrically conductive second material.

0005Further Provided is a semiconductor module comprising a substrate and a includes an integrated circuit. The substrate is such as the above- Described substrate formed. The integrated circuit is applied to the substrate.

0006Of Furthermore, a method in which a semiconductor substrate is provided, having a first main surface, a second main surface and at least one of the first main surface to the second major surface of reaching Channel is provided. The at least one channel has, in a first section of a first cross-sectional area and in a second portion a second cross-sectional area on. In the first portion of the at least one channel is at Pressure in the molten state, an electrically conductive first material filled.

0007The pamphlet <patcit><text>DE 10 2005 042 074 A1</text></patcit> describes a method in which a substrate leading conical blind holes galvanically filled will.

0008The pamphlet <patcit><text>EP 0 926 723 A1</text></patcit> describes a method in which blind holes in first a CVD process with a first layer and then galvanically are covered with a metal layer.

0009The pamphlet <patcit><text>US 5,618,752 A</text></patcit> describes the filling of cylindrical blind holes via CVD method, Sputtering or vapor deposition.

0010The pamphlet <patcit><text>WHERE 2005/088699 A1</text></patcit> indicates a method, in which by a Substrate-reaching channels from a first side by means of LPCVD process, and by a second Side are filled by means of galvanic deposition.

0011The pamphlet <patcit><text>US 7,176,128 B2</text></patcit> describes a method in which the blind holes by means of CVD method and galvanic deposition be filled.

0012The Publication Yamamoto, S. et al .; "Si through-hole inter connections filled with Au-Sn solder by molten metal suction method "; Micro Electro Mechanical Systems, 2003. MEMS-03 Kyoto; January 19 to 23 2003, pp. 642-645 describes a method for filling of blind holes from a melt.

0013The pamphlet <patcit><text>JP 2006-013454P </text></patcit> describes toward filling a to the center widening channel with molten material.

0014in the Below are some embodiments described the characteristics of which merely illustrate the invention to serve and this limit in any way.

0015<figref idrefs="S33">1A</figref> to <figref idrefs="S34">1C</figref> show schematically a substrate <figref>100</figref> and a process for preparing the substrate <figref>100</figref>,

0016<figref idrefs="S35">2A</figref> to <figref idrefs="S36">2E</figref> show schematically a substrate <figref>200</figref> and a process for preparing the substrate <figref>200</figref>,

0017<figref idrefs="S37">3A</figref> to <figref idrefs="S38">3D</figref> show schematically a substrate <figref>300</figref> and a process for preparing the substrate <figref>300</figref>,

0018<figref idrefs="S39">4A</figref> to <figref idrefs="S40">4D</figref> show schematically a substrate <figref>400</figref> and a process for preparing the substrate <figref>400</figref>,

0019<figref idrefs="S41">5A</figref> to <figref idrefs="S42">5D</figref> show schematically a substrate <figref>500</figref> and a process for preparing the substrate <figref>500</figref>,

0020<figref idrefs="S43">6A</figref> to <figref idrefs="S43">6C</figref> show schematically substrates <figref>600A</figref>. <figref>600B</figref> and <figref>600C</figref>,

0021<figref idrefs="S44">7</figref> shows schematically a semiconductor module <figref>700</figref>,

0022<figref idrefs="S44">8th</figref> shows schematically a semiconductor module <figref>800</figref>,

0023<figref idrefs="S44">9</figref> shows schematically a semiconductor module <figref>900</figref>,

0024in the Hereinafter, substrates as well as process for the preparation of the substrates described. The substrates may as support serve on the micro or nanometer scale structured devices, z. B. integrated electrical or electro-optical circuits, To keep sensors or micromechanical devices in position and / or in connection with the outside world to set. The substrates may be semiconductor substrates contain, in particular silicon substrates, germanium substrates, GaAs substrates, SiC substrates, or completely partially oxidized macroporous Silicon etc. The semiconductor substrates may because of their good structurability and semiconductors inherent electronic properties of both as support as well as devices with integrated active components, eg. As transistors, diodes, movable structural elements, sensor elements etc., are used. Due to the advanced semiconductor process technology can the active components with a very high density in a semiconductor substrate to get integrated.

0025provided the semiconductor substrates as carriers are used, receive one or more further semiconductor substrates ( "chips"), which itself both as a carrier can serve and / or in which active components are integrated. The chips can on the carrier substrate be glued or soldered or similar Way be attached. The electrically conductive contacts between the chips, or between the chip and the outside world may optionally by bonding wires, flip-chip bonding or additionally applied Conductor tracks are produced. In this way can be a semiconductor substrate as a carrier for the production of compact, highly integrated "System in Package" (SiP) modules use. These modules can in the field of communication technology and automotive, industrial and consumer electronics (Z. B. RF module Mobile phones, base station or radar modules for automobiles) be used.

0026The Use of silicon as substrate support has the further advantage that most integrated components also in silicon are integrated. In this case, a carrier substrate had from Silicon the same coefficient of thermal expansion (CTE) such as the mounted components him. This reduces the destructive mechanical forces between carriers may form and the component due to thermal cycles during operation. by virtue of the good structuring of semiconductors and advanced Semiconductor technology can the channels in the semiconductor substrates have very small cross-sectional areas. Thereby, a channel density on the substrate surface be that the structural widths of a semiconductor integrated circuit device equivalent, eg. as a few 100 nm.

0027For a high System integration, it is helpful if the substrate electrically conductive feedthroughs from a major surface to the other major surface comprising the substrate. This can Interconnects electrically with each other on both sides of the substrate are conductively connected. In this way, short electronic Connections between electronic components and devices Manufacture on opposite major surfaces of the substrate are arranged. This allows a predetermined substrate surface economically used, minimizing package sizes additional and effort Interconnect layers are avoided.

0028For example can direct connections between a on the one main surface of the semiconductor substrate Flip-chip mounted integrated component and on the other major surface of the Substrate arranged contact elements are manufactured. Are the positions of the electrically conductive feedthroughs at the positions of the chip contacts aligned, can the bushings for short Connections to the contact elements provide to z. B. fast signals, (Z. B. RF) signals possible trouble- and without delay outward to lead.

0029If a substrate on an integrated circuit comprises a front side and beyond electrically conductive feedthroughs are present, these can be used, signals from the integrated device directly on the substrate backside to lead. In this way, using soldered to the electrically conductive feedthroughs contact elements particularly short electric connections between the integrated Circuit and the outside world getting produced. The back Contact elements also allow a stack structure in which integrated Components superimposed can be stacked and contacted directly.

0030The electrically conductive feedthroughs are in channels introduced by the semiconductor substrate. The channels extend each extending from a first major surface of the semiconductor substrate to a second main surface of the semiconductor substrate. Usually the first and the second main surface, the two large opposite faces of Semiconductor substrate. Specifically, the main surfaces are the both surfaces a circular monocrystalline semiconductor wafer ( "wafer") or whose sawn Parts ( "chip"). The surfaces a semiconductor wafer are i. A. standardized to predetermined Wheel diameter, z. B. 4-inch, 8-inch, 10-inch, 12-inch (300 mm). The thicknesses of the slices can vary in areas of typically 100 to 1000 .mu.m, be these values ​​in specific applications also less than or greater can.

0031Of the at least one or multiple channels each have a first opening on the first major surface and a second opening on the second main surface of the semiconductor substrate on. Overlie one another, the two openings, so, the channel can in the first or second major surface substantially perpendicular Toward the first opening with the second opening connect. In this case, the channel length corresponds substantially to the thickness of the semiconductor substrate.

0032In the at least one channel is an electrically conductive first material and in particular introduced a second electrically conductive material. The electrically conductive first and second materials as well as possibly more electrically conductive materials form the electrically conductive implementation through the at least one channel. The electrically conductive materials can For example, metals such. as copper, silver or gold, or Alloys or brazing alloys, z. B. silver-based (eg. B. AgCu28), soft solders, z. B. tin-based, etc.. The choice of the electrically conductive Materials can the desired Requirements and application areas of the substrate to be adjusted.

0033Of the at least one channel through the semiconductor substrate has, on a first location a first cross-sectional area and the second at a Stel le a second cross-sectional area. The first and second Cross sectional area vary in size. Further , the at least one channel from more locations within the first or second cross sectional area exhibit. For example, within a first portion the first cross-sectional area are present and within a second section, the second cross sectional area. Furthermore It is also possible that at least one channel at a third location, or in a the third portion has a third cross-sectional area which is of the first and / or second cross-sectional area is different. Correspondingly Example, the at least one channel from more locations other Cross-sectional areas exhibit. Dependent on the method of preparation, with which the at least one channel is produced in the semiconductor substrate, there may be more or less sharp transitions between different cross-sectional areas come.

0034The Cross-sectional areas the at least one channel can for example, be substantially circular formed, they can but also have other geometric shapes. have, in the case of circular cross-sectional areas the first and second cross sectional area different diameters. Depending on the application and substrate material, the cross-sectional areas values assume that to between some 100 square nanometers up a few square millimeters are. Larger or smaller values ​​can, however, are not excluded. The size of the cross-sectional areas can depend on, how much current to flow through the electrically conductive implementation, whether the electrically conductive performing well for thermal Dissipation of heat of such. B., heat to serve producing integrated circuits, whether certain induction or capacity requirements met to be, etc. Finally, hanging the Cross sectional area also depends on how many passages are generated and how big the Density of penetrations should be.

0035It These are detailed descriptions of exemplary embodiments, which in the accompanying figures are schematic and not to scale are illustrated.

0036<figref idrefs="S33">1A</figref>. <figref idrefs="S33">1B</figref> and <figref idrefs="S34">1C</figref> show -Sections A-A ', BB' and CC 'by a substrate <figref>100</figref>, The sections BB 'and CC 'parallel to each other and perpendicular to the section A-A '. substrate<figref>100</figref> consists for example of a circular semiconductor substrate <figref>1</figref>. in the at least one channel <figref>2</figref> has been introduced. Of the channel <figref>2</figref> extending from a first major surface <figref>3</figref> to a second main surface <figref>4</figref> of Semiconductor substrate <figref>1</figref>, At a first location<figref>5</figref>. through the section BB 'runs, has the channel <figref>2</figref> a first cross-sectional area <figref>6</figref> and at a second place <figref>7</figref>Through which the section CC 'extends, has the channel <figref>2</figref> a second cross-sectional area <figref>8th</figref> on. For example is the second cross-sectional area <figref>8th</figref> smaller than the first cross-sectional area <figref>6</figref>, Subscribe to Channel <figref>2</figref> is an electrically conductive first material <figref>9</figref> brought in.

0037following are based on the <figref>2</figref> to <figref>6</figref> additional substrates <figref>200</figref> to <figref>600</figref> and their methods of preparation described. substrates<figref>200</figref> to <figref>600</figref> put Developments of the in <figref>1</figref> shown substrate <figref>100</figref> represent. The embodiments described below the substrates <figref>200</figref> to <figref>600</figref> and their method of preparation can in a corresponding manner to the substrate <figref>100</figref> be based.

0038In <figref idrefs="S36">2E</figref> is the substrate <figref>200</figref> shown schematically, the plurality a of channels <figref>2</figref> contains. In the <figref idrefs="S35">2A</figref> to <figref idrefs="S36">2E</figref> are Steps for producing the substrate <figref>200</figref> shown.

0039to Preparation of Substrate <figref>200</figref> firstly the semiconductor substrate <figref>1</figref> provided, in which in the places where the channels later <figref>2</figref> through the semiconductor substrate <figref>1</figref> run should, blind holes <figref>10</figref> generated will. The production of the blind holes<figref>10</figref> can in many Because happen. A possible Producing variant represents the electrochemical etching. In preparation for the electrochemical etching is the first major surface <figref>3</figref> of Semiconductor substrate <figref>1</figref> selectively to a mask with z. B. 10% potassium hydroxide for z. B. etched 10 minutes. subsequently is the first major surface <figref>3</figref> With an electrolyte, eg. B. HF acid, rain and a voltage between the second major surface <figref>4</figref> and the electrolyte applied. Simultaneously, the second major surface is<figref>4</figref> With a light source, for. example, with 800 nm wavelength is irradiated. The intensity of the light source is adjusted so that a predetermined current density, for. example 10 nA per blind hole, between the semiconductor substrate <figref>1</figref> and the electrolyte flows. The current between the etched first main surface <figref>3</figref> of Semiconductor substrate <figref>1</figref> and the electrolyte form the etched locations Pores in the semiconductor substrate <figref>1</figref> grow and the blind holes <figref>10</figref> form.

0040The electrochemical etching can be connected to p-doped or n-doped Semiconductor substrates <figref>1</figref>, In particular silicon semiconductor substrates, accomplished be with their resistivity typically in a range from 1 to 2000 ohm-cm and especially is in a range from 800 to 1200 ohm-cm. The shape, diameter, the depth and density of the blind holes produced <figref>10</figref> depend heavily on the current density, the doping, the acid strength and the etching time from and must Accordingly, for each new application to be re-determined.

0041The electrochemical etching open the possibility, by changing by etching parameters during the etching process the cross-sectional areas within the individual blind holes <figref>10</figref> to vary. For example, formed in the blind holes<figref>10</figref> a more larger cross-sectional area of, the greater the etching current is. Specifically, there is between the etching current and of data generated by the electrochemical etching Cross sectional area a quadratic dependence. For example, was during etching one in <figref idrefs="S35">2A</figref> first portion shown <figref>11</figref> of the blind holes <figref>10</figref> on greater etching current adjusted as for etching a second portion <figref>12</figref>, This has in the first section <figref>11</figref> formed a larger cross-sectional area than in the second portion <figref>12</figref>, The first paragraph<figref>11</figref> contains the first place <figref>5</figref> and the second section <figref>12</figref> contains the second location <figref>7</figref> of the channels <figref>2</figref>,

0042In <figref idrefs="S35">2 B</figref> is as an alternative to <figref idrefs="S35">2A</figref> shown that the etching current also can be adjusted so that the blind holes <figref>10</figref> initially with produced a small diameter, and after a certain Time of etching current is adjusted so that the blind holes <figref>10</figref> expanded will.

0043Around from the blind holes <figref>10</figref> each a complete channel <figref>2</figref> from the first major surface <figref>3</figref> to the second major surface <figref>4</figref> form, can blind holes <figref>10</figref> in a further etching step, z. B. by means of a dry or wet etching process, weitergeätzt are, to this, the second main surface <figref>4</figref> of the semiconductor substrate <figref>1</figref> to accomplish. Alternatively, the blind holes <figref>10</figref> by removing material from the second major surface <figref>4</figref> here open will. For example, the second main surface<figref>4</figref> by Planarization by CMP opened polishing (CMP) will.

0044For the production the blind holes <figref>10</figref> and the channels <figref>2</figref> can place the electrochemical etching, other etching techniques described above be applied. in principle can to the known etching process in micromechanics, such. as RIE (Reactive Ion Etching) method, laser drilling, sandblasting or Ultrasonic drilling, be used as long as these etching methods allow, the cross-sectional area the channels <figref>2</figref> in dependence to vary the depth. Below are related with the description of <figref>4</figref> to <figref>6</figref> Other methods of preparation of the blind holes <figref>10</figref> and channels <figref>2</figref> presented.

0045The completely through the semiconductor substrate <figref>1</figref> extending channels <figref>2</figref> are in <figref idrefs="S35">2C</figref> shown. The semiconductor substrate<figref>1</figref> can a thickness in the range of 25 to 2000 .mu.m, in particular in the range of 100 to 250 microns exhibit. The channels<figref>2</figref> can a Diameter in the range of 2 to 150 microns and more particularly in the range comprise 10 to 30 microns. The relationship of channel length to channel diameter (aspect ratio) may be in a range of 2 to 1000, in particular, relatively size Aspect ratios be above z., 100.

0046Around the bushings adjacent channels <figref>2</figref> electric to isolate from each other, can the surfaces the channels <figref>2</figref> With a first insulating layer <figref>13</figref> are provided, the in <figref idrefs="S35">2C</figref> is illustrated by a thicker line. The first insulation layer <figref>13</figref> , an oxide and / or a be nitride. Insofar as the semiconductor substrate<figref>1</figref> out Silicon is made, the first insulating layer <figref>13</figref> z. B. a SiO₂his film, for example, by means of a CVD (chemical vapor deposition) process from TEOS (Tetra-ethyl-ortho-silicate) is generated or is sputtered or Si₃N₄Layer, which of silane (SiH₄) and ammonia (NH₃) is produced. The first insulating layer <figref>13</figref> can also be a combination of different its insulation layers, eg. as an ONO layer, the combination of a the above-mentioned oxide-nitride-oxide layers is.

0047Of Furthermore, the insulating layer may <figref>13</figref> a thermally generated SiO₂his film. In the thermal oxidation the SiO₂no layer is deposited, but the already exposed on the silicon surface is silicon by heating (ca. 900 to 1200 ° C) and oxygen in silica converted. Thermally generated Silica forms unlike produced in other ways Silica has a very impurity-interface with the silicon lattice. Thereby, leakage currents in silicon at the Si / SiO₂-Grenzfläche Reduced. Further, the parasitic capacity between the later in the channels <figref>2</figref> introduced electrically conductive materials and the silicon is minimized. Minimal parasitic capacitances especially important for High-frequency applications.

0048The Thickness of the first insulation layer <figref>13</figref> is depending on the application in the range of 5 to 1000 nm, in particular between 100 and 200 nm.

0049Especially is not only the surface in the channels <figref>2</figref> rather the entire surface of Semiconductor substrate <figref>1</figref>, Ie in the channels <figref>2</figref> and on the two main surfaces <figref>3</figref> and <figref>4</figref> of the semiconductor substrate <figref>1</figref>. with the first insulation layer <figref>13</figref> provided. In the event of a silicon substrate <figref>1</figref> This can in a single step happen, for. example by thermal oxidation or nitriding of the with the channels <figref>2</figref> provided silicon substrate <figref>1</figref>, This is a procedural economy Manner to the semiconductor substrate <figref>1</figref> both in the channels <figref>2</figref> as well as to the main surfaces <figref>3</figref> and <figref>4</figref> from the later in the channels <figref>2</figref> introduced conductive materials electrically isolate. Specifically, the first insulation layer <figref>13</figref> applied so that the layer thickness the first insulation layer <figref>13</figref> in the channels <figref>2</figref> from the layer thickness on the first or second main surface <figref>3</figref>. <figref>4</figref> around less than 50% and in particular by less than 20%.

0050provided the first insulation layer <figref>13</figref> of a thermally generated Silicon dioxide, this can be connected to the first and / or second major surface <figref>3</figref>. <figref>4</figref> as oxide for the gates of MOS transistors are used. The silicon dioxide thermally generated also offers the advantage of very defect-Si / SiO₂-Grenzfläche, whereby leakage currents be minimized in silicon. By using a thermal Oxide as a first insulation layer <figref>13</figref> the manufacturing process is the bushings through the semiconductor substrate <figref>1</figref> compatible with standard CMOS processes. this makes possible there, a silicon chip or wafer having integrated circuits and with any number of penetrations low cost equip.

0051Optional can on the first insulation layer <figref>13</figref> a barrier layer <figref>14</figref> upset are the diffusion of the later in the channels <figref>2</figref> introduced electrically conductive materials in the semiconductor substrate <figref>1</figref> prevented. The barrier layer <figref>14</figref> z can. B. a TiN or TaN film be formed by vapor deposition or a CVD process on the surfaces of the channels <figref>2</figref> upset becomes. The layer thickness of the barrier layer<figref>14</figref> is z. B. 100 nm. The barrier layer <figref>14</figref> is exemplary only in <figref idrefs="S35">2C</figref> by a dashed line and, as optional, in the following FIGS no longer indicated.

0052<figref idrefs="S36">2D</figref> shows the substrate <figref>200</figref>After the channels <figref>2</figref> with the electrically conductive first material <figref>9</figref> have been filled. The filling of channels <figref>2</figref> with the electrically conductive first material <figref>9</figref> serves the for a electrically conductive implementation required material or at least a part of it available to put. The electrically conductive first material<figref>9</figref> becomes preferably above its melting temperature in the channels filled. The electrically conductive first material <figref>9</figref> is especially so selected that it has a melting point temperature which is less than that of the semiconductor substrate <figref>1</figref>, One advantage of filling the channels <figref>2</figref> With the electrically conductive first material <figref>9</figref> in the liquid state may be that this process higher throughput and lower Process cost than conventional Types of metal filling may have, especially when compared to from the gas phase (CVD) made deposits or electrochemical or chemical plating (Electroless plating).

0053As electrically conductive first material <figref>9</figref> For example, Copper (melting point: 1084 ° C), silver (Melting point: 962 ° C) or gold (melting point: 1064 ° C) be used. These materials have excellent electrical conductivities and a lower melting point than silicon (melting point: 1,410 ° C).

0054Conceivable furthermore also brazing alloys, eg. as silver-based (eg. B. AgCu28) Soft solders, z. B. tin-based, and other metals, such as., Aluminum, Lead, zinc, etc. The choice of the electrically conductive first material <figref>9</figref> can the wished Requirements and application areas of the substrate <figref>200</figref> be adjusted.

0055The To fill with the electrically conductive first material <figref>9</figref> can channel way or in parallel. to fill the channels <figref>2</figref> can the semiconductor substrate <figref>1</figref> For example, in the melt the electrically conductive first material <figref>9</figref> submerged are such that the melt is substantially simultaneously in the channels <figref>2</figref> penetration can.

0056Especially is the first electrically conductive material <figref>9</figref> at a relative negative pressure in the channels <figref>2</figref> brought in. By applying a relative negative pressure, it is possible also bring bad wetting materials in narrow channels. Where, that the smaller the cross-sectional area, the longer the channel and the worse wetting, the greater the for the filling the channel required relative vacuum is. A relative Under pressure in the channels <figref>2</figref> can by an overpressure, the in filling the electrically conductive first material <figref>9</figref> from the outside to exercised the melt be is produced.

0057by virtue of the in <figref>2</figref> shown in sections Narrowing or widening of the channels <figref>2</figref> are within a channel <figref>2</figref> -Spaces having different inflation pressures. For the filling of in <figref>2</figref> second portion shown <figref>12</figref> of the channels <figref>2</figref> With a molten metal or alloy is due to its lower second cross-sectional area <figref>8th</figref> on greater inflation pressure required as for the first section <figref>11</figref> with the larger first cross-sectional area <figref>6</figref>,

0058At the To fill the channels <figref>2</figref> With the electrically conductive first material <figref>9</figref> you can the above-described different filling characteristics of the first and second sections <figref>11</figref> and <figref>12</figref> advantage do. at a specific inflation pressure is only the first section <figref>11</figref> with the melt the electrically conductive first material <figref>9</figref> filled. With increasing increasing the pressure is reached, a limit pressure at which eventually also the filling of the second portion <figref>12</figref> takes place and the entire channel <figref>2</figref> With filled melt is. The state in which the entire channel<figref>2</figref> with the melt the electrically conductive first material <figref>9</figref> is filled, however, is undesirable, since the channel <figref>2</figref> when pulling from the melt would drain. Instead, the pressure should be set such that the first portion <figref>11</figref> With filled the melt is, the second portion <figref>12</figref> but not yet filled. In this case the second section acts <figref>12</figref> as grafting, the full the filling the channel <figref>2</figref> with melt prevented. This has the advantage, that the channels <figref>2</figref> at the Pulling out of the semiconductor substrate <figref>1</figref> from the melt Do not drain. Due to the narrowing of the channels<figref>2</figref> in the second section <figref>12</figref> behavior the channels <figref>2</figref> at the To fill with the electrically conductive first material <figref>9</figref> just like that such as blind holes. Even with the blind holes configured channels in a semiconductor substrate has a relative vacuum applied be to bring a melt in the blind holes. However, holes must after Introduction of the melt are open to continuous channels to ultimately an electrically conductive carrying to provide through the semiconductor substrate. This process step may occur when in <figref>2</figref> shown procedure be saved.

0059Of the Step process for filling the channels <figref>2</figref> With the electrically conductive first material <figref>9</figref> For example, as follows be configured. First the semiconductor substrate <figref>1</figref> in a gas-tight process chamber introduced which the melt of the electrically conductive first material <figref>9</figref> contains. While the Process chamber is evacuated, there is the semiconductor substrate <figref>1</figref> outside of the melt. After a predetermined pressure in the range of 0.001 is up to 100 mbar, in particular less than 1 mbar, is reached, the semiconductor substrate <figref>1</figref> immersed in the melt and the Process chamber then pressurized. The pressure is in the range 1 to 20 bar, in particular in the range of 5 to 10 bar. The to fill the first portions <figref>11</figref> the channels <figref>2</figref> required dependent pressure In addition to the cross-sectional areas <figref>6</figref> and <figref>8th</figref> of the channels <figref>2</figref> especially on the process temperature and the surface tension of the electrically conductive first material <figref>9</figref> from. The semiconductor substrate<figref>1</figref> becomes under the filling the channels <figref>2</figref> set Pressure drawn from the melt. After solidification of the melt in the channels <figref>2</figref> becomes the pressure in the process chamber is reduced again to atmospheric pressure.

0060By the while filling the channels <figref>2</figref> expended Printing needs the surface in the channels <figref>2</figref> also a poorly wetting electrically conductive first material <figref>9</figref> not be provided with an adhesive layer. By eliminating adhesive materials in the channels <figref>2</figref> can costly additional Processing steps can be saved.

0061A filling the channels <figref>2</figref> With a poorly wetting electrically conductive first material <figref>9</figref> under Pressure can cause the one hand, the electrically conductive first material <figref>9</figref> in the channels <figref>2</figref> penetrates and where, following solidification, an electrically conductive or implementation forming part thereof and on the other of the two main surfaces <figref>3</figref> and <figref>4</figref> of Semiconductor substrate <figref>1</figref> bead up. Thus, by beading a layer formation of solidifying by cooling the first material <figref>9</figref> on the two main surfaces <figref>3</figref> and <figref>4</figref> avoided will. The avoidance of such a film forming on the major surfaces<figref>3</figref> and <figref>4</figref> can prevent the semiconductor substrate <figref>1</figref> during cooling and Solidification of the liquid electrically conductive first material <figref>9</figref> due to different coefficients of thermal expansion so great mechanical stresses is exposed, that it would be damaged.

0062As in <figref idrefs="S36">2E</figref> is shown, after filling the first portions <figref>11</figref> with the first electrically conductive material <figref>9</figref> the second portions <figref>12</figref> with a electrically conductive second material <figref>15</figref> filled. Thereby is in each of the channels <figref>2</figref> a electrically conductive implementation produced the off the electrically conductive first and second materials <figref>9</figref> and <figref>15</figref> composed and from the first major surface <figref>3</figref> to to the second main surface <figref>4</figref> of Semiconductor substrate <figref>1</figref> extends.

0063The electrically conductive second material <figref>15</figref> is above its Melting temperature in the channels <figref>2</figref> filled. The To fill the second portions <figref>12</figref> with the electrically conductive second material <figref>15</figref> is also carried out at a relative Negative pressure. The above in connection with the filling of the first portions<figref>11</figref> described Process steps can in a corresponding manner during filling the second portions <figref>12</figref> be performed. It should be noted, that due to the smaller second cross-sectional area <figref>8th</figref> in the second portions <figref>12</figref> a higher inflation pressure can be adjusted have to be.

0064For the electrically conductive second material <figref>15</figref> are particularly suitable metals and alloys. The electrically conductive second material<figref>15</figref> becomes especially chosen to that it has a melting point temperature which is less than that the electrically conductive first material <figref>9</figref>, Thus, be avoided, that the electrically conductive first material <figref>9</figref> during the filling of the electrically conductive second material <figref>15</figref> in the second sections <figref>12</figref> melted by excessive heating. The electrically conductive second material <figref>15</figref> is especially so selected that there is no low-melting eutectic alloy or with the electrically conductive first material <figref>9</figref> forms. In principle, suitable for the electrically conductive second material <figref>15</figref> the metals, alloys, Hard and soft solders, the above for the electrically conductive first material <figref>9</figref> were called. Exemplary the following combination may be mentioned: For the electrically conductive first material <figref>9</figref> is eg AgCu (mp.: about 780 ° C) used and for the electrically conductive second material <figref>15</figref> z. B. SnAgCu (Melting point: about 250 ° C).

0065The Semiconductor substrate <figref>1</figref> , during the in <figref>2</figref> shown Process steps to be part of a semiconductor wafer. This makes it possible the electrically conductive feedthroughs for many produce semiconductor chips simultaneously. Only in a later process step the semiconductor wafer is divided into a plurality of semiconductor chips, for example by sawing.

0066In front or after the preparation of the electrically conductive from the two materials <figref>9</figref> and <figref>15</figref> existing penetrations can on the semiconductor substrate <figref>1</figref> integrated component are applied. It can Process steps are carried out, by transistors, diodes or other circuit elements or sensor elements or micromechanical elements to the semiconductor substrate <figref>1</figref> integrated will.

0067alternative or additionally, can additional substrates with or without integrated circuits on the substratum <figref>200</figref> be applied. In this manner, a high packing density can be achieved.

0068In <figref idrefs="S38">3D</figref> is schematically the substrate <figref>300</figref> as another embodiment shown. In the<figref idrefs="S37">3A</figref> to <figref idrefs="S38">3D</figref> are Steps for producing the substrate <figref>300</figref> shown. The substratum <figref>300</figref> and its preparation are essentially the in <figref>2</figref> shown substrate <figref>200</figref> and the production thereof. In contrast to the substrate<figref>200</figref> point the channels <figref>2</figref> of substrate <figref>300</figref> However, not only the first and second portions <figref>11</figref> and <figref>12</figref>. but in addition, each a third section <figref>16</figref> with a third Cross sectional area <figref>17</figref> on. The third cross-sectional area <figref>17</figref> can from the first and second cross-sectional areas <figref>6</figref> and <figref>8th</figref> of the first and second sections <figref>11</figref> and <figref>12</figref> differ. Here, the third cross-sectional area <figref>17</figref> especially greater than the second cross sectional area <figref>8th</figref>. but smaller than the first cross-sectional area <figref>6</figref>, If the above electrochemical etching for the production of the blind holes <figref>10</figref> applied is, the etching current is for the generation of the third portions <figref>17</figref> correspondingly varied.

0069The To fill the channels <figref>2</figref> of substrate <figref>300</figref> with the electrically conductive first material <figref>9</figref> carried out as described above at a relative vacuum. In this case, the Pressure in the process chamber is set so that the melt of the electrically conductive first material <figref>9</figref> of the first major surface <figref>3</figref> of Semiconductor substrate <figref>1</figref>To which the third portions <figref>16</figref> adjoin, in the channels <figref>2</figref> here penetrates and the second portions <figref>12</figref> not with the melt filled (cf.. <figref idrefs="S38">3C</figref>). The pressure during the filling of channels <figref>2</figref> With the electrically conductive first material <figref>9</figref> must therefore be set such that the limit pressure of the filling third portions <figref>16</figref> has already exceeded the limit pressure for To fill the second portions <figref>12</figref> is not yet reached.

0070On Advantage of the substrate <figref>300</figref> to the substrate <figref>200</figref> is, that the electrically conductive first material <figref>9</figref> after this Introducing in the channels <figref>2</figref> again can be melted. In a subdivision of channels<figref>2</figref> in only two sections as in the substrate <figref>200</figref> would a Melting of the electrically conductive first material <figref>9</figref> in the channels <figref>2</figref> to to lead, that the melt from the channels <figref>2</figref> out would run. Due to the narrowing of the channels <figref>2</figref> in the substrate <figref>300</figref> to two main surfaces <figref>3</figref> and <figref>4</figref> out the electrically conductive first material <figref>9</figref> at a remelted from the channels <figref>2</figref> not leak. Such melting of the electrically conductive first material <figref>9</figref> can occur in various process steps, in which a temperature above the melting temperature of said electrically conductive first material <figref>9</figref> prevails.

0071In <figref idrefs="S40">4D</figref> is schematically the substrate <figref>400</figref> as another embodiment shown. In the<figref idrefs="S39">4A</figref> to <figref idrefs="S40">4D</figref> are Steps for producing the substrate <figref>400</figref> shown. in the Difference to the substrates <figref>200</figref> and <figref>300</figref> will at the substrate <figref>400</figref> no blind holes <figref>10</figref> with varying Cross-sections in the semiconductor substrate <figref>1</figref> brought in. Rather, the blind holes <figref>10</figref> a constant cross sectional area on. Only the top<figref>18</figref> the blind holes <figref>10</figref> is tapered. The rejuvenation the top <figref>18</figref> may be due to manufacturing, for example, results in such a taper in an etching process or by drilling, and can be used for preparation of the substrate <figref>400</figref> be exploited. After the production of the blind holes <figref>10</figref> will this by a material removal from the second main surface <figref>4</figref> ago opened. As in <figref idrefs="S39">4B</figref> As shown, there is only so much semiconductor material on the second main surface <figref>4</figref> ablated until the tips <figref>18</figref> the blind holes <figref>10</figref> are reached. Since the tips <figref>18</figref> rejuvenated are concerns in the area of ​​the tips <figref>18</figref> a section with a smaller cross-sectional area. This smaller cross-sectional area can as well as the substrate <figref>200</figref> as pressure-dependent barrier while the filling the channels <figref>2</figref> With the electrically conductive first material <figref>9</figref> be used (see. <figref idrefs="S40">4C</figref>).

0072Opening the blind holes <figref>10</figref> from the second main surface <figref>4</figref> out For example, by a CVD process, and possibly a previous lithographic patterning are performed. alternative can also be the semiconductor material on the second main surface <figref>4</figref> mechanically be applicable sanded until the tips <figref>18</figref> the blind holes <figref>10</figref> reached are.

0073There it in the manufacture of the substrate <figref>400</figref> not mandatory is the cross-sectional area the blind holes <figref>10</figref> to vary, can next to the electrochemical etching also techniques for creating the blind holes <figref>10</figref> applied are, in addition to the rejuvenation in the top <figref>18</figref> the blind hole <figref>10</figref> no cross-sectional area variation would allow. Besides etching techniques count this example, mechanical drilling, sandblasting, ultrasonic drilling and laser drilling.

0074As in <figref idrefs="S40">4D</figref> is shown, the exposed tips <figref>18</figref> of the blind holes <figref>10</figref> just like that as in the substrate <figref>200</figref> with the electrically conductive second material <figref>15</figref> filled will.

0075In <figref idrefs="S42">5D</figref> is schematically the substrate <figref>500</figref> as another embodiment shown. In the<figref idrefs="S41">5A</figref> to <figref idrefs="S42">5D</figref> are Steps for producing the substrate <figref>500</figref> shown. As in <figref idrefs="S41">5A</figref> is shown, for the preparation of the substrate <figref>500</figref> uniform channels <figref>2</figref> without Varying their cross-sectional area in the semiconductor substrate <figref>1</figref> brought in. The channels may, for example, by drilling, punching, etching or other techniques can be generated. Then, on the second main surface<figref>4</figref> of Semiconductor substrate <figref>1</figref> an insulating material <figref>19</figref>. z. B. SiO₂ or Si₃N₄Deposited. This can, for example, by sputtering or CVD process happen. While the deposition of the insulating material <figref>19</figref> rearranges the insulating material <figref>19</figref> not only on the second main surface <figref>4</figref> rather also in the edge region to the second main surface <figref>4</figref> on the surfaces of channels <figref>2</figref> from and generates in the edge region to the second main surface <figref>4</figref> a Narrowing of the channels <figref>2</figref>, These Constriction, as in the <figref idrefs="S42">5C</figref> and <figref idrefs="S42">5D</figref> shown is back as a pressure-dependent Barrier to the filling the channels <figref>2</figref> With the electrically conductive first material <figref>9</figref> be used. The starting substrate <figref>1</figref> may in the present case, for. B. used microchannel glass or partially oxidized silicon will.

0076In the <figref idrefs="S43">6A</figref>. <figref idrefs="S43">6B</figref> and <figref idrefs="S43">6C</figref> schematically the substrates <figref>600A</figref>. <figref>600B</figref> and <figref>600C</figref> as more embodiments shown. substrates<figref>600A</figref> to <figref>600C</figref> consist each consisting of stacks of semiconductor substrate layers <figref>20</figref> to <figref>23</figref>, In the single semiconductor substrate layers <figref>20</figref> to <figref>23</figref> are each channels, for example by etching, Drilling, punching or other techniques, has been generated and the semiconductor substrate layers <figref>20</figref> to <figref>23</figref> are one above the other been stacked such that their respective channels are overlaid and create channels that from the first major surface <figref>3</figref> by the stack to the second main surface <figref>4</figref> towards extending.

0077there can be provided that the channels in the semiconductor substrate layers <figref>20</figref> to <figref>23</figref> different Cross-sectional areas exhibit. For example, in the substrate<figref>600A</figref> the cross-sectional area of ​​the channels in the Semiconductor substrate layer <figref>23</figref> smaller than in the remaining semiconductor substrate layers <figref>20</figref> to <figref>22</figref>, Thereby is to the major surface <figref>4</figref> down a narrowing of the channels extending through the stack <figref>2</figref> generated, as pressure-dependent Barrier during filling the channels <figref>2</figref> With the electrically conductive first material <figref>9</figref> be used can.

0078Further can, as in the substrate <figref>600B</figref> a semiconductor substrate layer <figref>22</figref> different Cross-sectional areas exhibit. In which, in<figref idrefs="S43">6B</figref> example shown causes this means that the center channel <figref>2</figref> only to the semiconductor substrate layer <figref>21</figref> With the electrically conductive first material <figref>9</figref> is filled.

0079Of Furthermore, as in the substrate <figref>600C</figref> be provided, that the constriction of the channels <figref>2</figref> either on the side of the first main surface <figref>3</figref> (Medium and right channel in <figref idrefs="S43">6C</figref>) Or on the side of the second major surface <figref>4</figref> (Left channel in <figref idrefs="S43">6C</figref>) Is arranged. Accordinglywill the channels <figref>2</figref> either from the first major surface <figref>3</figref> (Left channel in <figref idrefs="S43">6C</figref>) Or from the second main surface <figref>4</figref> (medium and right channel in <figref idrefs="S43">6C</figref>) From the first electrically conductive material <figref>9</figref> filled.

0080The Fixing the semiconductor substrate layers <figref>20</figref> to <figref>23</figref> among themselves can be done for example by bonding, diffusion soldering or other techniques.

0081In the <figref idrefs="S43">6A</figref> to <figref idrefs="S43">6C</figref> is the filling the narrowed regions of the channels <figref>2</figref> With the electrically conductive second material <figref>15</figref> not shown. This can in a corresponding manner as in the substrate <figref>200</figref> happen.

0082<figref idrefs="S44">7</figref> shows schematically a semiconductor module <figref>700</figref> to a substrate <figref>701</figref>. one carrying <figref>702</figref> from the first major surface <figref>703</figref> to second main surface <figref>704</figref> having. The implementation <figref>702</figref> is prepared by one of the methods described above, z. B. as in the in the <figref idrefs="S35">2A</figref> to <figref idrefs="S36">2E</figref> shown substratum <figref>200</figref> (The narrowing of the channel and performing <figref>702</figref> is in <figref idrefs="S44">7</figref> not shown). substrate<figref>701</figref> is z. B. a silicon chip and responsive to said first and second major surfaces <figref>703</figref>. <figref>704</figref> of substrate <figref>701</figref> applied insulation layers <figref>705</figref> on Oxide.

0083On the oxide layer <figref>705</figref> is the back side of an integrated Semiconductor device <figref>706</figref>That on the front of a integrated circuit <figref>707</figref> having, with an adhesive <figref>708</figref> glued been. The semiconductor device<figref>706</figref> is by a bonding wire <figref>709</figref>. of a bond pad <figref>710</figref> of the semiconductor component <figref>706</figref> to a bond pad <figref>711</figref> the substrate <figref>701</figref> leads, with the substrate <figref>701</figref> electrically connected. The bond pad<figref>711</figref> the substrate <figref>701</figref> is in the present case directly to the bushing <figref>702</figref> the substrate <figref>701</figref> been applied. By this, the bonding wire <figref>709</figref> directly to an external contact <figref>712</figref>. in this case, a solder ball <figref>712</figref>, connected.

0084The Contacting the bond pad <figref>711</figref> the implementation <figref>702</figref> happens to the person skilled in well-known manner: first, the oxide layer must <figref>705</figref> on the first major surface <figref>703</figref> at the place of carrying out <figref>702</figref> be opened. This can by etching selectively to a photolithographically produced mask (not shown) happen. subsequently a metal layer, eg., aluminum, to the oxide layer <figref>705</figref> upset and photolithographically structured such that a wire for a compound <figref>711</figref> sufficient great layer element <figref>711</figref> remains.

0085The Contacting the solder ball <figref>712</figref> is analogous in a known to the expert way: you must first oxide layer <figref>705</figref> on the second main surface <figref>704</figref> at the place of carrying out <figref>702</figref> be opened. This can be achieved by etching selectively to a photolithographically produced mask (not shown) happen. subsequently is the second main surface <figref>704</figref> With brought a Kupferlotschmelze in contact, so that the copper solder the surface performing <figref>702</figref> wetted. After cooling, remains a spherical globule <figref>712</figref> back.

0086<figref idrefs="S44">8th</figref> shows schematically another semiconductor module <figref>800</figref> with a substratum <figref>701</figref>, The two bushings <figref>702</figref> of the first major surface <figref>703</figref> to second main surface <figref>704</figref> having. The semiconductor module <figref>800</figref> is like that of <figref idrefs="S44">7</figref> built up. however has the present semiconductor module <figref>800</figref> in contrast to <figref idrefs="S44">7</figref> two integrated components <figref>706A</figref>. <figref>706B</figref>. with their front sides, ie with the side with the integrated circuits <figref>707A</figref>. <figref>707B</figref>To the substrate <figref>701</figref> upset have been. The electrical connection to the substrate<figref>701</figref> takes place in not about this case bonding wires but over Lotkugelkontakte <figref>713</figref>. which the bond pads of the integrated components <figref>706A</figref>. <figref>706B</figref> With on the substrate <figref>701</figref> applied conductor tracks <figref>714</figref> connect. This bonding method is also known under the term "flip-chip blanks" known and should not be further explained will.

0087As one <figref idrefs="S44">8th</figref> can be found, run some interconnects <figref>714</figref> directly via feedthroughs <figref>702</figref> and associated with these electrically conductive. is In this way, it is possible to Bonding pads of the integrated components <figref>706A</figref>. <figref>706B</figref> on the bushings <figref>702</figref> directly one of the external contacts <figref>712</figref> to to lead. This saves long interconnects and improves signal transmission, especially at high frequencies.

0088furthermore you can <figref idrefs="S44">8th</figref> found that some interconnects <figref>714</figref> so extend to the bond pads of an integrated component <figref>706A</figref> with those of the integrated device <figref>706B</figref> connect. In this manner, different integrated circuits <figref>706A</figref>. <figref>706B</figref> together be connected, without this further external contacts <figref>712</figref> require. Thus, integrated circuits can be packed more densely.

0089It be noted that the embodiments of <figref idrefs="S44">7</figref> and <figref idrefs="S44">8th</figref> silicon wafers or silicon chips as a substrate <figref>701</figref> have. This has the Advantage that the temperature expansion coefficient (CTE) of the substrate <figref>702</figref> of the same is prepared as the mostly also based on silicon integrated circuits. This helps mechanical stresses between the substrate <figref>702</figref> and the integrated component <figref>706</figref> to to reduce. Further, silicon, compared to eg. As a ceramics, a good thermal conductivity, the integrated by the Circuits generated heat effectively dissipate. Furthermore, leaves the etching of blind holes particularly effective to perform electrochemical way with silicon.

0090<figref idrefs="S44">9</figref> shows schematically another semiconductor module <figref>900</figref> with a substratum <figref>701</figref>, The implementation of a <figref>702</figref> of the first major surface <figref>703</figref> to second main surface <figref>704</figref> having.

0091The Semiconductor Modules <figref>900</figref> is like that of <figref idrefs="S44">7</figref> built up. However, in contrast to <figref idrefs="S44">7</figref> integrated circuit <figref>707</figref> into the substrate <figref>701</figref> itself integrated. In <figref idrefs="S44">9</figref> For example, a transistor <figref>715</figref> shown. Source S and drain D of the transistor <figref>715</figref> are by doping the monocrystalline silicon substrate <figref>701</figref> generated while the Gate G by a thermal oxidation, for. Example in the production the insulation layer <figref>705</figref> is created, is generated. <figref idrefs="S44">9</figref> shows further interconnects <figref>714</figref>That the source S to the implementation <figref>702</figref> connect and / or each contact, the gate G and the drain D. The implementation<figref>702</figref> allows to Thus, short connections to the active and passive components the integrated circuits (resistors, transistors, diodes, coils, Capacitors, etc.) to the external terminals. This saves long pathways and therefore the need for multiple interconnect layers.