Process for producing contact holes on a metallization structure

The This invention relates to a process for the production of contact holes on a metallization, the example for the production of electrical contacts between adjacent metallization can be used advantageously.

at the manufacture of integrated circuits are usually the electrical cables housed in more metallization, wherein the metallization by a dielectric material ( "Interlayer dielectric", "ILD") isolated from each other will. To provide electrical contacts between the individual metallization contact holes in the dielectric open material and filled with an electrically conductive material.

The <patcit><text>US 6207554 B1</text></patcit> shows in the <figref>3</figref> and <figref>4</figref> on A method for producing a dielectric layer of low permittivity and subsequently to etch a fully landing contact hole on the interconnects, which with sections a single- or multilayer hard mask covered. The method to etch extends the contact hole two stages, the Ätzgasmischungen specified obviously the other layer etch. Out <figref>4b</figref> It can be seen that the contact holes on the Top of the conductor tracks have been etched out continuously. It will not determined if the hard mask layer is achieved by the first etching step, to end then.

In of the <patcit><text>US 6174800 B1</text></patcit> becomes a two-step etching method described in which during the first etching step the contact Loche is etched through the dielectric layer and in the second etching step one on the conductor as an etch stop etched applied covering becomes. For the second stage is sputtering with argon, so no selective etching method, indicated. Attainment of the etch stop layer not found.

In of the <patcit><text>US 5700737 A</text></patcit> becomes a two step process for etching a contact hole indicated. The first etching step is carried out selectively to the underlying etch-stop layer so that the etching time not is critical. Reaching the hard mask layer is not detected.

In of the <patcit><text>US 4943539</text></patcit> becomes a method of two-step etching vias described. In this method, an additional etch stop layer as is serving sacrificial layer over the conductor tracks are arranged, which leads selectively to the conductor paths and isotropic etching is to the landing area the contact holes, enlarge. Of the second etching step non-selectively to the dielectric layer, as in the <figref>3</figref> and <figref>4</figref> shown is, there rückgesputtertes Material from the Kontaktlochinnnenfläche in the dielectric layer Will get removed.

In JP 08-023028 A is an isotropic etch a on a conductor track deposited TiN layer to increase the land area described. It will not be noted that the TiN layer is reached.

at an increasing miniaturization of feature sizes and the integrated circuits result in generally the problem that subsequent metallization always accurate must be aligned with each other. In the lithographic imaging of a level to another can be but can not prevent a certain intrinsic defects alignment. whereas, by design, certain tolerances are installed, secured by the is that the tracks contacts a contact hole plane safely to the wire the underlying metallization can land.

On conventional A process for producing a contact hole on a metallization For example, in the <figref idrefs="S20">2A</figref> and <figref idrefs="S20">2 B</figref> shown.

In <figref idrefs="S20">2A</figref> numeral <figref>1</figref> an interconnect a metallization, numerals <figref>2</figref> remnants of Hard mask, which was used for patterning the conductor track, numeral <figref>3</figref> the dielectric material for isolation adjacent metallization and adjacent interconnects, numeral <figref>4</figref> a contact hole, and numeral <figref>5</figref> a Substrate surface, For example, a processed semiconductor wafer with Bauelement- and metallization, separated from each other by insulating layers are separated.

As in <figref idrefs="S20">2A</figref> shown, land the contact holes <figref>4</figref> by virtue of the misalignment of the etching mask for etching the The contact hole is not exactly on the interconnects, but it will displacement instead. place after the current state of lithography usually an offset in the range of 40 nm and in the worst Case an offset instead of more than 100 nm.

Becomes, as in <figref idrefs="S20">2 B</figref> shown, the contact hole <figref>4</figref> with an electrically conductive material <figref>6</figref> filled, so there the risk of short circuits between adjacent interconnects.

This Drawback has hitherto been minimized by the fact that the achievable overlap has been empirically determined between two lithography levels &lt;?page 3?&gt;and considered in the layout of circuit patterns in the way was that a corresponding metal overlap at an interconnect landing pad a contact was maintained. For a given size of the contact hole had to yet the area the underlying interconnect on all sides by a certain Value greater than be the landing contact.

This approach but is not compatible with a further miniaturization of feature sizes, because by him in particular a minimum distance between adjacent Conductor tracks is predetermined and the so-called routing pitch is larger. Specifically, must, so not a predetermined distance between the interconnect land surfaces is not reached, a considerable Minimum distance between adjacent interconnects are respected.

The <patcit><text>US 6015751 A</text></patcit> refers itself. The problem is not the country forming vias One with a second dielectric layer covered metallic layer is to strip conductors structured and with a conformally deposited third dielectric layer covered. subsequently depositing a fourth dielectric layer. The etching of the Contact hole is performed in three steps through each of the dielectric Layers, each of the dielectric layers selectively to the etched adjacent becomes. This method is disadvantageous in that in addition the required conformally deposited third dielectric layer is to avoid that the Contact hole lands on the first dielectric layer or that the contact hole adjacent interconnects touches.

Also in the <patcit><text>US 5451543</text></patcit> becomes addressed the problem no country forming contacts. In this document a conforming or non-conforming etch-stop layer is provided, as mentioned above, is disadvantageous. is also found in this publication are not an indication a step of recognizing that reaches the hard mask layer is, and end the first etching step.

The document <patcit><text>US 5935868</text></patcit> also describes a method of etching by not fully on the interconnects landed vias.

Of the the present invention is therefore the object of providing an improved A process for the production of contact holes to a metallization specify.

According to the present Invention the object is achieved by a method for forming contact holes on a metallization comprising the steps of: <ul><li>- Provide a metallization structure having at least one conductor track, which surface is a portion of a hard mask layer covered on a Substrate surface,</li><li>- applying a dielectric layer so that at least the surface of the a portion of the hard mask layer from the dielectric layer is surrounded, wherein the dielectric layer contains carbon and a includes other material as the hard mask layer,</li><li>- Etching vias through the dielectric layer during a first etching step, using a Ätzgasgemisches, the C₄F_8th containing and oxygen contains at a first concentration,</li><li>- Determine that the Hard mask layer is achieved, and stopping said first etching step, as soon as the hard mask layer is reached,</li><li>- below Carry out a second etching step using a Ätzgasgemisches, the C₄F_8th containing and oxygen contains a second concentration,</li><li>- Selectively etching the Hard mask layer with respect to the dielectric layer,</li><li>- in which the second concentration of oxygen is chosen so that the selectivity of etching the Hard mask layer is increased in relation to the dielectric layer. The schematic sequence of the method is in the <figref idrefs="S18">1A</figref> to <figref idrefs="S19">1D</figref> illustrated.</li></ul>

In <figref idrefs="S18">1A</figref> designated numeral <figref>5</figref> a substrate surface, such as a processed Semiconductor wafers usually Bauelement- and metallization used. However, it is obvious that the substrate surface and the surface any substrate, for example a glass or other Insulator substrate or a conductive substrate with may be applied insulating layer.

In <figref idrefs="S18">1A</figref> are the conductor tracks <figref>1</figref> the hard mask material <figref>2</figref> on the surface the conductor tracks <figref>1</figref> on the substrate surface <figref>5</figref> shown, the conductor tracks in the control of the underlying layers are electrically insulated by an insulating layer. Below certain feature sizes is done the structuring of the metal webs using a hard mask, which may consist of silicon dioxide, for example. A hard mask layer is constructed of a material which selectively to that for the metallization etched metal layer used can be and that is not a photoresist material, so no photoactive comprising component, and is preferably inorganic. The hard mask material can be dielectric, but it can also be conductive, for example, can also TiN are used as hard mask material.

ever after initial thickness of the mask and used etching process remains after the metal structure a residue of this hard mask as a "cover" of the traces left and is at deposition of the subsequent dielectric layer in these integrated. A cover of the conductors according to the present However, the invention also be made by alternative methods.

Thereon the following is, as in <figref idrefs="S18">1B</figref> shown, a dielectric layer <figref>3</figref> on the metallization <figref>1</figref> With the hard mask layer <figref>2</figref> applied, wherein the dielectric layer <figref>3</figref> of a different material than the hard mask layer <figref>2</figref> consists, So that the surfaces the portions of the hard mask layer <figref>2</figref> full of the dielectric layer <figref>3</figref> be covered.

Subsequently a two step process for etching the contact holes, <figref>4</figref> performed. First of the contact holes <figref>4</figref> in the dielectric material <figref>3</figref> etched, whereby this step is completed, as soon as the hard mask layer <figref>2</figref> is reached. This can for example, by a timer or by an automatic Endpoint detection occur. Then, the hard mask layer<figref>2</figref> selectively with respect to the dielectric layer <figref>3</figref> etched. The called, there is an etching method applied, which only the hard mask layer <figref>2</figref>, no but the dielectric layer <figref>3</figref> etched. This is a breaking of the Contact hole toward the adjacent trace as in <figref idrefs="S20">2A</figref> shown, avoided, and it results in the in <figref idrefs="S19">1C</figref> illustrated Course of the contact hole. Characterized in that the second stage of the etching process, preferably partially isotropic done, also is the cross-sectional of the contact hole in comparison with the cross-section after completion the first stage is increased, that the electrical resistance of the completed contact remains low.

According to a preferred embodiment of the present invention, the second stage of the etching process, partially isotropic, that is, not with exactly the same etch rate perpendicular in all directions, but with a greater etch rate in a direction to the substrate surface than in a direction parallel to the substrate surface, wherein the relative etch rate parallel to the substrate surface is greater than in the direction at the first stage the etching process is. As a result, increases the cross-section of the contact holes in the direction of the substrate surface.

As in <figref idrefs="S19">1D</figref> shown, is below the contact hole with an electrically conductive material <figref>6</figref>, especially Metal filled. It is clear to see that due to the two-step etching method, wherein during the second etching step selectively etched is the risk of short circuits is drastically reduced.

The the present invention underlying concept can in many Process variants can be realized. The important thing is that right arranged on the conductor tracks sections of a hard mask material are derived from the dielectric material that at least the surfaces the hard mask material completely Is covered different, so that the two-step etching method as described above accomplished can be.

For example can the conductor paths are structured by a method, according to the Metal layer over the entire surface is applied, then a hard mask material <figref>2</figref> applied and photolithographically is structured and finally the metal layer for example, by a reactive ion etching etched is so that the in <figref idrefs="S18">1A</figref> Structure shown results. After Applying the dielekrischen layer also results in the <figref idrefs="S18">1B</figref> shown Layer structure.

According to the present Invention, the dielectric layer of a so-called low-k material be constructed, that is of a material having a low dielectric constant, include, for example lower than 4. Examples of such materials carbon doped silicon oxide (SiCOH), the example by a CVD method is deposited, doped with halogens such as fluorine Silicon oxide, spin-on polymer films and others which will generally known are.

The Use of such low dielectric constant materials is particularly advantageous in that they allow the mutual can minimize capacitive coupling of the conductor tracks.

As Hard mask layer are, in particular dielectric materials such as SiO₂, Si₃N₄, SiON and more into consideration. However, it also conductive layers such as TiN may be used.

It However, it is apparent that the present invention with any combination of hard mask and dielectric layer can be made as long as the Hartmas identifier and dielectric layer are different from each other and the hard mask layer selectively in relation to the dielectric layer etched can be.

A total of be by the inventive process the following benefits provided: <ul><li>- Thereby, that during the second etching step the Hard mask layer is selectively etched to the dielectric layer, is a breaking of the contact hole in the dielectric layer prevented; shorts between adjacent &lt;?page 5?&gt;Conductor tracks or contact holes are avoided.</li><li>- As result can Interconnects are densely arranged without the performance and reliability compromising.</li><li>- If the second etching step partially isotropic occurs, it is possible, a contact hole diameter to reach the bottom of the contact hole which is approximately the original lithographically corresponding defined. Thus, the misalignment of the mask lithography balanced. Further, the contact surface between the contact hole and Trace over not landing contacts in which a horizontal portion of the Contact hole does not land on an interconnect, enlarged, creating the terminal resistance is reduced and the nucleus formation during the application of the electrically conductive bonding material is facilitated.</li><li>- The but misalignment of lithography mask is substantially also compensated when the second etching step does not take place isotropically, since in this case an error-free contacting of the conductors takes place.</li><li>- According Is it possible, the requirements to relax regarding the overlay, which means less Reworking of lithography is required and ultimately the manufacturing cost can be reduced.</li><li>- Of Furthermore, the distances the conductor paths are reduced to each other without shorts are to be feared.</li></ul>

The present invention is described below with reference to the accompanying drawings explained will.

<figref idrefs="S18">1A</figref> to <figref idrefs="S19">1D</figref> illustrate schematically illustrates the steps of the inventive method for generating contact holes;

<figref idrefs="S20">2A</figref> and <figref idrefs="S20">2 B</figref> illustrate schematically illustrates the steps of the conventional process for producing contact holes; and

<figref idrefs="S21">3A</figref> to <figref idrefs="S22">3D</figref> illustrate schematically an embodiment of the present invention.

On a substrate surface <figref>5</figref> becomes first a Metallization of an aluminum-copper alloy is formed, by first through known methods a AlCu layer with a slight addition of copper the whole area of ​​about 0.5% is deposited. Then, as a hard mask material a SiO₂Layer over the whole area. After applying a photoresist layer by photolithography using this structured a mask, then is by known methods initially Hard mask layer <figref>2</figref> using the resultant resist mask etched subsequently the photoresist layer is removed, and then a reactive ion etching to etch the AlCu layer on the exposed areas and a passivation treatment the conductor tracks generated carried out so that the finally in <figref idrefs="S18">1A</figref> Structure shown results. This leaves a Layer thickness of the hard mask material of about 100 to 150 nm (nanometers).

Thereon Following the novel process is for the production of contact holes Duch performed in the just-created metallization. First by a CVD method as a dielectric layer <figref>3</figref> for isolating adjacent Metallization with carbon-doped SiO₂ deposited which because of its low dielectric constant a so-called low-k dielectric. The use of this dielectric is particularly advantageous because it is easy to integrate and has high GaPFilL properties. The dielectric layer <figref>3</figref> is applied so that the spaces between adjacent interconnects completely padded be and eventually which interconnects with the remnants of the hard mask material <figref>2</figref> With the dielectric layer <figref>3</figref> are covered, so that adjacent Metallization planes are electrically isolated from each other, as in <figref idrefs="S21">3A</figref> is shown.

Typically is now using chemical-mechanical polishing (CMP), the resultant surface polished to compensate for differences topography and the surface of the dielectric layer <figref>3</figref> flatten.

Subsequently to define the contact holes first a photoresist material <figref>7</figref> over the entire surface, which subsequently is patterned by photolithography using a mask, as in <figref idrefs="S21">3B</figref> is shown. In this case, a misalignment not avoid the mask in general, so that the in the photoresist material <figref>7</figref> generated vias towards the Lateral interconnects can also be easily moved. The misalignment is thereby typically about 30 to 80 nm. Then, the step to etch vias <figref>4</figref> by the dielectric layer <figref>3</figref> performed as in <figref idrefs="S22">3C</figref> shown is. This step is terminated as soon as the hard mask material is reached; but it is not necessarily selective to the Hard mask material is etched. Usually by a dry etching, for example, with C₄F_8th in an Ar / O₂/ C₄F_8th/ N₂Plasma, either automatic endpoint detection or etched after a preset etching time. at Using this etchant gas the selectivity etching on the Oxygen content of the etching be adjusted. The larger the Oxygen content more &lt;?page 6?&gt;greater than the etching rate for the C-doped SiO₂,

The etching process can be carried out isotropic or anisotropic in which an anisotropic etching process, in which substantially perpendicular contact hole walls or but a slightly tapered Via diameter tweak with a difference in diameter top and bottom diameter of about 30 nm yield, preferably is. is typically the via diameter at the bottom depending on the metallization technology generation and about 150 to 300 nm.

thereupon is an etching method, the hard mask layer <figref>2</figref> selective with respect to the dielectric layer <figref>3</figref> etched, conducted as in <figref idrefs="S22">3D</figref> is shown. For example can SiO₂ as a hard mask material using the Ätzgasgemisches used above of C₄F_8th in an Ar / O₂/ C₄F_8th/ N₂-Plasma selective with respect to carbon-doped SiO₂ are etched. The selectivity of the etching amounts to For example, 4: 1, ie was on Blank discs an etch rate of SiO₂ measured from about 360 nm / min, while the etching rate of Carbon-doped SiO₂ about 80 nm / min. The selectivity etching can about the O₂Content can be controlled in the etching gas and is for a O₂Stake of 0 greatest.

to selective etching can However, other fluorine-containing etching gases be used.

This selective etching step is preferably carried out partially isotropic, so that the landing area on the Interconnects is increased, whereby the contact resistance is reduced and depending on the used electrically conductive bonding material facilitates nucleation becomes. After completion of the etching vias the remaining photoresist mask <figref>7</figref> removed from the surface.

The Contacting is ended in that an electrically conductive Material, such as tungsten, by known processes in the etched contact holes is filled. For this, first by Sputtering a Ti / TiN liner as a bonding agent deposited. Subsequently Tungsten deposited by a CVD method, and the excess material contact hole of tungsten and Ti / TiN is polished off, such that only conducting material in the contact holes remains.