Method of instruction sequence processing and device for this method realization

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The following related applications are "on-line lawyers and are incorporated." The technical equipment of potrvt-a_cu was filed on Apr. 4, 1990, and the technician with Lfri-erTTi nt tau ^: The data dependence of the data 20 and the universal process N990019 filed May 4, 1990, ser. No. 07/519 ,. Technology

The invention relates generally to parallel processing by an instructional computer and in particular relates to the processing of a flow of instructions for identifying those instructions that can be issued and operated in parallel in a specific configuration of the computer system. ad._st av_tvni k ^

The concept of parallel execution of instructions helped to increase the performance of computer systems. Parallel implementation is based on the existence of separate functional units that can simultaneously perform two or more same unborn instructions.

Another technique used to improve the performance of computer systems is chained processing. Chained processing is generally achieved by dividing the function performed by the calculator into independent sub-functions and by including a separate component of the technical equipment or the step to perform each sub function. Each step is defined for the timing of one clock. Chained processing provides a form-parallel processing, since multi-step instructions can be performed simultaneously. Ideally, one new instruction can be inserted into a chained line in one cycle, where instructions in a chained line are in a different The operation is analogous to translation from the language of the symbolic addresses, with a number of instances of processing the product in different stages of assembly.

However, the success of parallel and / or chained processing is often not achieved due to delays caused by interlocking during data transfer and interlocking interference depending on the instrumentation technique. An example of a reciprocal blocking, depending on the data, is the so-called "write-read" block, where the first instruction must write its result before the second instruction can be read and then used. An example of a mutual blocking technique is where the first instruction must take the special component of the technical equipment and the second instruction must also use the same special component of the technical check.

One of the previously used techniques for blocking mutual blocking (sometimes called chained ha-zards) is dynamic layout. Dynamic scheduling is based on the fact that by inserting special technical equipment, it is possible to shift the instruction sequences after the dwells are delivered to the chained design.

Several attempts have also been made to increase the effectiveness of the so-called static layout, which is done before the instruction flow is recalled from memory. Static scheduling is accomplished by moving the code and shifting the instruction sequence before the calculation. All recipients will create an equivalent flow of instructions that will make the most of technical equipment using parallel processing. Such static scheduling is typically performed by compile time. However, the redistributed instructions remain the same in their original form, and normal parallel processing still requires some form of dynamic determination just before instructing the instructions to decide whether to perform the two most detailed instructions serially or in parallel.

Such scheduling techniques can improve the overall performance of a chained computer, but can not itself satisfy the persistent existing performance requirements. In this respect, many modern designs for universal computing address the use of the instructional level beyond that achieved by the chaining. For example, additional parallelism of the instructional level has been achieved explicitly by issuing multiple in-fractions in one cycle, so-called superscalar machines, rather than by implicitly dynamic scheduling of individual or vector machines. The superscalar name for machines that issue multiple instructions in a single cycle is to distinguish them from scalar machines that issue one instruction per cycle. In a typical supercomputer, the operating codes are decoded and analyzed by the instruc- tional instructional logic to instruct the instructed stream in order to determine the linkage can be performed in parallel. Criteria for such dynamic scheduling in the last minute are specific to each instruction file architecture, as well as to the implementation of this architecture in any given instruction processing unit. Its effectiveness is therefore limited by the complexity of the logic to determine which combination of operations can be performed in parallel, and the cycle time of the unit for processing the instruction is rather increased. Enhanced technical equipment and cycle time of these superclasses becomes even a major problem in architectures that have hundreds of different instructions. With dynamic scheduling, static layout, or a combination of these, there are other drawbacks. For example, each scalar instructor must be reconsidered each time it is invoked to make a decision whether it is fit for parallel execution. There is no provision for identifying and marking pre-tactical instructions / which are suitable for parallel transitions. There is no provision for identifying and timely identifying in advance those scalar instructions / which are capable of parallel execution.

Another lack of dynamic layout in the execution of superscalar machines is the way in which scalar constructions are tested for possible parallel processing. Super scalar machines test scalar instructions on the basis of their operating code and there is no provision to take into account the technical means of the computer. In-Structures are also issued by the "First Ranked, First Selected" method, eliminating the ability to create groups to prevent or reduce interlocking. Several technical solutions have taken into account the requirements of the technical equipment for the parallel processing of the instruction. One such solution is for the machine to process very long instruction words, in which the powerful compiler translates the instructions so that it simplifies the layout of the instruction by technical means. In this approach, the compiler must be more complex than standard compilers, so a larger window can be used to find a larger number of parallels in the instruction sheet. The resulting instructions can not necessarily be the destination code that is compatible with the existing architecture, so one problem has been resolved while creating new problems. In essence, other problems also arise in view of the frequent branching that limits its parallelism. Thus, none of the prior art procedures are close to parallel parallel processing to be sufficiently comprehensible to minimize all possible interlocking while simultaneously preventing the new 5 major design of the instruction file structure and eliminating the complex logical circuits for dynamic decoding of the instructions invoked. so a larger window can be used to find a larger number of parallels in the instruction sheet. The resulting instructions can not necessarily be the destination code that is compatible with the existing architecture, so one problem has been resolved while creating new problems. In essence, other problems also arise in view of the frequent branching that limits its parallelism. Thus, none of the prior art procedures are close to parallel parallel processing to be sufficiently comprehensible to minimize all possible interlocking while simultaneously preventing the new 5 major design of the instruction file structure and eliminating the complex logical circuits for dynamic decoding of the instructions invoked. so a larger window can be used to find a larger number of parallels in the instruction sheet. The resulting instructions can not necessarily be the destination code that is compatible with the existing architecture, so one problem has been resolved while creating new problems. In essence, other problems also arise in view of the frequent branching that limits its parallelism. Thus, none of the prior art procedures are close to parallel parallel processing to be sufficiently comprehensible to minimize all possible interlocking while simultaneously preventing the new 5 major design of the instruction file structure and eliminating the complex logical circuits for dynamic decoding of the instructions invoked. The resulting instructions can not necessarily be the destination code that is compatible with the existing architecture, so one problem has been resolved while creating new problems. In essence, other problems also arise in view of the frequent branching that limits its parallelism. Thus, none of the prior art procedures are close to parallel parallel processing to be sufficiently comprehensible to minimize all possible interlocking while simultaneously preventing the new 5 major design of the instruction file structure and eliminating the complex logical circuits for dynamic decoding of the instructions invoked. The resulting instructions can not necessarily be the destination code that is compatible with the existing architecture, so one problem has been resolved while creating new problems. In essence, other problems also arise in view of the frequent branching that limits its parallelism. Thus, none of the prior art procedures are close to parallel parallel processing to be sufficiently comprehensible to minimize all possible interlocking while simultaneously preventing the new 5 major design of the instruction file structure and eliminating the complex logical circuits for dynamic decoding of the instructions invoked.

What is needed is a more perfect numbering of data processing, which facilitates the parallel implementation of existing machine instructions to increase the efficiency of the processor. Since the number of instructions executed per second is the product of the basic CPU cycle time and the average number of cycles required to complete the instruction, a solution must be found that takes into account both of these parameters. More specifically, there is a need for a mechanism that reduces the number of cycles required to execute the instruction for a particular architecture. In addition, there is a need for some improvement, which would reduce the complexity of the technical fitting necessary to support the parallel execution of the instruction, thus reducing any possible increase in the time cycle to a minimum.

The subject matter of the invention

Brief Contents and Objects of the Invention

In view of the above, it is an object of the present invention to provide a static analysis method prior to decoding and executing existing instructions, a sequence of existing instructions for generating compound instructions formed by adjacent groups of existing instructions capable of parallel execution. is the addition of the appropriate control information to the instruction flow including the group information indicating where the compound instruction begins, just as - 6 - the notification of the number of existing instructions that are incorporated in each compound instruction.

Another object of the invention is to analyze a large window syllabic syllable flow before the instruction is invoked, the window being adjustable to different positions in the syllabus instruction in order to obtain the optimal selective clustering of the adjacent adjacent instruction instructions.

A further object of the invention is to provide a method for compiling an instruction of the aforementioned characteristics that is applicable to complex instruction constructs with varying instruction lengths and with data mixed with instructions and which is also applicable to the chipset dispatched instruction architecture where the instructions are usually constant lengths and dates are not mixed with the instructions.

Another object is to provide a method of pre-processing the instruction flow to create compound in-structions, wherein the method can be implemented by program and / or non-technical equipment at various points of the computer system before decoding and executing the instruction. A parallel object is to create a pre-processing method of an existing instruction that handles the flow of binary instructions as part of a downstream compiler or portion of the input memory store, or as part of a buffer, the instruction handler unit, and which can be initiated by instructions at the beginning of the syllable flow , without knowing the limitations of the instructions.

The invention thus relates to a method for pre-processing the instruction flow to create compound instructions constructed from scalar instructions that still retain their original contents. Composite instructions consist of no changes to the object code of the scalar instructions, which constitute a composite instruction, allowing existing programs to perform an improvement in the performance of machines for the composition of the instrument while preserving compatibility with previously implemented scalar instruction machines.

More specifically, the invention provides a set of rules for composition based on the analysis of existing in-structions for the purpose of their division into different classes. Analysis determines which instructions I qualify for, with instructions in their own classes or with instructions in other classes, for parallel execution in a particular arrangement of technical means. Such compilation rules are considered a standard for pre-processing of in-stream flow to find groups of two or more-second scalar instructions that can be performed in parallel. In some cases, certain types of blocked in-struc- tures can be made in a parallel fashion where blocking a qualified association in a special configuration of technical means. In other arrangements where the blocking is non-associable, instructions,

Each composite instruction is identified by a control information such as a combination associated with a compound instruction, the length of the composite instruction being capable of transferring technical units over a wide range, starting with a set of two scalar instructions up to any maximum number that can be performed in parallel with the specific equipment. Since composition rules are based on identifying instruction classes rather than on individual instructions, there is no need for complex matrices to show all possible combinations of specific individual instructions. While their own sequence remains unaffected, the individual instructions are selectively populated and combined with one or more other adjacent 8 scalar instructions to create a compound instruction that contains scalar instructions, which still have a pre-metric code of compatibility with uncompleted scalar instructions. The control information is appended for identifying information about executing compound instructions.

These and other objects, features and advantages of the invention will become apparent to those skilled in the art with reference to the following detailed description and the accompanying drawings. Eshshid_photo_of_the_results

Fig. 1 is a diagram of a higher level of the invention.

Fig. 2 a time diagram of a sequential processor implementation illustrating the parallel execution of certain unblocked instructions that have been selectively grouped into tokusted instructions.

Fig. 3 time diagram of the implementation of a multiprocessor showing the parallel execution of scalar and compound instructions that are not mutually blocked.

Fig. 4 (shown as Figures 4A and 4B) illustrate an example of a possible selective sorting of the part of the instructions executed by the existing scalar machine.

Fig. 5 shows a typical program path from the source to the actual execution.

Fig. 6 is a flowchart showing the program generation of a composite instruction from a program in the assembler language.

Fig. 7 is a flow chart illustrating the execution of a composite instruction file program. 9

Fig. 8 is an analytical flow diagram for flow instruction instructions with identifiable instruction reference points.

Fig. 9 analytical flowchart for flow instruction instruction with variable length instruction without a reference point, showing their concurrent sets of possible composite identification bits.

Fig. 10 illustrates a logical realization of the ability to fold a tool for processing the instruction flow text as shown in Figure 9.

Fig. 11 is a flowchart for plotting a flow of instructions with reference marks to identify instructional reference points.

Fig. 12 shows an example of a composite instruction control field.

Fig. 13 a flowchart for derivation and application of folding rules applicable to the specific arrangement of the computer system hardware and its special architectural instruction set.

Fig. 14 shows how different clusters of valid unblocked pairs of the instruction form a multiple multiple instructional sequencing or branched target embodiment.

Fig. 15 shows how different clusters of valid unblocked triple instructions form multiple folded instructions for a sequential or branched target embodiment.

Fig. 16 (FIG. 16A and FIG. 16B) is a flowchart developmental schematic similar to FIG. 9, which includes variable length instructions without boundary reference points. 10

Fig. 17 is a diagram showing typical foldable instruction pair pairs for part of the System / 370 instruction set in FIG.

The essence of the present invention consists in pre-processing a set of instructions or a program to run a computer for static determination, which unblocked instructions are to be combined in a compound instruction, and the control information for the identifiable compound instructions is appended. Such determination is based on the rules of composition, which are elaborated as a toolkit of special architecture instructions. The existing scalar instructions are categorized on the basis of an analysis of its operation, use and function of the technical equipment, so that grouping the instruction by composition for reasons of exclusion by the blocking effect of the incompetence of pooling rests on the comparator of the instruction categories rather than the comparison of the specific instructions.

As shown in various drawings and in more detail described herein, the invention of the title "Computer for converting units of assembled instruction files" is intended for the flow of scalar instractions that need to be stacked or grouped together by pre-decoding the instruction so that they are already identified and identified for simultaneous parallel execution by the respective basic units. Since such a composition is non-volatile, existing programs can achieve performance improvements while maintaining compatibility with previously implemented systems.

The instruction assembly unit 20 in FIG. 1 takes over a stream of 21 binary scalar instructions (including or without the data contained therein) selectively grouping some adjacent scalar instructions to produce the coded compound-11 instructions. Thus, the resulting instruction stream 22 combines scalar instructions that are ineligible for parallel execution and sketches instructions made up of groups of scalar instructions that are suitable for parallel execution. When the instructional base unit 24 is provided with the instructions, the corresponding functional unit for serial execution is forwarded.

When a composite instruction is offered to the instruction base unit 24, each of its scalar components is forwarded to a respective functional unit or pooling unit by a simultaneous parallel embodiment. Typical functional units include but are not limited to the arithmetic and logic units 26, 28, the floating-point arithmetic unit 30 and the memory address generating unit 3, respectively. The example of the unit of dependent data is debugged in the concurrent application ser. No. 07 / 504,910 entitled "Technical Equipment of Devices Associating Dependent Data" filed April 4, 1990.

It is to be appreciated that the technique of the invention is extended with the intent of simplifying the parallel issuing and instruction of instructions in all computer architectures that process multiple instructions in one cycle, although different instructions may require more than one cycle of execution.

As can be seen from FIG. 2, the invention can be implemented in a sequencing processor wherein each functional processing unit handles the scalar instruction (S) or alternatively a composed scalar instruction (CS). As can be seen from the drawing, instruction flow 33 comprising sequential scalar and composite scalar instructions is provided with a control label (T) associated with each compound instruction. Thus, the first scalar 34 can only be performed by a functional unit A in cycle 1; triple-folded instruction 36 identified by the T3 denomination, the three composite scalar instructions can be executed by the parallel function units A, C and D in Cycle 2; another compound instruction38 identified by the T2 tag may have its own pair of scalar instructions executed in parallel by the A and B units in cycle 3; the second scalar instruction 40 may be performed by a singularly functional unit C in Cycle 4; the large group of instructions 42 may have their four scalar constructions executed by parallel units of AD in Cycle 5; and the third scalar instruction 44 may be performed individually by a unit A in Cycle 6.

It is important to realize that multiple in-structure compositions are eligible for parallel processing in certain arithmetic computer systems. For example, the invention can potentially be realized by the equipment of the processor as shown in FIG. 3, wherein the compound instruction being treated as a parallel convolution unit is one of the base units. As illustrated in the drawing, the same instruction 33 could only be processed in two cycles as follows. In the first cycle, the CPU # 1 base unit performs the first scalar instruction 34; the CPU functional units 2 will execute the triple compound instruction 36; and the functional unit from the CPU 3 performs two composite scalar instructions enclosed by the instruction 38. In the second cycle, the base unit CPU # 1 performs the second scalar instruction 40; Functional units from CPU # 2 perform four composite scalar instructions in compound instruction 42; and a functional unit from CPU 3 passes a third scalar instruction 44. An example of a computer architecture that can be adapted to the processing of compound instructions is an IBM System / 370 instruction level arithmetic, in which multiple scalar instructions can be issued to execute in each stroke cycle. In this concept, the machine cycle corresponds to the all-chain steps or steps required to execute the scalar instructions. Scalar arrays work with operands using unambiguous parameters. When the scalar flow is a cluster, the adjacent scalar instructions are selectively clustered for the purpose of simultaneous or parallel execution. which can be adapted to the processing of compound instructions is an IBM System / 370 instruction level arithmetic, in which multiple scalar instructions can be issued for execution in each stroke cycle. In this concept, the machine cycle corresponds to the all-chain steps or steps required to execute the scalar instructions. Scalar arrays work with operands using unambiguous parameters. When the scalar flow is a cluster, the adjacent scalar instructions are selectively clustered for the purpose of simultaneous or parallel execution. which can be adapted to the processing of compound instructions is an IBM System / 370 instruction level arithmetic, in which multiple scalar instructions can be issued for execution in each stroke cycle. In this concept, the machine cycle corresponds to the all-chain steps or steps required to execute the scalar instructions. Scalar arrays work with operands using unambiguous parameters. When the scalar flow is a cluster, the adjacent scalar instructions are selectively clustered for the purpose of simultaneous or parallel execution. Scalar arrays work with operands using unambiguous parameters. When the scalar flow is a cluster, the adjacent scalar instructions are selectively clustered for the purpose of simultaneous or parallel execution. Scalar arrays work with operands using unambiguous parameters. When the scalar flow is a cluster, the adjacent scalar instructions are selectively clustered for the purpose of simultaneous or parallel execution.

The instruction files for different IBM / 370/370/370 / ESA / 13 architecture architectures / 370-XA / and 370 / ESA / 13 architectures are well known. In this respect, we recommend the publication "Principles of IBM System Activity / 370" (published # GA22-7000-10 1987), and "Principles of Operation, Architecture of Operating Systems IBM / 370" (published SA22-7200-01988). Generally, the instruction folding device will search for instruction classes that can be executed in parallel, and will ensure that no interlocking between the members of the compound instruction will result in no interference by technical means. If a sequence of instructions is found, the compound instruction is created. For a more detailed specification, the System / 370 instruction set can be categorized into instruction categories, which can be done in parallel in a special computer system architecture. Instructions in some of these categories can be combined or composed with instructions from the same categories or instructions from certain other categories to create a compound instruction. For example, a portion of the System / 370 instruction file can be divided into categories as shown in Figure 4. A reasonable justification for this categorization consists of the functional requirements of the System / 370 instructions and the use of the hardware for the typical architecture of the computer system. The remainder of the System instruction / 370 is not specifically considered for folding in this example link. This does not prevent their folding using the methods and techniques of the present invention. It is known, that the structures of the technical equipment needed to perform the composite tooling can be routinely controlled by horizontal microcodes which allow for the use of parallelism in the remaining instructions that were not selected for composition or not included in the categories of FIG. 4, thereby increasing performance. 14

One of the most common intervals in System / 370 programs is to execute the instruction - test with mask TM or non-alignment formats (RX) - compare C, compare half of CH, compare CL logically, compare logically immediately CLI, comparatively CLH mask test, is the command to execute a type-conditional jump BC / RX-format / from a conditional jump / RR-form / from which it immediately follows. Performance can be improved by parallel execution - pitch and jump - and this is sometimes done dynamically by high-performance instructional processors. Sometimes there are difficulties in quickly identifying all different members by class -multi-class instruction and all members of the instruction-class - in a typical architecture during the decoding process. This is one of the reasons why superscalar machines usually consider only a small number of specific scalar instructions for possible parallel processing. Such limited dynamic scheduling, based only on a comparison in the last minute of two specific instructions, is eliminated in the present invention, because the analysis of all members of the classes is completed in advance due to the adherence to the compliant rules for folding during the formation of the compound instruction to be performed. The dynamic layout of each instruction is a big problem when the program is called, as shown. 4, which shows that a two-way composition of fifty-seven instructions produces a 57 x 57 matrix of more than thirty possible combinations. This is in sharp contrast to the 10x10 smatrician in Figure 17 for the same number of instructions as a reference to the possible combination categories,

Many classes of instruction can be done in parallel depending on how technical equipment is designed. In addition to the above-described foldable pairs - to compare and branch - many other foldable combinations (see Fig. 17) can be executed in parallel as a program / category 7 deployment with RR / category 1 instructions, branching / 3-5 / folded with a bootloader by address / category 8 / etc. In some cases, the sequence command affects the possibility of parallel execution and determines whether it can be complicated adjacent instructions. With respect to line headers 45, they identify the category of the first instruction of the syllabus and the column headers 47 identify the category of the closest instruction following the first instruction. For example, blessing / category 3-5 / followed by certain -po-suvy / category 2 / ~ are always collapsible 49,

State "sometimes" identified as "S" in schema schema. 17 can often be changed to "always" identified as "A" in the schematic by adding other functional units of the technical equipment in the computer system layout. Taking into account, for example, a two-way assembly that does not have a clustering unit, but instead has a common arithmetic and logic unit and a separate switch. In other words, there is no mutual blocking of clustering equipment for processing blocked "add-shift" instructions. It follows the following instruction sequence: AR R1, R2 SRL R3 after D2

It is clear that this pair of instructions is foldable for paralleling. In some cases, however, it will not be compliant with incompatible interlocking, as follows from the following instruction sequence: AR R1, R2 SRL R1 to D2

Thus, the schema shows that Category 1 of the instruction / AR / followed by Category 2 of the instruction / SRL / is sometimes collapsible 53. 16 In the existence of an arithmetic and logical unit that associates certain mutual interlocks, such as blocking, add / from above, can be changed to "A" in the diagram in Figure 17 "$". According to this, the composition rules are readily responsive to all changes made by the particular layout of the computer system. As an additional example, consider the instructions contained in Category 1 composed of instructions of the same category as the following 1 instruction sequence: AR R1, R2 SR R3, R4

This sequence is without random interlocking with the following data provided by the following results, which contain two independent System instructions / 370: R1 = R1 + R2 R3 = R3-R4

Performing such a sequence would require two independent and parallel two to one arithmetic and logical units, based on the instruction level architecture. It is to be understood that these two instructions can be grouped in the form of a compound instruction in the arrangement of a computer system that has such arithmetic and logical units. This exemplary composition of scalar instigations can be generalized by all pairs of instruction sequences that are blocked by dependent data and also blocked by techno-dependent equipment. In any actual instruction processor, there is an upper limit for the number of individual instructions that may contain a compound instruction. This upper limit must be specifically integrated into the technical and / or programming unit, which consists of compound instructions, that the composite instructions will contain more than one instruction (for example, parcel groups, triple groups, groups of four) than the jemaximal competence subject to the technical implementation. This upper limit is a severe consequence of the realization of technical equipment in a particular configuration of the computer system, and it does not limit either the total number of instructions to be taken into account for the composition or the length of the window of the group in the given code sequence to be analyzed for the composition.

Generally, the longer the window length of the ana-lysed group for the composition, the greater the parallelism it lstens with respect to the more advantageous composite combinations. From this point of view, consider the sequence of instructions in the following table:

Table 1

X1 * from any of the bearing instructions X2, II, X1, X1, X1, X2, X1, X2, X3, COMP R, R3, compares Rf with R3 X3 from any collapsible installation X4 II II H

If the upper limit for the composition is included in the technical checkup is equal to two (at most, two instructions can be performed in parallel in one cycle), then there are several ways of composing this sequence of instructions depending on the range of the programmable folding equipment.

If the composition range was equal to four, then the program layout equipment would take into account together / XI, X2, LOAD, ADD / a then forward forward one instruction at a time to be taken into account together / X2, LOAD, ADD, SUB / a / LOAD, ADD, SUB, COMP / a / ADD, SUB, COMP, X3 / a / SUB, COHP, X3, X4 / / ADD SUB / / COMP X3 / / X4- /

This optimal pairing according to the invention completely eliminates interlocking between the LOAD and the ADD and between the SUB and the COMP, thus providing additional possibilities XI comprised of its foregoing instruction and the X4 folded with its following structure.

On the other hand, the superscalar computer, which dynamically parallels the instructions into its instructional logic release, by following the "first ranked, first selected" method, would only create the following pairings as candidates in a parallel configuration: / X1 X2 // LOAD ADD // SUB COHP // X3 X4 /

This inflexible pairing brings complete remediation of certain blocking instructions, and is achieved only by partial successes of parallel processing. The flowchart in Figure 13 gives an explanation of the different steps taken for reasons that decide which of the neighboring instructions in the syllabic flow are categories or classes, by which they are qualified to create mixed groups in the form of a compound instruction for the specific configuration of the computer system.

According to Figure 5, there are many possible locations in the computerized system, where the composition can occur in program or non-technical equipment. Each has its advantages and disadvantages.

As shown in Fig. 5, there are various stages in which the program typically goes from the source code to the actual transmission. During the compilation phase, the default program is the machine code transcribed and stored on the disk 46. During the execution phase, the program from disk 46 is read and loaded into the main partition 48 of the special computer system 50 when instructed by the respective instruction base units 52,54, 56. Composition can occur anywhere on the road. Generally, the closer the fuser is placed 19 to the instructional base unit or the central base unit of the CPU, the more time becomes more urgent. Being located further from the central base unit C PU, more instruction may be attempted in a larger window of the in-flow stream in order to determine the best clusters for composing in increasing work performance.

One of the important objects of the invention is to provide programs for existing programs written in higher programming languages ​​or existing assembler language programs to be processed by software that can identify sequences of neighboring instructions capable of parallel execution by individual functionalities j ednot kami. The flowchart in FIG. 6 shows the generation of a program of composite instruction from an assignee language program, depending on the set of custom folding rules 58, which adversely reflects both the system architecture and the technical equipment. The Asian-language language program is prepared to enter the programmable folding device 59, which is a composite instruction program. The following instruction blocks of predetermined length are analyzed by the program folding device 59.

As shown in Figure 6, this special folding device is designed for two-way assembly of "m" and fixed length instructions in each block. The primary first step is to determine whether the first and second instructions form a stackable pair, then the second and third form a stacked pair, then the third and fourth form a stackable pair, and so on until the end of the block. 20

After identifying the various possible convertible pairs C1-C5, another very desirable step is to determine the optimum hatching of compound instructions formed by adjacent scalar instructions for parallel execution. By way of example, the possible composition of the instructions from the following different sequences is shown (no branching is envisaged): 11, C 2, 13, 15, C3, C 5, 11 0; 11, C2, 14, 15, 16, C4, 19, 110; C1, I3, I4, I5, C3, C5, 110; C1, 13, 14, 15, 16, C4, 19, I10. In the basic arrangement of special technical equipment, the composition device may select a preferred sequence of compound in-struc- tures and use the identification or identification bits to identify the optimal sequence of the compound instruction.

In the absence of an optimal sequence, all foldable adjacent scalar instructions can be identified so that any branch of the composite pairs may be used by the branch to the target located between the various composite trains (see Figure 14). Where multi-fold folding units are available, it is possible to simultaneously fold the following blocks into the flow of instructions.

The specific design of the programmable folding device will not be discussed here, because the details are specific for the given instruction set architecture and are the basis for the realization. Although the design of such composite programs is somewhat similar to conceptually modern compilers that execute instruction scheduling and other optimizations based on specific machine architectures, the criteria used to complete such compositions are unambiguous as best illustrated by the flowchart of Figure 13. In both cases, for a given input program and a description of the instruction kit as well as the architecture of the technical equipment (that is the structural aspects of the realization), an output program is created. In the case of a modern compiler, a new sequence of obsolete instructions is optimized.Parallel Transparency Instructions with Composite Instructions Mixed with Unsupported Scalar Instructions and Controls to Perform Composite Instructions Simultaneously as a Part of an Exercise.

It is easier, of course, to pre-process the instruction flow in order to create a compound instruction if there are already known reference points for marking where the instructions begin. The reference point as further used is indicated by any marked field or other indication that provides information about placing the instructions between. In many computing systems, such a reference point is only known from compilation compilation times and only from the base unit when invoking the instruction. Such a reference point is not known between the compilation time and the instruction when the special reference scheme is adopted.

After compilation is complete, the compiler can be labeled with reference marks (see Fig. 11), which labels contain the first instruction syllable and which contain dates. This special information contributes to a much more efficient composition, as the exact location of the instruction is known. Of course, the compiler can identify instructions and vary instructions and data in other ways to provide specific information to the folding device by indicating instructional limits.

If such instructional information is known, the generation of the respective identification bits will be forwarded forward by the forwarding rules specified for the special architecture and the layout of the technical equipment system (see FIG. 8). The non-literal instructional information between the known and the instructions of the varying lengths becomes a much more complex problem (see Figures 9 and 16). These figures are by chance based on the preferred coding scheme, which is described in more detail in Table 2A below, where the bi-directional composition is designated by bit "1" when the instruction is compounded with another bit and marked with "0" if not composed with additional instructions. The control bits in the control field added by the composition device include information relating to the execution of the composite instructions and may contain little or large information, as deemed appropriate for a particular realization. Vobr. 12 is an example of an eight-bit control array. However, a simpler connection in one unit is required by the first control bit to indicate the beginning of the compound instruction. Other control bits provide additional optional instruction information. In an alternate coding pattern for a compound instruction that can be used for both the two-way assembly and for large groups, the first control bit & quot; 1 & quot; is determined to indicate that the corresponding instruction is the beginning of the composite instruction. All other members of the compound instruction will be set to "0" for their first control bit. It will not be possible to combine the instruction with the other instructions, so that the given instruction will appear as a compound instruction of length one. This means that the first control bit will be staged "

It should be emphasized that both the C and EU / 71 execution units, such as the arithmetic and logical units of the ALUs in the system of composite instruction computers, are able to perform either scalar instructions one after the other or alternatively composed scalar instructions in parallel with the other composite scalar instructions. Such parallelepipedal embodiments may thus be made in different types of execution units such as ALU * s, FPDs 75, AUs or multiplex units of the same type F F1, FP 2, etc.) in accordance with the architecture of the computer and the organization of a specific computer system. Configuration of technical means, the embodiments of the present invention are thus available up to an unlimited number of implementing units to achieve the maximum performance of the parallel processing. By combining several existing instructions into a single composite instruction, it allows one or more of the instruction processing units in the computer system to efficiently decode and perform in parallel these stacked instructions without delay, which arises from the normal processing in computer systems. In the simplest exemplary coding schemes of this application, the minimum information for the composition of the instruction stream is added as one bit for each two text / instruction and data / syllables. For each instruction in a composite stream, a label containing control information can generally be added, which means for each uncompleted scalar 24 instruction as well as for each compound scalar instruction including pair, triple, or larger composite groups. The identifiers bits further used herein refer to the co-tagging that is specifically used to identify the sorting of the compound scalar instructions a composite group from the remainder of the unstretched scalar lines. Such uncompleted scalar instructions remain a composite instruction program, and when invoked they are executed individually. In the system, with four four-labels compared to four-sided interfaces, one label is assigned to each four-syllabic text. Similarly, if arbitrary instructions can be used, it is necessary to mark the text of each text. The identification bits further used herein refer to the partial labeling which is specifically used to identify the sorting of the composite scalar instructions forming the composite group from the remainder of the non-stacked scalar patterns. Such uncompleted scalar instructions remain a composite instruction program, and when invoked they are executed individually. In the system, with four four-labels compared to four-sided interfaces, one label is assigned to each four-syllabic text. Similarly, if arbitrary instructions can be used, it is necessary to mark the text of each text. The identification bits further used herein refer to the partial labeling which is specifically used to identify the sorting of the composite scalar instructions forming the composite group from the remainder of the non-stacked scalar patterns. Such uncompleted scalar instructions remain a composite instruction program, and when invoked they are executed individually. In the system, with four four-labels compared to four-sided interfaces, one label is assigned to each four-syllabic text. Similarly, if arbitrary instructions can be used, it is necessary to mark the text of each text. Such uncompleted scalar instructions remain a composite instruction program, and when invoked they are executed individually. In the system, with four four-labels compared to four-sided interfaces, one label is assigned to each four-syllabic text. Similarly, if arbitrary instructions can be used, it is necessary to mark the text of each text. Such uncompleted scalar instructions remain a composite instruction program, and when invoked they are executed individually. In the system, with four four-labels compared to four-sided interfaces, one label is assigned to each four-syllabic text. Similarly, if arbitrary instructions can be used, it is necessary to mark the text of each text.

In the shown assembly in a single set, all System / 370s are aligned in the half-width (two-sided) limits with either two or four or six syllables, with half-markings for each half. On the example of a small grouping of complex pairs of adjacent instructions, the identifying bit 1 indicates that instructions starting with the syllabus considered are followed with the following instruction, whereas "O" indicates that the instruction starting with the syllabus under consideration is not folded. The identification bit assigned to halves that do not contain the first syllable of the instruction The identifying bit for the first syllable of the second instruction in the composite pair is also ignored, however, in some branching situations, these identification bits are not ignored.This result of the toothocoding procedure for the identification bits is, in the simplest case of two-way composition, only one bit of information is needed for the base unit during operation to identify the compound instruction. 25

Where more than two scalar instructions can be grouped to create a compound instruction, additional identification bits may be required to provide adequate control information. However, due to the reduction of the number of bits required for the minimal control information, there is still another alternative format to continue to track the composite information. For example, even if a large group is stacked, one bit can be used for instruction when the following code is used: the value "1" means the composition with the following instruction, and the value "0" means the following instruction. bits / 1,1,1,0 / layouts. As with the other composite instructions described herein, the composite identification bits are for the composition of the half-

According to the preferred coding scheme shown below, the number of identification bits needed to provide additional information indicating a specific number of actual scalar instructions is a logarithm at base 2 / rounded up to the nearest whole number / maximum number of scalar instructions that can be grouped to form the compound instruction . For example, if the maximum is two, then one identifier bit is required for each compoundinstruction. If the maximum is three or four, then two identification bits are required for each compound instruction. If the maximum is five, six, seven or eight, then three identification bits are needed for each compound. This coding scheme is shown in Tables 2A, 28, 2C below: 2o

Table 2A / maximum two /

Identifying bits Encoded meaning Total # of a deposit 0 This instruction is not compiled with the following instruction None 1 This instruction is compiled with one following instruction Two Table 20 / Maximum four / Identifying bits Encoded meaning Total # with a deposit 00 This instruction is not a folder -in following instruction no 01 This instruction is composed of one following instruction two 10 This instruction is composed by two following instructions three 11 This instruction is composed of four with three following instructions 27

Table 2C / maximum eight /

Identifying bits Encoded meaning Total with deposit 000 This instruction is not composed with the following instruction none 001 This instruction is composed of the following instruction two 010 This instruction is composed of two following instructions tri 011 This instruction is composed of three following instructions four 1 00 This instruction is compiled with the following four instructions five 101 This instruction is composed of the following five instructions six 110 This instruction is compiled by the six following instructions seven 111 This instruction is composed of the following seven instructions eight

Therefore, it is deduced that each half-need is marked, but according to this preferred schematic, the base unit ignores all but the first instruction - 28 - in the conducted instruction flow. In other words, the syllabus is tested to assess whether it is a composite instruction by testing, their identification bits. If the beginning of the compound instruction is zero, its identification bits are zero. If the syllable starts with a compound instruction containing two scalar instructions, the identification bits are "1" for the first instruction and "0" for the second instruction. compound instructions containing three scalar instructions, the identification bits are "2" for the first instruction and "1" for the instruction instruction and "0" for the third instruction.

These exemplary encoded instruction methods assume that the three instructions are compiled to create a group and the second with the third instruction are also compiled to form a pairing group. In other words, if it appears in a triple branching group to a second instruction, it communicates the identification bit "1" for the second instruction that the second third instruction will be executed as a composite parallelized pair even if the first instruction in the triple group is not executed.

However, the invention is not limited to the particular coding preferred scheme. Various other coding rules such as the previously described alternative coding scheme are possible in the area and interpretation of the invention.

It will be appreciated by those skilled in the art that the present invention requires only one instruction set composition of a special computer system configuration, and any recall of the compound instruction will also cause the identifiable identification bits to be generated. As a result, the ineffectual determination at the last minute and the selection of certain 29 scalar instructions for parallel execution are repeated, each time the same or different instructions are executed for execution in the so-called super scalar instrument i.

In spite of all the advantages of binary instructional stacking, this procedure becomes difficult for certain computer architectures unless a technique is developed to determine the instructional limits in the syllabus. If varying instruction lengths are allowed, such determination is more complex and complicated when the data and instructions are mixed together, or if it is allowed to modify the instruction flow directly. However, during the execution, the instructional limits must be known with regard to the correct design. However, as soon as the composition is done well enough before the instruction is performed, a unique technique for the instruction composition was developed without the knowledge of where the device starts and without knowing which syllables are the data. This technique is further described in detail and can be used to construct compound instructions made from adjacent pairs of scalar instructions as well as to create compound instructions made from larger groups of scalarinstructions. This technique is applicable to all instruction sets of various common types of architectures, including RISC-computed readers, whose architecture structures are usually of constant length and are mixed together. Further details of this assembly technique are described in co-pending Ser. No. 07 / 519,382 entitled & quot; Universal Technique for Composition of Instructional Level Processors & quot; filed 4 & quot ;. 5. 1 990. Generally speaking, the technique of composition is provided by two or more scalar instructions from an instructional shot without knowing the starting point or the length of each individual device. Typical instructions already contain an operative code in the forward-determined field of the field that identifies the instruction's length. Those neighboring instructions which qualify for parallel execution in a special configuration of the computer system 30 are provided with appropriate marks to indicate that they are candidates for composition. In the IBM System / 370, the instructions of which are either two, four or six slabs long, it is assumed that the positions of the operating code field are based on the estimated instruction length of the code. The value of each designation associated with the expected code is recorded and the instruction length of the code the operating code is used to place a whole sequence of possible instructions. Once the limitations have been established,

This unambiguous composition technique is illustrated by way of example in the drawings of Figures 8-9 and 14-15, where the rules of composition are defined to determine that all instructions with the length of two syllables or four syllables are one with the other composite / , that the two-sided instruction is capable of paralleling in this special configuration of the computer with another two-way or other four-way in-structure. The exemplary composition rules further imply that all six six-syllable instructions are not at all comprehensible (that is, in this special configuration of the pointer, the six-sided instruction is self-sufficient). The invention is of course not limited to such rules for exemplary composition, but is applicable to any set of rules on composition,

A set of instructions used as an example of a composition in these devices according to the invention is taken from the System Architecture 370. By checking the operating code of each instruction, it is possible to determine the type and length of each instruction, and then generate a tag containing the identification bits for the tutorial specific instruction as described in more detail below. Before - 31

However, the present invention is not limited to any specific architecture or instruction set, and the above-mentioned rules are merely an occasional example.

The preferred coding scheme of the compound instructions was previously shown in the overview of Tables 2A-2C. In the first case, with a fixed length of non-mixed date instructions and a known location of the reference point of the operating code, the composition may continue to conform to the applicable rules for this particular computer configuration. Since the field reserved for the operating code also contains the length of the in-structure, a sequence of scalar instructions is normally determined, each sequence instruction being considered as a parallelepiped for parallel execution with the following instruction. The first encoded value in the control denomination indicates that the instruction is not collapsible with the next instruction, the coded value of the control label indicates that the instrument is foldable for parallel execution with further instruction. In the latter case, the variable length instruction of the unmitigated data and the known location of the reference point for the operative code and also for the instruction length code, which is included as part of the operating code in the system, may be performed in a conventional manner. The operative codes shown in FIG. 8 indicate the instruction sequence 7Q as follows: the first instruction is 6 syllables long, the second and the third of the lengths are 2 syllables, the fourth is 4 syllables long, the fifth edges are 2 syllables, the sixth is 6 syllable long, and seventh and eighth-long lengths of 2 syllables. The C-vector 72 in FIG. 8 shows the values ​​of the identification bits / of the drawings called the bits of the composition / for the specific instruction sequence 70 where the reference point indicates that 32 is known to start the first instruction. Based on the values ​​of these identification bits, the second and third instructions form a composite pair, V in the identification bit for the second instruction. The fourth and fifth instructions form a different composite pair as "1" * in the identifying bit of the fourth instruction The second and the eighth instructions also form a composite pair as denoting the "1" identifying bit for the seventh instruction The C-vector 72 in Figure 8 is relatively is easily generated because it does not contain any data syllables mixed with instructional syllables and the instructions are all of the same lengths of known limits.

Another situation occurs in the third case where the instructions are mixed with non-instructions and the reference point still provides the beginning of the instruction. The basic diagram of Figure 11 shows one way of marking the instruction reference point where each half has been indicated by a reference mark to indicate that it contains or does not contain the first instructional weakness. This can be both a fixed and a variable length instrument. By determining the reference point, it is necessary to evaluate a part of the syllable flow data for the possible composition. The composition unit can be used to skip and ignore all non-surgical syllables.

A much more complex situation occurs where the syllable contains variable length / no data / instructions, but it is not clear where the first instruction starts. Since the maximum length of the instruction is six syllables, and since the instructions are sorted into two bits between two, there are three possible starting points for the first flow instruction. The technique thus provides all the possible starting points at the choice of the first instruction in the text of the syllable flow 79 as shown in FIG. 9.

Sequence i assumes that the first instruction begins with the first syllable and proceeds with the forward composition according to 33 assumptions. In this exemplary connection, in a whole, the length of the array is also critical to the value of the C-vector of each instruction. Therefore, the C-vector 74 has for sequence only the value "1" for the first instruction of the possible compound by pairwise combinations of the 2-sLabic and 4-sLabic instructions.

Sequence 2 assumes that the first instruction enters the third syllable / beginning of the second half and advances to the front according to this assumption. The value of the field length of the slash is 2 indicating that the next instruction starts with the fifth syllable. By skipping forward every possible instruction based on the length of the previous instruction field, the full potential of the sequence instructions 2 is generated by the possible identification bits as seen from the C-vector 76.

Sequence 3 assumes that the first instruction begins with the fifth syllable / beginning of the third half / and continues as forwarded. The value in the length of the field for the fifth syllable is 4 indicating that the next instruction starts with the ninth syllable. By proceeding forward with each possible instruction based on the value of the preceding instruction field length, the full potential of the sequence of the sequence 3 is generated by the possible identification bits as shown by the C-vector 78. cases, the three sequences of potential instructions converge into a single sequence. Vobr. 9, attention is paid to the three sequences that converge between the eighth syllables at the end80. It is also noted that if another sequence begins at the end of the sixth, eighth, and tenth syllables, they converge as quickly. The passages 2 and 3, when crossed to the limits instructed by the end of the fourth syllable, are out of phase when folding to the end of the sixteenth syllable. In other words, these two sequences take account of the different pairs of instructions based on the same sequence of instructions. Since the seventeenth syllable is still in a bearable instruction at 84, the phase-out is terminated.

If valid validation does not occur, it is necessary that all possible sequences of instruction continue to the cone-window. However, where a valid maturity occurs and it is determined, the number of sequences from three docks / one of the identical sequences will be combined to become ineligible operation, and in some cases from two to one. Thus, experimental instructional limits for each possible instruction sequence are assigned before the infiniteness and assigned identification bits for each such instruction indicating the location of the potential compound instruction. It is clear from FIG. 9 that this technique generates three separate identifying bits for each two syllables of the text. In order to match pre-processing in AD cases, it is desirable to reduce the three possible sequences to a single sequence with identifying bits, where only one bit is allocated to each half.

For parallel purposes, the associated bits of the associated CC vector are equivalent to the individual C-vectors of each of the three sequences 1-3. Other verbal identifier bits of the CC vector allow for any possible sequences of the correct parallel execution of the compound instructions or individual uncompleted instructions. Associated identification bits also contribute to the correct branch. For example, if a branch starts at the beginning of the ninth syllable88, then the ninth syllable must begin the instruction. Otherwise, there is an error in the program. The identification bit & quot; 1 & quot; associated with the syllabus is used to correct the parallel execution of this instruction with its next progressive instruction. 35 The various steps in the composition method shown in Fig. 9 as described above are shown in Fig. 16, which contributes to the explanation itself.

The best time to provide the reference information for the instruction limits is the compilation time. As you can see. The reference label 10 may be connected during the compilation to identify the commencement of each instruction. This makes it possible for the composition apparatus to proceed with the simplified technique in the above-mentioned first, second and third cases as previously stated. However, the compiler could identify the instruction limits and distinguish between instructions and data in other ways in order to simplify the work of the unit and to avoid the complications of the technique as shown in Fig. 9.

Fig. 10 illustrates a flowchart of a possible realizing unit for processing the instruction flow, as shown in FIG. 9. The multiple number of folding units 204, 206, 20 could be as large as the number of halves in the cache text. The three constituent units in this version would begin to process the sequences of the first, third and fifth syllables. Upon completion of a possible surgical sequence, each constituent unit starts testing another consecutive sequence translated into six slabs from its previous sequence. Each composing unit is a composite identifier bits / C-vector values ​​/ everywhere text. The three sequences of the three folding units are read 110 and the resulting combined identifier bits / values ​​of the CC vector are stored in memory and assigned to their corresponding text syllables.

A beneficial advantage provided by associated CC-vector identification bits is the formation of a sequence of multi-fold compound bits based on which instruction is directed to the branching goal. As best seen in FIGS. 14-15, it is possible to shape differently from the same syllable flow of the compound instruction.

Fig. 14 illustrates possible combinations of compound instructions when the computer configuration provides a parallel release and a lead of no more than two instructions. Where the instruction tok90 with compound instructions is processed into one normal sequence, the composite instruction I will be issued to a parallel embodiment based on the decoding of the bit-sinking identifier CC-vector 92. However, if the syllable branch is present, the composite instruction II to a parallel embodiment based on the decoding of the Bitstream Fifth syllable identification.

Similarly, the normal sequential processing of another compounded syllable stream 94 results in sequentially executed composite instructions IV, VI and VIII / instruction of the components in the every-step instruction being performed in parallel. The branching in the third syllable of the composite syllable flow follows the sequential execution of the composite instructions V and VII, and an instruction beginning with the fifteenth syllable / forming a second partial instruction VIII / will be issued and executed individually, all based on the identification bits in CC -vector 96. Branches in the seventh syllable result in sequential execution in compound instructions VI and VIII, and the branching in the eleventh syllable results in sequential branches in compound VIII.

Thus, identification bits "1" in the CC vector 96 for compound instructions IV, VI and VIII are neglected when one of the composite instructions V or VII is performed. Alternatively, the identification bits "I" in CC-vector 96 of the printed instructions V and VII are neglected when performed in any of the folded instructions IV, VI or VIII. FIG. 15 illustrates possible combinations of compounded features when the computer arrangement provides parallel delivery and execution up to three instructions. Where instructions 98 containing compound instructions are processed in a normal sequence, compound instructions X (triple group) and XIII (pair) will be executed. The twentieth-second syllable, on the other hand, results in a compound XI structure (triple group)

The bits "2" of the identifier in the CC vector 99 for compound XI and XII are neglected when the instructions X and XIII are executed On the other hand, when the compound instruction XI is executed, the bits of the identifier for the other three composite instructions X, XII, XII Similarly, when the compound instruction XII is executed, the identifier bits are neglected for the other three folded instructions X, XI, XIII.

There are many possible unit constructions for composing instructions depending on its location and knowledge of the text content. In the simplest situation, it would be desirable for the compiler to show signs of syllables containing the first instruction syllable and containing data.

This extra information results in a more účinnějšíjednotku for the composition, as they are known inaccurate umístěníinstrukce / fig. 13 /. It means that the composition can be vždyprovádět such situations case C in order generovániC-vector identification bits for each composite INSTRUCTION-ci / fig. 8 /, the compiler could thus add another infor-MACI as a prediction of static branch or even a direction-nice into the composition unit. 38

To distinguish the data from the instruction, other methods can be used where the instruction flow to be composed is stored in memory. For example, if parts of the data are sparse, a simple list of addresses containing data less space than the label would require. Such combinations of technical and programmed compositional means provide many alternatives for efficiently generating inline instruction.

While exemplary preferred embodiments have been described in the entirety of the invention, it will be appreciated by those skilled in the art to evaluate various modifications and changes which can be derived from the spirit and scope of the invention as defined in the following claims.