Connexion for synchronized horizontal wobbling on horizontal frequency's multiples

Rodriguez-Cavazos Enrigue, Tndianapo1, OS (54) Circuit for synchronized horizontal sweep at multiples of horizontal frequency (57) The first phase lock loop (12) generates the first horizontal synchronization frequency timing signal (1f ,,). The derailleur converter circuit (5b) is from a first timing signal a second frequency timing signal (2f ') to a multiple of the first frequency that is subject to frequency changes at a frequency corresponding to the first frequency. The second phase locked loop (62) includes a controllable oscillator (66) for generating a balanced horizontal synchronization signal at the second frequency. The second phase locked loop (62) has a characteristic loop response, determined by a low pass filter (63), preventing the voltage-controlled oscillator (66) from changing the frequency as quickly as the rate of change of the second timing signal. This leads the error signal to the controllable oscillator (66) towards the average value, resulting in a corrected, symmetrical, synchronization signal at the second frequency. The horizontal output biasing stage (60) may be energized to the second phase lock loop (62) for synchronized horizontal numbing in accordance with the second frequency.

Sco-CM

- i Connection for synchronized horizontal sweep at multiples of horizontal frequency

Technical field

The invention relates generally to horizontal deflection systems for television apparatus. In particular, however, the invention relates to the generation of horizontal synchronization signals usable in systems displaying video signals at a higher than the fundamental or standard frequency of the horizontal.

The television set requires that the scanned raster generating circuits are synchronized with the scanned image signal. Video signals. For example, NTSC standards are displayed by interleaving consecutive fields, wherein each field is generated by a scan pattern at a basic or standard horizontal scan frequency of approximately 15,734 Hz.

The fundamental sweep frequency for video signals / is variously referred to as f, Jf and IH. The actual frequency of the signal 1f will vary according to the different television standards. In accordance with an effort to improve the picture quality of the television apparatus, systems have been developed for progressively displaying video signals in an interlaced manner. Successive sweep requires that each displayed frame be swept λ 'in the same time period that it is. assigned to sweep one of two interlaced format fields. Hence the horizontal sweep frequency must be twice the Juni of the interlaced video signal. The sweep frequency for such a progressively swept image is variously referred to as 2f_TT and 2H. rejection frequency 2ík_T according to US standards, for example, 31,408 Hz. A similar situation occurs when an image signal with a higher horizontal sweep frequency than that transmitted or augmented by a cable distribution system, for example 2P, is to be displayed at a frequency of 4f or other multiples of frequency.

The problem that can occur when generating the second horizontal synchronization signal, e.g. at the frequency 2f of the first horizontal synchronization signal, e.g. at the frequency 1fj in the video signal, is to provide a sufficiently accurate symmetry of the second synchronization signal during the first synchronization signal. The period of the second signal may fluctuate due to the ripple of the pulse edges in the first signal. For example, if the symmetry synchronization signal 2f is not very accurate, for example, during any period Ifjp, the track 2P will be initiated at a different time in every other line in the rasir, which may cause an illusion. k. Raster duplication as shown, for example, in FIG. 8. The trap has a first set of two rows of spaced lines forming an image portion K, the kits being shifted to the right, and a second set of two rows of swept lines forming an image portion L, which is shifted to the left. Adjacent pulses of reverse run have a different amplitude, since during the adjacent waveforms the differences between the peak yoke currents are different. Different peak-to-peak currents flow during adjacent waveforms because adjacent waveforms are of different lengths. The magnitude of the sweep difference between adjacent rows of buc-e depends on the magnitude of the period difference_and the overall energy efficiency of the deflection circuit. The effect of bifurcation of the grid is exaggeratedly illustrated in FIG.

8, where the imagery lines of the image portion L begin less than 3.

The time difference between. however, adjacent track periods of the order of only 100 nanoseconds may cause an unacceptable amount of bifurcation of the image.

Phase locked loop circuits are widely known and used in television sets. Indeed, two-loop phase-locked loop systems have been developed to provide accurate sync signals 11b. In such a configuration, the first phase locked loop is a conventional phase locked loop in which the output of the voltage-controlled oscillator or the counter-split digital oscillator output is compared to an incoming horizontal sync pulse selected from an image signal that Kt has processed and displayed on the screen. with this synchronization pulse synchronized. The second phase locked loop, which also operates at the frequency lfjj, compares the same outputs of the first loop oscillator to the frequency lf imms, representing the reverse run voltage H at the deflection yoke used to generate the sweep current at the frequency li1. The error voltage from the second phase comparison sc uses the pulse width modulated signal, which is determined by initiating on the output device 1f and then initiating the reverse or phase of each line in c vertical field. The monostable timing apparatus can provide a constant duty cycle ratio of the pulse width of the modulating output signal and the output switching transistor 1f.

IX

The loop response of the first phase locked loop is usually relatively slow. The receiver has a first phase locked loop normally narrowing the bandwidth to optimize the reduction of phase variation with a decrease in RF signal strength as seen in the edge range of the transmitter. The second phase locked loop generally has a faster loop response. Hence, the second phase locked loop has a wider bandwidth allowing the second phase locked loop to closely monitor the ripple current variation due to variations in the output transistor memory time and tuning effects of the high-voltage transformer, resulting in a direct non-shaking raster under all current load conditions. electron beam. The only significant exception in this mode of action is. with regard to the compromises necessary in the first phase locked loops, the adaptation of the VCR signal, and the like, where it is sometimes encountered to change the steps up to 10 microseconds in phase. Certain compromise solutions can be used in appropriate loop responses to provide adequate low signal performance without significant overall degradation of receiver performance.

The asymmetry in the first synchronization signal, e.g. 1f, may be introduced directly by the phase locked loop nature used in the synchronization system, which requires the first timing signal, or Ifjp, to be used as a feedback signal to the phase comparator in the phase locked loop. Asymmetry has been corrected in the past by, for example, special signal processing circuits associated with the operation of the first phase locked loop and / or the circuit used to convert the timing signal 1f_TT on the timer or synchronization signal 2f_TT. This can be costly and can cause unwanted delays in the propagation of the synchronization information by the deflection circuits.

Under the moor you nálczn

It is an object of the present invention to provide a horizontal deflection system having accurate synchronization circuits for use in displaying video signals at a multiple of the scan frequency unless the asymmetry is based on periodic synchronization / timing signal disturbances. According to this feature of the invention, the first phase locked loop generates a first timing signal at a first horizontal synchronization frequency corresponding to the horizontal synchronization component λ 'of the video signal. The converter circuit derives from the first timing signal a second timing signal having a second frequency multiple of the first frequency and subject to frequency variation at a frequency corresponding to the first frequency. The second phase locked loop receives the second timing signal and the feedback signal in accordance with the second frequency, and includes a voltage-controlled oscillator to generate a balanced horizontal synchronization signal at the second frequency. The second phase locked loop has a loop response characteristic preventing the 'voltage controlled' oscillator from changing the frequency as quickly as the frequency of variations of the second timing signal. The horizontal output deflection stage may be coupled to a second phase locked loop for synchronized horizontal sweep in accordance with the second frequency. The two phase locked loops are arranged in tandem in conjunction with a signal converter or multiplier. No additional signal processing circuits are required to correct the symmetry of the timing signal generated by the first phase locked loop or the symmetry of the converter's multiple frequency timing signal.

In an exemplary embodiment, the first phase locked loop is at a first sweep horizon, not for example 1, and the second phase locked loop comprising a voltage controlled oscillator operates at a second horizontal sweep frequency that is a multiple of the first frequency, 2f. The first phase locked loop synchronizes the output 1f of the voltage controlled oscillator or the counter-split output of the oscillator s,

- sv ne nr they per cm m signal of the incoming video signal lf. The second phase lock loop H synchronizes the raster sweep with the image frame 2f from the accelerated image processing system 2f.

H * H

The symmetry of the second timing signal in the period of the first timing signal may not be accurate. Rather, the second phase locked loop is characterized by the operation of a loop that averages asymterio errors caused by deviations of the first timing signal from the signal utilization factor. Therefore, the second phase locked loop automatically provides asymmetric correction while closing the horizontal output deflection stage generated by the second synchronization signal. The second synchronization signal and the horizontal deflection circuit have the same frequency and fixed phase relationship.

The response of the second phase locked loop is slow enough to suppress any component of the first timing signal, but fast enough to follow VCR-type signals, since these types of signals will produce the first response from. first loop and second from expensive loop. The second phase locked loop has a low pass filter that prevents its voltage controlled oscillator from changing the frequency as fast as sc changes the error signal due to the asymmetry of the uncorrected full timing signal. The error signal sc changes at the frequency of the first timing signal. For example, in system 1f

H to 2f, the non-sustained controlled oscillator 2f does not respond sufficiently to H1 * fast enough to vary the frequency of the uncorrected timing signal 2f from the transducer, which changes to frequency 1f,. By the time,

When the non-nanoseconded oscillator 2f increases a bit of Junitocet, for example in response to the error correction control signal, the error control signal seeks to reduce the frequency. This has the effect of supplying the error signal closer to the average value, resulting in a balanced frequency 2f. The grid bends are corrected by the velocity of the second phase lock dream.

Another feature of the present invention is to provide a smoothing circuit for correcting asymmetry errors in multiple frequency synchronization systems caused by periodic disturbances in the synchronization or timing signal. In accordance with this feature of the invention, the signal source generates a first timing signal at a first frequency subjected to periodic frequency variation at a frequency of a second, lower frequency. The phase locked loop for receiving the first timing signal and the feedback signal in accordance with the first frequency includes a controllable oscillator for generating a balanced horizontal synchronization signal at the first frequency. The phase locked loop provides a characteristic loop response to prevent the Fracture of the controllable oscillator from changing the frequency as fast as the frequency

C1 fluctuates in the first timing signal. The horizontal deflection stage may be coupled to a phase locked loop for synchronized horizontal sweep according to the first frequency. The errors are corrected by the operation of the low pass filter in the phase locked loop, adapted to suppress any component of the signal according to the second frequency. The second phase locked loop may generate a second timing signal in accordance with the second 1-anit 0n, synchronized by the horizontal sync component of the video signal. The low pass filter prevents the oscillator from changing the frequency as quickly as the error signal changes due to the asymmetry of the first timing signal in the period of the second timing signal. As a result, the error signal tends to an average value, which balances the output of the oscillator. The first, the frequency, is a multiple of the second frequency, for example an even multiplier.

Overview of the drawings

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a horizontal deflection system according to the invention having synchronizing circuits for generating timing signals for displaying image signals 1f in FIGS. 2 (a), 2 (b); useful for the explanation of FIG. 1, at the horizontal sweep frequency 2f ^,

2 (c), 2 (d) and 2 (e) are the waveform signaling asymmetry of the inherent circuit shown in FIG. Fig. 3 is a diagram of an analog signal converter 1f to 2f suitable for use in the synchronization system shown in Fig. 1. Fig. 4 is a block diagram of a horizontal deflection system according to the invention having synchronization circuits to generate timing signals to display sequentially swept video output and comprising a digital signal converter 1f to 2f, FIG.

(b), 5 (c), 5 (d), 5 (θ) and 5 (f), the waveforms are useful to explain the asymmetry inherent to the digital circuit shown in Fig. 4, Fig. 6 (a), 6 (b) Figures 6 (c) and 6 (d) are waveforms useful for explaining the manual phase adjustment between the synchronization signals 1f and 2f for the circuit shown in Fig. 4 and / or Fig. 7 is a wiring diagram showing in greater detail the second phase loop 4 and FIG. 8 schematic representation of image bifurcation caused by asymmetry of synchronization signal 2f in the periori de of synchronization signal 1f

H '

Examples of the invention

A synchronization system 10 for displaying video signals 1f at a frequency 2f_T. For example, the analog circuit 12 comprises a synchronization pulse separator 1.4, a phase comparator and a voltage-controlled oscillator 18 having an output signal at a frequency 1f. The voltage-controlled oscillator 18 is designated 1f, rl-h

- 11 VCO. The video signal 1f is input to line 13 to the sync pulse separator 14. Video signal 1 f

H may be a standard interlaced video signal according to the IsTSC standard. The sync pulse separator 14 provides horizontal sync pulses 11a as a single input to the phase comparator 6 and vertical sync pulses on another output line (not shown). The output of the phase comparator 16 on line 1p is the input to the low pass filter 20, referred to as LPF. The error control signal generated by corroator 6 on line 1p is integrated by a lowpass filter 20 to generate an error control signal for the voltage-controlled oscillator 18. The output of the voltage-controlled oscillator 18 at line 12 is a timing signal at frequency 1f. The timing signal 1f on line 17 is the input to signal converter 22f to signal 21f. The timing signal 1f on line 17 is fed back to line 19 as a second input to phase comparator 6. The phase comparator 6, the voltage-controlled oscillator 18 and the line 19 form the first phase locked loop, generating an output signal at frequency 1fj. The timing signal 1f on line 17 is phase-synchronized with the upper-edge signals of the video input 1f on line 11.

H -—

Signal converter 22f. on signal - Il if generates timing signal at frequency 2f, "on line 23 from timing signal h

Lí na ve <

The timing signal 2f on line 23 is an uncorrected timing signal 2f-UF. The operation of the transducer 22 of the sulfide 1f to the sulfite 2f is illustrated in more detail in the signal line of FIG. 3.

The timing signal 2f on line 23 will be asymmetric only Π dc of the degree v as the timing signal lf .. on line 37 pc.i has a perfect or nearly perfect 50 utilization factor, and narrow-range components are used in the signal converter 1f to signal 2f. H XI tolerance. In practice, the utilization factor of the signal lf may show unacceptable deviations from the 50% utilization factor due to the ripple of the signal lf_T..

Herein, the waveform of the signal 1f is used for the eclectic changes of the low pass signal 1f. 20, which is an error correction signal for the voltage-controlled oscillator 18. The ripple of the signal 1f causes cydial changes in the output voltage of the voltage-controlled oscillator 18 at frequency 1f. The sync chronization pulses 1f, shown in Fig. 2 (a), are separated from the image signal 1f by the start pulse sync separator 14. The error signal or control voltage shown in FIG. 2 (b) is typical because the wobble of the lfy signal may occur. The wobble may be the result of feedback of the timing signal 1f to the phase comparator. The error signal gradually decreases for most of the period if · ^ »^CCauses the frequency 1f of the voltage-controlled oscillator to decrease gradually during each period 1f. The signal 1f produced by the voltage controlled oscillator 18, shown in FIG. FIG. 2 (c), j is a xase synenronization with sync pulses. The frequency of the voltage-controlled oscillator 13 sc changes 18 sc to follow the synchronization IIf pulse 1f.

H

The timing signal Sf ^, which is derived from the signal I1, has two pulses for each signal period 11 ', as shown in Fig. 2 (d). First impulse. 2f._rwho j_; depicted is the period t, and the subsequent successive imouls of the period A ~ at t. Due to typical variations in the control signal for the voltage-controlled oscillator 1f, the peu H may not be the same. As shown, for example, in Figure 2 (c), t is less than t_n. Therefore, the reverse pulses resulting from the uncorrected 2f-REF signal have greater amplitudes during alternating periods t than during alternating periods t, as shown in Fig. 2 (e). An alternating sequence of reverse pulses having different amplitudes X1 and X2 results in two sets of both rows of ordered rows with different origin points as shown in Fig. 8. Uncorrected timing signal 2f -REF on line 23 may exhibit unacceptable asymmetry, which may result in image bifurcation.

The second phase locked loop is formed by the television horizontal processor circuit 24, which may be for industrial use as industrial type CA 139 · 1 · CA 139-1 features include phase-comparator, oscillator, voltage-regulator Vcc and> řcdzesilovač.

a lasing signal 2f - REF on line 21, which, as fcvlo ri

14, mentioned above, can be adversely affected by the ripple of the timing signal If? On line 17, being an input to the phase. the comparator 26 of the processor circuit 24. Phase comparator output 20 to v / v^IN vv Z ·>

dtm 25 is the input to the low pass filter JO. The chase catches the rogue oscillator 28 generating a 2f output signal._T. The error control signal generated by the phase comparator 26 is integrated with the low pass filter 30. The output of the voltage controlled oscillator on line 27 provides a corrected signal 2f_TT for horizontal input circuit J2. The horizontal output circuit J2 generates a horizontal sweep current and provides backfeed pulses 2f ^ on line J3. The backfeed pulses are input pulses to the delay circuit J4 for adjusting the phase of the corrected signal 2f.

H relative to the uncorrected 2f-ELF timing signal. The uncorrected timing signal 2fEC -ECF has a fixed phase relationship with the timing signal 1f via the signal converter 22f of the signal 1f to the H * ii signal 2f. The output of the delay circuit 14 on line 35 is the second input of the phase comparator 26.

The operation of the second phase locked loop is so high that it averages the fluctuations of the periods and frequency of the pulses in the timing signal 2f - ICiF, xx caused by the undulation of the timing signal 1f ,,. In particular, the time constants of the low pass filters of the respective phase locked loops are set to provide a phase locked loop 1f, with a slower loop response than the phase locked loop 2f response.

* Loop 1f is slowly active in Z> 'in ZZZ, ie it has a narrow bandwidth to optimize the phase ripple suppression with decay: the intensity of the high-frequency signal that may be apparent in the peripheral reception areas. The loop 2f is typically faster, i.e. it has a wider bandwidth to optimize tracking of raster sweep current due to fluctuations in the accumulation time of the horizontal output transistor and the tuning effects of the high-voltage transformer. The result is a straight, non-bent grid under all load conditions, electron beam current. An exception to this mode of operation occurs with respect to the compromises needed in loop 1f to match the VCR signal. and the like, which may sometimes experience incremental changes of up to 10 microseconds. • A compromise can be made on the performance of a weak signal without significant overall degradation of receiver performance.

If the asymmetry of the pulses 2f is within a given iriocation, ff is stingy. that the first of the two pulses in a given period 1f has a frequency, if any, that is too high, the next pulse will have. a frequency that is too low and vice versa. As is apparent from FIG. 2 (c), t, + t is constant and is equal to period 1f._at· Signal variation A e H

2f -RDI · 'will always result in successive momentary signals in K opposite for each period. This will be true except in those cases where there is no Jt asymmetry error and no momentary deposition in the given non-period lf. Lower nropnst n of loop 2f_r does not allow a voltage-controlled oscillator 2f,_T change H n. frequency i au fast as. sc discover the zmnnv in the momentary control

- 16 signal due to variation of uncorrected timing signal

Rf -RriF, which appears at frequency 1f. ilo ť.obv, kdv Hanéli ri ''^x The oscillator 2f "decreases the frequency slightly, for example ri, depending on the frequency increase of the 2f -i-eOF H timing signal during the period t", the error signal changes the sense of increasing the kk frequency in response to at the time of subsequent ocriodv t, of the same period li ,,. This has an effect^x The supply of the error control signal closer to the average value results in a balanced driving signal 2f. Hence, the corrected synchronization signals on guide 2.7 are sufficiently symmetrical in the period of timing signal 1f to prevent bifurcation. More generally, the second phase locked loop is not only effective for amplifying the corrected signal

2f, but the second loop of the phase H ri 'hinge is also effective in averaging the timing errors of the uncorrected 21 * -REF signal caused by the ripple 1f'. timing errors h H cannot be corrected using a phase control loop that does not include an oscillator.

Giant. 3 shows a suitable signal converter circuit 2.1f to a signal 2f that can be used in the circuit shown in FIG. 1. The circuit 22 generates a timing signal 2f on the line 21 in response to the timing signal 1f, on the line. Positive pulses H of output si ^ n. lu 21 '—ikri' on line 23 are reverses, once the transistor Q, 14 leads. The inverted output signal is available on the collector of transistor Q13. The routing of transistor Q14 of the jrcpinac is controlled by two pairs of transistor transmissions, on one side and Q 12 and '<13 on the other side.

The timing signal 1f is capacitively connected to the converter circuit 22 via capacitor C2. the effect of capacitor C2 is to convert each leading edge of timing signal 1f into a positive pulse and each falling edge thereof into a negative pulse as shown in the waveform on line 21 In the absence of such pulses, the voltage level based on transistor Q12 will be Vcc / 2; as a result of the operation of a voltage divider formed from resistors R 12 and Π 13. For example, the voltage Vcc may be + 16V. The quiescent voltage on the emitters of transistors Q 12 and Q 13 will be Vcc / 2 - V, due to the configuration of the emitter b 12th transistor Q 12. The anode of diode D 11 will be rotated to the voltage of Vcc / 2 and the cathode of diode D 11 will therefore be at the voltage Vcc / 2 - Vbe, which voltage appears on the basis of transistor Q 13. Hence, in the idle state, transistor Q 12 is closed and the tristor Q 13 is open. The base of transistor Q 11 will be at Vcc / 2 - Vbe due to voltage drop across diode D 10. The base of transistor Q10, which is also line 21, will be at

<td>Vcc / 2. Kmitory tra</td><td>. nzisto r</td><td>Q 10 and Q</td><td>11 will be on</td><td>Tension</td>

<td>Vbe. From there in the same</td><td>key</td><td>stav bud</td><td>e transistor</td><td></td>

<td>and transistor Q 11</td><td>bude rozi</td><td>pnut. when</td><td>positive.</td><td>napě-</td>

<td colspan="2">W in W from VAV 2VV5.1 voltage level</td><td>on the anode</td><td>diodes b 1.1 n</td><td>and hod-</td>

note Vcc / 2 τ Vbe, the voltage based on transistor Q 1 'j rises n;

- 1 R value of Vcc / 2, which is jc. sufficient value to switch on transistor Q 13. Simultaneously transistor Q, 12 opens. When transistor Q13 closes, the base of transistor Q14 will be pressed to ground and transistor Q14 will close. When transistor Q14 turns on, a positive pulse of frequency is initiated on the collector of transistor Q14

2f_TT. When the positive voltage spike on line 17 ends, the additional voltage on capacitor G2 dissipates at a time constant determined by the values ​​of resistor It 1a and capacitor C2. When capacitor C2 is sufficiently discharged, transistor Q 13 opens and transistor Q12 closes. When the thyristor Q1J opens, the transistor, V / / vx * ZV odone, and pulse 2f is terminated. When the negative voltage spike reduces the voltage at line 21 to Vcc / 2-Vbe, transistor Q1

K 11 turns on, transistor Q if it turns on and generates another positive pulse 2f ^. When the negative surge peak ends and the charge on capacitor C2 discharges, transistor &lt;11 opens, transistor Q14 opens, and terminates the positive pulse. Although the pulse width of 2fp -REF on line 23 will vary somewhat, this variation is of no significance since the phase comparator 26, which is an integrated circuit of type 1391), is edge sensitive. It is only necessary. abv pulse width for imoulsú 2f_T-bKF bvla broad blade approached not 1/2 pulse derived from the reverse run, the second input to the phase comparator. This minimum width can be provided by a suitable choice of capacitor Cz and resistor K l.

At the same time, the pulse width should be maintained as narrow as necessary to maintain a fast switching response in the transducer circuit.

The single chip circuit 12, which is the analog circuit shown in Figure 1, is in the form of an industrial type single chip circuit TA 80. The line image signal 1f, which is the input to the sync pulse separator 14, provides vertical sync pulses on line 43 and burns the zontal sync pulses 1f on line 3b. The synchronization signals 1f on line I / i shown in Fig. 3 (a) are input to the phase comparator 6. The output of the phase corrector 6 on line 15 shown in Figure 5 (b) is an error control signal input to the low pass filter 20 The low pass filter frequency response, for example in the TA 80 circuit, is determined primarily by the external timers. From here, block 20 is shown in dashed lines. The external elements may be a series RC circuit having a capacitor of 10 microfarads and a resistor of 3 kiloohmv resistor connected between the capacitor and ground. The channel-controlled oscillator 48 responds at a frequency of 32 fv * II in response to a ceramic resonant circuit 30 - Rated timing signal 32f on line 49_; shown in Fig. 5 (c), is input to circuit 3.2; 32 is the excitation signal 1f 'shown in FIG. 5d. tignal. 3 f ,.

H h jt. input to line 33 to the second phase comparator LOR 15, which may result in the error control voltage of FIG. 10 (b) being. adversely altered by the ripple 1f, p as shown

- 21 neiio. If the width of the pulses fed back to the phase comparator 1b is too wide, the pulse width may be reduced, for example, by a series capacitor 5, -4. The output 32 Γ ** of the resonant circuit 50 is also accessible from the outside of the single-chip circuit on the 5.1 vedení line.

The progress sweep control circuit 50 also provides a number of control functions. The output 31 of resonant circuit 50 on line 51 and output 1f on line Fg are inputs to circuit 50, divided by 6. The signal provides a clock output for the 5S circuit. The output of circuit 58 divided by the number 6 is a timing signal at frequency 2f, which is twice the frequency 1f.

Η h of the output of circuit J2, divided by 32. Timing signal lf_I.Eon line 17 provides a preset synchronization signal for initiating the counter of the circuit 38 divided by the number 6 and the synchronization of the circuit 58 with the signal lf on the line 17.^C input of the pulse width OO circuit. The pulse width bp circuit provides. the pulse width in the uncorrected signal 2f, - - JdJF on the ole line will be wide enough to ensure proper operation of phase comparator 64 in the CA 1391 phase locked loop loop integrated circuit.

As is also the case in the circuit shown in FIG

2í_r} iiicincky only to t &lt;; mi.ry, into mz is conceived vur signal utilization factor lf 5Ctip percent. The effect of the ripple of the signal 1f on the momentary control loading oro of the voltage-controlled oscillator 52f η n is reflected in the form of the signal in Fig. 5 (b). The error control voltages periodically decrease during each period 1f. Hence, the solar frequency f,.,., From the voltage-controlled oscillator

IN WHAT

32i 'decreases periodically, during each period 1f. As the turn '*' ll turns, each successive output pulse from the voltage controlled oscillator 32f_TT has a lower frequency. When the frequency drops.

r1 rotates the signal 1f, which has a period 32 of output pulses of the voltage-controlled oscillator 32f, by halving the period, i.e. into two periods with 1.6 pulses. However, due to the decreasing frequency of the voltage-controlled oscillator 1f and due to the pulsation-wise pulse widths, the summed width of the first 16 pulses t is less than the summed width n of the following sixteen pulses t. . When duration t so¹ Β does not equal duration t_in, the timing signal 21-KEK of symmetry 11 is not during the signal period 1f regardless of the accuracy of the digital divider. This asymmetry can cause reverse pulses of alternating amplitudes Ϊ1, Y2 as shown in Figure 5 (f), which are analogous to the reverse pulse shown in Figure 2 (c), which can lead to bifurcation of the grid. The 2f -RilF signal generated by the digital circuit must therefore be treated as an uncorrected signal, which requires further processing.

The line comparator error control signal 64 on the line is the low pass filter input 63. Lowpass output 6 /

22 is the control input of a voltage controlled oscillator 66 that operates at a frequency of 2f and is referred to as a 2f VCO. Working

XX XX the frequency of the 1391 oscillator and the low pass filter response are determined by the external timing components as shown in more detail in FIG. From there, block 63 is shown in dashed lines. The low-pass filter 6 is determined by a series fc circuit made, for example, by a capacitor C 53 with a capacity of 1.5 microfarads and a resistor K 68 with a resistance value of 2 kilograms. The output of the voltage-controlled oscillator 66 on line 67 provides corrected synchronization signals 25 for the horizontal output circuit 68. The output of the horizontal output circuit 68 on the line provides a signal 2f in the form of a reverse run pulses 2f. Reverse run irrigation 2f is an input to the uplink function accelerator / 0, which is podio he n of a manually controlled phase delay via a manually controlled delay circuit 72. The output of the rising function generator 70 on line 7.1j is alternately coupled by capacitor C 56 to the second input of phase comparator 64 by line - o

The waveforms of Figures 6 (a) to 6 (d) show the relative phase positions of the 1f and 2f-bPF signals. generated in the circuit of FIG. Fig. 6 (a) shows synchronization pulses 3, separated by a separator 11 of the sync ons of the pulses and provided by a phase comparator Ifa on line 13. FIG. 6 (b) showing the output 1f of circuit 52 by division number 32 on line 53.

The first phase locked loop is therefore responsible for maintaining the relative phase of the leading edge of the pulses 1f and the center point h.

for example synchronization pulses 3 f. Thus, the centering can be adjusted by a delay or filter circuit, shown as a capacitor. As shown in Figures 6 (a) and 6 (b), the delay circuit is not a delay delay. Giant. 5 (c) shows a 2f signal,_T- * µF, generated by the pulse width circuit OO on the line λ, which is one of the inputs to the phase comparator of the second phase locked loop 62. How? even in the case of the circuit of FIG. 1, the second phase lock of FIG. 4 for the synchronization of the corrected signal 21 &amp; apos ;, with the synchronization signal 1f and being effected by averaging the asymmetric timing errors in the non-corrected 2f-kappa signal caused by ripple 1f. Ο'τ. δ (c) shows a backfire pulse 2f on line 69. The in-line control circuit 7,2 for the ascending function generator 20 allows the phase difference to be adjusted between the corrected I3 and the pulses 21 &amp; apos ;.

η n

The wiring diagram for part of the block diagram shown in Fig. 4 is shown in Fig. 7. The phase locked loop circuit 62 is embodied by an industrial type of integrated circuit CA 1391. The circuit 62 comprises an oscillator 66, phase detector 64, pre-biaser 4, output driver 86 Phase Detector &amp; Numeric Controller &amp; 7 Vcc. Oscillator 60 is of type 0 with terminal 2 used for frequency control. The external capacitor O is connected from terminal 2 to ground and charges sc via the external resistor 62, connected between terminals 6 and 2. When the voltage at terminal 2 exceeds the internal potential biases, the capacitor C1 discharges through the internal resistor. This line causes the generation of an excitation pulse that ends when the capacitor is sufficiently discharged. The discharge cycle is performed in response to the sawtooth signal at terminal 4. Negative synchronization pulses; at terminal 2 they are phase-aligned with the sawtooth at terminal 4, which is derived from the horizontal pulses of the return run. If there is no phase difference between the synchronization signal and the sawtooth waveform, there is no net output current at terminal 2 · When a phase shift occurs, the current flows either to terminal 2 or from terminal 2 P^ro frequency correction. The utilization factor of the preamplifier 84 can be adjusted by setting the potential at terminal 8. In the circuit of FIG. 7, this is determined by a voltage divider formed from particles 63, 64, and potentiometer 37 connected to terminal 2 via line 72 may be. used for manual frequency adjustment on oscillator 66.

The ascending function circuit 70 includes an Iran resistor 34, a resistor 35, and a capacitor C 50 The rising signal generated on the capacitors 50 is alternately connected to the terminal j via the capacitor C. Tranzisior ^ 2^and potentiometer:. 20 for virus¹ , a manually operable delay circuit / 2, which changes the charge required to charge the increasing capacitor C 5C. Changes in the time required to charge the C 50 condensate give a variable delay of approximately 0 to 2 microseconds in the relative phase of the pulses kf-talk and the corrected irnnuls h ii

Corrected output 2f of preamplifier84 on line 6 / jc of symmetrical excitation circuit input containing transistors

Q 5 and Q 6, which provides an excitation output signal 2f "to the 1x horizontal output circuit.

<img file="CS9100800A2_D0001.tif" />

nr. a first horizintal synchronization frequency corresponding to a horizontal synchronization component in the video signal, characterized by means (56) for deriving a second timing signal on the line (61) from the first timing signal, wherein the second timing signal has a second frequency at the beer frequency multiplier and subjected to frequency changes with a frequency corresponding to the first frequency, a second phase locked loop (O 2) for receiving a second guide signal (6l) and a line feedback signal (73) in accordance with a second frequency, including a voltage controlled oscillator (66) for generating a balanced horizontal synchronization signal on the line (6?) at a second frequency where the second phase locked loop (62) has a chav, _in a characteristic loop response preventing the voltage controlled oscillator (66) from changing the frequency as fast as j; the frequency of the variation of the second timing signal, and the horizontal output deflection stage (68) connected to the second phase locked loop (62) for synchronized horizontal sweep. second frequency.

2. Connection according to claim 1, characterized in that it is set. feedback signal on line (55) Ρ'Ρ first loop (12) ι ~ ι z

phase lock is derived from the first timing line (l?) ​​·

3 · Poodle connection: claim 1, characterized by a signal at the third stage and (o J) of the phase lock ()j) (22) of the phase lock comprises a low-pass filter a voltage-controlled oscillator (66). who down has a frequency response determining the loop response.

4. Connection according to claim 1, characterized by. that the feedback signal on the line (73) is derived from the pulse feedback pulses (69) from the horizontal

<td> ( /6 )</td><td>priovi tcho</td>

<td></td><td></td>

<td>nálu</td><td>on leadership</td>

<td>happening</td><td> (69).</td>

an output deflection stage (68).

5. The wiring of claim 4, wherein the DC signal circuit is used to generate a feedback signal. _of (73) in response to the backward pulses in claim 1, characterized in that the four-week pulse periods of the second timing signal (s) in each pulse period of the timing signal (17) are constant.

A horizontal deflection engagement comprising a means (56) for generating a first timing signal on the line (0o) at a first frequency subjected to periodic variation

O. C ont. · Η ipo t 1 e.

the sum of us on the line of the line to the in line frequency at the frequency of the second lower frequency, the phase locked loop for receiving the first timing signal on the line (6l) and the feedback signal on the line (73) in accordance with the beer frequency comprising a controllable oscillator (6) for generating a balanced horizontal synchronization signal on the line (67) at the first frequency, wherein the phase loop (62), _xThe hinge has a characteristic loop response preventing the controllable oscillator (66) from changing the frequency as fast as the frequency of the first timing signal on the line (ol) and the horizontal output deflection stage (68) connected to the coil. a phase locked loop (62) for synchronized horizontal scanning according to the beer frequency.

The wiring of claim 7, wherein the external frequency 2f is a multiple of the second frequency 1f._T.

th

Connection according to claim 7, characterized in that the external frequency. 2f, 1 is an even multiple of the second frequency 1f. - ri

10. Connection according to the bead 7, indicating the seeding 1; wherein the phase locked hay (62) comprises a low pass filter (63) for controlling the oscillator (66), wherein the low pass filter (63) has a frequency response determining the loop response.

The wiring of claim 7, wherein the feedback signal on the line (73) is derived from the feedback pulses on the line (69) from the horizontal output deflection stage (66).

12. The circuit according to claim 11, characterized by a saw circuit (?) Of the signal to generate a feedback signal on the line (7a) in accordance with the pulses of the feedback god.

Connection according to claim 7, in which the phase timing loop (12) is 1 υ nave ri at a rate synchronized with the component (13) of the obi

<td>y</td><td>Z Π</td><td>and no</td><td>aj</td><td>í c í</td><td>se</td><td>d ru -</td>

<td>záv</td><td>CS u.</td><td>for</td><td>Γ n.</td><td>Rendering</td><td>ri ruin.</td><td>him</td>

<td>her</td><td> (17:</td><td>| v í</td><td>&gt; About 1 cii</td><td>du s dr</td><td>uhým</td><td>km i-</td>

horizontal synchronization of the wobble signal (II).