Method of packet communication in information system

The invention relates to information systems in which data is transmitted in packets and in particular is swept into a method of memorizing data in packets transmitting information from the originator to the designated recipient by entering the information into the packets. Each packet contains an introduction (control data) and information (a message), the introduction tyrically contains network control data, synchronization information and destination information. The information section contains part of the overall report of the originator.

A packet issued by the originator is typically not received directly by the recipient. The packet may be transmitted by several intermediate stations before reaching the specified destination. As the transmission speeds of packet networks increase, the need for intermediate stations to be able to efficiently handle and process packets increases.

In the direct way of handling packets, the received packets are stored in a certain memory location. The packet determination contained in the introduction is validated just like other network control information. The correct reception or evaluation of control information and data information is verified. Assuming no errors are detected, a new packet is created corresponding to the received packet and λ is stored⁷ another place - memory for transmission. At the appropriate time, the rebuilt packet is sent by the intermediate station to its final destination.

The} - packet is treated differently in the local area of ​​your Ethernet network. A powder ring structure consisting of a series of fixed length buffers is used to remember received packets. The beginning and end of the memorized packet are identified by the addresses stored in the page start register and the page trace register, n sequential ring buffers are used to memorize the packet. The number of packets can be sequentially stored in a ring structure, the rockets are normally selected from the ring reception buffer of the FIFC order and are recovered for resending in a memory separate from this ring.

It is an object of the present invention to provide an improved method of organizing and handling packets that minimizes data transfer to additional memory locations prior to sending a packet. The present invention allows the assembly of packets for transmission from information stored in separate memory locations by creating in

hierarchy of compressibility. This addressing provides a high level of flexibility in defining or redefining a packet, without duplicating data in multiple memory locations.

The invention is illustrated in the drawing, where Fig. 1 is a block diagram of an example of a pellet switching system according to the present invention; Fig. 2 is a block diagram of the packet switch of Fig. 1; 4 shows the information contained in the pajset header

Fig. 3 is a diagram illustrating a method of addressing a packet and an organization according to the present invention; Fig. 3 shows the contents and format of a virtual circuit register of Fig. 5; 5, FIG. 5 shows the contents and format of the packet description of FIG. 5, and FIG. 5 shows the contents and format of the buffer description of FIG. 5. ·

Fig. 1 shows a packet switching system capable of outputting, receiving and transmitting information in a packet network. The central processor 10 is connected by a local communication bus 12 to the processor memory 14, a personal contact device 16, an interface 18 in^OF in the character data and with the packet switch 20. The host processor 10 may be connected to other interfaces by the local communication bus 12. The personal contact device 16 may include available peripheral interface devices suitable for a particular microprocessor contained in the central microprocessor 10, for inputting and outputting information to the user. The output information may consist of lights, visual displays and auditory signals. The inputs of the personal contact device 16 may be controllable switches, buttons, control potentiometers and other transducers.

The 18-character data interface may consist of available integrated circuits as translators for adapting a particular microprocessor via its bus to an RS232 device to allow data input and output. Other interfaces may also be used to interpret data supplied by other protocols, such as Ethernet,. ^ or have a token-circuit and ΪΕΚ327Ο format, as well as other forms of data transfer.

The packet switch 20 is connected to the local communication bus 12 and the rocket bus 22. The interface 24 is connected to the packet bus 22 and is used to provide input and output for a particular communication device or network. A number of interfaces suitable for connecting various networks or devices to the packet bus 22 may be used. For example, interfaces may be used to connect the packet bus 22 to a telephone, a TI circuit, an 18LK circuit, and network devices, and the packet switch 20 is to receive and transmit packet data between interfaces on the packet bus 22. It also communicates via the processor bus 12. with the central processor 10 and other networks and is provided via interfaces connected to the processor bus 12. the rocket switch 20 acts as a traffic officer.

Fig. 2 shows a block diagram of an exemplary embodiment of a packet switch 20 that includes elements connected by bi-directional buses. The processor interface 26 connects the processor bus 12 to the memory interface 28. This memory interface 28 is connected to a random access memory 30, which is divided into a control memory 32 and a data memory 34. The rocket bus 22 is connected to a packet bus break 36, input control function 38 and output control function 40 with memory interface 28.

Packet switch 20, as generally shown in FIG. 2, is merely an example of the general organization and function of packet switch and is intended only to facilitate understanding of the method of the present invention. Because various types of packets are known in the art

The specific operation and details of the internal function of the packet switch will not be explained, as the present invention is not limited to a particular packet switch. In general, the functions of a packet switch may be fulfilled in hardware by a machine state implementation or may be primarily fulfilled by a software implementation.

Fig. 3 shows a typical format of information sent during one time slot on the packet bus, the format shows the transmission of local bus control information, packet origin and packet header and packet information (messages). The local bus control information consists of the address of one of the interfaces connected to the packet bus. The packet introduction is created for synchronization purposes.

The packet header will be explained in detail below. the rocket information (message) contains information transmitted between users.

Fig. 4 shows information contained in the packet header of Fig. 3 according to the present invention. The header contains the identification of the virtual circuit, packet length information, intermediate determination information and evaluation information. The virtual circuit identification contains information that identifies the virtual circuit register contained in the packet switch 20. More information about this element is provided with reference to the following figures. Packet length information indicates the length of the packet information (message). The destination information contains the destination address. The evaluation information contains data related to the calculation of the accuracy of the CRC data.

Fig. 5 shows an example of a packet handling method and organization according to the present invention. In an exemplary embodiment

In the present invention, the packet information identified in Figure 3 is stored in buffers 52A-52C and 54A-54C. These buffers form part of the data memory 34. The control memory 32 provides memorization for commands associated with the other elements shown in FIG. These elements facilitate the way packets are organized and reorganized according to a hierarchical approach.

Virtual circuit register 41 indicates or addresses order control block 44. Each order control block can write or read a packet description. As shown, order control block 44 points to packet description 46A.

Each packet description may be directed to a read buffer description and a write buffer description. Alternatively, it may point to another description of the packet. As shown, the description of the 4AA packet points to the description of the 4SA buffer and to the description of the 46N packet.

Buffer phrases always point to one buffer and to the following description of the write buffer. In an exemplary embodiment, the description of the 4SA.-4C buffer is directed to buffers 52A-52C. Also, the description of the 48A buffer is directed to the description of the 48B buffer, which is directed to the description of the 48C buffer, thus forming a continuous chain or bond. The 5OA-5OC buffer descriptions are similarly organized relative to each other and relative to the 54A-54C buffers.

Before further explaining the functions of these elements, it is believed that explaining the benefits of this organization will help to understand the organization and function of each element. An important aspect of the present invention is to provide an improved level of flexibility in defining and redefining a packet without requiring substantial duplication of data by the microprocessor. This is generally accomplished by creating a hierarchy

-Addressability, where received packets / are disassembled and stored in separate memory locations, the rockets to be transmitted are grouped sequentially, addressing separate memory locations.

Fig. 6 shows an example embodiment of the contents of the viral circuit register 42, which forms the address level of the ultrapacket. As shown, it contains the control block order address 56, * maximum packet size information 58, virtual circuit type identifier 60, interrupt data 62 transmitted^of of the CPU, the CPU interrupt data of the CPU, and various control data 66. The address 56 is used to route to the order control block 44.

The maximum packet size field identifies the largest packet that can be received for a given virtual circuit register® - it can be used to protect the packet from memory overwriting.

Virtual circuit type pats indicate whether a special virtual circuit register is valid as an input or output circuit.

The transmission and reception interrupt fields of the CPU interrupt the information to be generated, and if so, its priority. An array of different control data can be used to accommodate additional control information, which may be useful for the specific implementation of the method of the present invention.

Fig. 7 shows the fields associated with the order control block 44, which forms the address level of the superpecker. The order control block consists of write and read packet description addresses 66 and 70. The write packet description address points to the description of the packet to be used to write the received packet. The read packet description address points to the description of the packet to be used to read the strong pfcicet. This address is overwritten when receiving and transmitting packets.

Cbr.S shows the fields associated with the descriptions of the 46 packets that make up the packet level address. Each packet has a description of the packet, which points to the descriptions of the read-write buffers, the address 74 of the description of the write buffer points to the description of the first buffer, which is used to receive the packet. Address 74 of the read buffer description points to the description of the first buffer, which? to be used to send a packet. The following packet description address 26 is used to point to the description of the nearest packet in circuit 77 (see Fig. 5). Ie illustrated embodiment descriptions? 46A to 46N form a circuit in which each points to the next, and where the description of the last packet 6M points to the first or initial description of the packet 46a. It should also be noted that packet descriptions may point to any packet description, not just the closest to the packet description in memory.

Further, the circuit may consist of only one packet description, in which the description address of the next packet is its own address, the frame number role 78 indicates in which frame the tulle packet is received.

Field 80 position? frames indicates the start position of the packet origin within the frame.

An array 32 of different control data may be used of the desirable data associated with the description level to remember the packet to facilitate specific implementations.

Figure 9 shows the buffer description field that forms the subpacket level address. Pol-e 34 addresses? buffer contains the addresses of the first byte in the buffer routed by the buffer description. In the illustrated example, the description of the 4SA buffer contained a buffer address pointing to the first byte contained in the buffer 522. The following field of the write buffer description address is used to refer to the next description of the buffer to be used to write the packet. Similarly, the following field of the SS address of the read buffer description is used to refer to the next description of the buffer to be used to read the packet. The size of the data field 90 indicates the size of the buffer used. buffer size 92 indicates the absolute buffer size. The various driver data fields 94 may contain useful data associated with the buffer description level for a particular implementation. For example, field 54 of various data may include a flag indicating the end of the packet.

The central processor is responsible for controlling the registers of the virtual circuit, block ;; order control, packet descriptions, buffer descriptions and buffers. It will be apparent to one skilled in the art that there are many ways in which a CPU can control the fields and memory associated with this organizational hierarchy for receiving, memorizing, and retransmitting a packet. For example, an order control block could be used to route to a fixed set of packet descriptions, which in turn point to a fixed set of buffer descriptions. Address 72 (when receiving packets) of the write buffer description or address 74 (when sending packets) of the read buffer description may be changed to add or delete packets from the sequence.

Alternatively, each packet would be assigned a set of buffer descriptions, which in turn would have an associated packet description. To add or delete packets from the sequence, packet descriptions could be added

-1Or deleted from the packet description circuit by changing the next missile description address 76 to route the packet descriptions in the desired sequence. These methods are only examples of, and show a high degree of flexibility with which a designer can control the transmission of packets by the method of the present invention.

Some other advantages of the method of the present invention will be explained below. Although the virtual circuit registers must each point to only one order control block, multiple virtual circuit registers may point to the same order control block. This may be desirable when handling a number of pskets that are identical or contain significant similarities. Differences between packets can be stored in different buffers and the common contents of the packets stored in a common buffer position. The CPU may stress the 88 of the nearest read buffer description in accordance with the move to its own sequence of buffers for slightly different packets.

The read and write addresses in the order control block allow the same virtual circuit register to be able to receive and transmit a packet. This preserves the number of virtual circuit registers that are required and minimizes the transmission of repetitive data between receive and transmit cycles.

Each packet description defines a specific packet. An important feature of packet descriptions is the ability to route to the next packet description via address 76 to create packet descriptions in a circuit that points to a plurality of packets. The size of the circuit, i.e. the number of packets that can be sequentially identified, is limited only by the capacity of the respective memory available in the control memory 31 ε data 34.

Because everything that is a genus of packet description levels is dependent only on

on a single packet, the CPU cannot move the redundant data and only be able to send the packet. This is a significant advantage, especially when tc is used in a packet repeater in which all or almost all of the received packets are to be retransmitted.

Buffer descriptions allow the economical use of a number of fixed size buffers. Because a number of buffers can be bound to buffer descriptions, it is possible to memorize common or repetitive information or control data in selected buffers and bring in, if desired, addressing the associated buffer description and changing the description address of the next buffer to read or write. For example, a shared packet introduction consisting of synchronization data may be stored in a single buffer, and that buffer may be addressed to multiple buffer descriptions, thereby creating multiple accesses to the common data. This also provides the advantage of permanently storing certain information in the buffers and allowing this information to be reused by reading it directly from the buffer with the appropriate sequence in later-wrapped packets.

FY £ C'2C ~ V <E