Encoder

O_B_L._A_S_T ___ T_E_C_H_N_I_K_Y

The invention relates generally to data encoding.

Business data is normally transmitted over a wireless or telephone connection, said data may relate to business or commercial operations and should be kept confidential.

The data thus transmitted may be received by competing companies of the considered company and used for their benefit or to the detriment of the considered company.

One solution to this problem is to encode the data before transmitting it and to decode it after receiving it, the data being encoded normally by a coding circuit using keys and a polynomial which manipulates the data. an example of a coding circuit is shown in FIG. The data to be encoded passes through the shift register in chronological order. Certain shift register outputs are fed back to the exclusive logical summation / OR / with the output of the previous stage. The polynomial determines in which states they are led back. The key determines the initial state of the shift register. The output of the circuit is encoded data, representing the original data, but about which they do not provide any data. When the encoded data is received, it is decoded using the same circuit and thus the same key and polynomial used in encoding the data.

Ideally, only the considered page has the key and polynomial used for encoding, and therefore only it is able to decode the captured data.

As the polynomial does not change, the competing party, equipped with the knowledge and equipment to decipher the code, has enough time to operate. Another problem occurs when the polynomial changes with motion

- 2 feedback paths. Then, the data from the shift register must be ejected using the old encoding before the new encoding can be started. Also, the gradual shifting of the data to be encoded creates a delay between the input of the data and its encoded output. This creates the need for a zero-delay coding circuit using programmable keys and polynomials that would make unauthorized decryption more difficult.

THE ESSENCE IS EXCELLENT

The present invention provides virtually zero latency encoding / decoding. The device consists of two memory logical product / AND / devices, a shift register and exclusive logical addition / OR / devices. Each of the outputs of the first storage device is connected to a shift register input. Each of the outputs of the second memory device is connected to the input of each of the logical product (AND) devices, the outputs of which are connected to the inputs of the shift registers. The output of the last stage of the shift register is connected to the input of each of the logical product / AND / devices. The output of the previous stage of the shift register is connected to the input of an exclusive adder (OR) device, the second input of which is connected to the output of a logical product (AND) device, the output of each of the exclusive logic adders (OR) devices is connected to the input of the next stage of the shift register. Each of the outputs of the first eight stages of the shift register is connected to each of the inputs of the exclusive logic adders (OR) devices. Each bit of the encoder input is associated with the input of an exclusive adder (OR) device.

The key is stored in the first storage device and the multi-member is stored in the second storage device. The key and polynomial used to determine how the input data will be encoded are known to the receiving side of the transmitted encoded data. The key is included in the shift register and each bit is shifted by exclusive logical adders / ORs / devices to the next stages of the shift register. The outputs of the last eight stages of the shift registers are exclusively logically added / OR / with the input data. The outputs of these exclusive logic adders (ORs) are encoded data.

S_T_R_U_Č_N_Ý ___ P_O_P_I_S ___ Y_Ý_K_R_E_S_g

The invention will now be described, by way of example, with reference to the accompanying drawings, in which: FIG.

Fig. 1 is a block diagram of the state of the art of data coding

Fig. 2 is a block diagram of the present invention

Fig. 3 is a block diagram of the present invention used in a typical system of use

Fig.4a memory map of polynomials for system use Fig.4b memory map of keys for system use Fig.5 coded information format

Fig. 6 shows a variation of the embodiment of the present invention.

___ p_B_Q_Y_e_d_e_n_í ___ v_y_n_á_l_e_z_u

The coding circuit of the present invention can encode / decode both voice and data information with substantially zero delay.

This is achieved in that the input encoded / decoded data is not shifted by a shift register, as was the case in the prior art. The only delay in the circuit that occurs is the delay associated with the exclusive logic add gates (OR, XOR), 105. The present invention also allows for easy key and polynomial changes by simply entering new values ​​in the appropriate register.

The coding / decoding circuit preferably comprises two registers; one lpi register for the key and one 1Q2 register for the polynomial. The key and polynomial, determined in advance, determine when and how the data will be encrypted. If both the key and the polynomial are zeros, the encoding / decoding device sends the data without encoding / decoding. If one of the mentioned devices has a non-zero value, then the circuit will encode / decode differently for different values.

Each output bit of the key register lpi is connected to the input of a parallel-filled shift register 104. The shift register 104 must have a length equal to the number of key bits. In a preferred embodiment, the key and the polynomial are 32 bits long. A modified embodiment of the invention may have different key and multi-member lengths and may still work properly.

Each output bit of the polynomial register 102 is connected to the input of three input logical product (AND) gates 103.

The second input of the logical product / AND / gate 103 J^E connected to a deactivated line, which is also connected to a free key register entry. The deactivated line releases the lpi key register and disables the polynomial, for transmission of input data by the coding circuit without encoding / decoding. The third input of each product (AND) gate 1Q3 is connected to the output of the last stage of the shift register 104.

Each output bit of shift register 1Q4 is summed / XOR / with the output of the respective product / AND / gate 1Q3. The output of the adder / XOF / gate forms the offset of the input of the next stage of the shift register 1Q4. In a preferred embodiment, the outputs of the last eight stages of the shift register 104 are summed (XOR) with the input data to be encoded / decoded. in a modified embodiment, any eight stages of the shift register can be used as inputs to the adders (XOR) gates. The outputs of these adders (XOR) gates 105 are encoded / decoded data.

At the beginning of the data encoding / decoding, the value stored in the key register must be specified. This value can be a predetermined key value, or a predetermined key value changed by an addition (XOR) operation using a modifier. The modifier may be in the data stream passing through the coding circuit by the position number or the frame number of the data to be encoded. The key value, modifier, and polynomial are known to both the transmitting and receiving devices and prevent the unintended recipient from receiving these values.

The circuit operates with the first content of the key register lpi with the key value or the changed value and the polynomial register 102 with its value. The contents of the key register are then inserted into the shift register 104 before encoding the data.

The polynomial then determines when the output of the shift register stage 10Q4 will add (XOR) to the output of the shift register output stage 104. The binary digit 1 in any part of the polynomial allows the summation of the (XOR) bits of the shift register 106 with the output of the output stage of the register 1Q4 fed back by the product / AND / gate 103. time cycle, after encoding each byte of input data and transmitting, the shift register is clocked to shift and decrease its contents by one bit, to encode / decode the next byte of input data.

In a preferred embodiment, the shift register may be time shifted by one bit. The rate of shift register timing may be programmable in another modified embodiment. In a modified embodiment, the shift register may be time shifted by one byte.

Figure 3 illustrates the use of the present invention in a conventional transmission network in which data and / or voice converted to digital display is transmitted in time division multiplex (TDM) frames between a first device 300 and a second device 320. The memory 305 contains keys and polynomials used for encryption. , the packet switch transmits the encoded data over the packet switch bus 30I to either the radio interface 303, the telephone interface 304, or another such interface on the bus 30I. said interfaces, on the other hand, transmit data to a receiving device 320 provided with similar interfaces 303, 304. the receiving device 320 is provided with the same device for decoding the received data.

Giant. 4a, 4b show possible memory maps of polynomials (Fig. 4a), and memory maps of keys (Fig. 4b) of such a system, memory addresses 305 of keys and polynomials are transmitted to the receiving device by the coding information word shown in Fig. 5. The addresses of the keys 501 and polynomials 502 in the coding information word indicate the location in the memory 305 of the polynomial key maps used to encrypt the data. This allows the receiving device, provided with the same memory maps with the same keys and polynomials, to decode the data. The logical sum frame number / XOR / 503 tells the receiving device whether the last valid bits have been summed / XOR / with the time division multiplex frame number. The frame numbers are synchronized between the two devices 300 «320« In a preferred embodiment, “1” indicates the possibility of placing a logical sum / XOR /, and O indicates that the key can be used without changes.

If the network bandwidth shown in Fig. 3 is reserved for transmitting information from the first device 300 to the second device 320, the key and polynomial address information is sent to the control device in the information allocation bandwidth. From reallocating the bandwidth as needed, the key and polynomial are directly changed. When the devices 320, 300 transmit the information, the keys and the multi-member determined by the communication of the addresses in the frequency bandwidth allocation are used. This allows the use of different key and multi-member combinations whenever transmitting information, if necessary. In other embodiments of the invention, the key and multi-member may be changed by directly sending an encrypted control message from the first device 300 to the second device 320 and vice versa.

A modified embodiment of the present invention is shown in Figure 6. This embodiment uses two polynomials, a multiple of the polynomial and a proportion of the polynomial. The method described above, relating to a preferred embodiment, also applies to this modified embodiment, except that the second polynomial must be stored in the second polynomial register. The output of the second polynomial is multiplied (ADN) by a deactivated signal and input to the first stage of the shift register. The outputs of the product (AND) gates are summed / XOR / with the first polynomial and with the outputs of the shift register as in the preferred embodiment. Connecting a second polynomial increases the operational safety of the device, as the unwanted listener now has to decode two ever-changing polynomials.

The use of an ever-changing key and a programmable polynomial or polynomials increases the security of the system, at a time when the unwanted listener is decoding the polynomial, a new key and polynomial is used to encrypt the data. The unwanted listener will always be one step back behind the coding circuit, which makes data decoding and / or digital voice expression very difficult.

The substantially zero delay of the present invention eliminates the time gap that occurs in prior art devices between input and output of data from the encoder. Another advantage is changing the keys and the polynomial at any time, without waiting for the data being encoded to be ejected from the shift register. This increases the frequency of possible key and polynomial changes, thus increasing system security.