System of connection of the control spare computer

BACKGROUND OF THE INVENTION The present invention relates to a connection system of a control computer and a back-up computer substantially identical to. a control computer forming a synchronous parallel connection of the control and back-up computers, which consists of pulse generators common to both computers and connected to them by means of a time bus which is part of the bus system, each computer comprising addressable functional units such as memory and arithmetic unit; control register, which are interconnected by data! busses and address and command busses which are part of the bus system, wherein at least one of the functional units comprises a plurality of optional instruction registers.

It is known to cooperate with a data processing device in which the backup computer is prepared in advance for the final start. This preparation prepares the control computer for parallel operation. The start-up sequence is introduced into both computers by preparing start-up instructions. For example, a backup computer is commanded to interrupt any test program, followed by a command to the control computer to issue a ready-to-start impulse at the earliest opportunity, for example upon termination of a routine program.

Another way of collaborating is to provide the backup computer with data, so that it can take control of the process at any time if necessary. Another very important way of collaboration is to continuously compare data for which a data conversion channel can be deployed. The fourth way of cooperation is to diagnose a defective computer using an identical, defect-free computer.

Furthermore, there are numerous possibilities for two identical computers to work together. By "parallel synchronous cooperation" it is to be understood here that the inputs of both the data processing devices and the output of the control device are connected to the controlled process. The data currently produced by the two devices is continuously compared with each other. In the event of an error, the control process is only stopped until it is determined which of the two devices is faulty. Then the control continues only with a device that is OK and the error is corrected as soon as possible, because this state of operation must be operated without continuous data comparison. Such an arrangement is also called a “twin”.

In systems consisting of a control device and a standby device operating in parallel synchronization, synchronization is achieved by means of synchronization pulses, for example generated by a synchronization pulse generator, shared by the two devices and connected to the synchronization buses belonging to the bus system of each data processing device. Each data processing device comprises a plurality of addressable functional units, for example, memory and arithmetic, control registers, between which data or data are conveyed. addresses and commands via data buses, resp. commands leading to said bus system, of which at least one functional unit comprises a plurality of select instruction registers storing instructions,. which are read and processed during one working period, activated by the synchronization generator and comprising a plurality of synchronization phases.

The aforementioned synchronization phase defines the smallest time period available for a logical state change in the data processing used.

One such data processing device with a set of command buses and data buses is described in U.S. Pat. No. 3,631,401. Compared to the more familiar data processing device, intended for a single specific task and therefore relatively inadaptable in terms of use for the new other tasks, enhancements, or upgrading capabilities of the individual components is the aforementioned device according to the aforementioned US patent, i.e. data processing equipment incorporating a general bus system, adaptable.

Thanks to a general bus system comprising a number of parallel wires for data, address and instruction transmission in parallel and digital form, to which all parts of the device are connected. For example, a data processing system provides a modular system in which the functional units of the data processing device are modular elements. The functional units are connected to the system of general buses in a uniform manner by means of uniform so-called interface. members or coupling units, for example in the form of registers controlled by codes. Choice of suitable modular elements. various constructions for data processing equipment, such as a mini-computer, can be obtained. - calculators or real-time data processing equipment for control. simple or complex processes.

Said modular principle of the general bus system is also used in the construction of telemechanical devices controlled by real time data processing equipment. Real-time control of telemechanical processes. however, it makes such demands that make it possible to distinguish between fast-functioning functional units from those which work slowly, ie. it is necessary to introduce different bus systems for different data processing speeds, the buffer units provided with contact elements being the connecting elements between the bus systems. Armed with the central function of the unit forming the control part of the data processing equipment and said buffer units between the central units. a. Peripheral units with very fast reactive logic elements, such as TTL circuits, ie transistor-transistor logic, and when connected to a central bus system, the characteristics of the bus system result in reaching the threshold to be taken into account when calculating the resulting data processing speed. Indeed, the data transfer rate achievable by one bus is influenced by the number of interface members, i.e. the number. connected functional units and geometric wire lengths in the bus system. An adapted limitation of the number of central portions therefore results in optimally short data processing periods over said central bus system and thus also a very effective real-time control of the telemechanical process.

In a real-time data-processing machine. over time, the processing periods are controlled by synchronization pulses from a synchronization generator that is connected to the functional units via a synchronization bus belonging to the bus system. Processing. the instructions apply to a certain number, for example four. If data is to be conveyed from the sending to the receiving functional unit, it receives instructions outside the code expressing the transport of the address of the sending and receiving functional unit in digital form. The instruction sequence counter activates the respective instruction register during all synchronization phases of the processing period, so that the code and addresses are supplied to the command bus of the bus system throughout the processing period. During the second to fourth synchronization phase, data is transmitted through the data bus by the unit's function. Finally, during the fourth synchronization phase, said data is written to the receiving functional unit. Since when changing the logical state in the bus system, it is necessary to take into account If such a similar or similar phase separation of the processing periods is necessary, the frequency of the synchronization generator is selected so as to achieve the fastest possible data processing. high so that the time delays can still be controlled due to said oscillation and reaction times of the elements. A 20 MHz synchronization frequency and a processing period of 200 ns are common cases in practice.

When data processing equipment cooperates with general buses, for example in a system consisting of control and reserve equipment. these delays present various problems. As mentioned above, reserve equipment. is used, for example, to help. a continuous comparison between the data currently produced by the two devices was. Increased real-time control reliability. and .. operational reliability of the control by over error. created in one of the two devices ... the management of faultless equipment could be continued,. without the continual comparison. After diagnosis of the data processing device by means of the real-time controlled device and repair of the defective device, parallel synchronous operation is restarted, with the starting position being that the data processing device is operating alone and that the spare device is not supplied with data, ie the data stored in the processing device does not match. The cooperation consists in the fact that the reserve data processing device is precisely determined in a parallel operation with the control data processing device, that the instant data of the data processing device are continuously compared and that the malfunctioning device is diagnosed.

Synchronization of the two data processing devices is most easily achieved by means of a common synchronization generator, the synchronization frequency of which is determined by the synchronization phases, respectively. processing periods of both devices. In other known parallel synchronous data processing systems, each device is controlled by its own synchronization generator, wherein the synchronization generators are synchronized with each other. Despite the exact synchronization obtained by one of the above methods, phase shifts between the processing periods of the two devices arise as a result of the delays caused by the oscillation and reaction times of the elements. If, as described in this example, a stable logical state occurs in the bus system of an orphaned data processing device only in the fourth phase of the processing periods, the above-mentioned continuous comparison between the instantaneous data of the cooperating devices is questionable if · Displacement between devices the size of the order of one synchronization phase.

This problem, arising from phase shifts between data processing equipment, is solved by an existing device equipped with a frequency divider by which the phase shift can be neglected. In this case, the data, for example, every second processing period is then compared. As far as data storage is concerned, such a frequency divider arrangement is totally unacceptable, since if data is to be input using data produced by the data processing controller, then all data must be transferred to the spare device without, for example, being skipped every second processing period. Known. data input methods therefore allow, for example, interruption of control work until the data input is completed.

Another trivial solution consists in allowing the synchronization frequency to be reduced, so that said phase shifts become negligible. However, such solutions result in a general reduction in the ability to process data in real-time control.

In previous systems with a control device and a standby device, it is necessary to interrupt the recording of the data to the control device when the cooperation of the two devices commences until the data transfer program from the control device to the standby device has finished. Therefore, all equipment for a long time is not available for data processing, such as process control, etc.

On the other hand, it is an object of the invention to allow data to be stored in the reserve device during operation of the control device.

The solution is achieved by a control computer and backup computer connection system according to the invention, which consists of a starter pulse source connected to a clock pulse generator and connected to the bus systems of both computers, the data bus of the control computer being connected to the data bus. back-up bus through the transmission channel · data with one-way traffic delay: to the backup computer, and in the starting impulse source, a delay circuit is connected on the backup computer side with a delay equal to the traffic delay of the data transmission channel.

Other expedient embodiments, respectively. improvements are set forth in other aspects of the invention.

The connection system of the control computer and the standby computer according to the invention allows the two information processing devices to cooperate without adversely affecting the processing speed of the information in the non-redundant device and without interfering with the operation of the control device. The data entry is performed without interruption of the operation of the control device, although when the data is transferred from the control device to the backup device, there are time delays that are essentially unacceptable when processing instructions in the backup data processing device.

In the following, the invention will be explained in more detail with reference to the drawings, in which Figures 1 to 3 show the connection system of the control and stand-by computer, with various connection examples.

1 to 3 show a common synchronization generator CG and a functional unit FUe, respectively. FUr leading to control device E, respectively. which are connected to each other by means of a bus system consisting of data buses dbe resp. dbr, 'command buses both, respectively. and the synchronization buses tbe, respectively. tbr. It is further indicated that each of the two data processing devices comprises a plurality of IRS registers, respectively. An IRSr, an instruction consisting of several registers storing instructions that are consecutively or in a different order, for example, in the order prescribed by a step instruction, stored in saidevel bus system. Of these instruction registers, the BIRe BIRr mark indicates an initial instruction register, storing an instruction that inadvertently initiates the operation of the data processing equipment. Said registers' initial instructions are selected by. start jump instructions, converted to the respective set of command buses, the processing period of which determines the synchronization phases of the respective data processing device during the subsequent cooperation of the two devices, as described below.

The use of step instructions is part of a well-known data processing technique and the step instruction processing method only concerns the idea of ​​the invention insofar as it relates to the processing of instructions using a set of general buses connected to functional units as described in the introduction.

The control computer and backup computer connection system according to the invention consists of a starter pulse source SP connected to the CG clock generator and connected to the bus systems of the two computers E, R, wherein the data bus dbe of the control computer E is connected to the data bus dbr of the backup computer R by a DCH data channel with a one-way traffic delay towards the backup computer R, and a delay circuit equal to the traffic delay DCH data channel.

Thus, the circuitry to enable cooperation between the data processing devices with the general bus systems of the invention includes, as major components, a DCH data transmission channel and a starter pulse source SP with at least one delay circuit.

The data transfer channel DCH runs directly from the control device to the standby data processing device is used to cooperate with both devices, for example to store data in the standby device, which is done using data that is present in the data buses during control work of the control device. dbe and which are transferred by the channel to data buses dbr of the reserve device, ie. The data input into the spare device is performed in such a way that the real-time control of the control device is not disturbed at all. As is clear from the introductory explanations,. are the functional units of the data processing device created. according to the general bus principle, arranged so that the geometric dimensions of the bus system are as small as possible.

In parallel operation of two processing machines. however, the distances between the two devices are such that a symmetrical line between the bus systems is used for data transmission, thus implying that the data transmission channel has twice the number of wires, including a pulse amplifier and pulse regenerators, compared to a data bus system. The construction of the data transmission channel is shown in principle only in the drawings, since many different kinds of arrangements can be used. It should be noted that all solutions impose a time delay on the transmitted data, which exceeds the time period of one and both of the devices of the common CG synchronization generator.

Produces a reserve during data entry. device, erroneous data that must not be sent to the addressed function unit FUr. Therefore, the data transmission channel includes a control memory CM to manually or automatically record the transmission state that controls the transformer logic TL to open the transfer channel while preventing transmission of said erroneous data when the transmission condition ts is recorded.

In the embodiments shown in Figs. 1 and 3, the bus system of the reserve data processing device is divided into a receiving portion, by means of. which is conveyed to one of the functional units and to the transmitting portion by which the data is transferred from one of the functional units. By means of the first gate circuit G1 belonging to the transforming logic element tL ·, said parts of the bus system are connected to one another, respectively. separated, depending on whether the standby device is operating normally or if a transfer status is recorded in the control memory. Furthermore, the transforming logic element TL, by means of the second gate circuit G2, interconnects said part during the data input with the bus system dbe of the control device, whose logical state during this processing periods is transferred to the addressed functional units of both data processing devices.

In the embodiment of FIG. 2, the transfer state is generally not recorded for the entire system, but separately for. each functional unit separately. In this case, the second gate circuit G2 of the transforming logic member is activated to open the data transfer from the control to the standby device by the gate G belonging to the interface member of the respective functional unit and whose activation conditions are that the SDEC transceiver the unit for the purpose of transmitting data and that the conversion state ts is recorded in the control memory CM of the functional unit, which takes the place of the aforementioned common control memory, or. in addition to this. Place mentioned. splitting the data buses into the receive and transmit portions of the standby device, and instead of the first gate circuit of the transforming logic element, is used in the standby device in this case. a transmitting gate circuit SG belonging to a contact member of the respective functional unit, which is connected to said control unit CM of the functional unit by one input to manually or automatically record the transfer state ts for that functional unit. As a result of the recorded transfer state, the transmission of data to the standby device is prevented, while the recorded transfer state in one of the functional units of the control device does not affect the transmission of the data to the control device.

For the sake of clarity, only a contact member of the bus system of the reserve device is shown in FIG. This includes the contact member register REG, the RDEC receiving decoder, and the RG receiving circuit that access said gate G, the control memory CM, the transmit SDEC decoder, and the transmit gate SG. By means of the synchronization bus tbe in the bus system, the transmitting resp. the receiving gate circuit is controlled such that the activation occurs only during the synchronization phases to be transmitted, respectively. for receiving.

Transmitting data from the register of the interface member via the transmission gate circuit to the data buses dbr of the bus system, respectively. the reception of data from the data buses via the receiving gate circuit to the register of the contact element occurs when it detects the transmitting and transmitting circuits, respectively. a receiving decoder, connected to the data buses of the bus system, addressing the functional unit to transmit data, respectively. to receive data, and activates one of the inputs of the transmission, respectively. receiving gate circuit.

Said start-up pulse source SP comprises an intermittent signal IU unit and start-up circuits SDe and SDr for starting the respective device E, respectively. R for data processing. The intermittent signal unit is shown in the drawings as an additional functional unit whose contact member is connected in a conventional manner to the bus system of the control device. However, this does not mean that the bus system has to be attributed an additional impedance load, since the intermittent signal unit actually passes to an interruption unit, which is not shown in the drawings for clarity but is contained in any real-time data-processing device for control telemechanical equipment. The task of such a known interruption unit is to receive the incoming interrupt signals, to prioritize them and to issue a step instruction for each change of priority which selects the initial instruction corresponding to the respective priority level in the instruction register sequence.

In a system consisting of a control and reserve data processing device, the primary start pulse ps for the start of the parallel synchronous operation produces such an interrupt signal in each of the data processing devices. A bistable flip-flop circuit is shown in the drawings to explain the principle of starting the starting sequence for parallel operation of both data processing devices. F, CD calling unit and DEC decoder. Said bistable flip-flop F is brought to said first stable position α by said primary start pulse, thereby activating the calling unit. Into the sequence of instruction registers is inserted a register, which is regularly selected and in which the transport instructions for eventual interrupt signals of the interruption unit are stored. For example, the interrupt signal coming from said CD calling unit is so prioritized in the data processing controller that the real-time control instruction being processed is closed and an instruction register containing an instruction to deliver a coded clear signal to start the interworking to the interrupt signal IU unit is selected. , wherein said DEC decoder converts said bright signal into a secondary DC start pulse, Thus, without taking into account certain constructional elements, the function of the interruption signaling unit is that, as a result of activation by means of the primary start-up or the start-up flip-flop circuit F. The start-up pulse ps interrupts the ongoing control work and causes a secondary start-up pulse DC for parallel operation of both data processing equipment. Taking into account the above example, namely that one processing period of one instruction comprises four synchronization phases and that one functional unit addressed to receive data registers the transmitted data during the last synchronization phase of the processing period, said secondary impulse for start-up occurs. outputting an interrupt signal unit in a fourth synchronization phase of a processing period in which the clear signal transport instruction is executed.

For the above-mentioned starting circuits SDe SDr contained in the source of the starting pulse SP, the same applies to the interrupting signal unit as those which are also present in the individual data processing devices. In order to explain the principle operation of the individual operation, the drawings show the SIR registers of the start instructions and the first and second phase transmitters PG1 and PG2, connected sequentially by the synchronization generator.

Said start-up instruction registers store start-up instructions, which are essentially step-by-step instructions. Start-up instruction converted to command. The bus addresses a functional unit provided with a plurality of instruction registers and selects the above start-up instruction BIR register, optionally through a series of blind instruction registers, as explained in connection with FIG. 2.

Said first PG1 phase transmitter comprises a shift register for sequentially engaging a trigger pulse, such as said secondary start pulse ss, wherein in various embodiments of the proposed engagement, sequential engagement is used to detect individual processing periods or portions thereof or time delay portions as will be described below.

Said second PG2 phase transmitter comprises a circular step chain whose number of stages corresponds to the number of synchronization phases of the processing period. Thus, according to an example of practical application, the second phase transmitter has four shift stages that cyclically activate the transmitter outputs associated with the respective synchronization buses.

The circular step chain is provided with an input o which in the activated state. sets the chain to zero, which remains in this position until the activated input s starts the stepping. In this way, it defines the logical state of the processing period in the synchronization buses of the general bus system and dividing them into synchronization phases.

In the embodiment shown in FIG. 1, the first phase transmitter PGle of the data processing controller is connected to the output of the intermittent signal unit that transmits said secondary DC pulse. The outputs of the PGle phase transducer, which are activated during the processing period that follows immediately after said processing period for conveying a clear signal to start cooperation on the interruption signal unit, are coupled to the first ORe of the ORle, which transport causes secondary in its last synchronization phase. start impulse. The pulse emanating from said summing gate ORle is of the duration of the entire processing period and activates the first product read gate ANDle, by means of which said start instruction stored in the start instruction SIRe register is fed to the command buses of both data processing controllers. In this way, the processing periods of the control device are completely trouble-free in sequence when switching from a single operation to a parallel operation. There is no reset and restart of the second phase transmitter PG2e, which normally controls the processing of the start instruction via the synchronization bus tbe of the control device. Should it be required in the context of the start-up of cooperation to determine the processing periods and their synchronization phases again in the control device, the embodiment according to FIG. 1 can be adapted, for example, as explained in connection with FIG. 2.

On the other hand, in connection with the start-up of parallel operation, it is always necessary to reset the second transmitter PG2r of the reserve device phase. According to FIG. 1, the stable position a of said flip-flop F activates the resetting of the phase transducer, with the result that the operation of the reserve device in operation stops completely. Otherwise the start-up of the reserve device proceeds substantially in agreement with the start-up of the control device. The only difference is that. The first step of generating a back-up phase PG1r transmitter together with the back-up ORlr of the back-up device produces a pulse that is delayed in time compared to the pulse obtained from the sum-up gate ORle of the control device.

The delay occurs according to FIG. 1 partly by the delay circuit DE, which is connected between the output of the interrupt signal unit IU and the input of the first reserve phase transceiver PG1r, and partly by the step switching which takes place in the PG1r phase transmitter before the switching steps. which activate the summing gate OR1r, and the first of which starts the second transceiver PG2r of the reserve device phase. In another possible but not illustrated embodiment, both the first PG1 and PG1r phase transmitters may be executed in agreement, the delay circuit causing an overall time delay.

The delay circuit is, for example, in the form of a delay line, a separate shift register, which is stepwise switched by means of special synchronization pulses or synchronization pulses, in the form of a transfer channel whose design substantially coincides with the DCH data transmission data transmission, in the form of a common first PG1 phase transmitter, optionally in the. in combination with the so-called blind instruction registers, as will be explained in connection with FIG. 2, or in the form of the DCH data channel itself, as will be explained in connection with FIG. 3. If no blind instruction registers are used, the circuit independently of the selected design is dimensioned so that the entire delay between. The sum gate pulses ORle and ORlr essentially agree with the time required by any data to be converted from the control device data bus dbe to the reserve device data bus dbr via the DCH data transmission channel.

In the embodiment shown in FIG. 2, said summing gates ORle and OR1r are connected to a common first PG1 phase transmitter, by which said secondary DC start pulse is switched in step, which in this embodiment also resets the two second PG2e and PG2r phase transmitters. After a certain number of incremental switching of the PG1 phase transmitter, the second phase transmitter PG2e of the control device is started and the activation of the summing gate ORle starts. After further incremental switching operations, the duration of which essentially corresponds to the time of the conversion of the data transfer channel, or after subtracting the number of processing periods, the second transceiver PG2r starts up and the activation of the OR1r sum gate starts. Said potential reduction by a certain number of processing periods is introduced if the necessary delay exceeds one processing period and if the sequence of instruction registers in the reserve includes a number of so-called blind instruction registers. By a blind instruction register is meant an instruction register whose instructions serve only to select a certain other instruction register, so selecting a blind instruction register equals interrupting the operation of the data processing apparatus by one processing period. Giant. 2 illustrates a BLR instruction register corresponding to a sequence of reserve device instruction registers comprising an instruction for selecting the above-mentioned starting instruction register BIRr. In this case, the start-up register of SIRr instructions in the start-up circuit SDr of the standby device includes an instruction for selecting said BLR of the blind instructions.

In the embodiment shown in Fig. 3, the data transfer channel DCH is used to cause the start-up instruction source to delay the start of the device compared to the control device. The secondary start pulse DC, stepwise transmitted by the first controller PGle of the control device phase, is used to determine two processing periods immediately following the secondary start pulse, and during the last period the ORle summing gate is activated to read the start command on the command bus. as explained in connection with FIG. 1. By means of a pulse which is obtained from the PGle phase transmitter in the first synchronization phase of the processing period immediately following the secondary start pulse, the above-mentioned gate circuit G2 belonging to the logic transfer member TL is activated by means of the data transfer channel memory. data is connected to the data bus of the standby device. During the remaining, immediately following processing period from the secondary start pulse, the PGle phase transducer activates reading the start instruction on the control device data bus dbc via the second OR2 read gate and the A2D read gate so that the start instruction is treated in the same way as the data, which are transported to any functional unit during instruction processing. The start-up circuit SDr of the standby device, whose second phase transmitter PG2r has been set to zero in one of the above methods, comprises a comparator start-up circuit whose inputs are connected to the start-up instruction SIRr register and the back-up data bus. The comparative starting circuit is represented symbolically by the EXORd non-equivalency circuit and the inverting output in FIG. If the received start instruction is deemed to be the same as the start instruction stored in the start instruction SIRr register, then the comparison start circuit sends an equality signal that is sent to the standby device by the first PG1r phase transmitter. Waiting for a suitable number of step switches before the PG1r phase transmitter first starts the PG2r phase transmitter, secondly starts the ORlr summation gate, and deactivates the second G2 gateway thirdly, gives the possibility to fine-tune the total delay so that the optimum delay cooperation. This means that the data transferred from the control device, for example the stored data, is flawlessly received in the synchronization phase intended for reception by the standby function unit, which is addressed based on the instruction fetched from the sequence of standby instruction registers to the standby command bus. In FIG. 3 it was assumed that each processing period includes four synchronization phases and that the data is transmitted to the respective data buses during the last three phases. Furthermore, it was assumed that the best data storage ratios would be obtained if said equality signal arrived at the standby device after two synchronization phases before processing the start instruction.

In the embodiment according to FIG. 3, the start-up time is one longer than in the embodiment according to FIG. 1. On the other hand, there are less demands on the time and temperature dependence of the transmission channel instruction elements.

With all embodiments of the proposed circuitry to allow interoperability between data processing devices with generic buses, it is achieved that the reserve device instructions are processed throughout parallel synchronous cooperation, but with a delay compared to the control device instructions, the delay being such that , figuratively speaking, the reserve device does not observe during the storage periods that the received data is not transmitted by its own functional unit, but the respective functional unit of the control device.

This result achieved by the start-up pulse source that the logical state at the output of the data transfer channel lasts for at least the time of the synchronization phase to receive data in the standby device, according to the fourth stage example considered in each processing period , is used to make a smooth comparison of the data currently produced in the data transmission devices. The operational comparison circuit is shown in FIG. 2 and is represented here mainly by the EXORd non-equivalence circuit, in which two logical states are stored during the synchronization phases considered for receiving data in the standby device, and which generates an alarm signal when the states are uneven.

The operational comparison circuit EXORd, ​​in combination with CM control memories, one of which is shown in FIG. 2, is used to diagnose a faulty data processing device with general buses, preferably using a substantially identical error-free data processing device with general buses. The purpose of this diagnosis is to detect a defective element, so that the repair of the data processing device consists solely of replacing the defective element with a new one.

The diagnosis is initiated by a parallel start-up as described, wherein the defective data processing device serves as a standby device and the faultless data processing device acts as a control device that normally controls, for example, a telemechanical device in a single operation. Thereafter, the faulty data-processing device is supplied with data, to which a transfer status is recorded in all CM control memories.

The following complete transition to normal parallel synchronous cooperation between the two devices would result in the operation-comparison circuit EXORd producing an alarm signal when the malfunctioning data functional unit is addressed for data transmission. On the other hand, in the gradual transition to normal cooperation, which eg. means that the number of functional units with a predetermined transfer state manually or automatically at suitable time intervals is increasingly reduced until no alarm signal is transmitted as the transfer state - for a malfunctioning unit. Said gradual transition, respectively. Thus, a gradual loss of transition state is offered as a very simple diagnostic method, whereby the alarm signal defines that functional unit whose transition state was last canceled by an alarm.

There are many modifications to this diagnostic method that utilize the ability to record the transition state separately in functional units. Modifying examples are always to hold all transfer states except one, or to divide functional units into groups and first define the group that contains the faulty functional unit. This division into groups shortens the average diagnosis time, although data must be re-supplied before the diagnosis within the group containing the malfunctioning unit is initiated.