Phase -locked loop and circuit

Phase-locked loop and circuit technology field

[0001] The present invention relates to a phase locked loop and a circuit.

Background technique

[0002] A phase-locked loop (PLL) is a control system that generates an output signal whose phase is related to the phase of the input signal. A typical phase-locked loop includes a variable frequency oscillator and a phase detector. The oscillator generates periodic signals. The phase detector compares the phase of the input signal with the phase of the periodic signal and generates a plurality of control signals that adjust the oscillator to keep the phases matched.

[0003] Keeping the input phase and output phase locked also means keeping the input frequency and output frequency the same. Therefore, in addition to synchronizing the phase between multiple signals, the phase-locked loop can track the input frequency, or it can generate a frequency that is a multiple of the input frequency.

[0004] Such phase-locked loops are widely used in radio, telecommunications, computers, and other electronic applications. They can be used to: demodulate signals, recover signals from noisy communication channels, generate stable frequencies that are multiples of the input frequency (frequency synthesis), or distribute accurately timed clock pulses in digital logic circuits such as microprocessors. Since a single integrated circuit can provide a complete phase-locked loop building block, phase-locked loops are widely used in modern electronic devices with output frequencies ranging from a fraction of hertz to several gigahertz.

[0005] In some cases, a phase-locked loop that can operate over a wide frequency band is desirable. In order to create such a wide-band phase-locked loop, a charge pump circuit is typically used in the phase-locked loop to generate a control signal that is sent to the oscillator. However, such charge pump circuits may be noisy, resulting in an undesirable amount of in-band noise.

[0006] Therefore, a new phase-locked loop design with a new charge pump circuit is desirable.

Utility model content

[0007] One of the objectives of the present invention is to provide a phase-locked loop with a new charge pump circuit that can avoid undesirable amounts of in-band noise.

[0008] According to an aspect of the utility model, the phase-locked loop includes a phase frequency detector (PFD) configured to compare the phases of the input signal and the feedback signal and generate a plurality of control signals therefrom An attenuation circuit, the attenuation circuit is coupled in series with the frequency discriminator and includes: a first current source and a second current source; a loop filter, the loop filter is coupled to the voltage-controlled oscillationDevice(VC0) between the control node and the ground node; an amplifier having an input terminal coupled to the voltage-controlled oscillator control node; an impedance network, the impedance network being coupled to the voltage-controlled oscillator The control node and includes at least one impedance element configured to be coupled to the first current source so as to indicate that the phase of the input signal is ahead of the phase of the feedback signal based on the control signal The phase causes the voltage at the voltage controlled oscillator control node to increase, and is coupled to the second current source to indicate that the phase of the feedback signal is ahead of the phase of the input signal based on the control signal so that The voltage at the voltage-controlled oscillator control node is reduced; a voltage-controlled oscillator, the voltage-controlled oscillator is coupled to the voltage-controlled oscillator control node and based on the voltage-controlled oscillator control node The signal generates an output signal whose phase matches the phase of the input signal; wherein the feedback signal is based on the output signal.

[0009] Preferably, the plurality of control signals include a first control signal and a second control signal; wherein, the first control signal is effective based on the phase of the input signal leading the phase of the feedback signal Wherein, the second control signal is validated based on the phase of the feedback signal leading the phase of the input signal; and wherein, the impedance network further includes: a first impedance network switch, so The first impedance network switch is coupled between the first impedance network node and the voltage-controlled oscillator control node, the first impedance network switch is actuated based on a third control signal; a second impedance network switch, The second impedance network switch is coupled between the first impedance network node and the second impedance network node, and the second impedance network switch is actuated based on the complement of the third control signal; and A third impedance network switch, the third impedance network switch is coupled between the second impedance network node and the output terminal of the amplifier, and the third impedance network switch is based on all of the third control signal The complement is actuated; wherein the at least one impedance element includes a first capacitor coupled between the second impedance network node and ground and is coupled between the first impedance network node and the ground The second capacitor between the nodes of the second impedance network.

[0010] Preferably, the third control signal represents the result of a logical AND operation between the complement of the first control signal and the complement of the second control signal.

[0011] Preferably, the first current source is coupled between the power supply node and the first attenuation circuit node; wherein the second current source is coupled between the ground and the third attenuation circuit node; wherein , The impedance network further includes: a first attenuation circuit switch, the first attenuation circuit switch is coupled between the first attenuation circuit node and the output terminal of the amplifier, the first attenuation circuit The switch is actuated based on the complement of the first control signal, the second attenuation circuit switch, the second attenuation circuit switch is coupled between the first attenuation circuit node and the second attenuation circuit node, so The second attenuation circuit switch is activated based on the first control signal, a third attenuation circuit switch, and the third attenuation circuit switch is coupled to the second attenuation circuit node and the third attenuation circuit node In between, the third attenuation circuit switch is activated based on the second control signal, a fourth attenuation circuit switch, and the fourth attenuation circuit switch is coupled between the output terminal of the amplifier and the Between the third attenuation circuit nodes, the fourth attenuation circuit switch is actuated based on the inverse code of the second control signal.

[0012] Preferably, the control signal includes a first control signal and a second control signal; wherein, the first control signal is validated based on the phase of the input signal leading the phase of the feedback signal Wherein, the second control signal is based on the phase of the feedback signal leading the phase of the input signal and is validated; wherein, the first current source is coupled to the power node and the first attenuation circuit Between nodes; wherein, the second current source is coupled between ground and a third attenuation circuit node; and wherein, the impedance network further includes: a first attenuation circuit switch, The first attenuation circuit switch is coupled between the first attenuation circuit node and the second attenuation circuit node, and the first attenuation circuit switch is actuated based on the first control signal; the second attenuation circuit Switch, the second attenuation circuit switch is coupled between the second attenuation circuit node and the third attenuation circuit node, the second attenuation circuit switch is actuated based on the second control signal; A third attenuation circuit switch, the third attenuation circuit switch is coupled between the fourth attenuation circuit node and the output terminal of the amplifier, and the third attenuation circuit switch is activated based on the complement of the third control signal And wherein the at least one impedance element includes a first resistor coupled between the second attenuation circuit node and the voltage controlled oscillator control node and is coupled to the second attenuation circuit A second resistor between the node and the fourth attenuation circuit node.

[0013] Preferably, the third control signal represents the result of a logical AND operation between the complement of the first control signal and the complement of the second control signal.

[0014] Preferably, the loop filter includes a loop filter circuit coupled to the voltage controlled oscillator control node.

A resistor and a loop filter capacitor coupled between the loop filter resistor and ground.

[0015] Preferably, the loop filter includes: a first loop filter resistor, the first loop filter resistor is coupled to the voltage controlled oscillator control node; a first loop A filter capacitor, the first loop filter capacitor is coupled between the first loop filter resistor and ground; and a second loop filter capacitor, the second loop filter capacitor Is coupled between the voltage controlled oscillator control node and ground.

[0016] Preferably, the loop filter further includes: a second loop filter resistor, the second loop filter resistor is coupled to the voltage-controlled oscillator control node and loop filter And a third loop filter capacitor, the third loop filter capacitor is coupled between the loop filter node and ground.

[0017] Preferably, the at least one impedance element includes a capacitor having a capacity smaller than that of the second loop filter capacitor.

[0018] According to another aspect of the present invention, the circuit includes a first current source, the first current source is coupled between the power supply node and the first node; a first switch, the first switch is coupled Between the first node and the second node and controlled by a first control signal; a second switch, the second switch is coupled between the second node and the third node and controlled by the second Signal to control; a second current source, the second current source is coupled between the third node and the ground node; a third switch, the third switch is coupled to the first node and output Between nodes and controlled by the complement of the first control signal; a fourth switch, the fourth switch is coupled between the second node and the output node and is controlled by a third control signal ; A fifth switch, the fifth switch is coupled between the second node and the fourth node and is controlled by the third control signal; a first capacitor, the first capacitor is coupled to the Between the second node and the fourth node; a second capacitor, the second capacitor is coupled between the second node and ground; a sixth switch, the sixth switch is coupled to the Between the fourth node and the fifth node and controlled by the inverse code of the third control signal; a loop filter, the loop filter being coupled between the fifth node and ground; an amplifier , The amplifier has a non-inverting terminal coupled to the fifth node, and is coupled to the output node And a seventh switch that is coupled between the output node and the third node and is controlled by the second Controlled by the inverse of the signal.

[0019] Preferably, the third control signal represents the result of a logical NAND operation between the complement of the first control signal and the complement of the second control signal.

[0020] Preferably, the loop filter includes: a first loop filter resistor, the first loop filter resistor is coupled to the fifth node; a first loop filter capacitor , The first loop filter capacitor is coupled between the first loop filter resistor and ground; and a second loop filter capacitor, the second loop filter capacitor is coupled Between the fifth node and the ground.

[0021] Preferably, the first capacitor and the second capacitor each have a capacity smaller than that of the second loop filter capacitor.

[0022] According to another aspect of the present invention, the circuit includes a first current source, the first current source is coupled between the power supply node and the first node; a first switch, the first switch is coupled Between the first node and the second node and controlled by a first control signal; a second switch, the second switch is coupled between the second node and the third node and controlled by the second Signal to control; a second current source, the second current source is coupled between the third node and the ground node; a first resistor, the first resistor is coupled to the second node And a fifth node; a second resistor, the second resistor is coupled between the second node and a fourth node; a third switch, the third switch is coupled to the first Between the fourth node and the sixth node and controlled by the third control signal; the loop filter, so

The loop filter is coupled between the fifth node and ground; and an amplifier having a non-inverting terminal coupled to the fifth node, coupled to the sixth node The inverting terminal of and the output terminal coupled to the sixth node.

[0023] Preferably, the third control signal represents the result of a logical NAND operation between the complement of the first control signal and the complement of the second control signal.

[0024] Preferably, the loop filter includes: a first loop filter resistor, the first loop filter resistor is coupled to the fifth node; a first loop filter capacitor , The first loop filter capacitor is coupled between the first loop filter resistor and ground; and a second loop filter capacitor, the second loop filter capacitor is coupled Between the fifth node and the ground.

[0025] Preferably, the loop filter further includes: a second loop filter resistor, the second loop filter resistor is coupled between the fifth node and the seventh node; A third loop filter capacitor, the third loop filter capacitor is coupled between the seventh node and ground.

[0026] According to another aspect of the present invention, the phase-locked loop includes: a frequency discriminator configured to compare the phase of the input signal and the feedback signal and generate a plurality of controls therefrom Signal; a logic circuit, the belonging logic circuit is configured to compare the phases of the input signal and the feedback signal and generate therefrom a selection signal indicating the lock of the phase-locked loop; charge pump circuit, the charge pump circuit Based on the selection signal, it indicates that the phase-locked loop is not locked and is to be selectively coupled in series with the frequency detector and includes: a first current source and a second current source; a loop filter, the The loop filter is coupled between the voltage controlled oscillator control node and the ground node; an amplifier having an input terminal coupled to the voltage controlled oscillator control node; a first switch, the first switch Is configured to couple the first current source to the voltage controlled oscillator control node so as to indicate that the phase of the input signal is ahead of the phase of the feedback signal based on the control signal so that the voltage control The voltage at the oscillator control node increases, and a second switch is configured to couple the second current source to the voltage-controlled oscillator control node to instruct the The phase of the feedback signal leads the phase of the input signal so that the voltage at the control node of the voltage controlled oscillator is reduced; an attenuation circuit based on the selection signal Indicates that the phase-locked loop has been locked and is to be selectively coupled in series with the frequency detector and includes: a first current source and a second current source; a loop filter, the loop filter being Is coupled between the voltage-controlled oscillator control node and the ground node; an amplifier having an input terminal coupled to the voltage-controlled oscillator control node; an impedance network, the impedance network is coupled to the voltage The controlled oscillator controls the node and includes at least one impedance element configured to be coupled to the first current source so as to indicate that the phase of the input signal is ahead of the phase of the input signal based on the control signal The phase of the feedback signal causes the voltage at the voltage controlled oscillator control node to increase, and is coupled to the second current source to indicate that the phase of the feedback signal is ahead of the phase of the input signal based on the control signal So that the voltage at the voltage-controlled oscillator control node is reduced; a voltage-controlled oscillator, the voltage-controlled oscillator is coupled to the voltage-controlled oscillator control node and based on the voltage-controlled oscillator The signal at the control node generates an output signal whose phase matches the phase of the input signal; wherein the feedback signal is based on the output signal.

[0027] Preferably, the control signal includes a first control signal and a second control signal; wherein, the first control signal is validated based on the phase of the input signal leading the phase of the feedback signal Wherein, the second control signal is validated based on the phase of the feedback signal leading the phase of the input signal; and wherein, the impedance network further includes: a first impedance network switch, the first An impedance network switch is coupled to the first impedance

Between the anti-network node and the voltage-controlled oscillator control node, the first impedance network switch is actuated based on a third control signal; the second impedance network switch is coupled to the second impedance network switch Between the first impedance network node and the second impedance network node, the second impedance network switch is actuated based on the complement of the third control signal; and a third impedance network switch, the third impedance network A switch is coupled between the second impedance network node and the output terminal of the amplifier, and the third impedance network switch is actuated based on the complement of the third control signal; wherein, the At least one impedance element includes a first capacitor coupled between the second impedance network node and ground, and a second capacitor coupled between the first impedance network node and the second impedance network node [0028] Embodiments of the present disclosure provide a phase-locked loop and a circuit with a new charge pump circuit that can avoid an undesirable amount of in-band noise.

Description of the drawings

[0029] FIG. 1 is a block diagram of a phase locked loop.

[0030] FIG. 2 is a schematic diagram of a charge pump circuit that may be used in the phase locked loop of FIG. 1, for example.

[0031] FIG. 2A is a block diagram of a circuit that can be used to generate control signals H and HB for the charge pump circuit of FIG. 2. [0032] FIG. 3 is a schematic diagram of a loop filter that may be used in the phase locked loop of FIGS. 1 and 4, for example.

[0033] FIG. 4 is a schematic diagram of another charge pump circuit that may be used in the phase locked loop of FIG. 1, for example.

[0034] FIG. 5 is a schematic diagram of a loop filter that may be used in the phase locked loop of FIG. 4, for example.

[0035] FIG. 6 is a graph showing the output current noise of the charge pump circuit described herein in comparison with the conventional charge pump circuit.

[0036] FIG. 7 is another graph showing the output current noise of the charge pump circuit described herein in comparison with the conventional charge pump circuit.

[0037] FIG. 8 is a schematic diagram of another phase-locked loop of the charge pump circuit of FIGS. 2 and 4, for example. [0038] FIG. 9 is a schematic diagram of another charge pump circuit that may be used in the phase locked loop of FIG. 8, for example. [0039] FIG. 10 is a block diagram of a logic circuit used in the charge pump circuit of FIG. 9 to generate a selection signal.

Detailed ways

[0040] One or more embodiments will be described below. These described embodiments are merely examples of implementation techniques as defined solely by the appended claims. In addition, in order to provide a focused explanation, irrelevant features of the actual implementation may not be described in the.

[0041] With reference to FIG. 1, the phase locked loop 100 will now be described. The phase-locked loop 100 includes a phase frequency detector (PFD) 110, which receives an input signal Fin having an input frequency and an output signal Fout having an output frequency. The output signal Fout received by the frequency discriminator 110 is the output signal Fout of the phase locked loop 100. The frequency discriminator 110 has a plurality of output terminals UP and DN coupled to the charge pump 200 or 300 (also referred to as an attenuation circuit). The charge pump 200 or 300 in turn has an output terminal coupled to the loop filter Z, which in turn is coupled to the voltage controlled oscillator (VC0) 120_oThe output terminal of the VCO 120 is coupled to the input terminal of the frequency detector 110 via an optional frequency divider 130.

[0042] In operation, the frequency discriminator 110 compares the input signal Fin with the output signal Fout, and generates control signals UP, DN for the charge pump 200 or 300 based thereon. When the phase of the input signal Fin leads the phase of the output signal of the output signal Fout, the control signal UP is validated at logic high, and the control signal DN remains at logic low. Conversely, when the phase of the input signal Fin lags the phase of the output signal of the output signal Fout, the control signal DN is validated

At logic high, the control signal UP remains at logic low. When the phase of the input signal Fin matches the phase of the output signal Fout, UP and DN are not validated.

[0043] The charge pump 200 or 300 generates a control signal for the VCO 120 that passes through the loop filter Z, which extracts the low frequency component of the control signal. The VCO 120 adjusts the phase and frequency of the output signal Fout based on the control signal. When UP is activated, the charge pump 200 or 300 increases the voltage of the control signal, as opposed to decreasing the voltage of the control signal when DN is activated. Those skilled in the art will recognize that since the phase of the input signal Fin cannot lead and lag the phase of the output signal Fout at the same time, the phase frequency detector 110 will not be able to simultaneously validate UP and DN.

[0044] An optional frequency divider 130 may be included in the feedback loop to couple the output signal Fout to the frequency discriminator 110. The frequency divider 130 is used to divide the frequency of the output signal Fout, so that the frequency of the output signal Fout to be generated by the VCO 120 is a multiple of the frequency of the input signal Fin. For example, if the frequency divider 130 divides the frequency by 2, in order for the phase discriminator 110 to see that the input signal Fin and the feedback signal (the output signal Fout after being fed through the frequency divider 130) have the same frequency, output The signal Fout will have twice the frequency of the input signal Fin. If the frequency divider 130 does not exist, or if the frequency divider is divided by 1, the frequency of the output signal Fout will match the frequency of the input signal Fin.

[0045] The details of the charge pump 200 and the loop filter Z will now be given with reference to FIGS. 2 to 3. The charge pump 200 includes a first current source 202 coupled between a power supply node Vcc and a node 204. The switch S1 is coupled between the node 204 and the node 206. The switch S2 is coupled between the node 206 and the node 208. The second current source 210 is coupled between the node 208 and ground. The switch S3 is coupled between the node 204 and the node 218. The switch S4 is coupled between the node 206 and the node 218. The switch S7 is coupled between the node 218 and the node 208.

[0046] The first capacitor Cs is coupled between the node 206 and the node 212, and the switch S5 and the first capacitor Cs are coupled in parallel between the node 206 and the node 212. The second capacitor Cs2 is coupled between the node 206 and the ground GND. The switch S6 is coupled between the nodes 212 and 214 and the loop filter Z is coupled between the node 214 and ground. In addition, the non-inverting terminal of the amplifier 216 is coupled to the node 214, and the inverting terminal and the output terminal of the amplifier 216 are coupled to the node 218. The capacitors Cs and Cs2 have a capacitance value smaller than that of the impedance element used in the loop filter Z. The value of Cs2 is different from the value of Cs by a factor of one less than the desired gain A of the charge pump circuit 100. In other words, the value of Cs2 is Cs*(Al).

[0047] The loop filter Z (the details of which are shown in FIG. 3) includes a resistor R1 and a capacitor C1 coupled in series between the node 214 and ground. The capacitor C2 is coupled between the node 214 and the ground, and the resistor R2 and the capacitor C3 are coupled in series between the node 214 and the ground.

[0048] In operation, the switch S1 is triggered in response to the activation of UP, and the switch S2 is triggered in response to the activation of DN. The switch S3 is triggered in response to the validation of the complement of UP (labeled as NUP), and the switch S7 is triggered in response to the validation of the complement of DN (labeled as NDN). The switch S6 is triggered in response to the activation of the signal HB (shown in FIG. 2A) representing the logical AND operation between the complement of UP and the complement of DN, and the switches S4 and S5 are activated in response to the signal H Validated and triggered, the signal Η is the complement of that signal.

[0049] Therefore, when the phase of the input signal Fin leads the phase of the output signal Fout, the frequency discriminator 110 validates UP and keeps DN low. The switches S1, S6, and S7 are closed and the other switches are opened, causing current to flow from the first current source 202 through the nodes 204 and 206 into the first capacitor Cs. This is used to charge the first capacitor Cs with the voltage seen at node 214. The amplifier 216 has unity gain, and therefore passes the voltage seen at node 214 to its output terminal at node 218. The control signal for VCO 120 is the output from node 214.

[0050] On the other hand, when the phase of the input signal Fin lags the phase of the output signal Fout, the frequency discriminator 110 validates DN and keeps UP low. Therefore, the switches S2, S3, and S6 are closed and the other switches are opened, causing the slave node 206 to attract

The current is received and therefore the voltage at the first capacitor Cs is discharged. Therefore, the voltage at node 214 drops, and amplifier 216 delivers the voltage to its output terminal at node 218. The control signal for VCO 120 is the output from node 214.

[0051] When the phase of the input signal Fin matches the phase of the output signal Fout, the frequency discriminator 110 neither validates UP nor validates DN. Therefore, the switches S3, S4, S5, and S7 are closed, while the other switches remain open. This is used to move current from the first current source 202 through the node 204, into the node 218, into the node 208, and through the second current source 210 to ground GND.

[0052] The charge pump circuit 200 described above provides various advantages over conventional charge pump circuits. For example, the charge pump circuit 200 uses high A factor charge pump currents 202 and 210, but maintains the entire PLL loop gain by an attenuation factor of 1/A obtained through capacitive voltage division. This is shown in Figures 6-7. In addition, the thermal noise from the current sources 202 and 210 in the charge pump circuit 200 reduces the A factor. The amplifier noise fed through the loop filter Z is proportional to Cs*Vamp*Fin (where Fin is the input frequency to the PLL and where Vamp is the voltage at the non-inverting terminal of the amplifier 216) and is smaller than from the current source 202 and 210 noise. Therefore, in order to make the loop gains in the charge pump circuit 200 the same, the noise entering the loop filter Z is reduced. This is also used to reduce in-band phase noise. The reduction in output noise for conventional charge pump circuits is on the order of 1/A and can be seen in FIGS. 6-7.

[0053] Referring first to FIG. 4, an alternative design for the charge pump circuit 300 will be described. The charge pump circuit 300 includes a first current source 302 coupled between the power supply node Vcc and the node 304 and a switch S1 coupled between the node 304 and the node 306. The switch S2 is coupled between the node 306 and the node 308. The second current source 310 is coupled between the node 308 and the ground GND. The resistor R3 is coupled between the node 306 and the node 312 and the loop filter Z is coupled between the node 312 and the ground GND. The resistor R4 is coupled between the node 306 and the node 314 through the switch S3. The amplifier 316 has its non-inverting terminal coupled to the node 312 and its inverting terminal coupled to the node 314 and its output terminal. The value of the resistor of the attenuation filter Z is high. The switch S4 is coupled between the node 304 and the node 314. The node 314 is coupled to the node 311.

[0054] The resistance of the resistor R3 may be equal to (A-1)*R4, and the resistance of R4 is selected to reduce the noise component from the resistance attenuation network and make the noise component smaller than the noise components of the current sources 302 and 310. In this case, R4>A/Gm, where Gm is the transconductance of the current sources 302 and 310. This causes l/A of the current from the current sources 302, 310 to flow through R3 and into the attenuation filter Z. The current sources 302, 310 conduct A times the current of a conventional charge pump current source, so the transconductance of the current sources 302, 310 can be A times the transconductance of the conventional charge pump current source. In addition, when the resistors R3 and R4 have larger values, the noise entering the attenuation filter Z from the amplifier 316 is reduced.

[0055] In operation, the switch S1 is triggered in response to the activation of UP, and the switch S2 is triggered in response to the activation of DN. Switch S3 is triggered in response to the activation of the logical AND operation (labeled HB) between UP and the complement of DN, while switch S4 is triggered in response to the complement of UP and the switch S5 is activated The complement of the validation of DN is triggered.

[0056] Therefore, when the phase of the input signal Fin leads the phase of the output signal Fout, the frequency discriminator 110 validates UP and keeps DN low. Then switches S1, S3, and S5 are closed and switches S2 and S4 are opened, causing current to flow from the first current source 302 through node 306, into resistor R3, and into node 312, thereby generating a voltage across resistor R3. The voltage is seen at node 312 by the non-inverting terminal of amplifier 316, which passes the voltage at node 312 to its output at node 314. The control signal for VCO 120 is the output from node 312.

[0057] When the phase of the input signal Fin lags the phase of the output signal Fout, the frequency discriminator 110 validates DN and keeps UP low. Switches S2, S3, and S4 are closed and switches S1 and S5 are open, causing current to be drawn from node 306. Therefore, the voltage at node 312 and therefore the voltage of the control signal for VCO 120 drops.

[0058] When the phase of the input signal Fin matches the phase of the output signal Fout, the frequency discriminator 110 neither validates UP nor validates DN. Therefore, the switches S4, S5 are closed, while the switches S1, S2, S3 remain open. This is used to couple the output terminal of the amplifier 316 to the non-inverting terminal of the amplifier 316 and ground, so that the voltage at the node 312 and therefore the voltage of the control signal for the VCO 120 is reduced.

[0059] The loop filter Z of FIG. 5 may be used in the charge pump circuit 300 and includes a resistor R coupled in series with the capacitor C. When the loop filter Z is used, the value of the resistor R3 is different from the value of the resistor R4 by a factor of one less than the desired gain A of the charge pump circuit 300. In other words, the value of R3 is R4*(A-1).

[0060] The charge pump circuit 300 has the same advantages as the charge pump circuit 200 described above. As mentioned, the charge pump circuit 300 provides an increased gain over the A factor of the conventional charge pump, while reducing the loop gain of the 1/A factor within the charge pump circuit 300, so the phase-locked loop 100 is maintained. The overall loop gain. In addition, the thermal current noise in the charge pump circuit 300 is increased by the A or L factor, but when entering the loop filter Z, the full factor is attenuated. The noise fed through from the amplifier 316 to the loop filter Z is proportional to the subscale. Therefore, in order to make the loop gains in the charge pump circuit 300 the same, the noise entering the loop filter Z is reduced.

[0061] An embodiment of a phase-locked loop 100 employing one of the charge pump circuits 200, 300 and an additional charge pump circuit 400 as described above will now be described with reference to FIG. 8. The phase-locked loop 100 operates like the phase-locked loop of FIG. 1, but the additional charge pump circuit 400 is coupled in series between the PFD 110 and the loop filter Z before the phase-locked loop 100 is locked, and the charge pump circuits 200, 300 One is coupled in series between the PFD 110 and the loop filter Z after the phase locked loop 100 is locked. The purpose of this choice between the charge pump circuit 200, 300 or 400 is to help quickly lock the phase-locked loop 100 while still receiving the advantages of the charge pump circuit 200, 300 as described above. It should be noted that if the current output by the charge pump 400 is I, the current output by the charge pump circuits 200, 300 will be I*A. The selection of the charge pump circuit 200, 300 or 400 is based on the selection signal.

[0062] As shown in FIG. 10, a selection signal LOCK is generated by detecting whether the phase-locked loop 100 has been locked by comparing the input frequency Fin with the feedback signal based on the lock detector. The inverted code ENH of this selection signal is used to activate the charge pump circuit 400, and the inverted code ENL of that signal is used to activate the charge pump circuit 200, 300.

[0063] As shown in FIG. 9, the charge pump circuit 400 includes a first current source 402 coupled between a power supply node and a node 404. The first switch S1 is coupled between the node 404 and the node 406. The amplifier 416 has a non-inverting terminal coupled to the node 406. The loop filter Z is coupled between the node 406 and ground. The inverting terminal of amplifier 416 is coupled to its output terminal at node 414 in order to bias amplifier 416 in unity gain mode.

[0064] The switch S2 is coupled between the node 406 and the node 408. The second current source 410 is coupled between the node 408 and ground. The switch S3 is coupled between the node 404 and the node 414, and the switch S4 is coupled between the node 414 and the node 408. In operation, the switch S1 is activated in response to the activation of UP, and the switch S2 is activated in response to the activation of DN. Switch S3 is actuated by the inverse code NUP of UP and switch S4 is actuated by the inverse code NDN of DN.

[0065] When the phase of the input signal Fin leads the phase of the output signal Fout, the frequency discriminator 110 validates UP and keeps DN low. Switches S1, S4 are closed and the other switches are opened, causing current to flow from the first current source 402 through nodes 404 and 406 into the loop filter Z and the non-inverting terminal of the amplifier 416, thereby increasing the The voltage seen. Due to the unity gain of the amplifier 416. The voltage seen at node 406 is delivered to its output terminal at node 414. The control signal for VCO 120 is at node 406.

[0066] When the phase of the input signal Fin lags the phase of the output signal Fout, the frequency discriminator 110 validates DN and

Keep UP low. Therefore, the switches S2 and S3 are closed and the other switches are opened, causing current to be drawn from node 406. Therefore, the voltage at node 406 drops, and amplifier 416 delivers the voltage to its output terminal at node 414. The control signal for VCO 120 is at node 406.

[0067] When the phase of the input signal Fin matches the phase of the output signal Fout, the frequency discriminator 110 neither validates UP nor validates DN. Therefore, the switches S3, S4 are closed while the other switches remain open. This is used to move current from the first current source 402 through the node 404, into the node 414, into the node 408, and through the second current source 410 to ground GND.

[0068] It should be understood that any loop filter Z described herein can be used in any embodiment described herein, and other types of loop filters (that is, active loop filtering using operational amplifiers)Device) can also be used in any of the embodiments described herein.

[0069] The present disclosure has been described in terms of a limited number of embodiments, and those skilled in the art who benefit from this disclosure will recognize that other embodiments can be envisaged that do not depart from the scope of the present disclosure as disclosed herein. Therefore, the scope of the present disclosure should be limited only by the appended claims.