Differential floating gate nonvolatile memories

Differential floating gate non-volatile memory

Related Cases This application is based on the joint resolution No. 10/190,337 filed on July 5, 2002 in the name of inventors Shail Srinivas, Chad A. Lindhorst, Yanjun Ma, Terry Haas, Kambiz Rahimi and Christopher J. Diorio. Part of the continuation application of the patent application and joint assignment here.

Technical field

The present invention is directed to non-volatile memory (NVM). Especially for NVM constructed with a differential structure using pFET (p-channel field effect transistor) floating gate devices.

Background technique

Many CMOS (Complementary Metal Oxide Semiconductor) integrated circuits require a small amount of on-chip non-volatile memory (NVM). Typical applications include storage of security settings, RFID (radio frequency identification) data, system configuration, serial numbers, calibration and fine-tuning settings, etc. Considering cost and yield reasons, the ideal NVM should be a logic CMOS with the latest technology with zero additional processing masks. Unfortunately, major memory manufacturers have focused on developing custom NVM processes that can produce ever-increasing storage densities (for example, 256Mb flash memory), and almost neglect the need for relatively small NVM applications (hundreds of words). Therefore, CMOS designers who require a small amount of non-volatile storage must (1) use technologies such as on-chip fuses; (2) pay the cost and bear the cost of product downgrades that use high-density embedded NVM; (3) adopt Off-chip storage; or (4) Use SRAM (Static Random Access Memory) storage powered by a related backup battery.

Designers who need a small amount of NVM in highly integrated CMOS applications face some unpleasant trade-offs. The obvious method is to use a CMOS process with embedded NVM. Unfortunately, the embedded NVM process not only has to bear higher chip costs, but also tends to become an earlier generation technology. The higher cost is due to the fact that the NVM process generally requires additional masking and fabrication steps (eg, in order to obtain the second polysilicon layer). Since it takes time and testing to add NVM to the logic process, an earlier generation of technology appears. Therefore, the NVM process usually lags behind the latest technology by one year. The result may be a few NVM bits, making the entire CMOS chip more expensive and lower in performance.

An alternative to embedded NVM is to use laser or electronically programmed fuses (or anti-fuses). Applications that require one-time programming can find this alternative to be attractive, but major technical problems such as fuse "healing" and programming costs are still troublesome. In addition, fuses and anti-fuses are usually not available in the latest technology CMOS process.

Another option is to use an off-chip solution, such as a backup battery with a separate NVM chip or on-chip SRAM. Unfortunately, this solution requires additional equipment, and in the case of off-chip NVM, the data is exposed to potential hacking. Of course, the benefit is that designers can use cutting-edge technology to build the rest of the chip without introducing the indirect costs of the NVM process. The disadvantage is the higher cost in the area of PCB (Printed Circuit Board) and the number of parts.

What CMOS designers need is NVM capability in the latest technology logic CMOS.

Summary of the invention

The present invention relates to the design of a differential floating gate non-volatile memory and a memory array using a large number of differential pFET floating gate transistors to store information. The present invention also provides a method of constructing the memory and the memory array, and operation and testing methods related to the memory and the memory array.

Description of the drawings

The drawings incorporated in the present invention and becoming a part of this specification illustrate one or more embodiments of the present invention, and together with the detailed description, explain the principle and construction of the present invention.

FIG. 1A is a graph of the drain current of the floating gate MOSFET of FIG. 1B versus the control gate power supply voltage.

Figure 2A is a front cross-sectional view of a device according to an embodiment of the present invention.

Fig. 2B is a MOS band diagram of the device of Fig. 2A.

Fig. 3 is an electrical schematic diagram of a memory according to an embodiment of the present invention. The pFET M2 is used to set the differential pair bias current through the signal "bias", and the floating gate pFETs M0 and M1 act as storage devices. The short-circuited pFETs T0 and T1 are used to remove charge from the floating gate and/or act as a control gate. As will be apparent to those skilled in the art, short-circuited nFETs can be used instead to construct T0 and T1.

Figure 4 is a graph of injection efficiency versus gate-to-drain voltage, where the injection efficiency is defined as the gate current divided by the source current.

FIG. 5A is an electrical schematic diagram of a memory according to an alternative embodiment of the present invention, which includes a differential memory without tunneling junction. UV light or other techniques well known to those skilled in the art can be used to erase the floating gate, and injection can be used to program the memory once.

FIG. 5B is an electrical schematic diagram of a memory according to an alternative embodiment of the circuit of FIG. 5A.

FIG. 6A is an electrical schematic diagram of a differential memory, which has a select transistor to determine which side of the memory will be subjected to the injection of the embodiment of the present invention.

6B is an electrical schematic diagram of a memory according to an alternative embodiment of the memory of FIG. 6A, which includes a row selection switch according to an embodiment of the present invention.

FIG. 7 is an electrical schematic diagram of a differential memory circuit coupled to a pFET current source, which has select transistors (S0, S1) (sometimes referred to herein as "sequence select switches") constructed with nFETs according to an embodiment of the present invention in this case ).

FIG. 8 is an electrical schematic diagram of a differential memory circuit, in which in accordance with an embodiment of the present invention, the current is controlled at the drain of the floating gate injection transistor. Because there are two separate current controls, the injection can be controlled separately in M0 and M1.

FIG. 9 is an electrical schematic diagram of the differential memory circuit of FIG. 8 according to another embodiment of the present invention. In this version, applying a positive bias to node deviation 0 or node deviation 1 and applying 0V to other nodes will write to the memory.

FIG. 10 is an electrical schematic diagram of a memory circuit according to an embodiment of the present invention, which includes a pFET read transistor associated with each floating gate.

FIG. 11 is an electrical schematic diagram of a memory circuit according to an embodiment of the present invention similar to FIG. 10, but including row selection transistors (M0, M1) to selectively isolate individual storage locations from a differential sense amplifier.

Fig. 12 is an electrical schematic diagram of an alternative part of the circuit contained in block 12 of Fig. 11 according to an embodiment of the present invention.

FIG. 13 is an electrical schematic diagram of an embodiment of the present invention for constructing bidirectional tunneling.

Fig. 14 is an electrical schematic diagram of an alternative embodiment of the present invention based on Fig. 13. In this version, the memory is written by electron injection, and a pFET read transistor is associated with each floating gate. The capacitively coupled control gate input node facilitates the margin read and write disturbance mitigation processes described herein.

FIG. 15 is an electrical schematic diagram of an embodiment of the present invention, in which half of the differential storage locations are shared by all memory locations of a row of memory arrays. This embodiment is particularly useful for memory banks of differential memories.

FIG. 16 is an electrical schematic diagram of the embodiment of the present invention in the version of FIG. 14 modified by adding a pair of floating gate transistors (M2, M3) to monitor the end of the tunneling process.

FIG. 17 is an electrical schematic diagram of an embodiment of the present invention, which uses feedback to deliberately inject a small amount into the memory during tunneling to prevent the overtunneling problem of the memory floating gate.

FIG. 18 is an electrical schematic diagram showing the simplified embodiment of the present invention in the memory of FIG. 17. FIG. The Read not signal is used to configure the memory to read mode.

19 and 20 are electrical schematic diagrams of embodiments of the present invention, which illustrate that the memory current can be controlled on the drain side of the injection transistor. The embodiment of Figure 20 has a clear nFET current sink M0 that controls the write and read currents.

FIG. 21 is a layout diagram of a pFET tunnel junction device according to an embodiment of the present invention.

FIG. 22 is a cross-sectional view taken along line 22-22 of FIG. 21. FIG.

FIG. 23 is a layout diagram of an n-well bulk nFET tunnel junction device according to an embodiment of the present invention.

FIG. 24 is a cross-sectional view of a MOSCAP type tunnel junction device according to an embodiment of the present invention.

FIG. 25 is an electrical schematic diagram of a differential memory according to an embodiment of the present invention.

FIG. 26 is an electrical schematic diagram of an alternative differential memory according to another embodiment of the present invention.

Figure 27 is an electrical schematic diagram of another differential memory.

FIG. 28 is an electrical schematic diagram of a differential memory, which has the ability to independently write different sides.

Figure 29 is an electrical schematic diagram of another alternative differential memory.

Figure 30 is an electrical schematic diagram of another alternative differential memory.

Figure 31 is an electrical schematic diagram of another alternative differential memory.

Figure 32 is an electrical schematic diagram of another alternative differential memory.

Figure 33 is an electrical schematic diagram of another alternative differential memory.

FIG. 34 is an electrical schematic diagram of another alternative differential memory for explaining the first method of boundary reading.

35 is an electrical schematic diagram of another alternative differential memory for explaining the second method of boundary reading.

FIG. 36 is a graph of write current and write disturb current versus write voltage of a memory such as those covered by the present invention.

Figure 37 is an electrical schematic of a modified memory designed to reduce write disturbance.

Figures 38, 39 and 40 are alternative constructions of differential memory arrays with various types of differential memory.

Figures 41 and 42 show an alternative construction of an external injection circuit, which is used to separate a memory made with a relatively high floating gate, which may instead prevent electrons from being injected into the floating gate.

FIG. 43 is a diagram illustrating an array layout of a memory according to an embodiment of the present invention.

FIG. 44 is an electrical schematic diagram of an exemplary write circuit according to an embodiment of the present invention.

FIG. 45 is an electrical schematic diagram of an exemplary differential sense amplifier circuit according to the prior art.

Fig. 46 is a front cross-sectional view of a UV erasable window storage device according to the prior art.

detailed description

In this paper, a differential floating gate non-volatile memory is used to describe the embodiments of the present invention. Those skilled in the art will understand that the following detailed description of the present invention is only illustrative and is not intended to be limited in any way. Those skilled in the art who benefit from this disclosure can easily understand other embodiments of the present invention. Reference will now be made in detail to the construction of the present invention as illustrated in the accompanying drawings of the present invention. The same reference numbers are used throughout the drawings and the following detailed description to refer to the same or similar parts.

For the sake of clarity, not all the conventional features of the construction are shown and described here. Of course, it should be understood that in the development of any of the actual constructions, countless specific constructions must be determined in order to achieve the specific goals of the developer, such as complying with application and business-related constraints, and these specific goals will vary according to each construction and each developer. In addition, it should be understood that the development work may be complicated and time-consuming, but it will become a routine task of engineering for those skilled in the art who benefit from this disclosure.

The present invention is generally used for non-volatile memories, and has special applications such as low-density embedded non-volatile memories that may be found in embedded CMOS applications. The embedded CMOS application includes (but is not limited to) storage: (1) chip serial number (ie, chip tag); (2) configuration information in ASIC (application specific integrated circuit); (3) radio frequency identification (RFID) Product, package and/or asset data in the integrated circuit; (4) the code or data of the embedded microcontroller; (5) analog fine-tuning information; (6) FPGA configuration information; and (7) as understood by those skilled in the art Many other applications. Compared with conventional nFET-based non-volatile memory, the use of pFET has at least the following advantages: reduced charge pump power, increased program/erase cycle durability (due to reduced oxidative wear), and availability in logic CMOS processes (due to memory Leakage reduction and the fact that the memory only uses nFET and pFET).

Any reprogrammable NVM technology must meet two key requirements: (1) durability and (2) retention. Persistence refers to the number of erase/write cycles (NVM ideally can have unlimited read cycles). Retentivity refers to memory storage time. In the past two decades, the development of flash memory and EEPROM technology has led to a set of commercially acceptable NVM design standards. Any design in the standard CMOS process should meet these same standards. The two criteria are 10-year retention and 10,000 (minimum) erase/write cycles.

NVM devices store information by changing the physical properties of transistors or other circuit elements. In the case of floating gate memory (eg, flash memory or EEPROM), the physical property is the amount of electrons stored on the electrically isolated (floating) gate of a silicon MOSFET (metal oxide semiconductor field effect transistor). All NVM devices wear out, which means that after a certain number of erase/write cycles, the memory will no longer meet its 10-year retention requirements. In the case of floating gate memory, the insulating oxide is always damaged because mobile electrons pass through the oxide insulator surrounding the electrical isolation gate.

Floating gate memory technology uses electrons on the floating gate of a silicon MOSFET to store information. The addition or removal of electrons from the floating gate changes the threshold voltage of the MOSFET. Figure 1A is a graph of drain current versus control gate power supply voltage for the floating gate MOSFET of Figure 1B. In order to read the memory, the channel current of the floating gate MOSFET is measured. If you observe the left curve of FIG. 1A, then the stored memory is logical "1"; if you observe the right curve of FIG. 1A, then the stored memory is logical "0", or vice versa. In the absence of a control gate, the voltage of the floating gate determines the state of its associated transistor. For pFETs, low floating gate voltage means that the transistor is more "on" (i.e., higher source-drain current), while high floating gate voltage means that the transistor is more "off" (i.e., lower Source-drain current). A logic "1" or a logic "0" can be read based on the relative on/off state of the floating gate transistor.

NVM designers can use n-channel or p-channel floating gate MOSFETs as memory transistors. Since the early 1980s, n-channel MOSFETs have been used because of their small size and the existence of a direct method of injecting nFET channel electrons onto the floating gate. This option enables high-density flash memory and EEPROM in a highly modified CMOS process. However, in logic CMOS, the situation is the opposite-pFET is much better than nFET because pFET NVM has better retention than nFET NVM, and pFET NVM allows more erase/write cycles than nFET NVM .

Of course, there are disadvantages to using pFET NVM. In the dedicated process, it is found that the pFET NVM has a larger size than the nFET NVM and tends to have a longer writing time. For small memories (that is, those less than or equal to about 60kbits), the retention and durability benefits and zero-process mask increase significantly outweigh these shortcomings.

Figure 2A is a front cross-sectional view of a device used in an embodiment of the present invention. Fig. 2B is a MOS band diagram used in the device of Fig. 2A. Figures 2A and 2B illustrate why pFET NVM has better retention than nFETNVM. The physical properties of the device show that the energy barrier for electron leakage from the pFET is 4.16 eV, while it is only 3.04 eV for the nFET. This difference means that under the same oxide thickness, the pFET memory can exhibit a higher energy barrier that is significantly smaller than the electron tunneling through the gate oxide of the nFET memory. In a dedicated CMOS process, this difference has no real impact, because process engineers only need to thicken the gate oxide until the memory has 10 years of retention. All current commercial nFET-based NVMs use 80 Å or thicker oxide. Unfortunately, there is no 80 Å oxide (0.35 μm and smaller process line width) in modern logic CMOS. Therefore, in logic CMOS, the nFET NVM constructed with a gate oxide of 70 Å or thinner cannot meet the 10-year retention requirement under normal process changes and temperature changes. The solution is to use pFET NVM. For example, the 70 pFET available in the modern double-gate oxide CMOS process has the same data retention as the 82 nFET in the dedicated process. In short, retentivity is critical to NVM, and pFET has 10 years of retentivity in current technology logic CMOS, but nFET does not.

US Patent No. 5,990,512 entitled "Hole Impact Ionization Mechanism for Hot Electron Injection and Four Terminal pFET Semiconductor Structure for Long-Term Learning" by Diorio et al. describes a method for transferring charge to and from the gate of a floating gate pFET. Some embodiments of the present invention use floating gate pFETs as memory storage transistors, and the impinging ionization hot electron injection (IHEI) and tunneling methods described in the 512 patent are used to write to the memory. Other embodiments of the present invention use direct tunneling instead of IHEI. Because IHEI and tunneling do not require a specific device process, floating gate devices can be built using the same IC process used to make standard digital logic transistors.

Differential memory technology uses differential memory instead of standard single-ended memory, so that the memory made according to the present invention exhibits increased read speed, reduced read current and power consumption, reduced tunneling and injection efficiency changes sensitivity The accuracy requirements of the current and voltage references on the chip are relaxed, and the temperature and power supply voltage sensitivity are reduced. Thus, the use of a differential pFET-based memory combination method can start the NVM in the logic CMOS.

Fig. 3 is an electrical schematic diagram of a memory according to an embodiment of the present invention. The pFET M2 is used to set the differential pair bias current Ib through the signal "bias", and the floating gate pFETs M0 and M1 act as storage devices. The short-circuited pFETs T0 and T1 are used to remove electrons from the floating gate and/or act as a control gate. As will be apparent to those skilled in the art, T0 and T1 can be constructed alternatively using short-circuited nFETs or MOSCAPs. (The control gate is a capacitor or a node capacitively coupled to the floating gate. According to the present invention, the control gate can be constructed as a capacitor or a short-circuited pFET, etc., without adding another layer to the semiconductor wafer) can be stored in two The difference in charge on the floating gates FG0 and FG1, rather than the on-off state of a single memory element as is common in nFET-based NVM, determines the logic state of the differential memory. Regardless of whether the memory element stores logic 0 or logic 1, both transistors have inverting channels. The conventional differential sense amplifier circuit D1 reads the drain currents I0 and I1 of M0 and M1, respectively, to determine the state of the memory.

The erase cycle of the basic memory element can operate as follows. The differential memory can be erased by using Fowler-Nordheim tunneling to remove electrons from the two floating gates. According to an embodiment of the present invention, this can be done by tunneling the two (T0 and T1) to about 10V. In order to stop the erase process before the pFET floating gate transistor tunnels to a fully off state, the drain current (I0 and I1) will be monitored during the erase process in a conventional manner. Once the drain current of the particular memory element reaches a predetermined minimum value (eg, about 10 nA according to one embodiment of the present invention), the tunnel complete (TunDone) signal is generated in a conventional manner. This signal can be used to stop the tunneling process on that floating gate or on a block of the floating gate. This feedback process ensures that no floating gate transistors are completely turned off when erasing.

The programming cycle of the basic memory element can operate as follows. To program logic 1 to a storage location, transistor M2 can be used to apply a bias current to the memory element while simultaneously applying a relatively large drain-to-source voltage on transistor M1 (by applying a low or negative voltage to the drain of M1). The typical values in the 0.18μm CMOS process are Vdd=1.8V and V_M1drain=-3.3V. The transistors M2 and M1 are conductive and use the IHEI process as discussed in US Patent No. 5,990,512 to inject electrons into the floating gate FG1. The same procedure is then followed to write logic 0, except that the transistor M0 is injected instead of M1.

The injection process is self-limiting, which means that when electrons are injected onto the floating gate, the transistor itself stops the injection process. Unlike nFET, pFET will self-limit its IHEI current, because injection will cause its floating gate voltage to drop. As the gate voltage drops, the drain-to-gate voltage of the injection transistor also drops. Because IHEI will decrease exponentially as the drain-to-gate voltage decreases (as illustrated in Figure 4, which is a graph of gate current/supply current versus gate-to-drain voltage), the The transistor itself stops the IHEI process.

Alternatively, those skilled in the art will now recognize that it is also possible to create a signaling circuit that can be used to terminate the injection process, for example, by blocking the current through the transistor M2 when the floating gate of the injection transistor reaches a predetermined voltage.

The read cycle of the basic differential memory element can operate as follows. In order to read the content of the differential memory element, the transistor M2 is first used to apply a bias current to the memory element. Reading operates according to the principle of distinguishing the more conductive path between the two half-differential memory elements. If FG0 has a lower voltage than FG1, then M0 will be more conductive and most of the bias current will pass through I0. If FG1 has a lower voltage than FG0, then the complementary situation is maintained. Next, the conventional differential sense amplifier compares I0 and I1 to determine whether the memory element maintains a logic 1 or a logic 0. Because the memory is differential, any small bias current can be used in transistor M2 when reading the memory. Thus, during a read operation, the memory can use arbitrarily low power. Tunneling Bonding FIG. 5A is an electrical schematic diagram of a memory of an alternative embodiment of the present invention, which includes a differential memory without tunneling bonding to remove electrons from the floating gates FG0 and FG1. Here, it is possible to use electromagnetic radiation such as UV light displayed on the floating gate through an appropriate window W in the package P containing the device on the chip C, or other techniques well known to those skilled in the art, according to the present embodiment For example, to erase the floating gates FG0 and FG1 on the chip C of the package P (as illustrated in Figure 46), and to use the injection powered by a current source, resistor, FET, or voltage source (referred to herein as a current source) to the memory Perform a programming. In this way, the layout area related to the tunnel junction can be saved. The option of excluding the tunnel junction is applicable to all embodiments of the present invention, and the option of placing the tunnel junction in the same or separate n-wells of the substrate is also applicable. If the tunnel junction is formed in a single n-well, then a single node of the memory (i.e., single side) can be selected for the purpose of erasure. If the tunnel junction is formed in the same n-well, the die area can be reserved and both sides of the differential memory can be erased at the same time. The exact configuration used in a particular embodiment will depend on the designer. FIG. 5B illustrates an alternative embodiment of the memory of FIG. 5A, which includes selection transistors S0 and S1 controlled by selection lines Sel_0 and Sel_1, respectively. No tunnel bonding is provided in this version.

The devices described herein may be erasable or programmable once. For a once-programmable device, tunnel bonding is not required (although it can be included as a design choice). Those embodiments of the present invention that require erasing can construct tunnel junctions to allow electrons to tunnel out of the floating gate. The tunnel junction can be constructed in many different ways. In one embodiment, the individual n-well is placed away from the n-well where the floating gate transistor is located. The floating gate transistor is a pFET, which can be used for IHEI, direct tunneling, or another similar process for moving electrons to the floating gate across an insulator. According to this embodiment, the floating gate is placed between two n-wells. The tunnel junction can be: (1) a MOSCAP, such as the element 124 shown in FIG. 24, which is constructed as an n+ region placed in an n-well; (2) a short-circuited nFET (with interconnected drains) And source); (3) a short-circuited pFET (with interconnected drain, source and well contacts); or other arrangements as will now be apparent to those skilled in the art. See FIG. 2A for the general layout of the memory according to an embodiment of the present invention.

Turning now to Figures 21 and 22, a pFET tunnel junction is illustrated. FIG. 21 is a layout (upper) view of the pFET tunnel junction, and FIG. 22 is a cross-sectional view taken along line 22-22 of FIG. 21. As can be seen, the device is placed in an n-well 100, where the n-well is placed in the substrate 102. The pFET tunnel junction device 104 includes an n+ well contact region 106 and a source p+ region 108 and a drain p+ region 110, all of which can be shared by individual memory elements within a page where possible. The floating gate 112 is seated on the channel formed between the source and drain, and is separated from the channel by a dielectric layer 114 such as silicon dioxide. The well contact, source and drain are short-circuited together by a conductor 116, which is made of any suitable conductive material.

Turning now to FIG. 23, the nFET tunnel junction device 118 is illustrated in the cross-sectional view. In this embodiment, the n-well 100 is placed in the p-substrate 102. Inside the n-well 100 are a pair of n+ regions 120 and 122 that constitute the source and drain of the transistor. These are short-circuited to each other by the conductor 116 as described above. As described above, the floating gate 112 is seated on the channel formed between the source and drain, and is separated from the channel by a dielectric layer 114 such as silicon dioxide.

Turning now to FIG. 24, the MOSCAP tunnel junction device 124 is illustrated in a cross-sectional view. In this embodiment, the n-well 100 is placed in the p-substrate 102. Within the n-well 100 is an n+ region 126 coupled to the conductor 116. The rest of the details of the device are as described above.

Restricted Injection to the Side of the Differential Memory Figure 6A is an electrical schematic diagram of a differential memory with a selection transistor that determines which side of the memory is subject to injection according to an embodiment of the invention. The advantage of the memory of FIG. 6A over the memory of FIG. 3 is that the drains of the two injection transistors M0 and M1 can be lowered during the injection period, and the corresponding selection can be initiated by applying selection signals to their corresponding selection lines Sel_0 and Sel_1. Transistors S0 and S1 are used to select one side for writing. The input node X of this differential pair can be connected to a bias transistor as shown in FIG. 3 or any other type of optional current source circuit. As in each of the embodiments shown herein, the input node X may be a current source placed in the actual memory, or a conductor leading to another current source placed elsewhere. For example, sharing the current source among the memory elements in the array column can save layout area, but the speed may be reduced due to the increased capacitance at the shared node. If it conforms to the design, it is also possible to guide the current to the appropriate node X by using an appropriate selection transistor, and use an in-element current source for one of the read/write operations, and an out-of-element current source for the other operations. In the claims, the term "current source" means to express the concept of a node from which current can be drawn, thus, for example, if there is a node supplied with current within a memory element, the node can be a current source, even if The same is true for the current supplied by transistors outside the memory element itself.

Row selection now turns to FIG. 6B, and the row selection transistor M2 is added to the basic structure of FIG. 6A. Whether the control current source C1 of the Row_Sel circuit coupled to the gate of M2 is coupled to the node X. Because up to half of the transistors have their source/drain connected to the node, the capacitance observed by the external (column) current source is reduced in this way. Due to the reduced capacitance, this method provides faster reading and writing.

Fig. 7 is an electrical schematic diagram of a differential memory coupled to a pFET current source, and the selection transistors (S0, S1) are constructed together with an nFET according to an embodiment of the present invention. The memory is activated by pulling up Vdd (to about 5V), by setting its gate voltage to Vdd to turn on one of the selection transistors (S0, S1), and by setting its voltage to ground to turn off the other selection transistor. Perform programming. The floating gate transistors (M0, M1) on the "on" side will experience IHEI, causing their gate voltage to drop. The floating gate transistors (M0, M1) on the "off" side do not have any channel current, so the injection is reduced to a negligible level, and the gate voltage remains roughly unchanged.

In an alternative embodiment, the select transistor in FIG. 7 may be constructed together with a pFET. It is also possible to use the select transistor in FIG. 7 to separate multiple memory elements in the array from a single sense amplifier D1.

FIG. 8 is an electrical schematic diagram of a differential memory circuit in which the current is controlled at the drain of the floating gate injection transistor according to an embodiment of the present invention. Because there are two separate current controls, the IHEI can be controlled separately in M0 and M1. In this embodiment, the current "sources" C0 and C1 may be current sinks. Current "sinks" can sink current, and current sources can supply current.

FIG. 9 is an electrical schematic diagram of the version circuit of FIG. 8 according to an embodiment of the present invention. In this version, applying bias to deviation 0 or deviation 1, and applying 0V to other signals will write to the memory. If deviation 0 is set to the bias voltage and deviation 1 is set to 0V, then current will flow through M2 and M0, causing IHEI in M1 and reducing the voltage on FG0. In this case, no current will flow through M3 and M1, so the injection rate at M1 will be much smaller than that at M0. When the deviation 1 is set as the bias voltage and the deviation 0 is set as 0V, the opposite is true. During reading, both deviation 0 and deviation 1 can be set to 0V to prevent current from bypassing the sense amplifier.

The read operation of the memory of FIGS. 6A, 6B, 7, 8 and 9 is similar to that described in FIG. 3.

The programming and reading functions are separated by adding pFET read transistors (M2, M3) to each floating gate in the circuit of Figure 10. Fig. 10 is a schematic diagram according to an embodiment of the present invention, which includes a pFET read transistor associated with each floating gate. This modification allows the drain voltage (Vinj) of the transistor to be lower than ground while speeding up the IHEI process during writing. This will also increase the design flexibility of the differential sense amplifier.

Figure 11 is a schematic diagram of an embodiment of the present invention similar to Figure 10, but including row select transistors (S2, S3, these will be selectively activated by the "EN" signal) to isolate the memory element from the differential sense amplifier. This modification allows multiple memory elements to share a single differential sense amplifier D1. If necessary, the selection transistors (S2, S3) can be nFET (as shown in the figure) or pFET.

FIG. 12 is an electrical schematic diagram of an alternative part of the circuit contained in block 12 of FIG. 11 according to an embodiment of the present invention. In this alternative embodiment, the selection transistors (S2, S3) are pFETs, and they are arranged differently from the pFET reading transistors M2, M3. But the effect is the same.

FIG. 13 is an electrical schematic diagram of an embodiment of the present invention for constructing bidirectional tunneling. In this embodiment, bidirectional Fowler-Nordheim (FN) tunneling is used instead of FN tunneling and IHEI for program/erase. In order to provide bidirectional tunneling in the single-well CMOS process, control gates CG0 and CG1 are added (in this example, the pFET has short-circuited source, drain and well (this is also a MOSCAP), which is capacitively coupled to the floating The gate allows the floating gate voltage to change. To program the memory, one of the MOSCAP control gates is set to a high voltage (Vcg is about 10V), and the tunnel junction is set to ground. By using the capacitance and Any large control gate MOS capacitor with parasitic capacitance, through capacitive coupling and the electron tunnel from the tunnel junction on the floating gate, makes the floating gate voltage close to Vcg. In order to erase the memory, the tunnel junction is raised (to About 10V), and pull the control gate to ground. The electrons tunnel out of the floating gate to tunnel junction. The control gate in FIG. 13 can also be applied to the memory as illustrated in FIG. 3 because it can float to the ground. The gate is biased to maximize writing efficiency. In one embodiment, the MOSCAP shown in Figure 13 can be placed in a separate n-well. Alternatively, the two MOSCAPs can also share a single n-well to save area. For saving More area, at the cost of reduced MOSCAP capacitance, which can be placed in the same n-well as other pFETs (M0 and M1) in the memory. Or, given enough capacitance, M0 and M1 can take over the functions of CG0 and CG1 , And then ignore it.

Fig. 14 is an electrical schematic diagram of an alternative embodiment of the present invention based on Fig. 13. In this version, a sense amplifier is added to the memory in Figure 13, and the memory is written in injection instead of bidirectional tunneling. If the pFET is initially off, the floating gate voltage can be pulled down through capacitive coupling to drive the start of the injection process. Similarly, when the tunneling is completed, the control gate can be used to end the tunneling by pulling the floating gate high, reducing the oxide voltage (that is, reducing the difference between the tunneling voltage and the floating gate voltage), and together with the tunneling current. Tunnel treatment. The latter example requires sensing and feedback circuits, which can be easily designed by those skilled in the art. The control gate transistor used here has the same options related to its n-well connection as the control gate transistor in FIG. 13.

FIG. 15 is an electrical schematic diagram of an embodiment of the present invention, in which half of the differential memory is shared by all memory elements in a row of memory. In the embodiment in FIG. 15, the right side of the differential pair in each memory element has been replaced by a single, shared right side containing transistors with Sel0 and FG0 as their gates. In this embodiment, the shared memory element is written to halfway between the logic 0 and the logic 1 state, and each unshared memory element (on the left side of the figure) to the 0 state or the 1 state is dependent on the storage value. During readout, except for one (this is for bit selection), Sel1_x will be set to Vdd for all x. Using the right side as the neutral reference, the differential sense amplifier will determine whether the selected floating gate transistor on the left side of the figure has been written to the 0 state or the 1 state. One possible modification to this memory is to remove the current source shown in the upper part of the figure. In this case, connect the sources of all selection transistors to Vdd. Although the circuit no longer functions like a real differential pair, the differential sense amplifier still compares the reference current (from the FG0 leg of the circuit) with the data current (from the FGx leg of the circuit). Alternatively, there may be two shared memory elements (replacing the Sel0 and FG0 devices in the figure), one of which is written to the logic 0 state, and the other is written to the logic 1 state, so that during a read operation Logic 0 and logic 1 currents are divided equally to produce a value halfway between logic 0 and logic 1. Alternatively, there may be any number (up to N) of sense amplifiers to allow multiple memory elements in the same row to be read at once. During the readout period, a plurality of Sel1_x lines are reduced to a low voltage at the same time, only those memory elements are provided and multi-bit reading is allowed. A current mirror and no bias transistors may be required in the construction to make a copy of the reference current for each bit.

FIG. 16 is an electrical schematic diagram of an embodiment of the present invention, which modifies the version of FIG. 14 by adding a pair of floating gate transistors (M2, M3) to monitor the end of the tunneling process. By applying the appropriate Tun_done_Vdd, those skilled in the art will now understand that the TunDone0 and TunDone1 signals generated by the circuit can be used to activate and/or deactivate the tunneling process. This design is particularly suitable for ensuring that the tunneling does not completely turn off any pFET floating gate transistors in the memory.

FIG. 17 is an electrical schematic diagram of an embodiment of the present invention, which illustrates how to use feedback during tunneling to explicitly apply a small amount of IHEI to the memory to prevent over-tunneling of the memory. As the voltage of the floating gate (FG0 or FG1) increases, the increased amount of current will flow through the injection transistors (M2, M3). The end result is that when the floating gate has tunneled to its high voltage, the number of electrons added to the floating gate by IHEI will be equal to and opposite to the number of electrons removed by tunneling. In this state, the floating gate voltage is stable. The careful design of the regulation circuit allows the designer to determine the final floating gate voltage. (Mainly depends on the Vtrip voltage (Vtrip0, Vtrip1) shown in the figure. This method can ensure that the memory will never be completely shut down, and allows to ensure that it is roughly mismatched with the tunneling rate, IHEI mismatch, device mismatch and other operating conditions Irrelevant erase processing.

FIG. 18 is an electrical schematic diagram showing a simplified embodiment of the present invention of the memory of FIG. 17. The Read_not signal is used to configure the memory in a relative write/erase read mode. During the write/erase period, the Read_not transistor M4 is turned off, the memory element is separated into two half elements, and the write/erase is simplified. During reading, the Read_not transistor M4 is turned on, and the two current sources M2 and M3 are combined to form a single current source, which supplies the equivalent of I deviation_read in FIG. 17. During the injection period, S0 and S1 are used as selection transistors, and during the tunneling period they are used as current controllers. (It assumes the same role of M3 and M4 in FIG. 1) FIGS. 19 and 20 are electrical schematic diagrams of embodiments of the present invention, which illustrate that the current can be controlled on the drain side of the injection transistor. The embodiment of Figure 20 has a clear nFET current sink M2 that controls the write and read currents. SEL_0 and SEL_1 have similar functions to the same signal in the memory of FIG. 6A. The differential sense amplifier used for this memory must accept a current of reverse polarity compared to the amplifier used for the memory presented above. Note that as shown in Figure 10, this form of current control can also be applied when the read and write functions are separated.

The example memory now turns to FIG. 25, which illustrates the novel memory 128. The memory 128 has an outgoing memory element bias current at node 130, which acts as a current source for the memory 128. The left and right sides 132 and 134 of the memory respectively include selection transistors (here a pFET) S0 and S1, which respectively couple the current source node 130 to the sources of the floating gate charge injection transistors M0 and M1, respectively (Shown here as pFET). The tunnel junction circuits T0, T1 (which are optional and can be constructed as described above) are provided to remove electrons from the floating gates FG_0 and FG_1, respectively. The drains of M0, M1 are coupled to nodes 136, 138, respectively, and these are respectively coupled to write circuits W0, W1, and to differential inputs 140, 142 of differential sense amplifier circuit 143, respectively. In order to read this memory element, a Row_Sel signal can be issued at node 144, and a bias current is applied to node 130 through, for example, the illustrated bias current circuit 146, to select a row containing memory elements (generally a row of a two-dimensional array of memory elements). ). The differential sense amplifier circuit 143 is then used to read the contents of the selected memory element. The writing is completed by sending the Row_Sel signal to select the row at the node 144 and applying a bias current to the node 130. By injecting electrons into the respective floating gates (FG_0 or FG_1), the left writing circuit W0 or the right writing circuit W1 is turned on to write the respective 0 or 1 (or the opposite depending on the configuration) into the memory 128. In this way, the same transistor is used for both reading and writing, and if necessary, the writing circuit, the differential sense amplifier circuit, and the current source circuit can be located outside the memory element, and the difference in density is greatly increased. The memory elements are shared, as those skilled in the art will now fully understand.

Turning now to FIG. 26, which illustrates a memory 148, a memory 148 and memory 128 of FIG. 25 except that the row select transistor is controlled by the signal Row_Sel is disposed in the current source section 130 and the node between the points 131, and It will be coupled to the sources of the selection transistors S0 and S1. This improvement reduces the capacitance observed by the current source circuit 146 of the memory element in which Row_Sel is not emitted. The reduced capacitance can improve performance at the cost of a single extra transistor per memory element. The operation of the memory is basically the same as that of the memory of FIG. 25.

Turning now to FIG. 27, it illustrates the memory 150 which differs from the memory 128 of FIG. 25 in that the current source circuit 152 is disposed within the memory 150 and is coupled to the current source node 130. To read the memory, use Row_Sel to select the row as described above, apply a voltage bias to the node 154 of the gate of the biasing transistor (here a pFET) 156, and measure the output through the differential sense amplifier circuit 143 . Writing is performed by selecting the row using Row_Sel, applying a bias to the node 154, and turning on one of the two writing circuits W0, W1. According to this version, for the entire memory array, the bias signal applied to the node 154 may be a global net. Placing the current source transistor 156 in the memory element itself can reduce the capacitance required for charging to complete reading and writing, thus achieving improved performance. There is a disadvantage associated with this embodiment that may or may not exhibit the difficulties of various memory applications. The current source matching from the memory element to the memory element will be insufficient because each memory element will have its own current source transistor 156, and it tends to be small area devices that vary from device to device and cause more variation. If necessary, it can be overcome by using known matching techniques in special applications, at the expense of increased circuit complexity and/or area.

Turning now to FIG. 28, it illustrates the memory 160. The difference between the memory 160 and the memory 128 of FIG. 25 is that the current source node 130 is omitted, and instead a pair of independent current sources 162, 164 (which may be Transistors or other suitable current source devices or conductors coupled to other current sources). The select transistor S2 (here a pFET) has a source and a drain coupled between the nodes 166 and 168 for coupling and decoupling the nodes 166 and 168. In this way, depending on the state of the signal Diff_Sel_b applied to the gate of the selection transistor S2, the memory element is allowed to be coupled to both the current sources 162 and 164 at the same time, or the right side of the memory and the left side of the memory are only coupled to their respective current sources 162 , 164. In this way, the sides can be independently (and thus single-ended) and simultaneously written to both sides of the memory element by decoupling the sides by the Diff_Sel_b signal. The row is selected by using the Row_Sel signal as described above, the current sources 162 and 164 are activated, the Diff_Sel_b signal is sent on the gate of the selection transistor S2 (to couple the right and left sides of the memory element), and the differential sense amplifier 143 Read the memory to complete the reading. By using Row_Sel to select a row, starting the current sources 162 and 164, deciphering the Diff_Sel_b signal on the gate of the selection transistor S2, and using one or both of the writing circuits W0 and W1 to write information to the memory 160, To complete the write.

The switch S2 in this application is important because it allows the differential memory element to be changed to two single-ended memory elements. By closing switch S2, the memory is differential. Applications include differential readout, where current can be directed from one side of the memory element to the other side of the memory element based on the floating gate voltage. In this mode, although there may be two (e.g., 162, 164 in this version), the circuit will still operate as if there is a single current source. By opening switch S2, the memory element will be divided into two separate halves. It is now possible to write to one side of the memory element at one time and write to the other side of the memory element at another time, or write to both sides of the memory element independently at the same time, without affecting the other side at all. It is also possible to read the current from one side of the memory in debug mode at once to determine the voltage of each floating gate.

Turning now to Figure 29, which illustrates the memory 172 and support circuitry. The difference between this memory and the description in FIG. 28 is as follows. The current sources 162, 164 are coupled to the sources (nodes 176 and 178) of the selection transistors S0 and S1. Also coupled to those nodes is a differential sense amplifier circuit 174. The drains of the injection transistors M0 and M1 are coupled to the node 180, as well as the current source 182 and the write circuit 184. To read the memory, Row_Sel is issued to select a row, a bias current from the current source 182 is applied, the current sources 162 and 164 are turned off, and the memory state is read through the differential sense amplifier 174. In order to write to the memory, the row is selected by the Row_Sel signal as described above, the bias current from the current source 182 is turned off, the bias current is applied through one of the current sources 162 and 164, and the write circuit 184 is activated to write to the memory. This memory can write to both the right and left sides at the same time (both the current source is turned on), and requires only one write circuit compared to the two presented in other designs herein.

Turning now to FIG. 30, it illustrates a memory 186, which is similar to FIG. 29, but with a slightly different support circuit. In this version, a single write circuit 184 is coupled to the node 180 without coupling an additional current source to the node, as in the embodiment of FIG. 29. The voltage input differential sense amplifier circuit 174' is used to read the memory. In order to read the memory element, the Row_Sel signal is issued as described above, and the bias current is applied to both sides of the memory element, and each side of the memory serves as an independent source for the follower. The voltage is read through the differential sense amplifier 174'. To write to the memory, a Row_Sel signal is issued, one or both of the current sources 162 and 164 are turned on, and the write circuit 184 is activated.

Turning now to FIG. 31, it illustrates another embodiment of a memory 190 according to the present invention. This memory has a pair of floating gate injection transistors M0, M1, the floating gates of which can be coupled to the tunnel junctions T0, T1 as described above (if required). The write circuits W0 and W1 are coupled to the drains of M0 and M1, respectively, and these drains may also include the input of the differential sense amplifier 174. Power supply transistors (pFETs) S0 and S1 have their gates coupled to Vbias and their sources coupled to VS_0 and VS_1, respectively. The drains of S0 and S1 are coupled to the sources of M0 and M1, and are cross-coupled through a selection transistor S2 (here, pFET), the gate of which is controlled by the Diff_Sel_b signal. VS_0, VS_1, Diff_Sel_b, and V_deviation are signals transmitted on lines, all of which are shared among the line memory elements of the two-dimensional array of memory elements. This is done by setting VS_0 and VS_1 to Vdd, applying a bias voltage with V-deviation to the power supply transistors S0 and S1, issuing Diff_Sel_b to couple the left and right sides of the memory 190, and reading the memory using the differential sense amplifier 174 Read. To write to the memory, set VS_0 and VS_1 to Vdd, apply a bias voltage with V_ deviation, de-send Diff_Sel_b to isolate the left and right sides of the memory 190, and activate one or both of the write circuits W0 and W1 to write The contents of the memory. This embodiment uses the current source in the memory (S0, S1) for faster operation, and can write to both sides of the memory (that is, both floating gates FG_0 and FG_1) at the same time, and only one is used for the embodiment of FIG. 30 Additional transistor (S2).

A variation of the embodiment of FIG. 31 is illustrated in FIG. 32. In the embodiment of FIG. 32, the floating gate injection transistor includes a control gate (it is not explicitly shown that it is not required in the embodiment, but it is always an option for any memory). The control gate terminals C0, C1 are coupled to the sources of the power transistors S0, S1, respectively, and are schematically represented as capacitors 194, 196, respectively. In this way, connecting the control gate to the VS_x signal line facilitates efficient routing, because VS_x serves as both the control gate input (to Cx) and the power supply (Sx) for the current source (x appropriately represents 0 Or 1). Setting VS_x to low not only cuts off the current source in the memory, but also pulls the floating gate FG_x to a lower voltage to reduce write interference. Note that the control gate signal is not required to be combined with the VS_x signal, and other versions of the memory described herein may be modified to use this feature. Otherwise, the memory 192 operates in the same manner as the memory 190 of FIG. 31.

In FIG. 33, another variation of the embodiment of FIG. 31 is illustrated. In the embodiment of FIG. 33, the VS_x signal is unclear, and there is a signal instead labeled VS applied to the node 200, which is connected to the sources of the power transistors S0 and S1. This embodiment saves the wiring of the second VS line, but suppresses the use of the technique of FIG. 32 together with FIG. 34. This is because once VS_0 and VS_1 are combined into one signal VS, as shown in Fig. 33, the two control capacitors in Fig. 34 cannot be independently controlled. Otherwise, the memory 198 operates in the same manner as the memory 190 of FIG. 31.

Multi-bit storage One way to store multiple bits of information in a differential memory structure such as those described herein is to write a reference on one side of the memory and store one of many levels on the other side of the memory. By adding various offsets to the readout system, and determining how many offsets are required for the readout to change state, the stored multi-bit value can be recovered. This is an example of a two-bit system: 1. Write 0.5 value to the A side; 2. Write any of the following {1, 0.75, 0.25, 0} to the B side; 3. During the readout, pass the offset Shift {0, +/-3/8} to compare side A and side B; 4. According to the first comparison result, it will be determined that the stored value is one of {1, 0.75} or {0.25, 0} One. In this two-bit case, the offset of the second comparison narrows the list to one value. Usually, the comparison is continued with different offsets until the value is determined. Each comparison produces one bit of information.

To apply an offset, current can be added to the memory or a capacitively coupled control input node can be used to directly shift the floating gate voltage.

In another example, different values will be written to both sides of the memory structure, some operations (such as subtraction) will be performed on them, and then the result will be obtained and compared with some fixed reference set.

Boundary reading The quality control process before delivery to the final customer usually requires the memory to be able to properly store and reliably retrieve the required value. Therefore, a method for checking the limit and the memory through which the stored value can be read is very valuable. The memory device described in this disclosure exhibits some interesting challenges when designing and performing the test. The problem is that the differential readout mechanism used by most of the memories presented here is so robust that even a very small differential floating gate voltage will produce correct operation. The goal is to ensure a considerable differential floating gate voltage for the best retention and a truly robust design. According to the first basic method, the memory 128' is illustrated in FIG. 34. Except for explicitly requiring a control gate, the memory 128' is the same as the memory 128 of FIG. 25 in most respects. In order to detect the boundary, the following procedure is used: Store zeros in the memory...

1. If zero is stored in the memory, then the FG_0 voltage should be lower than the FG_1 voltage; 2. Apply a voltage to the node C0 of control_gate_0, which is higher than the voltage applied to the node C1 of control_gate_1 by a small amount you want ; 3. Due to capacitive coupling, the voltage of FG_0 increases relative to that of FG_1, so it is more difficult to read the contents of the memory correctly; and 4. If the memory is still read correctly under these conditions, then between FG_0 and FG_1 The voltage boundary is as desired.

Store one in the memory...

1. If 1 is stored in the memory, then the voltage of FG_0 should be greater than the voltage of FG_1; 2. Apply a voltage to the node C0 of control_gate_0 that is smaller than the voltage of the node C1 applied to the node control_gate_1 by a small amount you want;

3. Due to capacitive coupling, the voltage of FG_1 increases relative to FG_0, so it is more difficult to read the contents of the memory correctly; and 4. If the memory is still read correctly under these conditions, then the voltage boundary between FG_0 and FG_1 Is as desired.

This technology can be used with other versions of memory described in this article. In addition, a specific test protocol can be accepted to provide control gates for the memory elements on the chip or in the array to perform the tests described above, without the need to provide control gates for all, and control some or all of them. The test of gate-supplied memory elements can be considered to be sufficient to verify a specific chip when there is no individual test for all memory elements on the chip. Also note that "control gates" are not essentially required, only low-leakage capacitors, each with a terminal coupled to (or) a floating gate. The capacitors are required to be independent of each other so that the floating gate can be manipulated independently.

Turning now to Figure 35, it illustrates an alternative boundary reading method. In most respects the memory 128" is similar to the memory 128 of FIG. 25. The difference is that it provides a mechanism for increasing/decreasing the offset current to the sense amplifier input (nodes 136, 138). According to the embodiment illustrated in FIG. 35, it provides The boundary current source (or tank) circuit 202. The switches 204 and 206 are independently controllable to couple the circuit 202 to the node 136 or the node 138 (sometimes referred to herein as the "sense node" because it is coupled to the differential The input of the sense amplifier 143). Set or design the current provided by the circuit 202 to the appropriate current boundary of the memory element. If the current increases/decreases from the input of the sense amplifier circuit 143, the memory still reads correctly , Then there is an appropriate boundary. If it is not, that is, the memory element output changes state, then there are improper boundaries and potential defects. For example, this can be done by the following procedure: 1. Store 0 in the memory 128" and V(FG_0 ) Is less than V(FG_1). This means that the source-drain current I0 through M0 is greater than the source-drain current I1 through M1. In order for the memory element to have an appropriate current boundary, I0 should be larger than I1 by a predetermined boundary.

2. Close switch 204 to "steal" a predetermined amount of current from node 136. This will reduce the current flowing from node 136 into differential sense amplifier 143.

3. If the state of the sense amplifier does not change, then there is an appropriate current boundary. If there is indeed a change, then the limits are inappropriate and there are potential flaws.

Or: 1. The memory 128" stores 0, and V(FG_0) is greater than V(FG_1). This means that the source-drain current I0 through M0 is smaller than the source-drain current I1 through M1. In order to To make the memory element have an appropriate current boundary, I0 should be smaller than I1 by a predetermined boundary.

2. Close switch 206 to "steal" a predetermined amount of current from node 138. This will reduce the current flowing from node 138 into differential sense amplifier 143.

3. If the state of the sense amplifier has not changed, then there is an appropriate current boundary. If there is indeed a change, then the boundary is inappropriate and there are potential flaws.

Reducing Write Disturbance Turn now to FIG. 36, which shows a graph of write disturbance versus gate-to-drain voltage for a 0.25 micron process device. When the gate is at a relatively high voltage and the drain is at a relatively low voltage, write disturbance occurs. The data labeled "A" represents the hot electron gate current (write current) in amperes shown on the vertical axis within the range of the gate-to-drain voltage shown on the horizontal axis. The data set labeled "B" represents the gate current (write disturbance) introduced by band-to-band tunneling. The write disturbance is related to the band-to-band tunneling current at the drain of the memory element in the off state during the write operation of the other memory element. Write disturbance can cause data corruption, so it needs to be minimized. As can be observed, a lower gate-to-drain voltage results in a lower write disturb current, and the magnitude of the difference between the write current and the write disturb current will increase significantly with the decreasing voltage. Data set A represents data that the well voltage Vwell was originally 3.3 volts, the gate voltage Vg was originally 2.2 volts, and the source voltage Vs was originally 3.3 volts. Data set B represents data with Vwell=3.3 volts, Vg=2.2 volts, and Vs=1.5 volts. As can be observed from FIG. 36, in the 0.25 micron process, the write current at 5.25 volts is six orders of magnitude higher than the write disturb current. As the size of the process continues to shrink, it is estimated that this boundary will shrink to approximately 4 steps in the 0.13 micron process. Reducing the gate drain will shift the results to the left of the figure, thus reducing the write disturb current to a small part of the write current.

Turning now to FIG. 37, it shows a memory 208 that is very similar to the memory 128 of FIG. 25. This memory includes capacitors 210, 212 coupled to FG0 and FG1, respectively, which include nodes C0 and C1, respectively. For example, these can be control gates.

In order to reduce the gate-drain voltage, the following procedures can be used: (control_gate_x refers to control_gate_0 and control_gate_1; Cx refers to C0 and C1) 1. For the selected row (the written row), set the control_gate_x of node Cx Is high; 2. For unselected rows (rows not written), set the control_gate_x of node Cx to low; and 3. The capacitor couples the floating gates in the unselected rows to a lower voltage, thus reducing it The gate-drain voltage, in turn, reduces its band-to-band tunneling current, thereby reducing write interference.

Note that this concept can now be applied to the various memory configurations described herein, and is not limited to being used only in a specific memory such as FIG. 37.

NVM Array FIGS. 38, 39, and 40 are electrical schematic diagrams illustrating examples of NVM arrays that can be manufactured according to embodiments of the present invention. Turning now to FIG. 38, which shows the memory array described in FIG. 32. In this example, the VS_0 and VS_1 conductors act as capacitor inputs. The design of Figures 21 and 22 according to the present invention uses pFETs to construct tunnel junctions, and all tunnel junctions in a specific row are connected together by conductors (for example, V_tunnel<1> ). Paging is defined as a set of memory elements that share a common erase signal and can therefore be erased at the same time. This example has two pages. Page 0 contains four bits at the bottom of the array, while page 1 contains two bits at the top of the array. The number and size of the pages can be constructed by coupling together tunneling of different numbers of rows.

Turning now to FIG. 39, which shows the memory array depicted in FIG. 25. Because 38 is in this embodiment, only one current source is required for each column, so less conductor wiring can be provided, which significantly reduces the complexity of the circuit compared to the figure. The disadvantage of this design is that the relatively large capacitance on the common current source conductor results in a slower read time. However, sharing a single current source for the entire memory column is advantageous because it can be larger in the array and its number can be smaller, providing better internal matching.

Turning now to FIG. 40, it shows the memory array depicted in FIG. 34. According to this embodiment of the present invention, as discussed above, there is one current source per column, and a capacitor (control gate or other) is used to provide boundary read capability and reduce write interference.

It is important to note that Figures 38, 39, and 40 do not include the extensive set of memory array configurations presented herein. The examples clearly illustrate that those skilled in the art can design a functional memory array of virtually any size based on the memory presented herein.

Turning now to FIG. 44, it illustrates a sample negative polarity charge pump write circuit such as labeled "W0" and "W1" in the various figures. Connect the output to one of the sense nodes. If required, the diode D1 can be a diode-connected pFET. The capacitor C1 can be a MOSCAP or any other suitable capacitor. In this embodiment, the gate G1 can be an AND gate, and when "ENABLE" and "CLOCK" are issued, the circuit causes the memory to be written. Those skilled in the art will now recognize that any number of different circuits can be used to accomplish the same basic function.

Turning now to Figure 45, it illustrates a sample prior art sense amplifier circuit. This embodiment uses nFETs T1, T2, T3, and T4. The sense inputs S+ and S- receive the currents I+ and I- of the sense nodes respectively from the differential memory. The amplifier output is at nodes V+ and V-. If I+>I-, then V+>V-; if I+<I-, then V+<V-. Those skilled in the art will now recognize that any number of alternative circuits (including those made with pFETs instead of nFETs) can be constructed to achieve the same basic functions.

Although external injection is not common, the NVM constructed according to the present invention uses a certain level of charge (and a relatively high gate voltage) placed on the floating gate to make recovery. The idea is to externally connect the applied voltage to the drain and/or source of the memory in order to subject it to IHEI and/or band-to-band tunneling. This applies to the following situations, in which the memory device has its gate set to "off", so that the internal charge pump can be restored because there is no drain-source current in the injection device and cannot cause a large amount of IHEI manufacturing process.

Turning now to Figure 41, one way is to switch to the drain of the memory under negative voltage. A switch can be used to selectively set the drain voltage (called V_External_Inject) through the pin. With an externally applied voltage, the drain can be set to a very low voltage (approximately -5 to -4 volts in the 0.18 μm process), which will cause band-to-band tunneling.

According to Fig. 41, the sense amplifier and write circuit 220 of each column are coupled to the external voltage source labeled V_external_inject through a pair of switches 222, 224, which will reduce the voltage of the drain of the injection transistor relative to the floating gate, and from The drain on the floating gate introduces band-to-band tunneling to "unstick" the memory. This is constructed by the following procedure: 1. Apply a relatively low voltage to the V_External_Inject line.

2. Close switches 222, 224 to couple V_External_Inject to the drain of the floating gate pFET of the memory (this can be done on a column-by-column basis, or by the width of the array at the same time if needed).

3. Wait when the bit is "unstick".

4. Turn on the switches 222, 224 to terminate the process.

5. Measure the bit current through a differential sense amplifier to verify proper operation.

According to the embodiment illustrated in FIG. 42, pFETs can be used as switches 222, 224. In this case, the switches 222 and 224 are constructed as pFETs, and their sources are coupled to the memory readout lines 226 and 228. Need another externally applied signal: External_Inject_Gate. This signal must be at least one Vt lower than V_External_Inject, and the body effect on the pFET is also considered because its well voltage does not match its source voltage. This requires the switches 222, 224 to be turned on. The well itself (driven by External_Inject_en_b) should be switched from 0V (to start external injection mode) to Vdd (to close external injection mode). This switch is needed to reduce the voltage on the pn junction in the pFET. Otherwise, malfunction may occur. According to one embodiment of the present invention, External_Inject_Gate is set to approximately -5 volts, V_External_Inject is set to approximately -3 volts, and External_Inject_en_b is set to approximately 0 volts.

As those skilled in the art will recognize, other ways can be used to achieve the same purpose. For example, setting the "source" voltage on the IHEI transistor to be very high while keeping its drain low (grounded or lower) can have the same end result, but it is not very easy to construct. Note that during normal operation, the "source" side here may actually be the "drain" side of the transistor.

Turning now to Figure 45, which shows a more specific construction of the concept illustrated in Figure 44. In this version, the switches 222 and 224 are constructed as pFETs with their sources coupled to the memory readout lines 226,228. Couple its well to the line labeled External_Inject_en_b, couple its gate to the line labeled External_Inject_Gate, and couple its drain to the line labeled V_External_inject. In one example, the External_Inject_Gate line is set to approximately -5 volts, the V_External_inject line is set to approximately -3 volts, and the External_Inject_en_b line is set to approximately 0 volts.

Tunneling junction layout Most of the arrays expected in the present invention share tunneling junctions among many memory elements. Some tunnel junctions require their own n-well to be separated from the n-well supporting the rest of the memory. Because the spacing between n-wells and n-wells tends to be relatively large due to manufacturing constraints, staggering the tunneling junctions with n-wells can provide an effective layout. When using this scheme, the memory page size is several times that of two memory element rows. An example of a tunnel junction layout according to an embodiment of the present invention is illustrated in FIG. 43. This example shows n wells for a 4-column, 3-row, 2-page memory array. Lines 230-276 are floating gates that, as illustrated, couple the main memory n-wells 278, 280 with the corresponding tunnel junction n-wells 282, 284.

In summary, in NVM applications, pFET floating gate transistors have several advantages over nFETs: 1. The p-channel floating gate MOSFET can inject electrons into the floating gate with a channel current smaller than the typical current used for n-channel floating gate MOSFETs. On the grid. Thus, charge pumps based on pFET memory (circuits that are generally required on a wafer to provide a voltage exceeding Vdd for erase and write operations) generally consume less energy than those designed for nFET memory.

2. IHEI in pFET mainly generates channel hot electrons, but the equivalent mechanism in nFET (channel hot electron injection or CHEI) generates channel hot electron holes. Because hot electrons do much less damage to the gate oxide than hot electron holes, pFETs have reduced oxide wear and better program/erase cycle durability compared to nFETs.

3. The barrier height from a floating gate pFET with a p+ doped gate will be about 4.2 eV (see Figure 2), compared to about 3.04 eV for an nFET with an n+ doped gate. Therefore, the leakage current in nFET is smaller than that in pFET. Therefore, the data retention characteristics of pFET floating gate memory with the same oxide thickness are better than that of nFET floating gate memory. As a result, pFET memories can use thinner gate oxides, such as 70 Å (via 3.3V I/O devices) as seen in standard double-gate oxide CMOS processes. In comparison, memories based on nFET floating gate transistors require additional process steps to produce thicker gate oxides (the minimum thickness is generally 80 Å).

In NVM applications, differential memory has several advantages over single-ended memory: 1. The logic state of differential memory is determined by the difference in charges on the two floating gates. When there are more electrons on the "0" floating gate than on the "1" floating gate, the readout current mainly passes through the transistor with the "1" gate, and vice versa. Therefore, although the two floating gates are negatively charged with respect to the n-well voltage, it is still possible to distinguish between logic 1 and logic 0 states. This characteristic means that neither side has such a high gate voltage that cannot be subsequently turned on and injected.

2. The charge leakage mechanism tends to cause the charges on the "1" and "0" floating gates to leak in the same direction (that is, both sides cause the charges to leak to their gates or leave their gates in a common direction). Differential memory has common mode rejection, which means that it is sensitive to the voltage difference between floating gates rather than the absolute value of its voltage. Therefore, common-mode charge leakage does not affect the stored logic state. Therefore, the retention of differential memory is better than single-ended memory.

3. The read operation uses the principle of distinguishing the more conductive path between the two halves of the differential memory. When reading the memory, as long as the differential sense amplifier has sufficient sensitivity to determine which path the current takes to pass through the memory, any small tail current can be used. Thus, the memory described herein allows for low-energy memory circuits.

4. Because the two halves of the differential memory are usually in close proximity on the wafer, they are appropriately matched to the transistor characteristics. For example, the gate oxide thicknesses of two adjacent floating gate transistors are more closely matched than those of two very far apart transistors. As a result, the differential memory design is not very sensitive to transistor changes that can affect the read accuracy of a single-ended memory.

5. Differential memory is self-referencing, meaning that one side of the memory is the reference on the other side. Thus, the differential memory eliminates the need for the accuracy of current or voltage reference circuits on or off the chip, typical of single-ended memories. This self-referencing characteristic can be maintained regardless of whether each element in the memory is differential (as shown in Figure 3), or whether multiple memory elements share a single half of the memory elements (as shown in Figure 15).

6. Since the differential memory is self-referencing, it has excellent common mode rejection. Common mode rejection provides differential memories with better immunity to power and temperature fluctuations than single-ended memories.

7. The differential NVM element has a differential output similar to the well-known SRAM element in CMOS design. Therefore, the differential NVM element can use the ultra-fast differential sense amplifier and bit line precharging that are common in SRAM design (well known to those skilled in the art, and in order to avoid making the present disclosure too complicated, it is not described here). technology. The result is that differential NVM elements allow faster readouts while lower energy consumption compared to single-ended memory elements.

In short, differential memories based on pFET floating gate transistors have many advantages over single-ended memories, nFET memories and differential nFET memories. It provides NVM with low energy consumption, high speed and high reliability in logic CMOS.

Although the embodiments and applications of the present invention have been shown and described, those skilled in the art who benefit from the present disclosure will easily understand that many modifications more than those mentioned above are possible without departing from the inventive concept herein .

For example, please note that although the concept of the present invention can be implemented in a single well, a single multi-process and will work with a low-voltage process (for example, <= 3 volts), the present invention is not limited thereto, and the present invention It can be implemented in a process supporting multiple polysilicon layers, multiple wells, and/or higher (or lower) voltage devices.

In addition, the n-well concept used in this article not only covers conventional n-well devices, but also covers NLDD (N-type slightly doped drain) devices that increase the reliable gate-drain and drain-source voltages of the device and other slightly doped drain devices. The doped or isolated structure makes it actually work like a conventional n-well device in this respect. It can also be constructed in the thin film on the substrate with the same thin film structure.

In one embodiment of the present invention, the current sink device can be used in whole or in part as an alternative to the current source device described above.

In another embodiment of the present invention, the selection transistors S0, S1, S2, etc. as discussed above can generally be constructed with nFETs instead of pFETs if necessary.

Finally, because the charge on the floating gate can be written carefully and accurately, it is possible to use these structures known in the prior art coupled with a higher-resolution readout circuit to store multiple data for each memory element. digit. Through the memory disclosed herein, for example, using the memory of FIG. 15 will directly store charges of four different levels. There can be stored separately , and The three reference half pairs FG0_A, FG0_B, and FG0_C replace the single reference half pair FG0 of the stored charge value. During readout, the differential sense amplifier sequentially compares the values stored on a floating gate, such as FG1, followed by FG0_A, FG0_B, and FG0_C. If the value stored on FG1 is less than that on FG0_A, then FG1 stores zero. If the value on FG1 is greater than FG0_A but less than FG0_B, then FG1 stores one. If the value on FG1 is greater than FG0_B but less than FG0_C, then FG1 stores two. If the value on FG1 is greater than FG0_C, then FG1 stores three. By storing four distinguishable charge values, each half element holds two bits of information. This method can be clearly extended to store three or more bits per memory, only limited by the accuracy of the write, hold, and read processing. Therefore, the present invention is only limited to the spirit of the above claims.