Method and apparatus for phase-domain semi-coherent demodulation

Method and equipment for phase domain quasi-coherent demodulation

Technical field

The present invention generally relates to the field of wireless technology, and more specifically relates to a method and system for a digital radio transceiver.

Background technique

For example, wireless technologies such as terrestrial and satellite mobile communications and short-range wireless systems such as BLUETOOTH (Bluetooth) generally use M-ary differential coding phase shift keying (MDPSK) for transmitting data. Due to the advantageous characteristics of MDPSK, such as no need for a carrier recovery circuit, fast acquisition performance, phase ambiguity resolution capability, and good performance on multipath fading channels, MDPSK is typically used.

Current solutions for improving MDPSK detection performance utilize a traditional differential detection circuit equipped with an infinite impulse response (IIR) filter combined with decision feedback. A carrier frequency tracking loop is used to compensate for the carrier frequency offset typically generated in mobile communications. The quasi-coherent demodulator approaches the performance of the coherent MDPSK demodulator without the need for carrier phase capture and tracking.

Referring now to FIG. 1, a known quasi-coherent demodulator 100 is illustrated. In the figure, the thick arrow represents a complex signal, and the thin arrow represents a real signal. The input signal xi in the form of a complex number is received by the quasi-coherent demodulator 100. The quasi-coherent demodulator 100 processes the input signal into the amplitude Ai100 and phase θi100 components of the real signal via an amplitude calculator 104 and a phase calculator 106 respectively according to the following equation: xi=Ai100ejθi100,i=1,2 ,3...---(1)]]>In order to generate a reference signal ui100, the modulation effect on the input signal xi is eliminated from Equation 1. The influence of modulation is eliminated by rotating the input signal xi by a delay decision φi-1100 of the decision unit 110. The decision φi100 is based on a reference phase ψi100 and phase component θi100 described in more detail below. The rotation of the input signal xi can be realized by subtracting the output decision i100 of the decision unit 110 from the phase component θi100 of the input signal xi.

In order to obtain a rotated input phase ξi100, the phase summation adder 112 performs subtraction of the decision φi100 from the phase component θi100. The rotated input phase ξi100 along with the amplitude Ai100 is input to an amplitude and phase to complex converter 114. The amplitude and phase to complex converter 114 outputs a reference signal ui100. The following equation applies to the reference signal ui100:The reference signal ui100 may always be interfered by such damages as noise and inter-symbol interference (ISI). The damage can be averaged by integrating at the integrator 108. To ensure that the amplitude Ai100 of the quasi-coherent demodulator 100 is taken into account, the integrator 108 operates in the complex domain. The coherence parameter α and the reference signal ui100 are input together to form the output of the integrator 108-the reference vector ri100. There are many ways to integrate the reference signal ui100. In an embodiment of the present invention, the exponential integration window produces the following equation: ri100=α*ri-1100+(1-α)*ui100,i=1,2,3...---( 3)]]> The reference vector ri100 is input to a complex-to-phase converter 116. The complex-to-phase converter 116 outputs the reference phase ψi100 to a unit delay 118.

As described above, in order to eliminate the influence of modulation, the decision unit 110 performs an experimental decision on the transmitted symbol of the input signal xi. The test decision is input to the phase sum adder 112. The decision φi100 made by the decision unit 110 is based on the phase difference between the actual input phase component θi100 and the previous reference phase ψi-1100. The previous reference phase ψi-1100 is output from the unit delay 118. The unit delay 118 receives as input the reference phase ψi100 from the complex-to-phase converter 116. The phase difference between the actual input phase component θi100 and the previous reference phase ψi-1100 is calculated by a second phase summation adder 120 and input to the decision unit 110.

The function of the decision unit 110 depends on the number of modulation levels M. For example, for M=2, the following equation is true:The decision i100 is entered into a second unit delay 122. The delay decision i-1100 output by the second unit delay 122 is then input to a phase summation adder 124 and a phase summation adder 126. The first additional phase summation adder 124 subtracts the delay decision φi-1100 from the output of the phase summation adder 120. The output of the phase summation adder 124 is the output yi100 of the quasi-coherent demodulator 100.

Replace the previous phase difference θi-1100 with a corrected previous phase difference γi-1100. The corrected previous phase difference γi-1100 includes less noise than the previous phase difference θi-1100. The previous corrected phase difference γi-1100 is expressed as follows: γi-1100=ψi100+i-1100i=2,3... (5) The output yi100 of the quasi-coherent demodulator 100, which is the output of the phase sum adder 124 It is given by the following equation: yi100=θi-1100-γi-1100i=2, 3... (6) The phase sum adder 126 subtracts the delay decision i-1100 from the decision i100 to generate a decision D of the output (yi100). Decision D (yi100) is input to a look-up table (LUT) 128 to output the detection bits.

Calculations in the phase and complex domains increase the computational complexity. Phase-to-complex converters, complex-to-phase converters, integrators, etc. are required to perform the necessary additional calculations. In order to obtain enhanced MDPSK quasi-coherent demodulator 100 performance, additional calculations result in excessive power consumption and silicon area.

Summary of the invention

These and other shortcomings can be overcome by the embodiments of the present invention, which provide a phase domain quasi-coherent demodulator. The embodiments of the present invention do not require complete carrier frequency synchronization between the transmitter and receiver in the communication system. Embodiments of the present invention also reduce complexity by performing calculations in the phase domain instead of the complex number domain. The phase domain quasi-coherent demodulator includes a receiver for receiving at least one phase component of an input signal. The phase-domain quasi-coherent demodulator may include a decision unit for forming a decision based on a delayed reference signal and the phase component of the input signal. In addition, the phase domain quasi-coherent demodulator may include: a phase summation adder, which operates in modulo 2π addition, for subtracting the decision from the phase component of the input signal to form a rotating input phase; A phase summation adder is used to subtract the delayed reference signal from the rotating input phase to form a composite signal; a scaler is used to scale the composite signal to form an update signal. A third phase summation adder adds the update signal and the delayed reference signal to form a reference signal.

According to another aspect of the present invention, a method is for a quasi-coherent demodulator to calculate information in the phase domain. The method includes receiving at least one phase component of an input signal, and forming a decision value through a decision unit based on a delayed reference signal and the phase component of the input signal. The method may include subtracting the decision value from the phase component of the input signal to form a rotated input phase, and subtracting the delayed phase signal from the rotated input phase to form a composite signal. The composite signal can be scaled to form an update signal. The update signal can be added to the delayed signal to form a reference signal.

In another aspect, the present invention relates to an article for phase-domain quasi-coherent demodulation of input signals. The article of manufacture includes at least one computer-readable medium and processor instructions contained on the at least one computer-readable medium. The processor instructions are configured to be readable from the at least one computer-readable medium by at least one processor, thereby causing the at least one processor to operate to receive at least one phase component of an input signal, and by a decision unit based on A delayed reference signal and the phase component of the input signal form a decision value. The decision can be subtracted from the phase component of the input signal to form a rotated input phase. The delayed reference signal is subtracted from the rotated input phase to form a composite signal. The composite signal is scaled to form an update signal. The update signal and the delayed reference signal are added to form a reference signal.

Description of the drawings

Through the detailed description given below in conjunction with the accompanying drawings, further advantages and specific details of the present invention will become apparent.

Figure 1 is a schematic illustration of a known MDPSK quasi-coherent demodulator, which was partially explained above; Figure 2 is a block diagram of a phase-domain quasi-coherent demodulator according to the principles of the present invention; and Figure 3 is a phase-domain quasi-coherent demodulator; A flowchart of the method for calculating the reference phase in the domain.

detailed description

Quasi-coherent demodulators usually use the amplitude information of the input signal xi to perform calculations. It should be understood that various symbols used in specific implementations may relate to the signal itself or used to transmit a signal of an angle or other values.

The quasi-coherent demodulator can be implemented in hardware or software, and the hardware is, for example, an application specific integrated circuit (ASIC). The software can run on a digital signal processor (DSP) or other processor. The implementation of the quasi-coherent demodulator may depend on the design choices and/or constraints of the manufacturer or communication product. The quasi-coherent demodulator shown in FIG. 1 requires performing various phase-to-complex and complex-to-phase conversions, thereby increasing complexity. The quasi-coherent demodulator 100 may be implemented in the receiver part 10 of the wireless communication device 20.

Referring now to FIG. 2, a phase domain quasi-coherent demodulator 200 is illustrated. A phase summation adder 212 subtracts the decision φi200 from a decision unit 210 from the phase component θi200 of an input signal xi. In the phase domain quasi-coherent demodulator 200, the output of the phase sum adder 212, that is, a rotated input phase ξi200 is not converted into a complex signal. The rotated input phase ξi200 is instead input to a phase summation adder 230. The phase summation adder 230 subtracts a delayed reference phase ψi-1200 from the rotating input phase ξi200 to obtain a composite signal ζi200. Rewriting Equation 3 in the phase domain can get the following equation: ψi200=phase(ri)]]>ψi200=phase(α*ejψi-1+(1-α)*ej&xi ;i)]]>ψi200=phase(ejψi-1(α+(1-α)*ej(ξi-ψi-1)))---(7)]] >ψi200=ψi-1200+arctan((1-α)*sin(ζi)α+(1-α)*cos(ζi))]]>The simplification of Equation 7 shows that the reference phase ψi200 at time i can be obtained by adding an updated value θi200 and the delayed reference phase ψi-1200 without calculation in the complex domain. Therefore, complex calculations that require additional processing and larger silicon area and consume additional power are avoided.

The updated value θi200 is a random variable with 0 mean value. For M=2, 4, and 8, it is limited to the ranges [-π/2, π/2], [-π/4, π/4] and [ -π/8, π/8]. The updated value θi200 may be relatively small, thereby allowing simplification in the calculation of the updated value θi200. The simplification is based on the following formula:c1=1-α]]>with--c2=16α-12α2+13α3---(8)]]>c3=-1120α+18α2-512α3+12α4 -15α5]]> θi200 can be approximated by the first three terms of the series expansion shown in equation (8) . As shown in Equation 8, the coherence parameter α is determined for the specific system related to the phase domain quasi-coherent demodulator 200.

In order to further simplify the phase domain quasi-coherent demodulator 200, the third-order equation with coefficients c1, c2, and c3 can be reduced to a first-order equation without significant performance loss. This first-order approximation allows the use of a scaler 232 to scale the instantaneous error signal ζi200 with a coefficient c1. The output of the scaler 232 is the updated value θi200 as described in Equation 8. The phase summation adder 234 adds an updated value θi200 and the delayed reference phase ψi-1200 to output the reference phase ψi200. If the implementation of scaling can be simply compared to phase addition, then the extra addition can be eliminated at the cost of additional scaling operations. This can be seen by the following formula: c1*(ξi200-ψi-1200)+ψi-1200=c1*ξi200+(1-c1)*ψi-1200---(9) ]]> The reference phase ψi200 is delayed by a unit delay 218 to form a delayed reference phase ψi-1200. The delayed reference phase ψi-1200 is used in further calculations. The phase summation adder 220 subtracts the delayed reference phase ψi-1200 from the phase component θi200. The decision unit 210 and a phase summation adder 224 receive the output of the phase summation adder 220.

The decision unit 210 forms a decision i200, which is delayed by a unit delay 222 to form a delayed decision i-1200. The phase summation adder 224 subtracts the delay decision i-1200 from the output of the phase summation adder 220. The output of the phase summation adder 224 is the output yi200 of the phase domain quasi-coherent demodulator 200. In the phase summation adder 226, the delayed decision φi-1200 is subtracted from the decision φi200 to produce the output decision D(yi200). The decision D (yi200) is input to a look-up table (LUT) 228 to output detection bits.

FIG. 3 is a flowchart illustrating a method 300 of calculating a reference phase in the phase domain. The process 300 starts at step 302. In step 302, the delayed reference signal ψi-1200 is subtracted from the rotated input phase ξi200 to obtain an instantaneous error signal ζi200. In step 304, the instantaneous error signal ζi200 is scaled by the coefficient c1 to form an updated value θi200. In step 306, the updated value θi200 is added to the delayed reference signal ψi-1200 to form a reference phase ψi200. As described above, in order to obtain the output yi200 of the phase domain quasi-coherent demodulator 200 and generate the output decision D(yi200), the reference signal ψi200 can be used in various calculations and decisions.

Although the scaler 232 used to scale the instantaneous error signal ζi200 has been shown in the above description, various other scalers can be used in the present invention to form a higher-order approximation to obtain better results. . However, in order to obtain more accurate results, a compromise is needed in the increased complexity.

The embodiments of the present invention may be implemented in integrated circuits or chipsets, wireless systems, and receiver system products, for example. For example, a computer is operable to execute software suitable for performing the demodulation technique of the present invention. The demodulation software is adapted to reside on a computer readable medium, such as a disk in a disk drive unit. The computer-readable medium may also include flash memory cards, EEROM-based memory, bubble memory, ROM memory, and so on. The software suitable for performing the demodulation method can also reside completely or partially in a static or dynamic main memory or firmware in a processor (ie, in the memory of a microcontroller, microprocessor or microcomputer). The demodulation method can also be applied to the implementation in integrated circuits, field programmable gate arrays (FPGA), chipsets or application specific integrated circuits (ASIC), wireless systems and other communication system products.

Although the exemplary embodiments of the present invention have been described, it should be appreciated that the present invention may be changed in various ways without departing from the present invention. Since the present invention can be varied in many ways, it should be understood that the present invention should only be limited by the scope as required by the scope of the following claims.