Clock extraction circuit for use in a linearly expandable broadcast router

Clock extraction circuit used in linear scalable broadcast router

CROSS REFERENCE This application relates to U.S. Provisional Patent Application No. 60/390,346 filed on June 21, 2002.

This application also involves co-pending US patent applications with the following serial numbers: PCT/____ (agent case number IU010620), PCT/____ (agent case number IU020157), PCT/____ (agent case number IU020158), PCT/____ (Agent case number IU020159), PCT/____ (Agent case number IU020160), PCT/____ (Agent case number IU020161), PCT/____ (Agent case number IU020162), PCT/____ (Agent case number IU020252 ), PCT/____ (agent case number IU020253), PCT/____ (agent case number IU020255), and PCT/____ (agent case number IU020256), all of these applications are assigned to the assignee of this application, hereby The full text is quoted for reference.

Technical field

The present invention relates to a broadcast router, and more particularly, to a circuit for extracting selected time information from a serialized digital audio data stream passing through a decoder circuit of the broadcast router, and the circuit is used by various components in the broadcast router.

Background technique

Traditionally, broadcast routers have incorporated serial digital audio decoders for extracting digital audio data from serialized digital audio data streams. However, if timing information is present, this serial digital audio decoder extracts very little timing information from the digital audio data stream. For example, in the art, existing serial digital audio decoders that output some form of "recovered clock" are known. It will be quite useful if a serial digital audio decoder is configured to extract other types of timing information from the received serialized digital audio data stream. For example, consider that the time information extracted by the serial digital audio decoder from the received serialized digital audio data stream can be used by the serial digital audio decoder itself, for example, the co-pending US patent application serial number 10/____ (Attorney's case) No. IU020159) and previously incorporated herein by reference, or used by other components of the broadcast router. However, to date, no serial digital audio decoder has been configured to extract this type of information. Therefore, the object of the present invention is to provide a serial digital audio decoder capable of extracting timing information from a received serialized digital audio data stream.

Summary of the invention

The present invention aims to provide a method for extracting selected time information from a serialized AES digital audio data stream. The first transition indicating the first preamble of the serialized AES digital audio data stream is detected, and once the transition is detected, the time count is initialized. Subsequently, the second transition indicating the subsequent preamble of the serialized AES digital audio data is detected and the time counting is stopped. The time separating the first and second transitions is then determined. Then, the interval time separating the first and second transitions, preferably determined in the form of fast clock pulse counts, can be transmitted to the decoding logic circuit for use in decoding the serialized AES digital audio data stream. Alternatively, the interval time separating the first and second transitions, which is also preferably determined in the form of a fast clock pulse count, may be transmitted to the encoding logic circuit for use in encoding the serialized AES digital audio data stream.

In another embodiment, the present invention provides a broadcast router including a decoder circuit and a target component coupled to the decoder circuit. The decoder circuit receives the serialized AES digital audio data stream, and during decoding, the decoder circuit extracts time information from the serialized AES digital audio stream. The decoder circuit then forwards the extracted time information to the target component, where the target component uses the time information during the execution of at least one function of the target component. The decoder circuit itself can also use the extracted time information to decode the received serialized AES digital audio data stream.

Description of the drawings

Figure 1 is a block diagram of a fully redundant, linearly scalable broadcast router incorporating a bi-phase decoder constructed according to the principles of the present invention; Figure 2 is the fully redundant, linearly scalable broadcast router of Figure 1 Figure 3 is an extended block diagram of the AES input circuit of the first broadcast router component of Figure 2; Figure 4 is an extended block diagram of the AES two-phase decoder circuit of the AES input circuit of Figure 3; and FIG. 5 is a flowchart of a method by which the time extraction circuit of the AES two-phase decoder of FIG. 4 determines the number of fast clocks that separate the continuous preambles of the AES-3 serial digital audio data stream.

detailed description

Referring first to FIG. 1, the fully redundant, linearly scalable broadcast router 100 will now be described in more detail. As can now be seen, the fully redundant, linearly scalable broadcast router 100 includes multiple broadcast router components that are coupled to each other to form a larger fully redundant, linearly scalable broadcast router 100. Each broadcast router component is a separate router device including a first and a second router matrix, the second router matrix being the redundancy of the first router matrix. Therefore, each broadcast router has first and second routing engines for one of the first and second router matrices, and each of the routing engines receives the same input digital audio data stream on its input side and combines The same output digital audio data stream is placed on its output side. As disclosed here, each broadcast router component used to construct a fully redundant, linearly scalable broadcast router is a broadcast router with a size of N×M. However, it is entirely conceivable that the fully redundant, linearly scalable broadcast router 100 can be replaced by broadcast router components of different sizes.

As further disclosed herein, the fully redundant, linearly scalable broadcast router 100 is formed by coupling the first, second, third, and fourth broadcast router components 102, 104, 106, and 108 together. Of course, the fully redundant, linearly scalable broadcast router 100 currently disclosed is composed of 4 broadcast router components purely as an example. Therefore, it should be clearly recognized that various other numbers of broadcast router components can be utilized to form a fully redundant, linearly scalable broadcast router constructed in accordance with the principles of the present invention. When all connected in the manner disclosed here, the first, second, third, and fourth broadcast router components 102, 104, 106, and 108 that collectively form a fully redundant, linearly scalable broadcast router 100 can be stored together in such as On the common chassis shown in Figure 1, or, if desired, stored on a separate chassis. Although the broadcast router components 102, 104, 106, and 108 may have different sizes from each other as previously described, or, alternatively, may all have the same size of N×M, they have proven to be suitable for expectation here. One size of usage is 256×256. In addition, an appropriate configuration of the fully redundant, linearly scalable broadcast router 100 can couple 5 broadcast router components each having a size of 256×256, thereby generating a 1,280×1,280 broadcast router.

The first broadcast router component 102 is composed of a first router matrix 102a and a second (or "redundant") router matrix 102b for replacing the first router matrix 102a in the event of a failure of the first router matrix 102a. Similarly, each of the second, third, and fourth broadcast router components 104, 106, and 108 of the fully redundant, linearly scalable broadcast router 100 is composed of the first router matrices 104a, 106a, and 108a, respectively, and used in the first router matrix 104a, 106a, and 108a. When a router matrix 104a, 106a, and 108a fails, it is composed of a second (or "redundant") router matrix 104b, 106b, and 108b that replaces the first router matrix 104a, 106a, and 108a, respectively. Of course, the second router matrices 102b, 104b, 106b are used as backup redundancy matrices for the first router matrices 102a, 104a, 106a, and 108a, respectively, in the event that the first router matrices 102a, 104a, 106a, and 108a fail. The designation of and 108b is purely arbitrary, and it is completely conceivable that any one of the router matrix pairs located in the broadcast router component can be used as a backup for the other of the router matrix pairs located in the broadcast router component.

As can be further seen in FIG. 1, the first router matrix 102a of the first broadcast router component 102, the first router matrix 104a of the second broadcast router component 104, and the first router matrix 106a of the third broadcast router component 106 , And the first router matrix 108a of the fourth broadcast router component 108 are coupled together in the first arrangement of the router matrix following the fully connected topology. Similarly, the second router matrix 102b of the first broadcast router part 102, the second router matrix 104b of the second broadcast router part 104, the second router matrix 106b of the third broadcast router part 106, and the fourth broadcast router part 108 The second router matrix 108b is coupled together in a second arrangement that follows a fully connected topology like the first arrangement. In a fully connected topology, each router matrix of the router matrix arrangement is coupled with every other router matrix forming part of the router matrix arrangement through separate links.

Therefore, for the first arrangement of the router matrix, the first, second, and third bidirectional links 110, 112, and 114 connect the first router matrix 102a of the first broadcast router component 102 with the first router matrix 102a of the second broadcast router component 104, respectively. The router matrix 104a, the first router matrix 106a of the third broadcast router part 106, and the first router matrix 108a of the fourth broadcast router part 108 are coupled. In addition, the fourth and fifth bidirectional links 116 and 118 connect the first router matrix 104a of the second broadcast router component 104 with the first router matrix 106a of the third broadcast router component 106 and the fourth broadcast router component 108 respectively. A router matrix 108a is coupled. Finally, the sixth bidirectional link 120 couples the first router matrix 106a of the third broadcast router component 106 with the first router matrix 108a of the fourth broadcast router component 108.

Similarly, for the second arrangement of the router matrix, the first, second, and third bidirectional links 122, 124, and 126 connect the second router matrix 102b of the first broadcast router component 102 with the second router matrix 102b of the second broadcast router component 104, respectively. The second router matrix 104b, the second router matrix 106b of the third broadcast router component 106, and the second router matrix 108b of the fourth broadcast router component 108 are coupled. In addition, the fourth and fifth bidirectional links 128 and 130 connect the second router matrix 104b of the second broadcast router component 104 with the second router matrix 106b of the third broadcast router component 106 and the second router matrix 106b of the fourth broadcast router component 108, respectively. The two router matrix 108b are coupled. Finally, the sixth bidirectional link 132 couples the second router matrix 106b of the third broadcast router component 106 with the second router matrix 108b of the fourth broadcast router component 108. Alternatively, the bidirectional links 110 to 120 may be formed by copper wire, optical fiber, or another transmission medium deemed suitable for digital signal exchange. Of course, in addition to the single two-way link between the pair of broadcast router components shown in FIG. 1, in an alternative embodiment of the present invention, it is envisaged that the pair of broadcast router components may be replaced by the first and second unidirectional links. coupling. This alternative configuration is shown in Figure 2.

The broadcast router components 102, 104, 106, and 108 will now be described in more detail. FIG. 2 shows the first broadcast router component 102. On the other hand, the second, third, and fourth broadcast router parts 104, 106, and 108 are configured similarly to the first broadcast router part 102, and there is no need to describe them in more detail. Of course, it should be clearly understood that in order to simplify the description, some parts of the previous description about the first broadcast router component 102 and the second, third, and fourth broadcast router components 104, 106, and 108 have been simplified. Note, however, that further details can be found by referring to the co-pending U.S. Patent Application Serial No. 10/____ (Attorney Docket No. IU020160) previously incorporated herein by reference.

As can be seen in FIG. 2, the broadcast router 102 includes N selectors 138-1 to 138-N, which are arranged such that the output of each selector provides one of the N transport streams. To the input side of each of the router matrices 102a, 102b of the first broadcast router part 102. As disclosed herein, each of the selectors 138-1 to 138-N is a first 2:1 selector circuit having a structure constructed by the Audio Engineering Society ("AES") input circuits 140-1 to 140-N, respectively As the first input to the first transport stream; and the second one constructed from the decoded digital audio data stream conforming to the MADI standard by the multi-channel digital audio ("MADI") input circuits 142-1 to 142-N, respectively Transport stream as the second input to it. Each of the first selector circuits 138-1 to 138-N also includes a control input (not shown) for selecting between two transport streams.

The selected transport stream output of each of the first selector circuits 138-1 to 138-N is supplied to the input side of the routing engine 144 of the first router matrix 102a, the transmission (or "TX") expansion port 276, and the A receiving (or "RX) expansion port 278, a second receiving expansion port 280, and a third receiving expansion port 282. The intention is to use the term "transmit" expansion port to indicate the expansion port from which data is transmitted to the selected destination. Similarly, the intention is to use the term "receive" expansion port to indicate the expansion port that receives data from the destination. Broadly speaking, the transmission expansion port 276 of the first router matrix 102a includes a memory subsystem, and the transport streams received from the first selector circuits 138-1 to 138-N of the first broadcast router component 102 are transmitted to multiple destinations. And the processor subsystem for controlling the transmission of the transport streams received from the first selector circuits 138-1 to 138-N to the first router matrix 104a and the third router of the second broadcast router component 104 The reception expansion ports of the first router matrix 106a of the broadcast router component 106 and the first router matrix 108a of the fourth broadcast router component 108. In contrast, broadly speaking, each of the first, second, and third expansion ports 278, 280, and 282 of the first router matrix 102a includes a memory subsystem, and the transmission of the first router matrix from another broadcast router component The input transport stream received by the expansion port can be buffered in it before being transmitted to its final destination; and the processor subsystem for controlling the input transmission flow received from the transmission expansion port of the first router matrix of another broadcast router component To the input of the routing engine 144 of the first router matrix 102a of the first broadcast router component 102.

The transport stream 1 to N containing the information extracted from the AES input terminal 1-32N and/or the MADI input terminal 1-N is transmitted from the first selector circuit 138-1 to 138-N to the routing engine 144 and the transmission expansion port 276 . The input transport streams 1 to N are forwarded from the transmission expansion port 276 to the first router matrix 104a of the second broadcast router component 104 through the link 110, and are forwarded to the first router matrix 106a of the third broadcast router component 106 through the link 112. And the first router matrix 108a forwarded to the fourth broadcast router component 108 through the link 114. In reply, the input transport streams N+1 to 2N are transmitted from the transmission expansion port of the first router matrix 104a of the second broadcast router component 104 to the first reception expansion port 278 via the link 110; and the input transmission streams 2N+1 to 3N is transmitted from the transmission expansion port of the first router matrix 106a of the third broadcast router component 106 to the second reception expansion port 280 through the link 112; and the input transport streams 3N+1 to 4N are transmitted from the fourth broadcast router through the link 114 The transmission expansion port of the first router matrix 108a of the component 108 transmits to the third reception expansion port 282. Finally, the first, second, and third receiving expansion ports 278, 280, and 282 respectively input the input transport streams N+1 to 2N, 2N+1 to 3N, and 3N+1 to 4N to the routing engine 144.

As mentioned above, the first and second router matrices 102a and 102b are redundant matrices of each other. In order to work in this way, the routing engine 152 of the second router matrix 102b must have the same set of input transport streams as the routing engine 144. Therefore, in a manner similar to that described above, the selected transport stream output of each of the first selector circuits 138-1 to 138-N is also supplied to the input side of the routing engine 152 and the transmission port 284. Similarly, the transport streams supplied to the first reception expansion port 278, the second reception expansion port 290, and the third reception expansion port 282 are also supplied to the first reception expansion port 286 and the second reception expansion port 286 of the second router matrix 102b, respectively. Expansion port 288 and third receiving expansion port 290. Broadly speaking, the transmission expansion port 284 of the second router matrix 102b includes a memory subsystem, and the transport streams received from the first selector circuits 138-1 to 138-N of the first broadcast router component 102 are transmitted to multiple destinations. And the processor subsystem for controlling the transmission of the transport streams received from the first selector circuits 138-1 to 138-N to the second router matrix 104b of the second broadcast router component 104, and the third The second router matrix 106b of the broadcast router component 106 and the second router matrix 108b of the fourth broadcast router component 108. In contrast, broadly speaking, each of the first, second, and third expansion ports 286, 288, and 290 of the second router matrix 102b includes a memory subsystem, and the transmission of the first router matrix from another broadcast router component The transport stream received by the expansion port can be buffered in it before being transmitted to its final destination; and a processor subsystem for controlling the transmission of the transport stream received from the transmission expansion port of the first router matrix of another broadcast router component to The input terminal of the routing engine 152 of the second router matrix 102b of the first broadcast router component 102.

The input transport streams 1 to N are transferred from the first selector circuits 138-1 to 138-N to the routing engine 152 and the transfer expansion port 284. The input transport streams 1 to N are forwarded from the transmission expansion port 284 to the second router matrix 104b of the second broadcast router component 104 through the link 122, and are forwarded to the second router matrix 106b of the third broadcast router component 106 through the link 124, And the second router matrix 108b forwarded to the fourth broadcast router component 108 through the link 126. In reply, the input transport streams N+1 to 2N are transmitted from the transmission expansion port of the second router matrix 104b of the second broadcast router component 104 to the third reception expansion port 290 via the link 122; the input transport streams 2N+1 are transmitted to 3N is transmitted from the transmission expansion port of the second router matrix 106b of the third broadcast router component 106 to the second reception expansion port 288 through the link 124; and the input transport stream 3N+1 to 4N is transmitted from the fourth broadcast router through the link 126 The transmission expansion port of the second router matrix 108b of the component 108 transmits to the first reception expansion port 288. From the third, second, and first receiving expansion ports 290, 288, and 286, the input transport streams N+1 to 2N, 2N+1 to 3N, and 3N+1 to 4N are respectively extended by the third, second, and first reception Ports 290, 288, and 286 are transmitted to the routing engine 154.

The routing engine 144 of the first router matrix 102a includes a switching device for distributing any of the 4N AES streams received as input to the routing engine 144 to any one of the M output lines of the routing engine 144. It can vary, considering that the routing engine 144 can be implemented by software (for example, a series of instructions), hardware (for example, a series of logic circuits), or a combination thereof. Similarly, the routing engine 152 of the second router matrix 102b is equipped with a switching device for distributing any of the 4N AES streams received as input to the routing engine 152 to one of the M output lines of the routing engine 152 Any one. Consider again that the routing engine 152 can be implemented differently by software, hardware or a combination thereof. Each of the 1 to M AES stream outputs of the routing engines 144 and 152 of the first and second routing matrices 102a and 102b of the first broadcast router part 102 are delivered to the second selector circuits 160-1 to 160- The corresponding one in M. The second selector circuits 160-1 to 160-M collectively determine whether the 1 to M AES stream outputs of the routing engine 144 of the first routing matrix 102a or the 1 to M AES stream outputs of the routing engine 152 of the second routing matrix 102b should be This is the output of the first broadcast router component 102. Each of the second selector circuits 160-1 to 160-M shares a common control input terminal (not shown), which is used to select whether the AES stream output of the routing engine 144 or the AES stream output of the routing engine 152 should pass through the first Two selector circuits 160-1 to 160-M pass.

The selected AES stream is sent from the second selector circuits 160-1 to 160-M to the corresponding one of the information reproduction circuits 162-1 to 162-M. In reply, the information reproduction circuits 162-1 to 162-M pass the received AES stream to the AES output circuits 164-1 to 164-M or MADI output circuits 166-1 to 166-M for encoding, and from the first The broadcast router part 102 outputs the AES stream. Similarly, if the received information streams are MADI streams, they can also be passed to the AES output circuits 164-1 to 164-M or MADI output circuits 166-1 to 166-M for encoding, and from the first broadcast The router part 102 outputs these MADI streams.

3, the AES input circuits 140-1 to 140-N will now be described in more detail. FIG. 3 shows the AES input circuit 140-1. The remaining AES input circuits, specifically, the configurations of the AES input circuits 140-2 to 140-N are similar to the AES input circuit 140-1, and do not need to be described in more detail. As can now be seen, the AES input circuit 140-1 includes AES two-phase decoder circuits 296-1 to 296-32 and a transport stream multiplexer 295. The input to each of the AES two-phase decoder circuits 296-1 to 296-32 is a respective input digital audio data stream that follows the AES-3 standard and is generated at a signal source (not shown). As will be described more fully below, the AES two-phase decoder circuits 296-1 to 296-32 decode each input digital audio data stream input thereto. The 32 decoded input digital audio data streams generated by the AES two-phase decoder circuits 296-1 to 296-32 are input to the transport stream multiplexer 295, and the transport stream multiplexer 295 decodes from 32 The input digital audio data stream constructs the input transport stream which is passed to the selector circuit 138-1.

The AES two-phase decoder circuits 296-1 to 296-32 will now be described in more detail. FIG. 4 shows the AES two-phase decoder circuit 296-1. The remaining AES two-phase decoder circuits, specifically, the configuration of the AES two-phase decoder circuits 296-2 to 296-32 is similar to the AES two-phase decoder circuit 296-1, and there is no need to describe them in more detail. description. As will be described more fully below, the AES two-phase decoder circuit 296-1 operates by using a fast clock to sample the input data stream, which here is the AES serialized digital audio data stream. In order to decode the AES serialized digital audio data stream, the AES two-phase decoder circuit 296-1 also needs an estimated bit time. As used herein, the term "fast clock" refers to a clock having a frequency that is at least 20 times faster than the frequency of the input AES digital audio data stream. On the other hand, the term "bit time" refers to the number of fast clocks that will occur during the input of a typical bit of the AES digital audio data stream. As disclosed herein, consider that the AES two-phase decoder circuit 296-1 can operate in two modes. In the first mode, the user selects the bit time for direct input to the logic circuit 298, while in the second mode, the bit time is automatically generated from the input serialized digital audio data stream.

As can be seen in FIG. 4, the AES two-phase decoder circuit 296-1 includes a time extraction circuit 297, a decoding logic circuit 298, a bit time estimator 300, and an appropriate size data storage, such as a 32-bit wide asynchronous first-in-first Out ("FIFO") memory 302. The AES two-phase decoder circuit 296-1 receives the serialized digital audio data stream from the AES input 140-1. Within the AES two-phase decoder circuit 296-1, the AES serialized digital audio data stream is then sent to each of the time extraction circuit 297, the decoding logic circuit 298, and the bit time estimator 300. The time extraction circuit 297 extracts specific time information, specifically, the number of fast clocks that separate continuous preambles from the second serialized digital audio data stream. The time extraction circuit 297 then passes the extracted time information to the decoding logic circuit 298 for decoding the AES serialized digital audio data stream. In addition to passing the extracted time information to the decoding logic circuit 298, the time extraction circuit 297 also outputs the extracted time information to the target part 400 of the broadcast router 100 (since it is not part of the AES two-phase decoder circuit 296-1, Therefore, it is shown as a dashed frame in Figure 4). Here, depending on the specific function of the target component 400, it is considered that the extraction time information extracted by the time extraction circuit of the AES two-phase decoder circuit 296-1 can be used for various purposes. For example, consider that the extracted time information can be used when encoding a serialized AES digital audio data stream. In such an example, for example, an encoding logic circuit that can form a part of the AES output circuit 164-1 will be used as the target part 400. Of course, the encoding logic circuit is only an example of a target component of the broadcast router 100 that can use the extracted time information to perform various functions. In addition, it is considered that the extracted time information may be forwarded to a plurality of target components, and each of the plurality of target components will use the extracted time information during the execution of various functions. Finally, consider that the extracted time information can also be used by the AES two-phase decoder circuit 296-1 itself to decode the received AES serialized digital audio data stream.

Further details on the operation of the decoding logic circuit 298 are described in more detail in the previously incorporated co-pending U.S. Patent Application Serial No. 10/____ (Attorney Docket No. IU020259). As described more fully therein, the decoding logic circuit 298 is configured to identify "Type X" preambles, "Type Y" preambles, and "Type Z" preambles in the AES serialized digital audio data stream. , Logic 1 and logic 0. After the preamble is recognized and it is determined that the recognized preamble is the "X" preamble, the "Y" preamble or the "Z" preamble, the decoding logic circuit 298 transmits the recognized preamble to the FIFO The memory 302, as disclosed herein, the FIFO memory 302 is a 32-bit wide register.

Once the digital audio data is extracted from the received AES serialized digital audio data stream, the decoding logic circuit 298 places the first such decoded preamble, typically a "Z" type preamble, in FIFO memory 302 in bits 31-28. If the decoding logic circuit 298 subsequently recognizes a logic "1" or a logic "0" in the AES serialized digital audio data stream, the decoding logic circuit 298 transfers the decoded data bits to the bit 31 of the FIFO memory 302, and the This moves the first decoded preamble to bits 30-27 of the FIFO memory 302. In this way, the decoding logic circuit 298 successively decodes each bit of data in the received serialized AES digital audio data stream, and recognizes each such bit as a logical "1", a logical "0" or a previous Part of the synchronization code. As each data bit is successfully identified, each data bit is transferred to bit 31 of the FIFO 302, thereby gradually filling the FIFO 302 with the first 32-bit subframe of AES digital data. However, as soon as another preamble is subsequently identified, the decoding logic circuit 298 will conclude that the decoding of the next 32-bit subframe of the AES digital data has already started. Therefore, the existing content of the FIFO 302 is clocked into the selector circuit 138-1, and the newly recognized preamble is placed in the FIFO In bits 31-28 of 302, the next 32-bit subframe of AES digital data is thus started to fill the FIFO 302.

Next, referring to FIG. 5, the method for the time extraction circuit 297 to extract specific time information from the AES serialized digital audio data stream, specifically, the number of fast clocks separating consecutive preambles will now be described in more detail. The method starts at step 350, and at step 352, the AES serialized digital audio data stream from which the aforementioned time information is to be extracted is input to the time extraction circuit 297. Proceed to step 353, the transition count "T" is set to 0, and the time extraction circuit 297 starts to check transitions on the input AES serialized digital audio data stream. In step 354, the time extraction circuit 297 detects the first transition in the input AES serialized digital audio data stream, and assumes that the detected transition indicates the beginning of the first preamble. The method then proceeds to step 355, where the time extraction circuit 297 starts to count the number of fast clock pulses between the preamble detected in the input AES serialized digital audio data stream and the subsequent preamble. To do this, the method will first proceed to step 356, where the transition count T is incremented by one.

Proceeding to step 357, the time extraction circuit 297 then compares the transition count T with 33, which is the number of transitions that occur between successive preambles of the AES-3 serialized digital audio data stream. If it is determined in step 357 that the transition count T is less than 33, the time extraction circuit 297 concludes that the subsequent preamble has not been detected yet. The method then proceeds to step 358, where counting of fast clock pulses continues. Proceeding to step 359, the time extraction circuit 297 continues to check subsequent transitions on the input AES-3 serialized digital audio data stream. Once the subsequent transition is detected, the time extraction circuit 297 again determines whether the detected transition indicates the beginning of the subsequent preamble in the input AES-3 serialized digital audio data stream. To this end, the method returns to step 356, where the time extraction circuit 297 will again determine whether the subsequent detected transition indicates the input of AES-3 serialized digital audio data in the manner previously described regarding the first detected transition. Subsequent preamble in the stream.

Now returning to step 357, if the transition count T is equal to 33, the method proceeds to step 360, where the time extraction circuit 297 concludes that the detected transition indicates the beginning of the subsequent preamble in the input AES-3 serialized digital audio data stream . The method will then proceed to step 362, where the time extraction circuit 297 transmits the fast clock pulse count to the decoding logic circuit 298 for use in the co-pending US patent application serial number 10/____ (Agent The method described in the case number IU020259) is used in the decoding of the AES-3 serialized digital audio data stream. Proceeding to step 364, the time extraction circuit 297 determines whether there is additional AES serialized digital audio data to be analyzed. If there is additional data to be analyzed, the method proceeds to step 366 for resetting the fast clock pulse count. The method will then return to step 353 for further analysis of the input AES serialized digital audio data stream in the aforementioned manner. However, if it is determined at step 364 that there is no additional AES serialized digital audio data to be analyzed, the method will instead end at 368.

Therefore, a method for extracting selected time information from a serialized digital audio data stream passing through a broadcast router has been disclosed and illustrated here for use by various components of the router. Of course, although the preferred embodiments of the present invention have been shown and described herein, those skilled in the art to which the present invention belongs can make various modifications and other transformations without departing from the essence or principle of the present invention. Therefore, the scope of protection is not limited to the embodiments described herein, but only by the appended claims.