Offset calibration system

Offset calibration system

Technical field

The present invention relates to an offset calibration system for an integrated analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) with a full scale range that is not related to a power of 2.

Background technique

Analog-to-digital converters (ADCs) usually have significant offset errors. That is, for 0 inputs, there will be no 0 outputs. The difference is the offset. In order to compensate for the offset, the offset can be determined by introducing 0 input to the ADC, and then the offset is subtracted from the ADC output during normal operation to eliminate the error, thereby calibrating the ADC.

Digital-to-analog converters (ADCs) usually also have significant offset errors. When used in a circuit with a calibrated ADC, the DAC can be calibrated to compensate for its offset. The input of the DAC is set to 0; its analog output represents the offset error and is fed to the input of the ADC. Thus, the output of the calibrated ADC represents the offset error of the DAC. During normal operation, the DAC offset measured with the ADC is subtracted from the input code. This solution has worked well. However, when the least significant bit (LSB) of the ADC and the DAC do not correspond to the same voltage, the offset error of the DAC measured with the ADC must be adjusted by the LSB voltage ratio in order to obtain the correct DAC offset correction. When the full scale range of the ADC and DAC is equal to or related to a power of 2, the adjustment can be performed by shifting the ADC output (in binary numbers) left or right. Shifting the ADC output to the left is equivalent to multiplying the value by a power of 2. Shifting the ADC output to the right is equivalent to dividing the value by a power of 2. When the full-scale range is not related to the power of 2, the adjustment can be done through multiplication and division. However, the multiplication and division of numbers that are not powers of 2 requires considerable digital circuits.

Summary of the invention

Therefore, the object of the present invention is to provide an improved offset calibration system.

The object of the present invention is also to provide such an improved offset calibration system for analog-to-digital converters and digital-to-analog converters having a full-scale range that is not related to the power of two.

The object of the present invention is also to provide such an improved offset calibration system, which adapts to different ranges without using division by a number that is not a power of 2.

The object of the present invention is also to provide such an improved offset calibration system, which adapts to different ranges without using multiplication of numbers that are not powers of two.

The object of the present invention is also to provide such an improved offset calibration system, which mainly uses circuits required for ordinary operations, such as accumulators for decimators of delta-sigma ADCs. , Complete its calibration function.

The present invention is derived from the recognition that by accumulating a predetermined number of offset-compensated analog-to-digital output values, and dividing them by the ratio of the ADC LSB voltage to the DAC LSB voltage by a preselected power of 2, it is possible to obtain Avoid multiplying or dividing by numbers that are not powers of 2, a simple and effective offset calibration system for integrated analog-to-digital converters and digital-to-analog converters with different ranges.

The present invention provides an offset calibration system, including an analog-to-digital converter with a first full-scale range, the analog-to-digital converter having a first offset compensation circuit; and a digital-to-analog converter with a second full-scale range , The digital-to-analog converter has a second offset compensation circuit. During calibration of the digital-to-analog converter, the digital-to-analog converter connects its output to the input of the analog-to-digital converter. The range adjustment circuit accumulates a predetermined number of analog-to-digital output values, and divides the accumulated value by the ratio of the voltage corresponding to the least significant bit voltage of the analog-to-digital converter to the voltage corresponding to the least significant bit voltage of the digital-to-analog converter Power of 2 to choose.

In a preferred embodiment, the range adjustment circuit may include an accumulator circuit for accumulating a predetermined number of modulus output values. The accumulator circuit may include a control circuit to determine the number of modulo output values to be accumulated. The accumulator circuit may include a register and a device for selecting a stage of the register, the stage representing the quotient obtained by dividing the accumulated value by a pre-selected power of two. The analog-to-digital converter can be calibrated before the digital-to-analog converter is calibrated. During normal operation, the accumulator circuit can operate as a digital filter.

Description of the drawings

For those skilled in the art, other objectives, features and advantages of the present invention can be found from the following description of the preferred embodiments and the accompanying drawings, in which: FIG. 1 is a schematic block diagram of the offset calibration system according to the present invention; 2, 3, and 4 are views similar to FIG. 1, respectively showing the signal paths used for analog-to-digital converter calibration, for digital-to-analog converter calibration, and for normal operation; and FIG. 5 is according to the present invention A schematic diagram of a configuration of the range adjustment circuit of FIG. 1.

Detailed ways

FIG. 1 shows an offset calibration system 10 according to the present invention, which is used to calibrate the digital-to-analog conversion when the full-scale range of the digital-to-analog converter (ADC) and the analog-to-digital converter (DAC) are not related to the power of two. DAC (DAC) 12 and analog-to-digital converter (ADC) 14. The multiplexer 16 provides the input of the ADC 14. The input of the ADC 14 can be selected from the output 17 of the DAC 12, the normal analog input 20, or the 0 input 22 (used for offset calibration). The output terminal of the ADC 14 is the ADC offset compensation circuit 24, which includes an adder 26, and the adder 26 receives the output from the ADC 14 and the output from the multiplexer 28. The register 30 is used to store the ADC offset determined by the offset compensation circuit 24. The register 30 provides the ADC offset to one input of the multiplexer 28; the other input 29 of the multiplexer 28 is a 0 code for the calibration mode. The range adjustment circuit 32 according to the present invention is interconnected between the digital output of the adder 26 and the input of the DAC offset compensation circuit 34 associated with the DAC 12. The offset compensation circuit 34 also includes an adder 36 and a register 38 for storing the DAC offset. The adder 36 receives one input from the register 38, the other input of which is a digital input on line 35. The adder 36 provides one input to the multiplexer 40; the other input of the multiplexer 40 is the 0 input for calibration. The output of the multiplexer 40 is sent to the input terminal of the DAC 12.

Before the normal operation starts and before the DAC calibration, as shown in FIG. 2, the ADC 14 is calibrated by providing 0 input from the line 22 to its differential input terminal. At the output terminal of the ADC 14, any signal that is not 0 is fed to the range adjustment circuit 32 through the adder 26. Select the 0 input to the multiplexer 28 on the line 29 so that 0 is input to the negative input of the adder 26. Thus, the output of the adder 26 represents the offset of the ADC. The output of the adder 26 is sent to the offset compensation circuit 24 through the range adjustment circuit 32. The value stored in the ADC offset register 30 is the offset error generated by the ADC 14. During normal operation, the value stored in the ADC offset register 30 will be introduced into the adder 26 through the multiplexer 28, and in the adder 26, this value will be subtracted from the output of the ADC 14 to eliminate the offset error. During the ADC calibration in Figure 2, the DAC circuit is not activated.

During the calibration of the DAC 12 in FIG. 3, the 0 input of the multiplexer 40 on the line 42 is sent to the DAC 12. The output of the DAC 12 (which is ideally 0, but usually has some offset error value) is sent to the input terminal of the ADC 14 through the multiplexer 16 on the line 18. Now by subtracting the value in the ADC offset register 30 that is sent to the adder 26 through the multiplexer 28, the output of the ADC 14 is offset. The output 27 is sent to the offset compensation circuit 34 of the DAC 12 through the range adjustment circuit 32. Here, regardless of whether any offset occurs, it will be stored in the DAC offset register 38 and will be provided to the adder 36 in the future to subtract this value from the digital input to compensate for the offset of the DAC 12.

In the normal operation shown in FIG. 4, the analog input to the multiplexer 16 on the line 20 is sent to the ADC 14. The output from the ADC 14 is compensated by the offset compensation circuit 24. This is achieved by the ADC offset stored in the register 30 through the multiplexer 28 to the adder 26, where the ADC offset is subtracted from the output of the ADC 14 to eliminate the ADC offset error. For the digital input 35 provided to the offset compensation circuit 34, the adder 36 subtracts the DAC offset stored in the register 38 from the digital input signal on the line 35, and compares the signal sent to the DAC 12 through the multiplexer 40 Pre-correction is provided, so the offset error of the DAC is compensated, and the output on line 17 has no offset error.

According to the present invention, the use range adjustment circuit 32 introduces necessary factors so that even if the DAC 12 and the ADC 14 have a full-scale range that is not related to the power of two, the offset compensation can be accurately completed.

The range adjustment circuit 32 is shown in more detail in FIG. 5, which includes an accumulator 48 having an accumulator register 50 and an adder 52. In normal operation, the accumulator 48 and the accumulator register 50 function as filters. The control circuit 54 determines how much output value from the ADC 14 will be accumulated in the register 50. The output lines 70 and 72 are means for selecting the stage of the register, the stage representing the quotient obtained by dividing the accumulated value by a preselected power of two. For example, if the DAC 12 has an output range of ±1 volt and the ADC 14 has a range of ±1.2 volts, obviously, the two ranges do not match, which will affect the accuracy of the DAC offset error compensation. Therefore, in order to adjust this without using explicit multiplication or division with numbers that are not related to powers of 2, several successive output values from ADC 14 will be accumulated in register 50 by using adder 52, Among them, the adder 52 receives on the line 27 from the ADC through the adder 26 14 input, and input from register 50 on line 56. The number of values to be accumulated is designated as M. In this example, M=ADCrange/2ADACrange/2D(2n)----(1)]]> Among them, ADCrange is the full-scale range of ADC, A is the resolution (number of bits) of ADC, and DACrange is DAC Full-scale range, D is the resolution (number of bits) of the DAC, and 2n represents a power of 2 pre-selected for ease of use.

Therefore, for an 8-bit ADC, an 8-bit DAC, and n=4M=1.2volts/1281.0volts/128*(16)=19.2----(2)]]> round 19.2 to 19, you need to enter the register The number of output values from ADC 14 accumulated in 50 is 19. By increasing the number of accumulated values, the accuracy can be improved. But this will introduce a delay in accumulating additional value. During ADC offset calibration, 16 values are accumulated in register 50, which is a 12-bit register. Ignore bits 0 to 3, and bits 4 to 11 represent the ADC offset. When performing ADC offset calibration, 19 values are accumulated in register 50. Bits 0 to 3 are ignored, and bits 4 to 11 represent the DAC offset. The full scale range is compensated by the accumulation period, that is, the difference between 19 and 16, that is, the difference between 1.2 volts and 1 volt. The ratio of the ADC range to the DAC range is approximately equal to or can be almost exactly equal to the ratio of the accumulated number M of the ADC to the number represented by 2n. The control circuit 54 determines the number of output values accumulated in the register 50. In this example, the ADC period is specified as 16, and the DAC period is specified as 19.

ADC 14 is a delta-sigma ADC, which includes a modulator and a digital filter. The realization of the digital filter requires an accumulator. The circuit used to implement the accumulator for the digital filter is also used to implement the range adjustment circuit.

Although specific features of the present invention have been shown in some drawings, they are not shown in other drawings for convenience only. According to the present invention, each feature can be combined with any or all other features. . The words "including", "including", "having" and "with" used herein should be interpreted and understood in a broad sense and are not limited to any physical interconnection. In addition, any embodiments disclosed in the application are not considered to be all possible embodiments.

Those skilled in the art will think of other embodiments, which are within the scope of the following claims: