Digitized automatic gain control system and methods for a controlled gain receiver

Digital automatic gain control system and method for controlled gain receiver

This application relates to an application for "a method and device for determining stored gain in response to a controlled gain receiver", its agent volume number is PT03355U, and it relates to an application for "square circuit and electronic equipment using it". The agent volume number is PT03211U, these two applications were submitted on the same day as this application, and both Hughes et al. were the inventors.

FIELD OF THE INVENTION The present invention relates to wireless automatic gain control circuits (AGC), and more particularly to digital AGC circuits.

BACKGROUND OF THE INVENTION Many conventional narrow-band zero-intermediate frequency (ZIF) receivers have a slow AGC loop setup time, such as on the order of 6-10 milliseconds, and a very narrow dynamic range of, for example, 85 decibels (dB). These characteristics result in lower than desired performance in attenuation conditions, which are found in mobile and portable wireless communication systems such as paging, personal communication systems, and cellular communication systems. Moreover, the inaccurate gain control provided by the prior art AGC increases the difficulty of reducing the DC offset, which reduces the signal performance. What is needed is a low-cost, low-power AGC that is fast, has a dynamic range of more than 110 dB, and provides precise gain control.

Description of the drawings

Fig. 1 is an electrical block diagram showing part of an automatic incremental control (AGC) system of a ZIF receiver according to a preferred embodiment of the present invention.

FIG. 2 is a flowchart showing the heating mode operation of the AGC system according to the preferred embodiment of the present invention.

Fig. 3 is a mapping table of a set of registers that maintains the stored gain response used in the AGC system according to the preferred embodiment of the present invention.

Fig. 4 is a flowchart showing a tracking mode according to a preferred embodiment of the present invention.

Fig. 5 is an electrical block diagram showing an AGC filter in an AGC system according to a preferred embodiment of the present invention.

Figures 6, 7, 8 and 9 are timing diagrams according to preferred embodiments of the present invention, which show the reset and accumulated duration (as part of the marked MEASURE signal), and the update of the gain value relative to the 6400 baud symbol ( write).

FIG. 10 is an electrical block diagram showing the RSSI function of the AGC system according to the preferred embodiment of the present invention.

FIG. 11 is an electrical block diagram showing a wireless device including an AGC system according to a preferred embodiment of the present invention.

FIG. 12 is an electrical block diagram showing a test setup for determining a stored gain response for a wireless device according to a preferred embodiment of the present invention.

FIG. 13 is a graph showing a graph of gain-gain control value of a typical low noise amplifier used in an AGC system according to a preferred embodiment of the present invention.

FIG. 14 is a flowchart illustrating a method for determining a stored gain response of an AGC system according to a preferred embodiment of the present invention.

Fig. 15 is an electrical block diagram showing a squaring circuit used in an AGC system according to a preferred embodiment.

detailed description

Although the description ends with the claims defining the features of the present invention considered to be novel, it is believed that the present invention can be better understood by considering the following detailed description in conjunction with the accompanying drawings, in which the same reference numerals are always used.

Description of the AGC system Referring to Fig. 1, an electrical block diagram shows a part of an automatic gain control (AGC) system 100 of a ZIF receiver according to a preferred embodiment of the present invention. The AGC system 100 is part of the AGC receiver 1101 (see FIG. 11) of the wireless device (FIG. 11), and includes a radio frequency (RF) front end 110 that uses an antenna 112 to intercept RF signals. The AGC receiver 1101 is a zero IF receiver of the preferred embodiment of the present invention, which attenuates the intercepted signal 113 in the step attenuator 114 according to the attenuator control signal 189, amplifies the RF signal in the low noise amplifier (LNA) 116, and The amplified RF signals located in the two mixers 118, 120 are converted into an unfiltered in-phase (I) signal 119 and a quadrature-phase (Q) unfiltered signal 121. The LNA 116 is controlled by a gain control signal 195, which is transmitted to the LAN 116 as an analog signal. The embodiments of the present invention introduced and claimed herein are optimized for wireless devices used in communication systems with a synchronous signaling protocol that has been well defined as consisting of normal data parts and preceding it Signaling cycle (signaling cycle), the signaling cycle is used in such as paging and cellular wireless systems. The header portion has a predetermined duration, the predetermined duration includes synchronization patterns such as included in symbols, words, frame start, and bit rate patterns, but the aspects of the present invention can also be applied to other similar patterns. ZIF wireless receivers and conversion receivers (for example, single and double conversion receivers) used in defined cyclic communication systems. An example of such a synchronous communication system used here is the well-known FLEXTM signaling protocol, in which cycles are called frames. The unfiltered I and Q signals 119, 121 are coupled to the back end 130 of the AGC receiver 1101 (FIG. 11). The back end 130 uses the paired sigma-delta converters 132, 134 to sample the unfiltered I and Q signals 119, 121. Then, the sampled I and Q signals are decimated and filtered by a pair of decimation functions 136, 138. In the DC offset precise control function 140, 142, the decimated I and Q signals are subjected to DC offset correction and filtered by baseband filters (BBF) 144, 146. The filtered I signal 145 and the filtered Q signal 147 generated by the DC offset precision control functions 140, 142 are coupled to other parts of the back end 130 and coupled to the controller function of the wireless device 1100 (see FIG. 11) 1105, in which the information in the wireless signal is decoded and processed in a conventional manner, and the symbol clock 185 is synchronized with the symbol of the protocol that transmits the information (also referred to as the protocol symbol).

The filtered I and Q signals 145, 147 generated by the BBF 144, 146 are also connected to the input terminals of the two squaring functions 148, 150 of the amplitude generator 160. The amplitude generator 160 also includes the squaring function 148, The output of 150 is added with the adder function 152. The output signal 154 of the adder function 152 is also the output signal 154 of the amplitude generator 160, and is called a binary voltage squared signal, and is connected to the AGC filter 162. The output of the AGC filter 162 is buffered in the latch (L) 164. The latch 164 holds the filtered and delayed binary voltage squared signal, and connects the binary voltage squared signal 165 to the gain corrector 170. The two signals of the bandwidth signal 156 and the symbol rate signal 158 generated by the gain corrector 170 control the AGC filter. It should be understood that the outputs of the amplitude generator 160, the AGC filter 162, and the latch 164 are binary values representing the scaled unit of the voltage squared. Therefore, they represent the received signals of the intercepted signal 113. The signal strength, or the converted value of the received signal power. Moreover, they are based on the power of the RF signal 113 that has been intercepted by the antenna 112, and are attenuated according to the attenuation control signal 189 or pass through a graded attenuator 114, which is controlled by the LNA 116 is modified (attenuated, passed or amplified) according to the gain control signal 195, and includes sigma-delta converters 132, 134, decimation functions 136, 138, DC offset precision control functions 140, 142, and baseband filter 144, The fixed gain (or loss) of the back-end function chain of 146 is modified to obtain the received signals 154 and 165.

Using conventional counting to design the low-noise amplifier 116, a gain-gain control value curve which is approximately the logarithm of a wide range, which will be described below with reference to FIG. 13, has been obtained. However, in order to make the cost of generating the LAN 116 low, only some LNAs are logarithmic to a wide range, so they were previously described as non-logarithmic amplifiers.

The gain corrector 170 includes a mode switch 175 with four modes: heating 171, tracking 172, calibration 173, and abort test 174. The gain corrector 170 produces two outputs: a combined signal 181 and a received signal strength indicator (RSSI) signal 183. The combined signal 181 is connected to the serial port interface (SPI) transmitter 186 through the sequence manager 184. The SPI transmitter 186 connects the combined signal 181 to the SPI receiver 188, and the SPI receiver 188 connects the gain control value 194 of the binary "word" of information conveyed in the combined signal 181 to the digital-to-analog converter (DAC) of the LNA 116. ) Input terminal, and connect the attenuation control signal 189 in the binary state transmitted in the combined signal 181 to the stepwise attenuation 114. Preferably, the gain control value 194 is 7-bit width so that the combined signal 181 can be transmitted in bytes, but it should be understood that the gain control value 194 "word" may have other binary widths. The gain corrector 170 also includes the stored gain response 180 from which the gain control value 194 is generated, and the RSSI function 182 from which the RSSI signal 183 is generated. The gain corrector 170 generates the gain control value 194 so that the gain of the LAN 116 changes with respect to the value of the gain control value 194 in a substantially accurate logarithmic manner.

According to the preferred embodiment of the present invention, the digital function of a conventional processor such as a digital signal processor (DSP) is used to perform the sampling function (as described above), sigma-delta converters 132, 134, decimation functions 136, 138, DC offset The functions 140, 142, and the baseband filters 144, 146 are precisely controlled, but it should be understood that these functions can be performed by analog circuits or digital logic, which are implemented in a custom integrated circuit (IC) state machine. The amplitude generator 160 is implemented by digital logic implemented as a part of the state machine IC, but may be implemented by a processor such as a DSP. Preferably, the squaring function 148, 150 is implemented in the only way described below, but alternatively, any technology that provides a predetermined level of accuracy to the square of the measured voltage value, such as a memory table implemented by an IC state machine, Or it can be performed by conventional multiplication performed in the processor. The adder function 152, the AGC filter 162, and the latch 164 are conventional functions, and are preferably implemented using digital logic that is part of a custom IC state machine, but alternatively, a conventional processor or a read-only memory can be used. The only program instruction set in the memory (ROM) is implemented by a digital signal processor. The gain corrector 170, which includes several unique functions introduced here, is preferably also implemented using a part of the digital logic of a custom IC state machine, but it should be understood that, alternatively, a conventional processor can be used or stored in ROM The only program instruction set is implemented by DSP. The mode switch 175, the stored gain response 180, and the mode of the RSSI function 182 are the only functions described in more detail below.

The sequence manager 184 is the only functional block that couples the new control value word to the LNA 116 through the SPI transmitter and receiver 186, 188 and the DAC 190 only when the protocol symbol passing through the LNA 116 has an edge. The sequence manager 184 compensates for the fixed and variable delays in the AGC loop 100, so that for a small portion of the symbol duration, at the edge of the next protocol symbol appearing in the LNA 116, the new gain control signal 195 Coupled to LNA116. Due to the inherent delays in the various stages of the AGC receiver 1101, the timing edges of the protocol symbols are different at the front end and the rear stages 110 and 130 of the AGC receiver 1101, and the timing edges follow the AGC system. The bandwidth of 100 (herein also referred to as "loop bandwidth" or "AGC bandwidth") changes as well as the duration of the symbol. SPI transfers occur very quickly relative to the duration of the symbol clock cycle. The unique feature of coupling the gain control value to the LAN 116 only at the edge of the protocol symbol in the LAN 116 helps to reduce the digital switching noise at the front end of the AGC receiver 1101 during the center of the symbol period. Similarly, to help reduce number noise, when the edge of the symbol block appears and the gain corrector 170 detects the LNA When the gain of 116 is still in the correct position (that is, the RF signal has not changed significantly, and the gain control value 194 does not need to be updated), the gain control value 194 is not passed through the SPI transmitter and the gain control signal 195 at the edge of the symbol block. The receivers 186, 188 are coupled to the LNA 116.

The AGC system 100 described herein adjusts the gain 110 of the front end to prevent the wireless device 1100 from being in an overload condition. The AGC system 100 allows the wireless device 1100 to successfully operate within a dynamic range of 115 dB. The AGC system 100 is the key to helping the AGC receiver 1101 obtain excellent intermodulation and adjacent channel specifications. The RSSI signal 183 allows the main processor to poll and check the measured value of channel strength for routine purposes such as handover decision and transmit power adjustment, and to obtain accurate tuning of the AGC receiver 1101.

The gain corrector 170 uses the voltage square value representing the restored signal power for all calculations involving the restored signal power. By doing so, it can move the value by simply shifting the value to the right or left (and when performing a left shift at the lowest effective Inserting zeros in the bits) works in +/-3dB increments, because this shifting results in half or twice the value representing the power level, which is very close to the +/-3dB change.

The technique of using binary shift to process the input power value in +/-3dB increments is the key to simplify the calculation in the AGC system 100. This is different from the prior art method that uses fixed-point multiplication and division. This technique is also The circuits (or storage requirements) and power used by the AGC system 100 are reduced.

The AGC system 100 is a negative feedback circuit, and therefore, it is affected by loop dynamic characteristics such as instability, overshoot, and undershoot. To minimize such effects, once the gain corrector 170 uses the changed gain control signal 195 to update the LNA 116 (by updating the gain control value 194) and/or the attenuation control signal 189 changes, before calculating the new gain control value 194 , The gain corrector 170 waits for approximately two symbol periods (two symbol periods (usec.) with a duration of 625 milliseconds) at 6400 baud. During this waiting state, the AGC filter 162 is cleared and kept reset. Such a reset state or delay allows any signal disturbance caused by the last AGC update to propagate through the system. In the preferred embodiment of the present invention, the propagation delay from LNA 116 to latch 164 is approximately 450 usec. The reset state ensures that the next new measurement period for the gain controller 170 is based on the clean data (clean data), and the AGC system 100 remains stable. Because the propagation delay is essentially independent of the symbol rate, for the symbol rate instead of 6400 baud, the reset state remains about 625usec. This reset state makes the AGC bandwidth faster than the prior art AGC system. (Typically, it can easily run on a 400Hz bandwidth, which is twice the bandwidth of existing technology products). This is useful because the AGC bandwidth of a conventional ZIF receiver is very low due to inherent transients such as the DC offset introduced by the LNA gain. The previous AGC design did not eliminate the loop filter. They allow transients introduced by the loop and therefore take longer to clear the disturbance from the AGC system. The AGC wait delay can be modified to match the propagation delay of other systems.

According to a preferred embodiment of the present invention, the RF step attenuator 114 is digitally controlled by the gain corrector 170 and has two states: an attenuation state, which provides an attenuation of about 17dB, and a pass or non-attenuation state, in which the signal is not attenuated, Or be magnified significantly. The decision whether to use the attenuation state of the step attenuator 114 is made near the beginning of the frame of the FLEX protocol. In the attenuation state, the wireless device 1100 uses the step attenuator 114 to start the heating mode 171. The gain correction function block 170 determines whether to switch to the non-attenuation state during the heating mode 171. After the wireless device 1100 changes to the tracking mode 172 that occurs during normal data receiving operations, the step attenuator 114 is switched to the non-attenuation state only when the recovered signal falls below the predetermined AGC "out of adjustment" threshold. After switching to the non-attenuated state, the hierarchical attenuator 114 cannot switch back to the attenuated state in the same frame. This feature prevents the step attenuator 114 from switching from non-attenuation to attenuation state and reverse switching during one frame. This improves the performance of the wireless device 1100 because it can cause large disturbances on the desired signal when the step attenuator 114 is switched, and repeated switching can result in a reduction in the sensitivity of the AGC receiver 1101. In most cases, you can set up a LAN The variable gain of 116 is low enough to handle a reasonably large signal when the step attenuator 114 is switched to the non-attenuated state. The hierarchical attenuator 114 is very useful when the AGC receiver 1101 is in a very strong inter-modulation (IM) or adjacent channel signaling environment, which usually lasts for at least multiple frames.

The present invention has three thresholds: AGC tracking threshold (AGC_THRES), AGC offset threshold (AGC_THRESSO), and AGC heating threshold (AGC_THRESWU). The unit of each threshold is square volts.

The AGC tracking threshold is set to be 16dB to 20dB higher than the signaling detection field (sense floor). The AGC tracking threshold is the recovered signal power. When the recovered signal power is greater than the AGC tracking threshold, during the tracking mode, the AGC system 100 adjusts the recovered signal power by controlling the gain of the LNA 116 by the gain control value 194. When the recovered signal power is less than the AGC tracking threshold, the gain corrector 170 keeps the LNA 116 at the maximum gain.

Preferably, the AGC offset threshold is set to be 12dB higher than the signaling detection field. When the step attenuator 114 is in the attenuated state and the LNA 116 is at the maximum gain, the AGC offset threshold is used to determine whether to switch the step attenuator 114 to the non-attenuated state.

Preferably, the AGC heating threshold is set to be 45 dB higher than the signaling detection field. As described in detail below, this threshold is used to meet IM specifications during heating mode.

The AGC system 100 uses a default value of +/-3dB higher than each of the three thresholds. Through proper programming, this default value can be increased to +/-6dB.

Heating Mode Referring now to FIG. 2, it shows a flowchart of the heating mode 171 operation of the gain corrector 170 according to a preferred embodiment of the present invention. When the wireless device 1100 (FIG. 11) is operating in synchronization with the synchronization signaling protocol, the heating mode 171 is used to determine whether to use the graded attenuator 114 in the attenuation mode during the tracking mode 172. (When the wireless device 1100 is turned on for the first time, the asynchronous heating mode not described here is used). Generally, after the wireless device 1100 has been operating in the communication system long enough to establish synchronization with the frame period, the heating mode is timed to start near the beginning of the preamble of the FLEX frame. In step 205, the wireless device 1100 turns on the AGC receiver 1101 and has started to receive information frames. It should be understood that in the FLEX communication system and other systems similar thereto, when the wireless device 1100 is operating in the synchronous mode, the AGC receiver 1101 remains in the "receiver-off" mode during one or more frames or cycles, During the frame period or period, the wireless device 1100 wishes to receive irrelevant new information (but the wireless device 1100 is substantially synchronized with the synchronization signaling protocol). Since the lowest gain is already set when the power of the AGC receiver 1101 is cut off, when the AGC receiver 1101 is powered on in step 205, the gain control value 194 is set to the lowest gain. According to a preferred embodiment of the present invention, this minimum gain is set lower than the minimum gain control value used during the adjustment of the normal LAN 116 during the tracking mode 172. The minimum gain is obtained by turning off the LAN 116. In step 210, the step attenuator 114 is set to an attenuation state. In step 215, a DC offset correction is performed, which lasts for 625 milliseconds. Then in step 220, the gain control value is set to the minimum gain control value. In step 225, the DC offset correction is completed and continues for 1. After 250 milliseconds, during 650 milliseconds at the beginning of the measurement period, the recovered signal power of the binary MAG with the binary voltage squared signal 165 is determined. The binary voltage squared signal 165 is also referred to as the first amplitude restoration signal with the settings of the step attenuator 114 and the LNA 116. In step 230, the MAG (of the first amplitude restoration signal) is compared with AGC_THRES. In step 235, when the MAG is greater than AGC_THRES, the step attenuator 114 is in the attenuation state, and the AGC system 100 is changed to the tracking mode 172. In an example of a VHF receiver implementation of the present invention, when the MAG is greater than AGC_THRES under these settings, the intercepted signal power is greater than -21dBm (relative to a decibel of 1 milliwatt). When the MAG is less than or equal to AGC_THRES, the LNA 116 is set to the maximum gain in step 235, and in step 240, after changing the gain of the LNA 116 for 1.250 milliseconds, during 650 milliseconds at the beginning of the measurement period, the LNA that is usually increased is determined again. 116 The gain has been increased to restore the signal power MAG. The binary voltage squared signal 165 is referred to as a second amplitude restoration signal with these settings of the step attenuator 114 and the LNA 116. In step 245, when the MAG (of the second amplitude recovery signal) is greater than AGC_THRES, the step attenuator 114 is in the attenuation state, and the AGC system 100 is changed to the tracking mode 172, step 265. In the case of VHF, when MAG is greater than AGC_THRES under these settings, the intercepted signal power is greater than -62.5 dBm. When MAG is less than or equal to AGC_THRES, the step attenuator 114 is set to a non-attenuation state at step 250, and at step 252, the step attenuator 114 is changed and continues for 1. After 250 milliseconds, during 650 milliseconds at the beginning of the measurement period, the restored signal power MAG, which has generally been reduced by the reduced step attenuator 114, is determined again. The binary voltage squared signal 165 is referred to as the third amplitude recovery signal with these settings of the step attenuator 114 and the LNA 116. In step 255, when the MAG (of the third amplitude restoration signal) is greater than AGC_THRESWU, the step attenuator 114 is reset to the attenuation state, and the AGC system 100 is changed to the tracking mode 172, step 265. In the case of VHF, when MAG is greater than AGC_THRES under these settings, the intercepted signal power is greater than -79.5 dBm. In step 255, when the MAG is less than or equal to AGC_THRESWU, the hierarchical attenuator 114 is set to a non-attenuation state, and the AGC system 100 is changed to the tracking mode 172, step 265. Through these determinations, it can be seen that the step attenuator 114 is set to one of the attenuation state and the pass state by the beginning of the normal data portion of the restored signal.

The tracking mode now refers to FIG. 3, which is a mapping table of a set of registers holding the stored gain response 180 according to a preferred embodiment of the present invention. Preferably, the register set is used as a plurality of register storage locations specially designed to maintain the stored gain response 180. At each of the predetermined multiple storage locations (marked as locations 0 to 19 in the example shown in FIG. 3), there is a "VALUE ADJUSTMENT" group for storing gain control value adjustments. In this example, the 31 predetermined maximum gain control values (identified as O7-O0 in FIG. 3) are adjustment values related to storage location 0. Using a fixed-power conducted RF signal coupled to the conducted input 111 (FIG. 1), other adjustment values are measured and stored during calibration mode 173. (Use the conductive input 111 to turn off the intercepted signal 113 from the antenna 112 of the step attenuator 114). Each position is associated with a gain that is very close to 3dB below the gain associated with the next higher sequential position. Therefore, these locations have gains related to those values shown in the gain column of FIG. 3 (but these gains are not stored). Each adjustment value stored in a position other than position 0 is an adjustment value that represents an approximate change in the gain control value 194. The gain control value 194 is required to change the gain of the LNA 116 at a lower position to the same value as the gain control value 194. Location-related LNA A gain of 116. It should be understood that the gain control value 194 for a specific correlation gain at a specific position is derived from the maximum gain control value, and the adjustment value for the position reaches to include the specific position. When the gain control signal 194 generated by the DAC 190 is applied to the LNA At 116, the gain control value 194 provides essentially the same gain reduction from the maximum gain at position 0 as obtained during calibration mode 173. However, it should be understood that the binary absolute value of the binary voltage squared signal 165 at a specific gain control value may be different in the tracking mode 172 than in the calibration mode 173 because the power of the intercepted signal 113 in the tracking mode 172 may be It is (usually) different from the power of the conducted RF signal used for the calibration mode 173. It is important to understand that the gain control value 194 can be adjusted by subtracting or adding an adjustment value related to the next higher or lower position, respectively, to obtain a positive or negative 3dB change in the power of the restored signal 165 . The pointer register holds the current value of the position related to the gain set by the current value of the gain control value 194, which has been determined from the adjustment values related to all positions between 0 and the position to be pointed to come out. It should be understood that, preferably, the stored gain response is a dedicated register set, but it can also be any other type of memory such as a part of the processor register or other memory such as random access memory (RAM), in this case , Add the pointer value to the base address in a conventional way to restore the gain and adjustment value. It should also be understood that the use of adjustment values reduces the amount of storage that must be generated for gain control values compared to storing absolute gain control fingers for each desired relative gain. According to a preferred embodiment of the present invention, the adjustment value is stored in two bits for each position. For example, the two bits associated with the storage location 5 currently pointed to by the pointer are identified as X5,1 and X5,0.

Referring to FIG. 4, a flowchart of the tracking mode 172 according to a preferred embodiment of the present invention is shown. In step 405, the binary value MAG of the filtered binary voltage squared signal 165 is obtained, and in step 410, it is tested to determine whether it is different from AGC_THRES by determining whether it is greater than a predetermined hysteresis value HYST, which is preferably 3dB. Then, if not, there is no change in the gain control value in step 415, and the flow returns to step 405 to wait for the next measured MAG. When the absolute value of (MAG-AGC_THRES) is greater than HYST, in step 420, the variable representing AGC_THRES, namely AGCSHIFT, is set equal to AGC_THRES, and the variable that counts the step length of the gain control value, namely COUNT, is set to zero.

If at step 425, MAG is greater than or equal to AGCHSHIFT, if at step 460 the pointer (POINT) is less than the maximum pointer value (POINTMAX), then at step 465 the adjustment value at POINT is obtained, and at step 470 it is used to reduce the gain control value One of the mentioned adjustment values. However, if POINT is equal to POINTMAX in step 460, the gain control value is not changed (it is already in the position where the gain of LAN 116 is set to the maximum gain), and the flow returns to step 405 to wait for the next measurement MAG. Next, in step 475, AGCSHIFT is shifted to the left by 1 bit, POINT is increased by 1, and COUNT is increased by 1. Next, if POINT is equal to POINTMAX, as described above, in step 490, the newly determined gain control value (which is the value that sets the gain of the LNA 116 to the maximum gain) is coupled to the LNA at the next symbol edge 116, and the flow returns to step 405 to wait for the next measured MAG. However, if in step 480, POINT is not equal to POINTMAX, and in step 482, COUNT is not equal to COUNTMAX, and in step 485, MAG is not less than AGCSHIFT, the flow returns to step 465 to continue to determine whether it is appropriate to reduce the gain by another approximately 3dB In step 485, make MAG<AGCSHIFT. If in step 482, COUNT is equal to COUNTMAX, then in step 490, the newly determined gain control value is coupled to the LNA 116 at the next symbol edge, and the flow returns to step 405 to wait for the next measured MAG. Use such a limit to prevent the absolute value of the gain change from being greater than approximately (3dB)*(COUNTMAX). For a typical combination of wireless environment and wireless device type, set COUNTMAX to 6 (approximately 18dB). In step 485, if the MAG is less than AGCSHIFT, at the next symbol edge, the newly determined gain control value is coupled to the LNA 116 in step 490, and the flow returns to step 405 to wait for the next measured MAG.

In step 425, if MAG is less than AGCSHIFT, then in step 430, if the pointer (POINT) is greater than the minimum pointer value (0), the adjustment value at POINT is obtained in step 435, and in step 440, this value is used to increase the gain control Value is an adjustment value. However, if POINT is not greater than 0 in step 430, the gain control value is not changed (it is the value that sets the gain of the LNA 116 to the maximum gain), and the flow returns to step 405 to wait for the next measured MAG. Next, in step 445, ACSHIFT is shifted by 1 bit to the right, POINT is increased by 1, and COUNT is increased by 1. Next, if POINT is equal to 0, and in step 453, if MAG is less than or equal to AGC THRESSO, in step 454, the hierarchical attenuator 114 is set to the non-attenuated state, and in step 490, at the next symbol edge, the newly determined The gain control value is coupled to the LNA 116, and the flow returns to step 405 to wait for the next measured MAG. In step 450, if POINT is equal to 0, and in step 453, if MAG is greater than AGC_THRESSO, keep the hierarchical attenuator 114 in the attenuated state, and in step 490, the newly determined gain control value is coupled to the LNA at the next symbol edge 116. The flow returns to step 453 and waits for the next measured MAG. However, in step 450, if POINT is equal to 0, and in step 452, COUNT is not equal to COUNTMAX, and in step 455, MAG is not greater than or equal to AGCSHIFT, the flow returns to step 435 to continue to determine whether the gain increase by another approximately 3dB is suitable In step 455, MAGAGCSHIFT is set. In step 452, if COUNT is equal to COUNTMAX, then in step 490, at the next symbol edge, the newly determined gain control value is coupled to the LNA 116, and the flow returns to step 405 to wait for the next measured MAG. Use these limits to prevent the absolute value of the gain from changing more than approximately (3dB)*(COUNTMAX). In step 455, if the MAG is greater than or equal to AGCSHIFT, then in step 490, at the next symbol edge, the newly determined gain control value is coupled to the LNA 116, and the flow returns to step 405 to wait for the next measured MAG.

It should be understood that, for those of ordinary skill in the art, there are many different tracking modes, and these modes can be used to achieve the same result obtained by the preferred embodiment of the present invention. In an alternative embodiment that has been implemented, the tracking mode technique introduced in FIG. 4 is used, except that the gain control value is not changed in the steps 470, 440 described, and the pointer value is not changed in the steps 475, 445 ( POINT). Then, when one of steps 485 and 455 is determined to be "YES", another loop is executed COUNT times, the pointer value POINT is adjusted by one each time, and the gain control value is changed by an adjustment related to each POINT value Value, then in step 490 the new gain value is transmitted. In a modified example relative to the preferred embodiment, MAG can be shifted instead of AGC_THRES to determine the need to generate a COUNT that is different from the previous 3dB MAG; the direction of pointer increase can be reversed; steps 470 and 475 can be reversed, etc. . Moreover, there are several characteristics of the tracking mode: if it is not implemented, it will be reduced, but it will not eliminate all the benefits of the present invention. For example, steps 482 and 452 can be omitted, thus allowing the gain to fluctuate in some situations, making the AGC system 100 less stable in these situations.

It should be understood that the use of the binary voltage squared signal and the storage gain response in the AGC system allow the gain to be changed by more than about 3dB by shifting the AGCSHIFT1 bit to the left or right when a new gain value needs to be determined. Compared with the prior art AGC system, the circuit is very simple and makes the gain control have a linear relationship with power. Without these linearities, the system may overshoot and may oscillate as the input power of the intercepted signal 113 changes. Moreover, the ability to provide a wide range of gain changes in the AGC update loop, for example, the ability of the AGC system 100 to vary between 3dB and 18dB enables the AGC system to operate with a faster time constant than the prior art. This AGC system 100 allows the control processor to change the magnitude of the gain change by changing the COUNTMAX. When the AGC system works near the AGC threshold, the magnitude of the gain change can be reduced, thereby reducing the setup time compared to the prior art AGC system, and The stability of the AGC system 100 is improved.

AGC Filter Referring to FIG. 5, there is shown an electrical block diagram of the AGC filter 162 according to a preferred embodiment of the present invention. The AGC filter 162 includes an accumulator 505 coupled to the input of a scaler 510. Coupled between the accumulator 505 and the converter 510 are the bandwidth signal 156 and the symbol rate signal 158.

As shown in Table 1, the accumulator 505 is controlled by the signals 156, 158 to accumulate the sample values shown. In a gain control update cycle, the accumulation has the duration shown.

Table 1

The accumulator 505 is further controlled by the symbol rate signal 158 shown in Table 2 to remain cleared in the reset state used in the samples shown, the reset state having at the beginning of each gain control update cycle The duration shown.

Table 2

Referring to Figures 6, 7, 8 and 9, the timing diagram shows the reset duration and the accumulation duration compared with the symbol period of 6400 baud symbols (labeled as 6400 baud symbol period), and shows According to the preferred embodiment of the present invention, the gain control value update (marked as the write gain value) occurs during each gain control value update cycle. These relationships are shown in 4 different loop bandwidths: 177 Hz in Figure 6, 320 Hz in Figure 7, 533 Hz in Figure 8, and 800 Hz in Figure 9. It should be understood from these figures that these accumulation durations for different loop bandwidths have a relationship of 2M, and the reset duration is substantially constant. It can be further understood from Tables 1 and 2 that for a specific bandwidth, the accumulation duration and reset duration for different symbol rates are substantially the same.

The output of the accumulator is 15 to 240 times the average amplitude of the unfiltered recovered signal 154. Then, the accumulator output is reduced by the converter as shown in Table 3 for the first gain conversion.

table 3

After this first conversion, the signal has a value of 15/16 of a sample. Then, it is normalized by a second conversion of 17/16 to produce an output that is normalized to a sample value, which is approximately the average value of the samples in the accumulator, regardless of the selected access Symbol rate and filtering bandwidth (which is the loop bandwidth). This simple filter conversion allows the AGC system 100 to use an AGC threshold set for the wireless device. The AGC threshold set is independent of the selected bandwidth and symbol rate, which is not available in the prior art AGC system.

It should be understood that the above relationship can be more generally expressed as: the symbol rate signal 158 indicates that one of the at least two symbol rates has a factor between the two relationships. The accumulator 505 produces a binary output that is an accumulation of the number of samples that occur during a gain control value update cycle. The number of wireless devices used for any two symbol ratio is essentially inversely proportional to the ratio of the two symbol rates. The converter reduces the binary output by a factor substantially equal to the amount by a binary right shift operation. The number is given by the formula ((2N-1)*2M). N and M are integers. The binary shift right operation will shift the output right by M+N bits. The factor is 2N*2M. The converter performs adjustment to reduce the binary output ((2N+1)/2N).

RSSI functional block Referring to FIG. 10, there is shown an electrical block diagram of the RSSI functional block 182 according to a preferred embodiment of the present invention. The RSSI function block 182 includes a log function (LOG2) 1020, an addition function (ADD) 1030, and a selection function 1050 (SELECT). The addition function 1030 adds up 4 binary values. One is the LNAGAIN (gain) 1005 obtained from the stored gain response 180. LNA GAIN 1005 represents the most recent relative gain that LNA 116 has been set to; that is, compared to LNA The difference in dB of the maximum gain of 116, the step size is 3dB. Preferably, this can be obtained by counting the gain step size from the maximum gain to the current pointer position (pointer position step size), and is preferably 4 bits wide. The other is the ATTENUATOR (attenuator) signal 1010, which has a value representing the attenuation relative to the non-attenuated state of the step attenuator 114 in 3dB steps, the unit is dB (for example, 0 or 18), and preferably 3 bits width. The third is a 5-bit binary Mu-law signal 1021 generated by the LOG2 function 1020. The value of this Mu-law signal 1021 is the sequential position of the highest bit of the value, that is, the MAG with the binary voltage squared signal 165 of "1", and preferably the value is 5 bits wide. The Mu-law signal 1021 is an approximation of Log2 (MAG). The fourth is the constant 1015, when this constant is added to the LOG2 signal 1021, LNA When 116 is working at maximum gain and the step attenuator 114 is in a non-attenuation state, the constant produces a result of 0 from the output of the addition function 1030, and the LOG2 signal 1021 is when the 0dBM signal is inserted into the conduction output 111 (Figure 1) It is generated during the middle (or intercepted by the antenna 112). The constant 1015 is preferably a 5-bit width value. The output of the addition function 1030 is a binary value width X representing the power (dBm) of the intercepted signal 113. This is called low-resolution RSSI, and the resolution is selected by the selection function 1050 when the AGC system 100 is in the tracking mode 172. When the low-resolution RSSI output is selected, it is coupled to the main processor of the wireless device 1100, and the wireless device 1100 includes a low-resolution RSSI conveyed to the fixed part of the wireless communication system in a message. The low-resolution RSSI is used to perform operations as fixed transmission power adjustment and fixed transmission selection, and is used in the AGC wireless device 1100 (FIG. 11), for example, to perform error correction on the restored signal. In the preferred embodiment of the present invention, X is 10. It should be understood that because the low-resolution RSSI is used for the purpose of allowing a longer delay time than the loop of the AGC system 100 allows, preferably, the log function 1020, the addition function 1030, and the selection function 1050 are used in the main processing of the wireless device. It is executed in a device, rather than in a portion of a custom integrated circuit that is preferably used for the other unique digital functions of the AGC system 100.

In the suspension test mode 174, the selection function 1050 selects the value MAG of the binary voltage squared signal 165. In the tracking mode 172, the full bit width W of the value MAG is passed to the output of the selection function 1050 and coupled to the main processor of the wireless device 1100. During the factory tuning operation, the main processor couples this high-resolution, uncorrected, filtered signal to the measurement device. According to a preferred embodiment of the present invention, W is 21, which provides a resolution of 0.01 dB and a total range of 63 dB. This allows high-precision peak tuning to be performed, making it possible to perform simple, precise, and automatic wireless tuning.

Referring to FIG. 11, there is shown an electrical block diagram of a wireless device 1100 according to a preferred embodiment of the present invention. The wireless device (also referred to as an AGC wireless device) includes an AGC receiver 1101 that is coupled to the AGC system 100. The AGC receiver 1101 is preferably a ZIF or direct conversion receiver, but may be another type. The recovered I and Q signals 145, 147 are coupled from the AGC system 100 of the AGC receiver 1101 to the controller 1105, which demodulates and decodes these signals in a conventional manner, and processes the information including the I and Q signals. The controller 1105 performs conventional functions, such as protocol symbol synchronization and demodulation, protocol decoding, error decoding, address checking, and so on. The controller 1105 includes a conventional microprocessor with suitable stored program instructions. The information decoded from the I and Q signals 145, 147 and the information generated in the controller 1105 are coupled to the display 1115 to be provided to the user. The AGC wireless device 1100 also includes other conventional user interfaces, such as switches (not shown in FIG. 11), and can optionally include one or more other conventional user interface elements, such as speakers, vibrators, and LED indicators (in Not shown in FIG. 11), and optionally includes a transmitter coupled to antenna 112 (not shown in FIG. 11). The controller 1105 controls the AGC receiver 1101 to select a specific wireless channel, and enters various operation modes by means of the control signal 1110. During the tracking mode 172, in a wireless device with a transmitter, a low-resolution RSSI is generated, and the RSSI signal 183 is coupled to the controller 1105, which couples the encoded low-resolution RSSI to the serial signal 1120 The transmitter informs the fixed network of the received signal strength. When the AGC wireless device 1100 is manufactured, the AGC wireless device is added to the suspension test mode 174. During this mode, the high-resolution RSSI is coupled to the controller 1105, and the controller 1105 couples the high-resolution RSSI via the serial signal 1120 To the factory tuning device, it is used to preferably tune the wireless device 1100 in the factory tuning device. It should be understood that, optionally, the high-resolution encoding and transmission can be performed when the AGC wireless device includes a transmitter. In order to achieve the purpose of obtaining high-resolution RSSI, the transmitter can reduce the wired connection to the AGC wireless device. Reduce manufacturing costs.

It is also desirable to include other structures in the box in FIG. 11. For example, the above-mentioned symbol demodulation and synchronization functions can optionally be performed by digital signal processing, and the digital signal processor performs the functions of the amplitude corrector 170 and other parts of the receiver 1101 described above.

It should be understood that although the AGC system 100 is introduced in the form of a radio frequency receiver, the present invention also provides similar benefits in other types of receivers, one example of which is an infrared optical receiver.

Determining the stored gain response Referring to FIG. 12, there is shown an electrical block diagram 1200 of the calibration establishment for determining and storing the stored gain response of the wireless device 1100 according to a preferred embodiment of the present invention. The calibration setup includes a signal generator 1210 coupled to the conductive input 111 of the AGC wireless device 1100. The signal 1205 is coupled to the AGC wireless device 1100, which puts the AGC wireless device into the calibration mode 173, and starts the calibration process. The signal generator generates a constant power level signal 1215, which can be located within a few dB of the predetermined signal level; it does not need to be accurately set to the predetermined signal level, because the use of calibration and unique memory gain response avoids Need to use absolute signal level. This reduces the cost of the testing process. Alternatively, instead of conductive coupling, the calibration signal radiatively coupled to the AGC wireless device 1100 may be used to perform the calibration described herein, as long as the power level signal intercepted by the AGC wireless device 1100 remains constant during the calibration procedure. This is another advantage of this procedure because several AGC wireless devices 1100 can be calibrated simultaneously.

Referring to FIG. 13, it is shown that the gain (dB relative to the maximum gain of reference 0dB) of a typical LNA 116 used in an AGC system according to a preferred embodiment of the present invention vs. the digital gain control value 194 coupled to the DAC 190 (FIG. 1) The graph of the graph. The figure shows three curves, one for high temperature, one for normal ("TYP") temperature, and one for low temperature. These gains are essentially all negative gains because they are lost relative to the amount of gain of the LNA 116 at the maximum gain control value. In this example, the loss digital value is 31. It should be understood that the curve is non-linear, and because the vertical coordinate is logarithmic, LNA 116 is properly represented as a non-logarithmic amplifier. It should be further understood that when the gain control value 194 is set to 0, the LNA 116 will be turned off. Therefore, as described with reference to the block 205 of FIG. 2, the gain control value 194 is the only state of the lowest gain.

Referring to FIG. 14, there is shown a flowchart of a method for determining a storage gain response for the AGC system 100 according to a preferred embodiment of the present invention. In step 1405, a predetermined modulation type 1215 is performed on a signal with a constant power level (in some types of systems, a modulated signal can be used), and the signal with a constant power level is coupled to the conduction input 111 of the AGC wireless device 1100 . In step 1410, the controller 1105 initializes the pointer to 0, and initializes the gain control value (GCV) 195 to the maximum gain control value GCVMAX. In this example, the maximum gain control value digital value is 31, and the gain control step size The counter DGCV is initialized to 0. In step 1415, the value SMAG called "shifted restored signal power" is initialized to the restored power value MAG (GCVMAX), which is measured at GCVMAX. Similarly, GCVMAX is stored in the stored gain response register at position 0 at the adjustment value (VALUE(0)) related to the maximum gain. Then, in step 1420, the pointer is incremented by 1, and the SMAG is shifted to the right by 1 bit. In step 1430, the step counter DGCV is incremented by one, and the gain control value 194 is decremented by one. The recovered signal power MAG (GCV) at the current gain control value is compared with SMAG. If in step 1435, MAG (GCV) is equal to or greater than SMAG, then in step 1440, the value of the gain control counter (DGCV) is stored in and In the adjustment value (VALUE (POINTER)) related to the current value of the pointer, in step 1445, the gain control value (DGCV) is reset to 0, and the method proceeds to step 1420.

When in step 1435, MAG (GCV) is less than SAMG, the method continues to step 1430. The method continues until the pointer reaches the maximum value (in this example, 19), at which point the stored gain response is completed. Using this method, the gain response is stored, providing a combined logarithmic gain response including the gain corrector 170 and the non-logarithmic LNA 116; that is to say, the linear change of the binary voltage squared signal (165) results in substantially The logarithm changes at the output of LNA 116.

It should be understood that the method just described in detail can be introduced in other ways as follows: Alternatively, the shift recovery signal power SMAG is described as a relative binary voltage squared signal, because this is determined by repeated right shifting the maximum gain control value Relative to the recovered signal power measured at the maximum gain control value. The comparison performed in step 1435 can be described as follows: The binary voltage square value (MAG(GCV)) of the restored signal generated at the second gain control value and the relative binary voltage square value (SMAG) (by comparing with the first gain control value) The relative binary voltage square value related to the control value is shifted to obtain) the comparison is performed to determine the sign of the difference in the value. Step 1430 can be described as follows: Determine the number of times to repeat the comparison step. The loop including steps 1430 and 1435 includes repeating until the sign of the difference is a predetermined value (in the detailed example, until MAG(GCV)<SMAG). Finally, step 1440 can be described as follows: The adjustment value is stored in the number of comparison steps repeated between two consecutive steps (1435) of determining the sign of the difference.

It should be further understood that this method of storing the gain response curve is easier and faster than the manual method of the prior art, and does not require adjustment of the signal generator to complete.

The gain response function stored by this method can be basically described as: comparing an ordered set of registers (where each register stores a gain adjustment value) with a gain control output, where each gain adjustment value is such a value: When subtracted from the gain control output or added to the gain control output, a new gain control output value is generated, which is a different amount from the current value, which actually changes the gain of the non-logarithmic amplifier by one The predetermined decibel.

In addition, the stored gain response can be described as follows: an ordered group of registers including a first register, where each register stores a gain adjustment value except for the first register, including a value coupled to a register (pointer register) Digital input pointer, and a gain control value output. Generates gain control output as the sum of the value stored in the pointer register and all the values stored in the register between the first register and the pointer register, combined by subtracting or adding to the value stored in the first register , Wherein the gain adjustment value uses the reference to the digital input in a logarithmic manner to control such a gain control output of the non-logarithmic amplifier.

It should be further understood that the gain response at multiple temperatures can be stored in the AGC wireless device 1100 in a relatively small amount of storage, and can be used in combination with the temperature measured by the AGC wireless device 1100 to further refine the gain performed in the AGC system 100 Adjust the accuracy. For example, during factory calibration, three gain curves such as those shown in FIG. 13 can be stored. For the AGC wireless device 1100, the high and low temperature curves occur at the maximum and minimum operating temperatures. Then, during operation, the AGC wireless device measures the temperature in the AGC wireless device 1100 (for example, the temperature at the heat sink of the LNA 116), and during factory calibration, compares the measured temperature with the temperature in the heat sink. The measured temperature at the place is compared. The linear interpolation of two of the three gain control values can then be used to determine the gain control value used for the refinement of the gain control value 194.

Squaring Function Referring to Fig. 15, there is shown an electrical block diagram of a squaring circuit 1500 for each of the two squaring functions 148, 150 (Fig. 1) according to a preferred embodiment of the present invention. Preferably, the two squaring circuits are implemented as part of the logic circuit of the state machine included in the customized integrated circuit. The signal coupled to the element of the squaring circuit 1500 is represented here as having the width of a binary parallel signal, where the number of parallel lines is represented as the width. The squaring circuit 1500 includes a logarithmic compression function 1510, a doubling function 1595, a squaring function 1590, and a logarithmic decompression function 1565. The logarithmic compression function 1510 accepts a binary input 1505 with a width W and a value X, and generates an output with the value POWER of a binary power component 1520 and the value AMGNITUDE (amplitude) of a binary amplitude component 1515, the value POWER and the value MAGNITUDE Together, it means that X is the predetermined precision N, that is, the answer is accurate to N significant digits. The binary input 1505 of one of the squaring circuit 1505 is coupled to the I signal 145 and the binary input 1505 of the other of the squaring circuit 1505 is coupled to the Q signal 147. The squaring function 1590 generates an adjusted squared amplitude component 1542 of width N and a selection signal 1561 from MAGNITUDE. The doubling function 1595 generates a doubled power component 1556 according to POWER and the selection signal 1561. The logarithmic decompression function 1565 generates an approximately squared output with a width of 2W from the doubled power and adjusted squared amplitude components 1556, 1542, which has an approximated amount of precision N that approximates the square of X to a predetermined amount of precision. According to the preferred embodiment of the present invention, W=32 and N=6.

According to a preferred embodiment of the present invention, the logarithmic compression and decompression functions 1510 and 1565 are Mu-law type functions. The logarithmic decompression function 1510 generates a binary amplitude component 1515 with a width N (N is a design choice) and a binary power component 1520 with a width P, where 2(P-1)<W2P, and P and W are Integer. In the preferred embodiment, P=5. The logarithmic compression function 1510 includes generating the power function of POWER according to the relationship POWER=int(log2(X)), and further includes generating the magnitude function of MAGNITUDE according to the relationship MAGNITUDE=int(X*2(N-POWER))-2N . The circuits that implement these relationships are well known to those of ordinary skill in the art. A specific example of the preferred embodiment is: X = 0000 0101 0111 1001 1101 0000 0001 1001 POWER = 1 1010 MAGNITUDE = 01 0111 The square function 1590 includes a value input in response to an increased amplitude input including a binary amplitude component 1515 increased by an upper bit 1524 Generate an exact square signal with a width of 2N+2 (exact square signal) 1526. Preferably, the squaring function 1590 includes generating a look-up table that generates an exact squaring function 1526 for each value of a 2(N+1) value for the increased amplitude input, the exact square having an increased input The value of the exact square. Other implementations than look-up tables can be used, such as conventional multiplication circuits dedicated to each exact square function 1590. For the example given above, the increased amplitude input is 1010111, and the exact square is 01 1101 1001 0001. The squaring function 1590 includes a manipulation circuit 1560 coupled to the exact squaring function 1525, which uses a comparator to compare the value of the exact squaring signal 1526 with binary 2 (2N+1), and generates a manipulation signal 1561. The manipulation circuit has a TRUE state when the value of the exact square signal 1526 is greater than or equal to binary 2 (2N+1), and has a FALSE state for the other result. In the example introduced, 2(2N+1) is 213, so the manipulation signal 1561 is FALSE. The squaring function 1590 further includes an adjustment function 1529 that generates an adjusted square amplitude component 1542 from the exact square. The adjusted square amplitude component 1542 has an N-bit precision and width. The adjustment function 1529 includes a first integer divider 1530 that performs an integer operation on the result of the division of the exact square signal 1526 divided by 2N, and a second integer operation that performs an integer operation on the result of the division of the exact square signal 1526 by 2 (N+1) The divider 1535, and when the state of the manipulation signal is FALSE, select the lowest N significant bits of the output of the first integer divider 1530 or select the lowest N significant bits of the output of the second integer divider 1535 when the manipulation signal is TRUEofmultiplexer 1540. The selected bit is the adjusted squared amplitude component 1542. In the introduced example, the first integer divider 1530 is selected, so the adjusted square amplitude component 1542 is 11 0110.

Preferably, the doubling function 1595 includes a left shift function 1545, which generates a doubled power signal 1546 with a width of P+1 by shifting the binary power component 1520 by 1 bit in a shift register and a value for doubling POWER, which also includes passing In the adder, the binary 1 is added to the value of the doubled power signal 1546 to generate an increased doubled power signal 1551. The adder 1550 also includes a multiplexer 1555, which selects the doubled power when the manipulation signal 1561 is FALSE Signal 1546, and when the manipulation signal 1561 is TRUE, the increased doubled power signal 1551 is selected to generate a doubled power component 1556. In the example presented, the manipulation signal 1561 is FALSE, so the doubled power component has a value of 11 0100.

It should be understood that in the introduced squaring circuit 1500, using the following relationship, the squaring function 1590 generates an adjusted squared amplitude component 1542 with a value of ADJSQMAG, and the doubling function 1595 generates a doubled power component 1556 with a value of DBLPOWER 1556: when (MAGNITUDE+ 2N)22(2N+1), ADJSQMAG=int(((MAGNITUDE+2N)2)*2-(N+1)) N least significant bits, and DBLPOWER=2*POWER+1; when When (MAGNITUDE+2N)2<2(2N+1), ADJSQMAG=int(((MAGNITUDE+2N)2)*2-N) the N least significant bits, and DBLPOWER=2*POWER.

The logarithmic decompression function 1565 generates an approximate square output 1570 from ADJSQMAG and DBLPOWER, as follows: (ADJSQMAG+2N)*2(DBLPOWER-N) In the example introduced, ADJSQMAG = 11 0110, and DBLPOWER = 11 0100 (decimal Is 52), so in this example the approximate square output is 1570=(1110110)*246.

In the squaring circuit 1500 with W=32 and N=6, the squaring circuit 1500 reduces the integrated circuit die area required by the prior art by 20%, reduces non-sequential implementation, and provides at least 0.1dB accuracy. Therefore, it should be understood that the cost and power savings of the present invention are important.

It should also be understood that, in another embodiment, the accuracy of the adjusted square amplitude component 1542 can be increased to 2N bits by changing the divisors of the first and second integer dividers 1530 and 1535. For example, by changing the first integer divider 1530 to not perform a division operation on the exact square signal 1526, and changing the second integer divider 1535 to perform an integer operation on the result of dividing the exact square signal 1526 by 2 to obtain 2N bits Accuracy. In these alternative embodiments, although fewer shifts are performed in the integer dividers 1530, 1535, more bits must be multiplexed in the multiplexer 1540, and at the input of the Mu-law decoder 1565 To process.

It should be further understood that although the squaring circuit 1500 is introduced with reference to the wireless receiving circuit, it is useful in any electronic device and in any integrated circuit. In the electronic device, there is a need for a squaring function. From the squaring function , The approximate result is satisfied, and the accuracy of the result can be adjusted by modifying the value N.

Although the preferred embodiments of the present invention have been described and introduced, it should be clear that the present invention is not limited to the preferred embodiments. For those skilled in the art, without departing from the spirit and scope of the present invention defined by the following claims, various modifications, changes, changes, substitutions, and equivalent substitutions are conceivable.