Method of pins multiplexing based on PCI bus

A PCI bus base pin multiplexing method and integrated - circuit

technical field

The invention and connected to multiplexing's method, is specific, connected with a PCI bus based on peripheral element and internet the base pin multiplexing method.

background technology

Along the radial of computer technology, a personal computer, a PCI substituted ISA and EISA bus to form a computer local bus new standard gradually, and on the personal computer with a longer provided ISA and EISA bus. Layer and a PCI bus's signal wire are multiple, the main control device of the signal wire is 49, the target device of the signal wire 47 with. Usually a PCI device has the I/O ports, wherein a PCI circuit device capable of generating multiple pins, an lift the circuit in production cost, a PCI board card for generating degree complication.

And is the general PCI interface, each PCI address/THE data line which is placed on the input of address output and data, usually unreadable and is used again. And the flow condition: isWhen the target device and a PCI memory (a) with the data the time, editable optimization to the input and output port.

The invention claims an increased circuit is connected, reducing integrated - circuit production cost, the simplified manufacturer degree production method.

invention content

For wherein the target, the invention claims a PCI bus base pin multiplexing method and integrated - circuit; the method comprises the following steps: --Fitting the PCI bus main device water inlet waiting state the step, namely target device is PCI and a reading data manipulation; and address of the target signal device TRDY# to maintain of the upper layer,--I/O reading data the step, comprising: When the main device is at the waiting state, wherein an bus is arranged on the no-load and time: Uses the step door is;

The selection, online outputs an I/O signal in THE the step; , Which to the according to the I/O address signal output or more I/O signal and step of I/O device; The choosing an I/O device, and multiple time, the main storage device to all the I/O device reading data manipulation of an online reading data the step; --PCI reading data manipulation the step, comprising: Completing the I/O with the data, and step door is; The selection; the drive data to the PCI step on THE bus,, Which to one or multiple PCI the signal, in PCI card reading data manipulation the step.

, Wherein the upper device, wherein the I/O device comprises expanded storage unit; the expanded storage device comprises a place guiding Boot ROM.

The integrated - circuit comprises: PCI THE line; I/O interface circuit; The base pin, the same is connected to a PCI THE line and I/O interface circuit for providing input or output; Door; The main device, the target device via a PCI the DALI, and a on the PCI bus the main device water inlet waiting state the step, namely target device is PCI and a reading data manipulation; and address of the target signal device TRDY# to maintain of the upper layer,The target device, comprising: The device for external interface, board is a PCI THE line and I/O interface circuit and corresponding to the interface;

The device, wherein the selection to the multiplexing connected to by, and different data interface the time sharing output same base pin; Device main storage element, displaying I/O for target device for reading the operation the final platform and storing from a PCI THE line reading I/O data; the target device the data driving to an bus is released, and PCI card reading the data manipulation.

Realizing PCI THE line and I/O interface circuit of the base pin is the same connected to the input or output, wherein the device is interface, and a PCI THE line and I/O interface circuit and corresponding the interface.

The device, wherein the selection by a group of three of the slide door to the multiplexing connected to the bar, an address, water inlet and data in different time or outputting the I/O address, a to the I/O data, and different data interface the time sharing output on the same connected to.

Brief for describing the drawings

The use of ion beam of the patented claim, a pointed is specifically the subject of the present invention, and systems for analysing patent the protection to a usage. However reference the following detail and on digital, the related structure of better separation the invention and realizing method and target, and superiority.

Digital 1 is a PCI bus base pin multiplexing reading operation time sequence diagram; Digital 2) is according to the invention PCI bus and I/O interface address line pin base; multiplexingDigital 3) is according to the invention PCI bus and I/O interface data line pin and high-efficiency multiplexing.

Detailed composed of illustrated embodiments

The following detail, drawing specific detail order to provide to the invention comprehensive separation. However the professional the technical for realizing of the invention is capable of using the similar detail a.

Although the invention is a voice on the; and the condition of the invention is: When the device and target device is the main device WITH card reading the command. Stipulated according to A PCI Bus Local a Standard of the single data reading and transmitting the following: Clock 1, a device of clock 1 lift is an transaction. The auxiliary device for driving the command and an and C/BE# (3:0) is AN (31:0). Of advocates device adopts FRAME# to for marking transaction started; the bus with the effective address and command.

The clock 2, wherein the bus is target device in clock 2 along the sampling address, command and FRAME#, all the address section. Whom the target for starting decoding of determining is a target of transaction. Main device adopts IRDY# indicated of the device to receive the first data one of claims, wherein the effective device, IRDY# at the same time wherein FRAME# invalidation indicated of the device to all the last a data. The main device a driving the command on C/BE# (3:0), and a time to drive kbytes to enable, indicated for a power source from one of reading data of a kbytes.

The clock 3, wherein the clock the 3) are, a sampling device DEVSEL# is invalid, indicated of the target with the transaction therefore, the first data (is last data) is device to all, wherein the air waiting state. The waiting state process, the main device of continue to drive kbytes to enable and effective IRDY#, in until the data transaction.

Target a clock 3, clocks 4 or a effective 5 DEVSEL# statement transactions. A PCI Bus Local Standard a stipulated of the corresponding high-speed device, the medium-speed device and low - speed device, permit the target the three different effective time DEVSEL#.

The target device receives the effective address signal; the clock, a I/O reading data. And the main device with been at waiting state.

A PCI Bus Local Standard a stipulated for receiving the target are effective of FRAME#, in the first data transmission a PCI 16 clocks.

Therefore, the 16 clocks, the target in the I/O data card reading, and effective data driving to THE on, simultaneously effective TRDY# for marking wherein a driving the first a signal to an bus on.

The clock, the main device and target device of effective along the sampling to IRDY# and TRDY# while the lift of clock, indicated for data preparation instrument, the main device, data in reading the transmission of data.

Target sampling FRAME# invalid, indicated of which is a final data one.

Each converter with, and main device IRDY# invalidation and a driving the kbytes to enable.

The target device is at the time invalid IRDY# and DEVSEL#, and driving with an line.

The clock, bus and no-load state.

At the middle process, a sees are Figure 1, wherein the main device comprises a waiting state to the time of target device valid data, an line is provided with a no-load state, the invention is the days's THE no-load state, a PCI the output driving, a PCI to output to the high-impedance and. Is a PCI output are high-impedance, permits an I/O output driving, outputting the I/O address of the original THE base pin, which are matched auxiliary signal wire, an I/O card reading the interface signal of the operation, which with the operation is side of the I/O, with an I/O data from other/D wire, the lower part and a memory; and an I/O device with the data manipulation. Terminal the data driving to on bus, a whole PCI card reading the data manipulation.

Digital 2, 3 said chart is the invention embodiment SAID pin base and I/O pin multiplexing drawing leds. Although the invention is a voice on the surface, matched digital 1 is invention is the following: Is a PCI bus is arranged on the no-load state, a PCI receiving input signal of (OE) is, wherein the selection three said of matter is 220 and 320, so an input to the target device, wherein the address platform; the target device can rotate and address, decodingThe comprises an I/O data reading platform; the invalid PCI input permits the signal and PCI output permits the signal, and effective I/O output associated the signal and I/O input permits the signal, a selection three said of matter is 230 and 330, online output an I/O address signal of SAID, combining the I/O sensor (usually is READ and OE equisignal) and corresponding I/O device, and multiple time, online with the data from SAID to the main storage; The are PCI data platform; the invalid I/O output permits the signal and I/O input permits the signal, of the effective PCI output permits the signal, a selection three of the slide frame 210, 310 and driving the data to on bus, and a light of the PCI power, comprising TRDY#, DEVSEL#; and PCI card reading the data manipulation.

Although matter compromised of the claims a and the invention realizing method, and is the professional the technical, and multiple revisions, replacing, and equivalent replacing failed. Therefore, the invention's protection range of protecting of wherein the range is adhered is a standard.