Integrated circuit collector

The first integrated circuit connector related application citation This application claims the priority of the U.S. Provisional Patent Application serial number 60,325,107 filed on September 26, 2001.

TECHNICAL FIELD The present invention generally relates to integrated circuit connectors. More specifically, the present invention relates to a power transmission system, a signal transmission system, a package design system, a thermal management system, and an electromagnetic interference (EMI) emission control system for supporting the advancement of semiconductor technology for integrated circuits.

Background technique

I. Semiconductor technology consumers need innovative electronic products with more functions, better performance, smaller size, lighter weight, higher reliability, lower cost and faster time to market. Semiconductor technology is a core component of innovative electronic products that consumers expect. Over the years, advances in semiconductor technology have led to a tremendous increase in the functionality and performance of integrated circuit (IC) devices, while minimizing the size, weight, defects, and cost of integrated circuit 20 devices.

Historically, the number of transistors that can be mounted on semiconductor chips in the electronics industry has doubled approximately every eighteen months. This rapid development cycle enables new and innovative products to be quickly put on the market. For example, it took nearly thirty years for semiconductor manufacturers to perfect the microprocessor clock rate to 25 and run at 1GHz, while current manufacturers have reached 1GHz in less than eighteen months.

T 2GHz processor clock rate. Manufacturers predict that there are no fundamental obstacles to the rapid advancement of semiconductor technology in the next decade by manufacturing faster silicon transistors. These transistors are expected to be about 20 nanometers in size and will enable manufacturers to manufacture billions of transistors that operate at speeds close to 20 GHz and operate at voltages of less than 1 volt in the next few years.³⁰ microprocessor. These new transistors are used to control the flow of electrons in a microprocessor

02818928.0, like the first switch, will be turned on and off more than one trillion times per second.

This advancement in semiconductor technology will produce faster clock rates, higher power, lower power supply voltages, higher DC currents, higher transient currents, narrower voltage tolerances, higher non-uniform thermal densities, and electromagnetic Interfering with a higher frequency microprocessor. The additional benefits of these advancements include increased interconnect density, reduced board space and package size, and improved product manufacturing capabilities and reliability of microprocessors.

The specification requirements of microprocessors in the near future: operating voltage 1.0V, current 100A, !0 transient current 300A/microsecond, efficiency greater than 90%, stability within 5%, and voltage ripple less than 1%. These requirements represent a significant advancement beyond current microprocessor design. Microprocessors with these characteristics and requirements and future microprocessors with more demanding features and requirements will require new support systems, such as power transmission systems, signal transmission systems, packaging systems, thermal management systems, and electromagnetic interference ( EMI) emission control system.

Stopping power transmission involves supplying power to devices that need power. Traditionally, it is assumed that there is an ideal power supply, and power transmission is hardly considered until the end of the design. Printed circuit board (PCB) designers try to create an ideal power transmission system that has conventional power and ground planes in the printed circuit board and has wide and thick traces on the printed circuit board for various devices on the printed circuit board. Power distribution between. High-frequency ceramic capacitors control the high-frequency noise generated by the on and off transistors by short-circuiting the high-frequency noise to the ground. The lower frequency bulk capacitors (such as lithium capacitors) then recharge the high frequency ceramic capacitors. There are various rules of thumb for determining the amount of various types of capacitors required by various integrated circuits.

In order to electrically model the power transmission system, considerations include the inductance and resistance of the cables, connectors, printed circuit boards, pins, contacts, and components such as resistors and capacitors of the receiving device and the power supply. In the past, the voltage drop due to inductance (V=Ldi/dt) and resistance (V=IR) has been nearly negligible relative to the device tolerances in most systems. As with 30, a simple rule of thumb determines the decoupling method for high-frequency noise.

02818928.0 Each generation of semiconductor technology has reduced the power supply voltage to support the requirements of deep submicron semiconductor technology and improve reliability. Lower power supply voltage should reduce power consumption. However, even at lower power supply voltages, the power consumption of the microprocessor will continue to increase due to more transistors, increased transistor density on the die, thinner insulators that increase capacitance, and higher operating frequencies. The power consumption of the microprocessor continues to rise as much as three times every two years, and the power supply voltage of the microprocessor is close to 1.0V, according to the formula (P=CfV²), the power consumption (P) is related to the operating frequency (f), power supply voltage (V) and chip capacitance (C) of the microprocessor. For example, a microprocessor with a typical chip capacitance of 20 nanofarads, a power supply voltage of 1.65 volts, and an operating frequency of 1 GHz will consume 55 watts (0.020x1.65x1.65x1,000). For another example, a microprocessor with a typical chip capacitance of 40 nanofarads, a power supply voltage of 1 volt, and an operating frequency of 3 GHz will consume 120 watts (0.040x1.0x1.0x3,000) «According to the formula (P=VI) , Power consumption (P) is also related to power supply voltage (V) and current (I). The 15 formula shows that high power consumption (P) at low power supply voltage (V) requires high current (I) (I=P/V) to be sent to the microprocessor. Continuing the above two examples, a microprocessor with a power consumption of 55 watts and a power supply voltage of 1.65 volts requires a power supply current of 33 amperes (55/1.65), and a microprocessor with a power consumption of 120 watts and a power supply voltage of 1.0 volts needs The power supply current is 120 amperes (120/1), which shows an increase of about 3.6 times compared to the 33 ampere microprocessor.

:0 At these voltage and current levels, it is more difficult for the central power supply to deliver high current and low voltage power in the entire computer system due to the impedance level that produces unacceptable voltage drops along the distribution path. Computer systems currently use distributed power systems, which are used to transmit high-voltage and low-current electrical energy in the entire computer system, which is then converted into low-voltage and high-current according to the needs of the microprocessor. The voltage regulator or modular DC/DC converter used to provide the necessary low voltage and high current power is arranged on the motherboard as close to the microprocessor as possible to minimize the impedance and the resulting voltage drop. The placement of the power distribution path on the motherboard takes up valuable space available for other components.

Even if a distributed power transmission system is used, each part of the distribution path must still have low resistance

02818928.0 The first reactance to minimize the voltage drop generated. Generally, the voltage fluctuation at the voltage regulator is smaller than the voltage fluctuation at the microprocessor (for example, about half). Traditionally, connectors with high pin counts and large copper power/ground planes have been used to minimize impedance. However, these solutions also consume additional printed circuit board space and increase costs.

In a power distribution scheme, the microprocessor and the voltage regulator each form a module and rely on the corresponding socket to connect each module with the motherboard. The microprocessor can be mounted on the built-in board, and the motherboard has one socket for accommodating the voltage regulator and another socket for accommodating the built-in board. The microprocessor and voltage regulator are modular, making replacement quick and easy to achieve efficient manufacturing and service. The current flows from the voltage regulator through a path starting from the voltage regulator, through its socket, motherboard, built-in socket and built-in board, microprocessor package, and flows to the microprocessor at the end of the mold. This long path current flow causes impedance and voltage drops, which are undesirable for advanced microprocessor designs.

An alternative power system solution bypasses the motherboard and microprocessor socket. In this solution, the built-in board carries the microprocessor module and the voltage regulator. The current flows from the voltage regulator to the microprocessor through a path starting from the voltage regulator, through the voltage regulator socket, built-in board, microprocessor package, and at the end of the mold. Since this solution bypasses the motherboard and built-in sockets, the current flow path is shorter. Therefore, this scheme improves the impedance of the shorter path and the resulting voltage drop: 0.

One day, the voltage regulator may be integrated into the microprocessor package to make the current flow path very short, reducing the impedance and the resulting voltage drop. However, semiconductor technology is not advanced enough to provide this level of integrated system.

Microprocessor response time or transient current requirements (di/dt), that is, the rate of change of current demand, is another consideration related to the power supply. The changing computing requirements of the microprocessor require changing current requirements from the power supply. Computational requirements vary due to high clock speed circuits and power-saving design techniques, such as clock gating and sleep mode. These technologies result in rapid, unpredictable, large changes in power source current, eventually requiring hundreds of amperes in a few nanoseconds.

02818928.0 According to the formula (dV=IR+Ldi/dt), the current surge from the voltage regulator required by the microprocessor will cause unacceptable voltage spikes to the transmission voltage.

Attempts have been made to manage the surge current by arranging decoupling capacitors in the entire power transmission system, such as on the voltage adjustment module, the motherboard, the built-in printed circuit board, the mold package, and the mold itself. The decoupling capacitors are usually located on a circuit board outside the microprocessor package, and several discrete decoupling capacitors mounted near the microprocessor package on the circuit board are usually used. In this solution, conductive traces on the circuit board connect the decoupling capacitors to the power pins and ground pins on the microprocessor. In another approach, discrete decoupling capacitors are formed as part of an integrated circuit.

These decoupling capacitors are commonly used to ensure that the power system can provide inrush current to the microprocessor when needed. The decoupling capacitor connects the power supply to the power leads of the microprocessor. The amount of decoupling capacitors required depends on the power requirements of the microprocessor. The microprocessor can absorb the surge current it needs from the electric energy stored in the decoupling capacitor. Therefore, the decoupling capacitor stabilizes the power transmission system by storing the electric energy near the microprocessor to meet the requirements of the microprocessor. However, the use of discrete and widely installed decoupling capacitors not only increases the cost of the power transmission system, but also consumes additional area on integrated circuits or circuit boards or elsewhere.

.0 As the power demand of microprocessors increases, so does the demand for more decoupling capacitors, which require larger value or size decoupling capacitors and more space to accommodate them. Unfortunately, decoupling capacitors of larger value or size consume more area on the circuit board.

According to the formula (XL=2BfL), as the switching speed of the transistor increases, the amount of undesirable resistance caused by the inductance associated with the interconnection between the semiconductor die and the decoupling capacitor also increases. The longer the conductive path used to interconnect the decoupling capacitor and the semiconductor die in the microprocessor, the higher the inductance. The higher the operating frequency of the microprocessor, the higher the system resistance caused by the inductance, and the higher the resistance that produces a higher voltage drop. Therefore, it is desirable to arrange the decoupling capacitor as close to the semiconductor mold as possible by disposing the decoupling capacitor inside the microprocessor package, for example, as described above, so as to minimize the conductive path and thereby minimize the inductance.

02818928.0 Moreover, in addition to capacitance characteristics, capacitors also have inductance and resistance characteristics, and can be electrically modeled as a series RLC circuit. At higher frequencies, such as higher than 100 MHz, the inductance characteristics limit the effectiveness of conventional discrete decoupling capacitors. If the microprocessor requires a large inrush current, this residual inductance will produce unacceptable voltage drops and AC noise.

Historically, electrical energy has always been brought to the integrated circuit through the pins in the integrated circuit socket. As the power demand of the integrated circuit increases, additional pins will be required to meet the power. These additional pins increase the size of the integrated circuit package, thus occupying valuable W space on the circuit board. The increase in the number of pins also increases the amount of force required to insert the integrated circuit into its socket in the circuit board and to remove the integrated circuit from its socket in the circuit board. The power pins pass through the same surface of the integrated circuit, usually the bottom surface, and at high density, the power pins and signal pins should be isolated from each other to prevent crosstalk and noise.

Therefore, there is a need for a transmission system for delivering low-voltage, narrow-voltage tolerance, high-current, and high-transient current power to high-performance integrated circuits such as microprocessors, minimizing cost and space, and improving reliability. Electric system.

III. Signal Transmission Signal integrity is a complex research field involving digital and analog design, circuit and transmission line theory, and phenomena such as crosstalk, ground bounce, and power supply noise. Although signal integrity is always important, in the past, the switching speed of microprocessor transistors was so slow that the digital signal actually resembled a high pulse representing 1 and a low pulse representing 0. Electrical modeling of signal propagation is often unnecessary. Unfortunately, at todays 1GHz 25 and above microprocessor speeds, even simple passive components of high-speed designs such as wiring, printed circuit boards, connectors, and microprocessor packages will affect the waveform and signal waveforms. The voltage level has a significant effect. In addition, these passive components can produce glitches, resets, logic errors, and other problems.

Usually, microprocessors use such as substrate grid array (LGA), ball grid array (BGA),

02818928.0 Pin Grid Array (PGA) and solder-like electroplating (ie: metal-to-metal) connection to contact the motherboard to transmit signals between the microprocessor and the motherboard. According to the formula (XL=23fL), as the switching speed of the transistor increases, the amount of undesired resistance caused by the inductance associated with the conductive interconnection between the semiconductor die located inside the microprocessor and the motherboard also increases. The longer the conductive path used to interconnect the semiconductor die and the motherboard in the 5 microprocessor, the higher the inductance. The higher operating frequency of the microprocessor produces a higher resistance due to the inductance on the signal path, and this resistance produces a higher voltage drop in the signal level. Therefore, it is desirable to minimize the inductance of the signal path as the operating frequency of the microprocessor increases. Other disadvantages of signal transmission through conductive contacts are disclosed in US Patent No. 5,629,838 issued on May 13, 1997. There is an engineering trade-off between increasing the desired operating frequency of the microprocessor and the signal integrity of the system.

Therefore, there is a need for a system that can increase the operating frequency of the microprocessor without deteriorating signal integrity. This system will make the interconnection technology used in the design of high-speed digital signals the highest performance and the lowest cost.

IV. Integrated Circuit Packaging Design The advancement of semiconductor technology has provided microprocessors with higher performance and smaller sizes, which directly affects the design of microprocessor packaging. Factors related to microprocessor package design include: current per contact and per socket, number of ground pins and power pins, number of signal contacts and number of signal contacts per square area, contact pitch, total number of contacts And the total number of contacts per square area, contact force along the Z axis, matching contact height, signal bandwidth, semiconductor die size and other factors.

Increasing the number and power of transistors in a microprocessor generally increases the current per contact and per socket in addition to increasing the number of ground pins and the number of power pins. Increasing the performance of the microprocessor will require increasing the number of signal contacts and the size of the semiconductor die. Increasing the power and performance of the microprocessor will increase the total number of contacts and decrease the contact pitch. Increasing the total number of contacts while reducing the contact spacing will increase the contact force required along the Z axis, which may require an increase in the mating contact height. Increasing the operating frequency of the microprocessor will reduce the signal bandwidth. Therefore, it should be understood,

02818928.0 There is an engineering compromise between these factors to make a microprocessor with the best package design.

V. Advances in thermal management electronic packaging design provide higher performance and smaller size devices, which leads to increased heat generation and heat density, which in turn may make thermal management a higher priority in package design to keep the device reliable Sex.

For microprocessors, improved performance, increased integration levels, and die size optimization have led to increased non-uniform heat density in certain areas of the microprocessor die. The calorific value and heat density continue to increase with more advanced semiconductor technology. The reliability of the microprocessor depends exponentially on the operating temperature of the die joint, and the operating temperature depends on the power consumption of the transistor with the die joint.

The thermal management of the microprocessor is related to the thermal management of the voltage regulator. The efficiency of the voltage regulator must be considered together with the power consumption of the microprocessor. For example, a voltage regulator that operates at an efficiency of 85% and drives a microprocessor with a power consumption of 120 watts consumes about 18 watts of power. This power must be drawn from the voltage regulator and microprocessor to cool the device and maintain its reliability. Therefore, as described above, there is a gap between setting the voltage regulator close to the microprocessor to minimize the impedance and the voltage drop generated, and setting the voltage regulator away from the microprocessor to minimize heat generation and heat density. Engineering compromise.

Therefore, there is a need for a thermal management that can place a high-power microprocessor close to the voltage regulator to minimize the impedance and the resulting voltage drop, while effectively dissipating the heat generation and heat density, so that the 25 reliability is large. solution.

VI. Electromagnetic interference Electromagnetic interference (EMI) emission sources include transistors in microprocessors and signal paths on circuit boards and cables. Microprocessors are one of the largest electromagnetic sources in computer systems. Today, the frequency of microprocessor clock signals has increased to 1 GHz and above. At 1GHz, these times

02818928.0 The second clock signal can generate harmonic frequency signals up to 5GHz. These two kinds of signals generate electromagnetic interference waves whose wavelength is inversely proportional to the signal frequency (that is, the higher the frequency, the shorter the wavelength).

Generally, conductive shields or covers are used to control electromagnetic interference. The shield is grounded to provide an electromagnetic interference dissipation path to prevent it from interfering with other circuits. The shield usually contains holes for thermal management to generate airflow to cool the device that generates electromagnetic interference. However, the large holes in the shield can allow electromagnetic interference to leak through the shield. In this way, the size of the shield hole must be designed so that the electromagnetic interference does not leak out without restricting the air flow for cooling the device. High-frequency signals require smaller holes in the shield for electromagnetic interference containers, but smaller holes limit the airflow available for cooling. Therefore, there is an engineering compromise in designing the size of the holes in the shield for cooling and electromagnetic interference containment purposes.

The shielding can be at the microprocessor level or the chassis level or both. The microprocessor generates high-frequency harmonic signals that generate electromagnetic interference. In this way, placing the shield close to the microprocessor can effectively contain the harmonic signals near the electromagnetic interference source. Localized airtightness prevents electromagnetic interference from interfering with other circuits in the computer system, but it also restricts the airflow required for the microprocessor to dissipate heat. Alternatively, the chassis of the computer system can be used as a shield, which improves the surrounding area of the microprocessor. Airflow, but it can cause electromagnetic interference to interfere with other circuits in the system. Chassis-level solutions require small holes in the chassis for electromagnetic interference closure, but reduce airflow.

Grounding the radiator located near the microcomputer is another way to reduce electromagnetic interference.

However, electromagnetic interference from the microprocessor coupled with the heat sink may cause the heat sink to act as an antenna and radiate electromagnetic interference. Grounding the heat sink through the microprocessor package is difficult, and although grounding the heat sink can reduce electromagnetic interference, the solution 25 alone cannot adequately pass the required FCC emission test. May need additional shielding to shield electromagnetic interference. Therefore, there is a need for an electromagnetic interference containment system for sealing electromagnetic interference from high-frequency signals without compromising the thermal management of the system.

In short, systems related to power transmission, signal transmission, package design, thermal management30, and electromagnetic interference (EMI) emission control for integrated circuits are needed to support the future and current semiconductor technology.

02818928.0 First improvement.

SUMMARY OF THE INVENTION Therefore, the general purpose of the present invention is to provide an improved power transmission system and device that overcomes the above-mentioned shortcomings when transmitting power to an integrated circuit without occupying a large amount of space on the circuit board.

Another object of the present invention is to provide a system and apparatus for supplying power to an integrated circuit by using one or more capacitors supported by a cover or the like engaged with the integrated circuit.

Another object of the present invention is to provide a connector for an integrated circuit, the connector includes a power transmission device in the connector body, and preferably can supply power to the integrated circuit along the side or top of the integrated circuit, which makes The number of conductive pins (leads) required by the integrated circuit is reduced, which in turn reduces the force required to insert the integrated circuit into the connector and remove the integrated circuit from the connector, and free up additional pins for integration Used in signal transmission between circuits.

Another object of the present invention is to provide a power transmission component in the form of a socket or a cover. The power transmission component includes a plurality of planar capacitors formed inside. The capacitors include at least two metal plates through which the two metal plates pass. The dielectric materials in the form of thin films are preferably separated from each other, and these capacitors are also separated from each other from the power transmission components, so that the capacitors provide multiple different voltages to different areas of the integrated circuit.

Another object of the present invention is to provide a power transmission component for integrating one or more capacitors inside and including a plurality of respective contact arms. The contact arms extend from the power transmission component so as to be integrated with the integrated circuit. The leads engage, and these leads are arranged to surround the top, bottom, or sides of the integrated circuit.

Another object of the present invention is to provide a microprocessor package that occupies less space on the circuit board and does not rely on electroplating coupling to match the leads on the circuit board. The package includes 30 for accommodating The housing of the integrated circuit, the housing has an intermediate for forming the housing wall

02818928.0 The first quality board, the shell also has a plurality of contact pads formed on its inner surface, the leads of the integrated circuit are connected to the contact pads, and the dielectric board connects the inner contact pads of the shell with the contact pads arranged on the circuit board. The contact pads on the mounting surface are separated, and the internal contact pads of the housing are aligned with the corresponding contact pads on the circuit board to realize capacitive coupling between the two, thereby realizing signal transmission from the integrated circuit 5 to the circuit board. The housing also has at least one capacitor supported by it, and the capacitor realizes power supply to the integrated circuit.

Another object of the present invention is to provide a device for supplying power to a microprocessor in a capacitive manner and including a device for dissipating heat generated by the microprocessor during operation.

The present invention relies on its unique and novel structure to achieve these and other objectives.

The power transmission system of the present invention includes: a power supply, a voltage regulator module, and a decoupling capacitor in the form of a discrete and/or integral capacitor. The voltage regulator module and the decoupling capacitor 15 are each located in a connector engaged with an integrated circuit. The connector may take the form of a cover, socket, or frame that engages the integrated circuit in a manner such that the system delivers power to one or more sides of the integrated circuit. The system may include a signal transmission system that couples signals from the integrated circuit through conductors or printed circuit board traces to a remote circuit located in a connector on the circuit board on which the integrated circuit is located.

»0 The package design system of the present invention enables signals and/or power to be coupled to one or more surfaces on the integrated circuit using connectors, which are located on the outside of the semiconductor package, flush with the semiconductor package, and the semiconductor package The recess or interior of the piece. The package design system preferably enables the transmitted signals to have different frequencies, such as high and low frequencies with different types of signal interfaces, such as conductance, capacitance, inductance, light, transmission lines, and wireless types.

The present invention also conceives a thermal management aspect for its various systems, in which a heat sink and a fan can be installed on the connector in a way so that the heat sink is in contact with the heating surface of the integrated circuit 30, so that the heat is dissipated The device can be integrated by integrated circuits and power transmission systems, including

02818928.0 The heat dissipation generated by the voltage regulator module used internally.

The present invention can also utilize an electromagnetic interference control system formed as a part of the connector for shielding electromagnetic interference radiated by the integrated circuit. The advantages of all these systems are the increase in interconnect density, the reduction in the space occupied by the circuit board and the volume of the integrated circuit package, and the improvement in product manufacturing capability and reliability.

These and other objects, features and advantages of the present invention will be clearly understood by reading the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS In this detailed description, reference will be made to the accompanying drawings from time to time. In the accompanying drawings: Figure 1 is a functional diagram of the broadest aspect of the present invention, showing the correlation between various system aspects of the present invention and integrated circuits Figure 2 is a detailed block diagram of the system of Figure 1; Figure 3 is a table listing alternative positions of various aspects of the system of Figure 2 and listing alternative connections between the system aspects; Figure 4A, Figure 4B, Figure 4C, Figure 4D and 4E are schematic diagrams of the integrated circuits of FIGS. 1, 2 and 3, respectively showing increasing integration levels 0, 1, 2, 3, and 4 and aspects of the package design system of the present invention; FIG. 5 is FIG. 4 Figure 4E is a schematic diagram of the integrated circuit, showing the power and signal connections of the IC package design according to the principles of the present invention; Figure 6A is the same diagram as Figure 5, but showing high frequencies coupled to different sides of the integrated circuit And low-frequency signal interface; Figure 6B is the same diagram as Figure 5, but shows the first (high) and second (low) frequency signal interface pair coupled to the same side of the integrated circuit; Figure 7A is the same as Figure 5 The same figure, but showing the first and second signal type interfaces coupled to different sides of the integrated circuit; FIG. 7B is the same diagram as FIG. 5, but showing a different first and second signal type interfaces coupled to the same side of the integrated circuit One and second type signal interface;

02818928.0 Figures 8A, 8B, 8C, and 8D are schematic cross-sectional views of the integrated circuit of Figures 4C and 5, showing the semiconductor package located on the outside of the semiconductor package, flush with the semiconductor package, the recess or the semiconductor package Internal signal connector and/or power connector;

9A, 9B, and 9C are schematic diagrams of the integrated circuits shown in FIGS. 5 and 8 to 8D, showing the signal contacts and/or power contacts on the respective top, bottom, and/or sides of the integrated circuit The position of the point; Figures 10A, 10B, and 10C show plan views of the integrated circuit shown in Figure 8A, Figure 8B, Figure 8C or Figure 8D and Figure 5, the integrated circuit having a location representing a preferred embodiment according to the present invention The signal W contacts and/or power contacts on the top, side, and/or bottom of the integrated circuit of the package design system; FIG. 11 is a schematic view of the integrated circuit of FIG. 5 in the connector; A schematic view of the integrated circuit of FIG. 11 in a connector that is a cover for the integrated circuit; FIG. 12B is a schematic view of the integrated circuit of FIG. 11 in a connector formed as a socket for accommodating the integrated circuit; FIG. 12C is a schematic view of the integrated circuit of FIG. A schematic view of the integrated circuit of FIG. 11 formed in a connection point of a frame for accommodating an integrated circuit; FIG. 13 is a schematic view of the integrated circuit of FIG. 11 coupled with a remote circuit located in a connector or on a circuit board;! 0 FIG. 14 is a schematic view of the integrated circuit of FIG. 13 coupled together in a stacked configuration;, 15 is a schematic view of the integrated circuit and remote circuit of FIG. 13 or 14, each circuit includes a voltage regulator module and a decoupling capacitor located in the connector; FIG. 16 is the integrated circuit and remote circuit of FIG. 13 or 14 A schematic view of the circuit, each circuit includes a voltage regulator module and a decoupling capacitor; Figure 17 is a schematic view of the integrated circuit and remote circuit of Figure 13 or Figure 14, each circuit includes a voltage regulator on the circuit board Module and decoupling capacitor; Figure 18 is a schematic view of the integrated circuit and remote circuit of Figure 13 or Figure 14, each circuit includes a voltage regulator module located on the conductor and a decoupling capacitor located in the connector:

02818928.0 Figure 19 is a schematic view of the integrated circuit and remote circuit of Figure 13 or Figure 14, each circuit includes a voltage regulator module located on the circuit board and a decoupling capacitor located in the connector; Figure 20 is related to the thermal management system A schematic view of the integrated circuit of FIG. 11 combined with an electromagnetic interference (EMI) control system; FIG. 21 is a secondary semiconductor package with a vertical semiconductor die and a capacitive signal interface and power supply to the integrated circuit side constructed according to the principles of the present invention 22 is a cross-sectional view of a secondary semiconductor package with a flip-chip semiconductor die and using a capacitive signal interface and power supply to the integrated circuit side constructed in accordance with the principles of the present invention; Figure 21 is a cross-sectional view of the integrated circuit package of Figure 21; Figure 24 is a cross-sectional view of a secondary semiconductor package with a vertical semiconductor die and a capacitive signal interface and power supply from the sidewall of the package: Figure 25 is a cross-sectional view of the package A cross-sectional view of the second-level semiconductor package of the present invention with a flip-chip semiconductor die, a capacitive signal interface, and power contacts on the top; Figure 26 is a cross-sectional view of a flip-chip semiconductor die, a capacitive signal interface, and power contacts on the top of the integrated circuit A cross-sectional view of a first-level semiconductor package; Figure 27 is a cross-sectional view of the integrated circuit of Figure 26 carried by a socket connector that supports a decoupling capacitor and a heat sink, similar to those shown in Figures 12B and 19 ; FIG. 28 is a perspective view of an integrated circuit package containing the system of the present invention, the integrated circuit package being formed as a secondary semiconductor package carried in a connector formed as a cover for supporting a decoupling capacitor and a heat sink And socket; Figure 29 is an exploded view of the system components of Figure 28; Figure 30 is a cross-sectional view of the components of Figure 28 taken along the line 30-30 of Figure 28; Figure 31 is an alternative system component constructed in accordance with the principles of the present invention Figure 32 is a perspective assembly view of another embodiment of the power transmission component of the present invention taken from the lower side, showing an alternative device for supplying power to its capacitor structure; wherein the integrated circuit is formed as The secondary semiconductor package shown in FIG. 4C; FIG. 33 is a perspective view of another system component cover used with the secondary semiconductor package shown in FIG. 4C and having an external device for connecting with a power source;

02818928.0 FIG. 34 is a perspective view of an alternative embodiment of a system component using the capacitor power transmission structure of the present invention located at the upper position of the chip package and having a device for communicating with the heat sink; FIG. 35 is along the line of FIG. 34 A cross-sectional view taken from line 34-34; FIG. 36 is a perspective view taken from the lower side of an alternative embodiment of the capacitor structure used in the power transmission system of the present invention and used to supply different levels of electricity to the integrated circuit; 37 is the same view as FIG. 36 but taken from a different angle, with the housing removed for clarity; FIG. 38 is a cross-sectional view of the capacitor structure of FIG. 37 taken along the line 38-38 of FIG. 37; FIG. 39 is based on Partial end view of another embodiment of a capacitor structure constructed in accordance with the principles of the present invention and having interleaved power leads extending therefrom; FIG. 40 is an enlarged perspective detailed view of a corner of another embodiment of a power transmission structure constructed in accordance with the principles of the present invention , Showing the use of more than two capacitor plates; Figure 41 is a perspective view of the power transmission component of the present invention installed in a housing mounted on an integrated circuit. For clarity, the housing is shown as transparent; Figure 42 is the view of Figure 35 Sectional end view: Figure 43 is a perspective view of a connector structure constructed in accordance with the principles of the present invention; Figure 44 is an alternative to using multiple discrete power capacitors constructed in accordance with the principles of the present invention and supported in a housing for supporting integrated circuits An exploded view of the power transmission system; Figure 45 is the same diagram as Figure 44, but the components are assembled together on the circuit board: Fig. 46 is a cross-sectional view of the assembly of Fig. 45 taken along line 46-46 of Fig. 45; Fig. 47 is a perspective view of the assembly of Fig. 45 with heat dissipation components located on the integrated circuit and the assembly; Fig. 48 is a view An enlarged detailed view of a part of the assembly of 45, showing a discrete capacitor used inside; FIG. 49 is a cross-sectional view of the connector assembly of FIG. 47 taken along line 49-49 of FIG. 47; FIG. 50 is FIG. 45 An enlarged detailed view of a corner of the component, showing the device used to hold the component in place;

02818928.0 Figure 51 is an enlarged detailed view of an alternative configuration of a socket connector constructed in accordance with the principles of the present invention, showing the use of wiring contacts for contact with integrated circuits and separate capacitors: Figure 52 is the connector of Figure 51 A perspective view of the assembly; FIG. 53 is an enlarged detailed cross-sectional view of the internal area "A" of the connector assembly of FIG. 52; FIG. 54 is a detailed exploded view of a part of the connector assembly of FIG. 52, showing the location of the discrete capacitors; Figure 55 is a perspective view of a lead-containing carrier tape used in the connector assembly of Figure 52; Figures 56 and 57 are underside perspective views of the cover member used in the system shown in Figure 30; and Figure 58 is An enlarged detail of an alternative way of installing discrete capacitors in the connector of the present invention.

DETAILED DESCRIPTION The present invention is directed to an improved power transmission system 12, a signal transmission system 14, a package design system 16, a thermal management system 18, and an electromagnetic interference emission control system 20 for an integrated circuit 22. Current and foreseen advancements in semiconductor technology have produced and will produce products such as microprocessors with faster clock rates, higher power, lower supply voltages, higher DC currents, higher transient currents, narrower voltage tolerances, Integrated circuits with higher non-uniform heat density and higher electromagnetic interference emission frequency. The additional benefits of these advancements include increased interconnect density and improved product manufacturing capabilities and reliability of microprocessors. Semiconductor manufacturers predict that microprocessors in the near future will usually require: operating voltage of 1.0V or less, current of 100A or more, transient current of 300 Aφ seconds or faster, voltage regulator efficiency greater than 90%, and voltage regulation rate of 5% Within or below, and the voltage ripple is less than 1%. These requirements indicate significant progress beyond the current microprocessor design. Microprocessors with these characteristics will need to be used for power transmission, signal transmission, packaging, and thermal management, just like future packages. , And a new support system for electromagnetic interference emission control. The present invention is aimed at the improvement of these systems and other systems, all of which will favorably support advanced semiconductor technology.

Fig. 1 to Fig. 20 generally shows, and Fig. 2 to Fig. 58 show the integrated circuit in more detail.

02818928.0 The power transmission system 12, the signal transmission system 14, the package design system 16, the thermal management system 18, and the electromagnetic interference emission control system 20 for the first road 22 are all in the different embodiments of the present invention described herein. Figure 1 shows a general block diagram of an electronic device or system 10, which includes a power transmission system 12 for an integrated circuit 22, a signal transmission system 14, a package design system 16, a thermal management system 18, and electromagnetic interference emission Control system 20. FIG. 2 shows a more detailed block diagram 32 of the power transmission system, signal transmission system, and package design system of FIG. 1, which is a diagram of the power transmission system 12, the signal transmission system 14 and the package design system 16 for the integrated circuit 22. The relationship is explained.

Figure 3 is a table 56 listing alternative locations of the system blocks shown in Figure 2 and alternative connections between these system blocks. 4 to 10 show various package design systems 16 for the integrated circuit 22 shown in FIGS. 1 to 3. 11 and 12A, 12B, and 12C show the connector 112 shown in FIG. 5 formed as a cover, socket, or frame or located on a printed circuit board (PCBJ114 and having conductors 116 and/or The signal connector 26 and/or the integrated circuit of the power connector 24 of the printed circuit board trace 118. Figures 13 and 14 show the remote circuit shown in Figure 11 and located in the connector 140 or on the printed circuit board 114. 52. Two configurations of the integrated circuit 22 coupled to each other. Figures 15 to 19 show one of those shown in Figures 13 and 14 with each located in the connector 112, on the conductor 116, or on the printed circuit board 114, or Any combination of the voltage regulator 38 and the decoupling capacitor 42 of the integrated circuit 22 and the remote circuit 52. Fig. 20 shows the thermal management system 18 and the electromagnetic interference emission control system 20 shown in Fig. 1 shown in Fig. 11 More detailed integrated circuit 22. Figure 21 and Figure 22 show the package design system 16 for the integrated circuit 22 with power contacts located on the side of the integrated circuit 22. Figure 23 shows the use of Figure 21 The assembly of the integrated circuit 22 of the system 10 is shown. FIGS. 24 to 26 show the package design system 16 for the integrated circuit 22 with power contacts located on the top of the integrated circuit 22. FIG. 27 shows the assembly of the system 10 using the integrated circuit 22 shown in FIG. 26. Figures 28 to 31 show various assembly diagrams of the system 10. FIGS. 32 and 33 show a connector 112 formed as a socket or a cover with a decoupling capacitor 42 formed as an integral capacitor₀34 to 44 show various embodiments of the decoupling capacitor 42 formed as an integral capacitor carried by a single or integral connector 112 formed as a cover, socket, or frame. Figure 45~Figure 60 show the

02818928.0 Various embodiments of the decoupling capacitor 42 formed as a plurality of discrete capacitors carried by the connector 112 formed as a cover, socket, or frame.

Referring back to FIG. 1, this figure shows a block diagram of the electronic device 10, which includes a power transmission system 12 of an integrated circuit 22, a signal transmission system 14, a package design system 16, a thermal management system 18, and an electromagnetic interference control system 20 -The present invention achieves its maximum efficiency when used with integrated circuits in the form of microprocessors used in the computer field, but it should be understood that the principles and structures of the present invention can be applied to other integrated circuits used in other applications. The power transmission system 12 supplies power to the integrated circuit 22, and the signal transmission system 14 transmits signals to or from the integrated circuit 22. The package design system involves the composition of the package or housing that can hold the integrated circuit 22, while the thermal management system 18 is used in the integrated circuit

During the operation of 22, the integrated circuit 22 is cooled, and the electromagnetic interference control system 20 shields electromagnetic interference from or toward the integrated circuit 22.

The power transmission system 12 is coupled with the integrated circuit 22 by means of a power connector 24, which preferably includes a power component and a ground component (not shown). Power connector

24 is illustrated in Figures 1 and 2, and is preferably a bidirectional connector, which means that power is transmitted from the power transmission system 12 to the integrated circuit 22 via the power path, and also that the ground path leads from the integrated circuit 22 to the integrated circuit 22. Electric system 12.

! 0 The signal transmission system 14 is coupled to the integrated circuit 22 by means of a signal connector 26. The signal connector 26 may include one or more signal paths so that a single signal can be transmitted along a single path and multiple signals can pass through Transmission on a single path or multiplexing via one or more paths. The signal connector 26 is also preferably a two-way connector, which means that the signal is transmitted from the integrated circuit 22 along the signal transmission system 14 and the signal is transmitted from the signal transmission system 14 to the integrated circuit 22. This signal usually includes data and/or control information.

The package design system 16 is generally inherent to the integrated circuit 22, and includes the structure of the integrated circuit 22 working with the various aforementioned systems 12, 14, 18, and 20 in a manner 30.

02818928.0 finished. Preferred thermal management system 18 optionally directly coupled or mounted to the integrated circuit 22, integrated circuit and the heat generating surface facing, and preferably above the thermal connector showing the heat flow path 28. The thermal connector 28 is shown as a two-way connector to indicate that heat is dissipated from the integrated circuit 22 to the thermal management system 18 and that cooling is directed from the thermal management system 18 to the integrated circuit 22.

The electromagnetic interference control system 20 is coupled with the integrated circuit 22 through an electromagnetic interference connector 30. The electromagnetic interference connector 20 represents a path of electromagnetic interference 30. The electromagnetic interference connector 20 is shown as a two-way connector, which is used to indicate that the electromagnetic interference 30 is generated and radiated by the integrated circuit 22 and radiated to the integrated circuit 22 by other circuits.

The integrated circuit 22 includes a semiconductor device having one or more of the characteristics and requirements described above for supporting advanced semiconductor technology. The integrated circuit 22 is preferably a microprocessor, but may also be any other type of signal processor, such as a digital signal processor (DSP) or an application specific integrated circuit (ASIC). Alternatively, in suitable applications, the integrated circuit 22 may be of another type, such as a storage device, a controller, a transmitter, or a receiver.

The electronic device or system 10 of FIG. 1 represents any type of electrical and/or mechanical system that uses integrated circuits, such as computers, telecommunications, and medical devices and systems. Computers usually include: workstations, desktop and notebook computers, handheld computers, personal digital assistants, and so on. Telecommunication devices and systems may include: communication systems, satellite systems, microwave systems, land-based telephone exchange systems, Internet systems and wireless telephone systems, and'Internet systems such as servers and routers. Medical devices and systems include: diagnosis, analysis and processing devices and systems, etc. All these devices may or may not be portable devices. A "portable" device generally refers in the art to a device with a power transmission system that is temporary and requires regular charging. The portable device draws direct current (DC) power from the power transmission system 12 through a rechargeable or non-rechargeable direct current power source.

A non-portable electronic device is a device having a fixed power transmission system for pumping electricity from an AC power socket to the power transmission system 12 in an alternating current (AC) form. Generally, these devices convert alternating current to direct current because the integrated circuit 22 draws direct current. However, in a certain

02818928.0 In some applications, the integrated circuit 22 can extract alternating current.

2 is a detailed block diagram 32 showing the power transmission system 12, the signal transmission system 14 and the package design system 16 for the integrated circuit 22. The power transmission system 12 includes: a power supply 34; a connector 36, which is located between the power supply and the voltage regulator module; a voltage regulator module 38; a connector 40, which is located between the voltage regulator module and the decoupling capacitor 42; 44, which is located between the decoupling capacitor and the integrated circuit; and, if desired, the connector 54, which is located between the voltage regulator module and the integrated circuit. The signal transmission system 14 includes a remote circuit 52 and a connector 50 between the remote circuit 52 and the integrated circuit, and the package design system 16 preferably includes an integrated circuit power connector 46 and an integrated circuit signal connector 48.

In operation, the power supply 34 can generate relatively coarsely regulated direct current at the power connector 36. The voltage regulator module 38 converts the coarse-adjusted direct current into a relatively fine-adjusted direct current downstream of the power connector 40, and sends the direct current to the decoupling capacitor 42 as needed, and the decoupling capacitor 42 stores a predetermined amount of the adjusted direct current. DC power is supplied to the integrated circuit along the power connector 44 to its power connector or input 46. Alternatively, the voltage regulator module 38 may directly supply the adjusted DC power to the integrated circuit power connector 46 of the integrated circuit without using the decoupling capacitor 42. The integrated circuit signal connector 48 transmits and receives signals to and from the remote circuit 52 through the signal connector 50 respectively.

In the power transmission system 12, each of the power connectors 36, 40, 44, and 54 is shown as a two-way connector, which is used to indicate that the power component and the ground component extend between adjacent system blocks. The power connector 24 in FIG. 1 is the same as the power connector 44 in FIG. 2. Similarly, as described above with reference to the signal connector 26, the signal connector 50 is shown as a two-way connector, used to indicate the routing of signals from the integrated circuit 22 to the remote circuit 52, and to indicate the routing of signals from the remote circuit 52 to the integrated circuit 22. Similarly, the signal connector 26 in FIG. 1 is the same as the signal connector 50 in FIG. 2.

As shown in row 2 of column A of table 56 in FIG. 3, the power supply 34 is preferably located in the electronic device

02818928.0 The remote location within the first or system 10. The remote location may be any location suitable for transmitting power to the electronic device or system 10. Therefore, if the electronic device or system 10 has a housing, enclosure, etc., the power source may be located inside or outside of the housing, enclosure, etc. Preferably, the power supply 34 will be located inside the housing and mounted to a structure such as a chassis or circuit board. If the power supply 34 is located on the outside of the housing, the power supply can generally be mounted on the outside of the housing. The power supply 34 is any type of device for generating electricity and preferably at or along the power connector 36 transforming electricity in the form of alternating current (AC) into electricity in the form of direct current (DC). As mentioned above, this conversion of alternating current to direct current is typical in non-portable electronic devices. Alternatively, the power source 34 may directly generate DC power from a DC power source 10 such as a battery, a capacitor, or the like. The power supply 34 preferably generates relatively coarse-regulated DC power to minimize the cost and complexity of the power supply 34.

The power supply 34 will generally generate a higher voltage and lower current direct current at the power connector 36, which is well known in the power supply field. However, the integrated circuit 22 may require a lower voltage and higher current direct current. Therefore, according to the preferred embodiment of the present invention, in the occasion of DC conversion from high voltage and low current to low voltage and high current, as well as power connectors for high voltage and low current DC power and low voltage and high current DC power Special consideration is given to the location and type of power connectors.

The advantage of high-voltage, low-current direct current is that power can be transmitted through power connectors such as wiring or circuit board traces that are made of light-weight and appropriate conductive materials. The conductive materials minimize the cost of power connectors. . These conductive materials may include metals, conductive inks, and the like. The trace design on the circuit board forming the power connector will generally determine the maximum amount of conductive plating on the circuit board. The conductive plating thickness on the circuit board is the same between the two ends of the entire circuit board. This is because it is not cost-effective to selectively apply different amounts or thicknesses of plating on different areas of the circuit board. The cost associated with circuit board power connectors can sometimes drive up the cost of the circuit board. For example, one ounce of copper plating is usually used to transmit the high-voltage, low-current direct current from the power supply 34 to various electrical components mounted on the circuit board via traces on the circuit board. In contrast, if the power supply 34 were to output low voltage and high current electricity, four ounces of copper plating would be required on the circuit board to transfer the same amount of electricity.

02818928.0 The components sent to the circuit board. Such a circuit board with four times the amount of plating is obviously more expensive.

According to the preferred embodiment of the present invention and as described in detail below, the circuit board traces used to form the power connector on the circuit board preferably transmit high-voltage, low-current direct current rather than low-voltage, high-current direct current, so that the circuit The cost of the board is minimal. In this case, the conductor transmits the low voltage, high current direct current directly from the voltage regulator module 38 and/or the decoupling capacitor 42 to the integrated circuit 22 without passing through the circuit board traces.

The voltage regulator module 38 may be any device for converting the high-voltage, low-current direct current at the power connector 36 into a low-voltage, high-current direct current suitable for the integrated circuit 22. Preferably, the voltage regulator module 38 generates relatively fine-tuned DC power, so as to minimize the cost and complexity of the voltage regulator module 38 and maximize the performance of the voltage regulator module 38. The terms "coarse" and "fine" as well as "high" and "low" used herein are relative terms used to distinguish the performance and operation of the power supply 34 and the voltage regulator module 38, and are not used to be restricted to any Specific value or level. It is desirable that the voltage regulator module 38 is constructed as a module of discrete and/or integrated circuit components and, if necessary, mounted on a separate circuit board. Alternatively, the voltage regulator module 38 may be composed of only discrete circuit components or only integrated circuit components as necessary or required.

The decoupling capacitor 42 may include any type of capacitor used to decouple electricity from the integrated circuit 22. As mentioned above, the advantageous aspect of decoupling capacitor 42 is to provide high transient current to integrated circuit 22 when needed. The decoupling capacitor 42 may be formed of a separate discrete capacitor or an integral capacitor. Discrete capacitors include (but are not limited to) ceramic, bare or gel (for example, enclosed aerogel) capacitors with lead or surface mount 25 end connectors. The capacitor also includes chip capacitors. The advantage of discrete capacitors is that they provide predetermined specifications and have well-known dimensions. The connection with discrete capacitors can use conductors such as stamped single-stranded or multi-stranded wires, stamped and formed, blanked leads, and the like. The discrete capacitors described above may be formed integrally with the carrying lead frame, and may include larger parallel plates separated by suitable dielectric materials. The integral capacitor can be rigid or flexible, and can use solid

02818928.0 The formation of the first body, liquid, paste, gel or gas. The advantage of the monolithic capacitor is that it can achieve customized specifications, shape and composition. The decoupling capacitor 42 will be described in further detail below.

Each of the power supply 34, the voltage regulator module 38, and the decoupling capacitor 42 can be combined in any suitable manner to form a single or integral module, device, or component. Preferably, the power supply 34, the voltage regulator module 38, and the decoupling capacitor 42 are constituted separately or alternatively. The power supply 34 and the voltage regulator module 38 can be designed as a single unit for generating low voltage, high current, and fine-tuned direct current. Integrated device. In addition, the voltage regulator module 38 and the decoupling capacitor 42 can be designed as a single integrated device capable of generating decoupling, low voltage, W high current, and fine-tuned direct current.

The integrated circuit 22 may draw power from the decoupling capacitor 42 through the power connector 44, or may draw power from the voltage regulator module 38 through the power connector 54 as desired. Generally, the specifications of the integrated circuit 22 will specify the required power output from the decoupling capacitor 42 and/or the voltage regulator module 38. If the integrated circuit 22 requires high transient currents that cannot be met by the voltage regulator module 38 alone, an appropriate amount of decoupling capacitor 42 is required. Alternatively, if the voltage regulator module 38 can meet the transient current required by the integrated circuit 22, the discontinuous need for decoupling capacitor> 42.

The power connector 44 includes any type of connector, including, for example, conductance, capacitance, inductance, and similar connectors. The signal connector between the integrated circuit and the circuit board may include solder, substrate grid array (LGA), pin grid array (PGA), ball grid array (BGA), spring contacts, and other similar connectors. The capacitive signal interface provides an interface for transmitting signals between two conductive plates of suitable size and separated by a suitable dielectric material. The inductance 25 signal interface provides an interface for transmitting signals between two conductors that have a specific orientation to each other and are separated by a predetermined distance.

The remote circuit 52 specifies: a storage device, a microprocessor, a digital signal processor, an application-specific integrated circuit (ASIC), a hard disk drive, a user interface device, a transmitter, a receiver, and so on. In some applications, the remote circuit 52 and the integrated circuit 22 may be the same or different

02818928.0 The first electronic circuit or device.

The signal connector 50 may include signal interfaces, such as conductivity, capacitance, inductance, light, transmission lines, and wireless signal interfaces. The conductance signal interface provides electroplating signals that rely on metal-to-metal contacts such as solder, substrate grid array (LGA), pin grid array (PGA), ball grid array (BGA), etc., which are known in the art interface. The capacitive signal interface is a signal interface that can transmit signals between two conductive plates that are preferably of similar size and separated by a suitable dielectric material or air. The inductive signal interface is a signal interface used to transmit signal 10 between two conductors that have a specific orientation to each other and are separated by a predetermined distance. The optical signal interface provides an interface for transmitting a signal such as light that is modulated by a transmitter and demodulated by a receiver at an optical frequency through an optical waveguide such as an optical fiber. The transmission line signal interface provides an interface for transmitting signals between or on two parallel conductors including coaxial conductors, microstrip conductors, coplanar conductors, stripline conductors, and the like. The wireless signal interface provides an interface for transmitting a signal modulated by a transmitter and demodulated by a receiver at the time of radio frequency through a radio transmission medium such as air or space through a radio frequency channel. Each of the power connector 44 and the signal connector 50 can be passed through components such as circuit boards, plug-in card components, pin and socket components, plug components, solder, conductive adhesives, Any type of mating configuration, such as pins, spring fingers, etc., is transferred to the integrated circuit 22.

Fig. 3 shows the alternative positions listed in columns A, C, E, and H of each system block 34, 38, 42, 22, and 52 shown in Fig. 2 and the system block 36 in Fig. 2 Table 56 for alternative connectors listed in columns B, D, F, G, I, and J between 40, 44, 46, 48, and 50. The system block reference numbers 36, 40, 44, and 50 of FIG. 2 that directly correspond to the columns in Table 56 are not enclosed in parentheses in Table 56. For example, the power connector 36 directly corresponds to the power connector described in column B and row 251. The system block reference numbers 34, 38, 42, 46, 22, 48, and 52 of FIG. 2 that do not directly correspond to the columns in Table 56 are enclosed in brackets. For example, the power supply 34 of FIG. 2 that represents the power supply itself, and column A , Line 1 describes the location of the power supply. In Table 56, the alternate voltage regulator module to integrated circuit power connector 54 of FIG. 2 is not shown for clarity. However, the alternative power connector 54 includes conductors and circuit board traces, which are the same as all other connectors listed in Table 32 of FIG. 3.

02818928.0 In Table 56, as shown in column A and row 2, the power location is described as remote. The term "remote in this description generally means that the power source is located at any suitable location away from the remaining circuitry of the electronic device 10. This description is used to reflect the current and expected future design of power supplies. These 5 power supplies are relatively complex circuits by their nature, and are usually formed as modules connected to the remaining circuits through interfaces. The term "remote" does not include the distance relationship where the power supply is set away from the remaining circuits, because, in practice, the power supply 34 is electrically coupled with the remaining circuits.

The positions of the voltage regulator module 38, the decoupling capacitor 42, the integrated circuit 22, and the remote circuit 52 described in row 1, columns C, E, H, and K, respectively, are each described as being located in row 2 of the same four columns. 3 and 4 are in the connector, on the PCB, and/or on the conductor, respectively.

The connector is a device used to electrically couple an electrical signal with an electronic device. The electrical signals transmitted by the connectors usually include power and/or information signals. The connector also has mechanical devices that facilitate electrical connection with 15 electrical devices. In a preferred embodiment of the present invention, the connector is formed as a cover, frame and/or socket of an integrated circuit.

A circuit board is a substrate that includes one or more layers of non-conductive materials used to carry conductive paths, or called traces or contact pads. The conductor is a device used to electrically couple an electrical signal from one electronic device with another electronic device. The electrical signals transmitted by conductors usually include power and/or signals. The conductor can be flexible, rigid, or a combination of the two. Examples of flexible conductors include flexible circuits, ribbon cables, wiring, cables, and the like. An example of a rigid conductor includes a conventional circuit board with conductive traces on it. The conductor is usually located away from the main circuit board and is usually called the mother board.

The power connectors 36, 40, and 44 and the signal connector 50 described in rows 1, columns B, D, F, and J, respectively, are described as conductors and/or circuits described in rows 2 and 3, respectively, of the same four columns Board traces. The term "conductor" in this description generally means the same as described above with reference to the position of the functional block. Therefore, the conductor can be used as a function block as well as the location of the power connector and/or the signal connector. Traces are provided on one or more layers of non-conductive materials

02818928.0 The first conductive path used to transmit electrical signals. The electrical signals conveyed by traces usually include power signals and/or information signals.

The positions of the integrated circuit power connector 46 and the integrated circuit signal connector 48 described in rows 1, columns G, and I, respectively, are each described as being on the top of the integrated circuit 22 described in rows 2, 3, and 4 of the same two columns, respectively. , Side and/or bottom. In this description, the terms "top", "side", and "bottom" refer to different sides or surfaces of the integrated circuit 22, which can generally be square, round, or rectangular, and these terms are for illustration purposes only. The relative terminology should not be seen as being limited to what can be conventionally referred to as the top, side, or bottom of the integrated circuit 22. Generally, the surface area of the top surface and the bottom surface of the integrated circuit 22 has a larger surface area than each side of the integrated circuit, which is typical for integrated circuits formed as microprocessors today. The positions of the integrated circuit power connector 46 and the integrated circuit signal connector 48 will be described in further detail below.

For this general overview of Table 56 of Figure 3, columns A, B, C, D, E, F, G, H,

I, J, and K describe 1, 2, 3, 2, 3, 2, 3, 3, 3, 2, and 3 individual alternatives in rows 2, 3, and 4, respectively. Therefore, Table 56 alone and without any other descriptions or diagrams reveals 11,664 possible combinations of various individual alternatives (ie: 1x2x3x2x3x2x3x3x3x2x3=11,664). The number of possible combinations indicates the power transmission system 12, signal transmission used by the integrated circuit 22 The system 14 and the package design system 16 can be implemented in many ways. The present invention is not intended to be limited to the number of possible combinations, because many other features and alternatives described in this text and shown in this drawing can be combined with the alternatives listed in Table 56. Moreover, the combination of various individual alternatives used at the same time will also increase the number of possible combinations.

As shown in Fig. 2, if an alternative power connector 54 is used instead of the decoupling capacitor 42 and the power connector 44, the total number of combinations will reduce 3 separate alternatives for the location of the decoupling capacitor 42 and reduce the power connector 44 2 separate alternatives for types (ie:

II, 664/(3x2)=1,994 possible combinations).

02818928.0 Fig. 4A, Fig. 4B, Fig. 4C, Fig. 4D, and Fig. 4E show that the integration level of the representative package design system 16 shown in Fig. 1, Fig. 2 and Fig. 3 is increasing, and is respectively denoted as level 0,

1, 2, 3 and 4 integrated circuits 22. FIG. 4A shows an integrated circuit 22 constructed with an integration level of 0, and includes a semiconductor die 58, or is called a chip, a wafer, and the like. FIG. 4B shows the integrated circuit 22 constructed using the integration level 1, and includes the semiconductor mold 58 mounted on the semiconductor substrate 60 shown in FIG. 4A. 4C shows an integrated circuit 22 constructed using integration level 2, and includes a semiconductor mold 58 mounted on a semiconductor substrate 60 enclosed in a semiconductor package 62 such as plastic, ceramic, etc. shown in FIG. 4B. FIG. 4D shows the integrated circuit 22 constructed using the integration level 3, and includes a semiconductor package 62 mounted on a circuit board 64 called a built-in board when there is W shown in FIG. 4C. FIG. 4E shows an integrated circuit 22 constructed using an integration level 4 and includes the semiconductor package 62 and printed circuit board 64 shown in FIG. 4D mounted on a larger circuit board 66 sometimes referred to as a mother board. Preferably, as shown in FIG. 4C, an integration level 2 is used to form the integrated circuit 22. However, as shown in FIG. 4B, integration level 1 is expected to be used to construct an integrated circuit.

The various integration levels are shown for reference only and should not be considered as critical definitions. Various combinations of integration levels are possible and are not specifically shown. For example, as shown in FIG. 4B, the semiconductor mold 58 mounted on the semiconductor substrate 60 may be directly mounted on the printed circuit board 64 without using the semiconductor package 62. Similarly, as shown in FIG. 4C, the semiconductor 10 package 62 can be directly mounted on the motherboard 66 without using the printed circuit board 64. Therefore, the respective components of the integrated circuit 22 at the level shown can be mixed and matched to provide numerous integrated combinations not specifically shown in FIGS. 4A, 4B, 4C, 4D, and 4E.

In FIGS. 48 to 4E, the package has multiple surfaces, and the multiple surfaces can generally be considered as a "top" surface or a "side" surface. These multiple surfaces are produced by stacking or installing elements one by one to form a stair-step profile. Therefore, the term "top" or "side" may include all surfaces facing the same direction, and is not limited to the surface furthest away in one direction.

Figure 5 schematically shows the integrated circuit 22, the power transmission system 12, the signal transmission system

02818928.0 No. 14. In this figure, the integrated circuit 22 generally includes a package design system 16 having an integrated circuit power connector 46 and an integrated circuit signal connector 48 formed therewith. Therefore, the block diagram shown in FIG. 5 is generally the same as the block diagram shown in FIG. 2, except that the integrated circuit 22 is shown as a schematic view. Figure 5 shows several conventional illustrations that apply to all figures.

The solid line represents the preferred path of the signal connector 26 and the preferred power connector 24. The short dashed line represents an alternative path for the signal connector 26. The long dashed line represents the alternative path of the power connector 24. These conventional illustrations are provided to increase clarity and understanding of the drawings and the description, and should not be considered as limiting in any respect, for example, implying that any connector is more important or better than another.

As described with reference to FIG. 2, the signal transmission system 14 is electrically coupled to the integrated circuit signal connector 48 of the integrated circuit 22 through the signal connector 26. The signal connector 26 may be electrically coupled to the top 68, bottom 70, and/or side 74 of the integrated circuit 22. Preferably, the signal connector 26 is electrically coupled to the bottom 70 of the integrated circuit 22. Therefore, the integrated circuit signal connector 48 shown in the view of the integrated circuit 22 means that the signal connector 26 can be located on any surface of the integrated circuit 22.

As described with reference to FIG. 2, the power transmission system 12 is electrically coupled to the integrated circuit power connector 46 of the integrated circuit 22 through the power connector 24. The power connector 24 may be electrically coupled with the top 68, bottom 70, and/or side 74 of the integrated circuit 22. Preferably, the power connector 24 is electrically coupled to the side 72 of the integrated circuit 22. Therefore, the integrated circuit power connector 46 shown in the view of the integrated circuit 22 means that the power connector 24 can be located on any surface of the integrated circuit 22.

In the preferred embodiment of the present invention, the signal connector 26 and the power connector 24 are located on different sides of the integrated circuit 22 (ie, the bottom 70 and the side 72, respectively). Placing the signal connector 26 and the power connector 24 on different sides of the integrated circuit 22 provides several advantages related to the package design system 16 of the integrated circuit 22. These advantages include: reducing the number of ground contacts and power contacts, increasing the number of signal contacts, increasing the number of signal contacts per square area, reducing the signal contact spacing, reducing the total number of contacts, increasing the total number of contacts per square area, and reducing the edge

02818928.0 p.

The force per contact per square area of the Z axis reduces the matching contact height, increases the signal bandwidth, increases the size of the semiconductor die, reduces the size of the integrated circuit 22, and improves other factors related to electronics, machinery and materials.

Alternatively, the signal connector 26 and the power connector 24 may be located on the same side or multiple sides of the integrated circuit 22 (ie, the top 68, the bottom 70, and the side 72). In this case, special consideration will be given to the positions of the signal connector 26 and the power connector 24 on the same side of the integrated circuit 22 in order to optimize the connectors for various engineering reasons, which will be described in further detail below.

Ό FIG. 6A shows the integrated circuit 22 shown in FIG. 5 having a first (high) frequency signal interface 76 and a second (low) frequency signal interface 78 different from the first (high) frequency signal interface 76, wherein, The respective interfaces are coupled to different sides of the integrated circuit 22 representing the package design system 16 according to the preferred embodiment of the present invention. Therefore, the signal connector 26 includes a first (high) frequency 15 signal interface 76 and a second (low) frequency signal interface 78. The frequency of the first (high) frequency signal interface 76 and the frequency of the second (low) frequency signal interface 78 are separated by at least one hertz. However, the benefit of separating signal interfaces on different sides of the integrated circuit 22 according to frequency increases as the separation between frequencies becomes greater.

:0 Each of the first (high) frequency signal interface 76 and the second (low) frequency signal interface 78 can be connected to either side of the integrated circuit 22 (ie: top 68, bottom 70 and side 72) .

Preferably, the first (high) frequency signal interface 76 is connected to the top 68 of the integrated circuit 22, and the second (low) frequency signal interface 78 is connected to the bottom 70 of the integrated circuit 22. The advantage of this position configuration is that the power connector 24 can be connected to the side 72 of the integrated circuit 22 without considering the position of the signal connector 26 on the side 72 of the integrated circuit 22.

And, the advantageous aspect of the position configuration is to interface with a type of signal to be used on one side of the integrated circuit 22 (shown in Table 84 in FIGS. 7A and 7B) and to be used on the other side of the integrated circuit 22 Corresponding to another type of signal interface used. For example, the first (high) frequency 30 rate signal interface 76 may use a capacitive signal interface, while the second (low) frequency signal interface 78

02818928.0 The conductivity type signal interface can be used. In this example, it would be advantageous for the second (low) frequency signal interface 78 to transmit signals to and from the printed circuit board through the conductivity type signal interface, and to make the first (high) frequency signal interface 76 pass the capacitive signal It would be advantageous for the interface to carry signals to and from the conductor. In other words, low-frequency signals will be transmitted through printed circuit board traces on the printed circuit board, and high-frequency signals will be transmitted through conductors. The conductor transmits the high-frequency signal directly to other circuits without entering the printed circuit board, or transmits it to other circuits through the printed circuit board, and continues in a short distance via the printed circuit board trace. This particular configuration can minimize the cost and size of the printed circuit board because it minimizes or eliminates the complicated routing of high frequency transmission lines between multiple printed circuit board layers.

6B is a view of the integrated circuit 22 having a first (high) frequency signal interface 76 and a second (low) frequency signal interface 78 different from the first (high) frequency signal interface 76 shown in FIG. 5, wherein each The interface is coupled to the same side of the integrated circuit 22 representing the package design system 16 according to the preferred embodiment of the present invention. Therefore, FIG. 6B is the same as FIG. 6A, except that the positions of the first (high) 15 frequency signal interface 76 and the second (low) frequency signal interface 78 on the side of the integrated circuit 22 (ie: top 68, bottom 70 and side 72).

The first (high) frequency signal interface 76 and the second (low) frequency signal interface 78 may be located on either side of the integrated circuit 22 (ie, the top 68, the bottom 70, and the side 72). Preferably, the first (high) frequency signal interface 76 and the second (low) frequency signal interface 78 are located at the bottom 70 of the integrated circuit 22. Alternatively, the first (high) frequency signal interface 76 and the second (low) frequency signal interface 78 may be located on the top 68 or the side 74 of the integrated circuit 22.

The advantage of arranging the first (high) frequency signal interface 76 and the second (low) frequency signal interface 78 on the same side of the integrated circuit 22 is that the high frequency signal and the low frequency signal can be connected to the same printed circuit board, connector, Conductors or other integrated circuits are electrically coupled. This position configuration is practical in many cases where the signal connector 26 has one frequency signal interface and rarely has another frequency signal interface, where assigning them to different sides of the integrated circuit will be more effective than assigning them to the integrated circuit 22. The same side is more expensive or more complicated.

02818928.0 This position configuration may require a hybrid interface connector between the integrated circuit 22 and the printed circuit board, connector, conductor or other integrated circuit to accommodate different frequencies. For example, the first (high) frequency signal interface 76 may use a capacitive signal interface, and the second (low) frequency signal interface 78 may use a conductivity type signal interface. In this case, the hybrid interface connection adapts to capacitive signals and conductance signals. More specifically, the hybrid interface connector will include dielectric elements for capacitive signals and galvanic contacts for conductive signals.

FIG. 7A is a view of the integrated circuit 22 having a first type of signal interface 80 and a second type of signal interface 82 different from this type of signal interface 80 shown in FIG. 5, where the respective interfaces and representatives are based on this Different sides (ie, top 68, bottom 70, and side 72) of the integrated circuit 22 of the package design system 16 of the preferred embodiment of the invention are coupled. Therefore, the signal connector 26 includes a first type of signal interface 80 and a second type of signal interface 82.

The first type of signal interface 80 and the second type of signal interface 82 may use the same or different frequencies to transmit signals.

As shown in Table 84 in Figure 7A, each of the first type of signal interface 80 and the second type of signal interface 82 includes (but not limited to): conductance, capacitance, inductance, light, transmission line, and wireless Signal interface. The examples of these types of signal interfaces are described in detail above. Note that these types of signal interfaces also include the signal characteristics transmitted by these types of signal interfaces: 0. The signal characteristics include (but are not limited): frequency, amplitude, modulation, etc.

Each of the first type of signal interface 80 and the second type of signal interface 82 can be connected to any side of the integrated circuit 22 (ie, the top 68, the bottom 70, and the side 72). Preferably, the first type of signal interface 80 is connected to the top 68 of the integrated circuit 22, and the 25th type of signal interface 82 is connected to the bottom 70 of the integrated circuit 22. Alternatively, the second type of signal interface 82 may be connected to the side 74 of the integrated circuit 22.

This type of signal 30 interface configuration is advantageous when the electrical and/or mechanical characteristics of the various types of signal interfaces are so different that it is less expensive or easier to arrange them on different sides of the integrated circuit 22. For example, the first type of signal interface 80 may be an optical signal interface

02818928.0 The second type of signal interface 82 can be a capacitive signal interface. In this case, the optical interface adopts the optical form to transmit the signal, and the capacitive interface adopts the electronic form to transmit the electrical signal. Therefore, it would be advantageous to configure the optical signal interface on one side of the integrated circuit 22 and the capacitive signal interface on the other side of the integrated circuit 22.

FIG. 7B shows the integrated circuit 22 shown in FIG. 5 having a first type of signal interface 80 and a second type of signal interface 82 different from this type of signal interface 80, wherein the respective interfaces and representative of the preferred according to the present invention The same side of the integrated circuit 22 of the package design system 16 of the embodiment is coupled. Therefore, FIG. 7B is the same as FIG. 7A, except that the first type of signal interface 80 and the second type of signal interface 82 are located on the side of the integrated circuit 22 (ie, the top 68, the bottom 70, and the side 72).

The first type of signal interface 80 and the second type of signal interface 82 can be connected to either side of the integrated circuit 22 (ie, the top 68, the bottom 70, and the side 72). Preferably, both the fifteenth type signal interface 80 and the second type signal interface 82 are connected to the bottom 70 of the integrated circuit 22. Alternatively, both the first type of signal interface 80 and the second type of signal interface 82 may be connected to the top 68 or the side 74 of the integrated circuit 22. The advantages of this configuration are similar to those described with reference to the hybrid interface connector in FIG. 6B.

Note that the frequency signal interface described in FIGS. 6A and 6B and the type of signal interface described in FIGS. 7A and 7B have some overlap, because the frequency signal interface described in FIGS. 6A and 6B must There is a certain type of signal interface, such as the signal interface described in Figures 7A and 7B. For example, in FIG. 6A, the first (high) frequency signal interface 76 is preferably a capacitive signal interface, and the second (low) frequency signal interface 78 is preferably a conductivity type signal interface. In this example, each type of signal interface uses different frequencies to transmit signals. Therefore, with the symbolic representation and through this example, various combinations of FIGS. 6A, 6B, 7A, and 7B are feasible and within the scope of the present invention.

FIGS. 8A, 8B, 8C, and 8D show the signal connector 48 and/or the electrical connector shown in FIGS. 4C and 5 representing the package design system 16 according to the preferred embodiment of the present invention.

02818928.0 A cross-sectional view of the integrated circuit 22 of the first source connector 46, where the signal connector 48 and/or the power connector 46 are respectively located outside the semiconductor package 22, flush with the semiconductor package 62, and on the back of the semiconductor package 22 Department or internal. Preferably, as shown in FIG. 4C above, the integrated circuit 22 is a semiconductor package 62 formed as a two-level design. Alternatively, as shown in FIGS. 4A, 4B, 4C, 4D, and 4E, the integrated circuit 22 may be formed in any level design, or any combination thereof. Note that, for the sake of clarity, the semiconductor mold 58 and the semiconductor substrate 60 shown in FIG. 4C are not shown in each block in the four figures of FIGS. 8A, 8B, 8C, and 8D.

As mentioned above, the common features of each of FIGS. 8A, 8B, 8C and 8D include: semiconductor package 62 (including: top 68, bottom 70, side 72 and 74), integrated circuit signal connector 48, integrated The circuit power connector 46, the signal connector 26 and the power connector 24. The integrated circuit power connector 46 and the signal connector 26 are the same as described above.

The semiconductor package 62 has a predetermined thickness 88. The predetermined thickness 88 may have any value, and may be different on one or more sides of the semiconductor package 62. The semiconductor package 62 may be formed of any suitable material. Preferably, the value of the predetermined thickness 88 is suitable for a microprocessor using the plastic or ceramic material for the semiconductor package 62. It is preferable that the value of the predetermined thickness 88 is the same on all sides of the semiconductor package 62.

Integrated circuit: 22 may have mechanical parts (not shown) that can align the integrated circuit 22 with another structure and/or be mounted on the other structure. The other structure includes (but is not limited to): a printed circuit Board, connector, forming cover, socket or frame, conductor, another integrated circuit, etc. These mechanical parts may be formed as separate parts mounted on the integrated circuit 22 or formed integrally with the integrated circuit 22. These mechanical components include (but are not limited to): pins, ridges, posts, pegs, protrusions, etc. extending to the outside of one or more surfaces of the integrated circuit 22, and/or extending to the inside of one or more surfaces of the integrated circuit 22 Of holes, recesses, grooves, etc. The mechanical part may form the holder itself, or it may cooperate with a separate holder to align with the integrated circuit 22 and/or be mounted on the integrated circuit 22.

02818928.0 The first integrated circuit signal connector 48 includes a signal contact 90. The signal contact 90 provides any type of path that allows the signal on the signal connector 26 to be received by the integrated circuit 22 and/or sent by the integrated circuit 22. Therefore, the signal contact 90 can be compatible with the tables in FIGS. 7A and 7B. The various types of signal interfaces shown in 84 are compatible. The signal interface categories include (but are not limited to): conductance, capacitance, inductance, light, transmission line, and wireless signal interface. According to the type of signal interface used, the signal contact 90 has various mechanical and electrical characteristics and characteristics. When the signal contact is compatible with the electrical conductivity type signal interface, the signal contact 90 is preferably made of metal to provide electroplated contacts.

W When the signal contact 90 is compatible with a capacitive signal interface, the signal contact 90 is preferably made of metal to provide one side of the conductive plate necessary for capacitive signal transmission. Alternatively, the dielectric material and the integrated circuit 22 are provided on the conductive plate. Note that the other side (not shown) of the conductive plate may be provided on the printed circuit board or the connector, which will be described in further detail below.

When the signal contact 90 is compatible with an inductive signal interface, the signal contact 90 is preferably made of metal to provide one side of a conductive element necessary for inductive signal transmission. Note that the other side (not shown) of the conductive element may be provided on the printed circuit board or the connector, which will be described in further detail below.

! 0 When the signal contact 90 is compatible with the optical signal interface, the signal contact 90 preferably forms one or more optical transmitters and/or optical receivers, which will be described in further detail below.

When the signal contact 90 is compatible with a transmission line-type signal interface, the signal contact 90 preferably forms a transmission line interface for the signal connector 26 outside the integrated circuit 22 and the signal connector inside the integrated circuit 22 (not shown) Out) to achieve correct impedance matching.

When the signal contact 90 is compatible with a wireless signal interface, the signal contact 90 preferably forms an antenna interface for the signal connector 26 outside the integrated circuit 22 and the signal connector inside the integrated circuit 30 (not shown). ) Through the antenna (not shown) to achieve correct impedance matching

02818928.0 First allocation. Alternatively, the signal contact 90 may form and provide the antenna itself.

The signal contact 90 is electrically coupled with a semiconductor mold 58 (not shown) located inside the semiconductor package 62. Conventional methods for providing electrical coupling include (but are not limited to): wire bonding, tab bonding, and elastic flipping bonding, etc., which are well-known in the semiconductor manufacturing field. Preferably, the electrical coupling between the signal contact 90 and the semiconductor mold 58 is performed using wiring and wiring bonders each of which are well-known in the field of semiconductor manufacturing.

The signal contacts 90 may be located on either side or all sides of the integrated circuit 22 (ie, top W 68, bottom 70, sides 72 and 74). Preferably, the signal contact 90 is located at the bottom 70 of the integrated circuit 22 so as to match the preferred position of the signal connector 26 described above. Alternative locations for the signal contact 90 are shown on the top 68 and the side 74 of the semiconductor package 62. For clarity, the signal contact 90 is illustrated as a simple block in each figure. In fact, the signal contact 90 includes a plurality of individual signal contacts corresponding to each signal path. The signal contact 90 15 may have any elevation angle relative to the semiconductor package 62. It is preferable that all the signal contacts 90 have the same elevation angle with respect to the semiconductor package 62. This configuration can facilitate the manufacture of the semiconductor package 62 and the connection with the signal contact 90. Alternatively, the signal contacts 90 may each have a different elevation angle relative to the package 62 to accommodate various desired engineering considerations. The signal contact 90 can have any shape, size, pitch, material, etc. Shape! 0 shape includes (but not limited to): square, rectangle, circle, oval, etc. Preferably, its size is in the range of 0.5-1.0mm x 0.5-1.0mm square. Preferably, its material is an electroplating material.

The integrated circuit power connector 46 includes conductive power contacts 92 formed of metal.

The power contacts provide any type of path through which the power on the power connector 24 can be sent to the integrated circuit 22. The power contact 92 is coupled with a semiconductor mold 58 (not shown) located inside the semiconductor package 62. It is preferable that the electrical coupling between the power contact 92 and the semiconductor die 58 is performed using wiring and wiring bonders each known in the field of integrated circuit packaging design. Preferably, the size of the power contact 92 is generally larger than that of the signal contact 90, and the electrical coupling between the power contact 92 and the semiconductor die 58 is greater than that between the signal contact 90 and the semiconductor die 58.

02818928.0 The electrical coupling between the 58th mode is strong. The advantage of this configuration is that the current transmitted to the semiconductor die 58 through the power contact 92 can be located on either or all sides of the integrated circuit 22 than the electrical power contact 92 transmitted to the semiconductor die 58 through the signal contact 90 ( Ie: top

68, bottom 70, sides 72 and 74). Preferably, the power contact 92 is located on the side 72 of the integrated circuit 22 to match the preferred position of the power connector 24 described above and, if desired, free up more on the integrated circuit that can be used for signal and other non-power applications. Contacts. Alternative locations for power contacts 92 are shown at the top 68 and bottom 70 of the semiconductor package 62.

Placing the power contacts on the side 72 of the integrated circuit 22 significantly reduces the force per signal contact per square area along the bottom 70 of the integrated circuit 22. This is because the force per power contact is on the X and Y axes. . Placing the power contacts on the top 68 of the integrated circuit 22 significantly reduces the force per signal contact per square area along the bottom 70 of the integrated circuit 22. This is because when the signal contacts 90 and the power contacts 92 are distributed In the case of the opposite side of the integrated circuit 22, less contact force is required. For clarity, the power contact 92 is shown as a simple block in each figure. In fact, as described with reference to FIG. 1, the power contact 92 includes a plurality of individual power contacts and ground contacts corresponding to each power path and ground path.

The power contacts 92 may have any elevation angle with respect to the semiconductor package 62, and; preferably, the power contacts 92 all have the same elevation angle with respect to the semiconductor package 62.

This configuration can facilitate the manufacture of the semiconductor package 62 and the connection with the power contact 92. Alternatively, if appropriate, the power contacts 92 may each have a different elevation angle relative to the semiconductor package 62 to accommodate various engineering considerations.

FIG. 8A shows that the signal contact 90 and/or the power contact 92 are located outside the semiconductor package 62. In this case, the signal contact 90 and/or the power contact 92 protrude a predetermined height 94 above the outer surface of the semiconductor package 62. The predetermined height 94 of the signal contact 90 and/or the power contact 92 may have any value, and may be different on one or more sides of the semiconductor package 62. Preferably, the value of the predetermined height 94 is suitable for a microprocessor using the plastic or ceramic material used for the semiconductor package 62. Preferably, the signal contact 90 and/or the power supply

02818928.0 The value of the predetermined height 94 of the first contact 92 is the same on all sides of the semiconductor package 62.

FIG. 8B shows that the signal contact 90 and/or the power contact 92 are arranged to be flush with the semiconductor package 62. In this case, the signal contact 90 and/or the power contact 92 are generally flush with the outer surface of the semiconductor package 62. FIG. 8C shows that the signal contact 90 and/or the power contact 92 are arranged to be partially recessed inside the corresponding groove 98 formed in the semiconductor package 62. In this case, the signal contact 90 and/or the power contact 92 are recessed by a predetermined height 96 below the outer surface of the semiconductor package 62. The predetermined height 96 of the signal contact 90 and/or the power contact 92 may have any value, and may be different on one or more sides of the semiconductor package 62.

It is preferable that the value of the predetermined height 96 is suitable for a microprocessor using the plastic or ceramic material for the semiconductor package 62. Preferably, the value of the predetermined height 96 of the signal contact 90 and/or the power contact 92 is the same on all sides of the semiconductor package 62. The advantage of the recess is to reduce contamination and/or damage of the signal contact 90 and/or the power contact 92. The recess may also provide mechanical alignment or mounting features for the power connector 24 and/or the signal connector 26.

FIG. 8D shows that the signal contact 90 and/or the power contact 92 are located inside the semiconductor package 62. In this case, the signal contact 90 and/or the power contact 92 are provided inside the inner surface of the semiconductor package 62. The advantageous aspect of this configuration is that contamination and/or damage of the signal contact 90 and/or the power contact 92 are eliminated.

The integrated circuit, the signal connector 48 includes a signal package interface 100. The signal package interface 100 is any type of interface that enables the signal contact 90 located inside the semiconductor package 62 to operate together with the signal connector 26 located outside the semiconductor package 62. The signal package interface 100 can be formed as a separate component separated from the semiconductor package 62, and then various methods such as 25 insert molding, over molding, snaps, interference press-fitting, bonding, etc. can be used with The semiconductor package 62 is mechanically bonded. The individual component may be formed of the same or different material as the semiconductor package 62. Alternatively, the signal package interface 100 may be formed as an integral part of the semiconductor package 62. For clarity, the signal packaging interface 100 is illustrated as a simple block in each figure. In fact, the signal packaging interface 100 30 may include one or more individual signal packaging interfaces 100 corresponding to each signal path.

02818928.0 As shown in Table 84 in Figure 7A and Figure 7B, the mechanical and electrical characteristics and characteristics of the signal package interface 1Q0 depend on the type of signal interface used. For example, a capacitive signal interface may require the signal package interface 100 to be formed of a dielectric material. In this case, the signal contact 5 90 provides one side of the conductive plate required for capacitive signal transmission. The second side (not shown) of the conductive plate is located outside the semiconductor package 62 and may be provided on a printed circuit board or a connector. The signal package interface 100 is formed of a dielectric material with a suitable dielectric constant, so that a capacitive signal can be transmitted between conductive plates with a signal of a suitable frequency, amplitude, and the like.

For example, an optical signal interface may require the signal package interface 100 to be formed as an optical lens. In this case, the signal contact 90 forms an optical transmitter and/or an optical receiver. The signal packaging interface 100 forms an optical lens to guide the modulated signal in the form of light waves through the semiconductor package 62. Alternatively, the signal package interface 100 may be formed with one or more holes extending through the semiconductor package 62 so that the signal connector 26 formed as an optical fiber can be mechanically aligned with the optical transmitter and/or optical receiver inside the integrated circuit 22 . In this alternative, one or more holes may also fix the optical fiber to the integrated circuit 22. As another example, a transmission line type or wireless type signal interface may require the signal packaging interface 100 to be formed as an impedance matching device.

The integrated circuit power connector 46 houses the power package interface 102. The power package interface 102 is any type of interface that enables the power contact 92 located inside the semiconductor package 62 to operate together with the power connector 24 located outside the semiconductor package 62.

The power package interface 102 may be formed as a separate component separated from the semiconductor package 62, and then may be mechanically joined to the semiconductor package 62 using methods such as insert molding, over molding, snaps, interference press fit, bonding, and the like. The individual component may be formed of the same or different material as the semiconductor package 62. Alternatively, the power package interface 102 may be formed as an integral part of the semiconductor package 62. For clarity, the power package interface 102 is illustrated as a simple block in each figure. In fact, the power package interface 102 may include one or more individual power package interfaces 102 corresponding to each signal path. Electricity

02818928.0 The mechanical and electrical characteristics and characteristics of the first source package interface 102 depend on the type of method used to transfer power from the power connector 24 to the integrated circuit 22 through the power contact 92.

In FIGS. 8A, 8B, 8C, and 8D, this feature is shown for illustration and not for limitation, and the device in any one of these figures can be combined with any device in the other figure , To provide multiple combinations of devices. For example, the signal contacts 90 located inside the semiconductor package 62 shown in FIG. 8D may be flush with the outside of the semiconductor package 62 shown in FIGS. 8A, 8B, and 8C, flush with the semiconductor package 62, or semiconductor package 62. The power contacts 92 of the recesses of the package 62 are combined.

9A, 9B, and 9C show the signal contacts 90 and/or the power supply of the package design system 16 according to the preferred embodiment of the present invention as shown in FIG. 8A, FIG. 8E, FIG. 8C or FIG. 8D and FIG. A plan view of the integrated circuit 22 of the contact 92, wherein the signal contact 90 and/or the power contact 92 are located on the top 68, the bottom 70, and/or the side 72 of the integrated circuit 22, respectively. In each of these three figures, the signal contact 90 and/or the power contact 92 are shown as equally spaced squares for illustration purposes only. In fact, the signal contact 90 and/or the power contact 92 may have any suitable size, shape, thickness, size, spacing, etc. Therefore, the configuration of the signal contact 90 and the domain power contact 92 on one or more of the top 68, the bottom 70, and/or the side 72 of the integrated circuit 22 provides many embodiments within the scope.

More specifically, FIG. 9A shows the top 68 of the integrated circuit 22 that can be used to carry signal contacts 90 and/or power contacts 92. FIG. 9B shows the bottom 70 of the integrated circuit 22 that can be used to carry signal contacts 90 and/or power contacts 92. In the preferred embodiment of the present invention, as shown in FIG. 9B, the signal contact 90 is located at the bottom 70 of the integrated circuit 22. FIG. 9C shows the side 72 of the integrated circuit 22 that can be used to carry signal contacts 90 and/or power contacts 92. In the preferred embodiment of the present invention, as shown in FIG. 9C, the power contact 92 is located on the side 72 of the integrated circuit 22.

10A, 10B and 10C show the signal contact 90 and/or the power contact 92

02818928.0 A more limited example of the arrangement and position on one or more of the top 68, bottom 70, and/or side 72 of the integrated circuit 22. FIG. 10A shows the exterior 104 of the top 68 of the integrated circuit 22 that can be used to carry signal contacts 90 and/or power contacts 92. The interior 106 of the integrated circuit 22 can be used to house a heat sink, a heat spreader, and the like. Preferably, the heat sink is in mechanical contact with the integrated circuit 22 to provide a thermal path for drawing heat away from the integrated circuit 22.

FIG. 10B shows the outer portion 108 and the inner portion 110 of the top portion 68 of the integrated circuit 22 that can be used to carry signal contacts 90 and/or power contacts 92. Preferably, the outer portion 108 carries the power contact 92, and the inner portion 110 carries the signal contact 90. This configuration is advantageous when the power contact 92 and the signal contact 90 have different types of signal interfaces as shown in FIGS. 7A and 7B, for example, when the power contact 92 is of a conductive type and the signal contact is of a capacitive type. of.

Figure 10C shows the outer 112 and the inner 114 of the top 68 of the integrated circuit 22, each of which can be used to carry the signal contact 90 and/or the power contact 92. Preferably, the outer 112 carries the power contact 92, and the inner 114 Carry signal contact 90.

In FIG. 11, the connector 112 includes suitable electrical and mechanical devices and features for providing an electrical interface between the signal connector 26 and/or the power connector 24 and the integrated circuit 22. The connector 112 is compatible with various types of signal interfaces described in Table 84 in FIGS. 7A and 7B.

According to a preferred embodiment of the present invention, the connector 112 carries the voltage regulator module 38 and/or the decoupling capacitor 42, which will be described in further detail below. Since the connector 112 carries the integrated circuit 22, the voltage regulator module 38 and/or the decoupling capacitor 42 are arranged as close as possible to the integrated circuit 22, thereby minimizing the length of the power connector 24. The length of the power connector 24 is minimized, and the impedance and inductance of the power connector 24 are in turn minimized, so that the voltage regulator module 38 and/or the decoupling capacitor 42 can reduce the voltage of low voltage, narrow voltage tolerance, and high current. Transfer to the high-performance integrated circuit 22.

The connector 112 can have various forms, shapes and sizes, and can be made of various materials.

02818928.0 The first material is made, it depends on various engineering considerations. The various forms, shapes and sizes are represented in FIG. 11 by the dashed lines 120, 122, and 124 of the side 74 of the integrated circuit 22 and the dashed lines 126, 128, and 130 of the side 72 of the integrated circuit 22. The dashed lines 120, 122, and 124 are horizontally aligned with the dashed lines 126, 128, and 130, respectively. The dashed lines represent various locations where the connector 112 can be terminated to form a specific form, shape, or size of the connector 112. Note that the dotted line is only for illustrative purposes, and should not be regarded as limiting the scope of the connector 112.

For example, the upper portion of the connector 112 located on the top 68 of the integrated circuit 22 may only extend to the dashed lines 120 and 126, thereby substantially forming a cover on the integrated circuit 22, or W is called a plate or a cap. In this case, the connector 112 formed as a cover has a bottom surface that is arranged to be coplanar with or above the top 68 of the integrated circuit 22. The connector 112 formed as a cover may further extend to the dashed lines 122 and 128 along the sides 72 and 74 of the integrated circuit 22. In this case, the connector 112 formed as a cover has a bottom surface located between the top 68 and the bottom 70 of the integrated circuit 22. The connector 112 formed as a cover may further extend along the sides 72 and 74 of the integrated circuit 22 to the dashed lines 124 and 130. In this case, the connector 112 formed as a cover has a bottom surface that is configured to It is coplanar with or below the bottom 70 of the integrated circuit 22 and can extend to the top surface of the printed circuit board 114, if present. Note that the connector 112 formed as a cover is shown to extend to the outside of the sides 72 and 74 of the integrated circuit 22, but should not be considered as limited by this. Alternatively, the connector 112 formed as a cover may be flush with the side portions 72 and 74 of the integrated circuit 22 or located inside the side portions 72 and 74. Figure 12A shows a more detailed illustration of the connector 112 formed as a cover.

As another example, the lower part of the connector 112 located under the bottom 70 of the integrated circuit 22 may only extend to the dotted lines 124 and 130, thereby substantially forming a socket, or a cup or a bag, under the integrated circuit 22. In this case, the connector 112 formed as a socket has a top surface, the top surface is arranged to be coplanar with the bottom 70 of the integrated circuit 22 or located below the bottom 70.

The connector 112 formed as a socket may further extend to the dashed lines 122 and 128 along the sides 72 and 74 of the integrated circuit 22. In this case, the connector 112 formed as a socket has a top surface located between the bottom 70 and the top 68 of the integrated circuit 22. form

02818928.0 The connector 112, which is a socket, may further extend along the side portions 72 and 74 of the integrated circuit 22 to the dashed lines 120 and 126. In this case, the connector 112 formed as a socket has a top surface that is arranged to be coplanar with or above the top 68 of the integrated circuit 22. Note that the connector 112 formed as a socket is shown to extend to the outside of the sides 72 and 74 of the integrated circuit 22, but should not be construed as being limited by this. Alternatively, the connector 112 formed as a socket may be flush with the side portions 72 and 74 of the integrated circuit 22 or located inside the side portions 72 and 74. Figure 12B shows a more detailed illustration of the connector 112 formed as a socket.

To give another example, the connector 112 located around the sides 72 and 74 of the integrated circuit 22

The center of W substantially forms a frame around the periphery of the integrated circuit 22, or is called a ring or boundary.

In this case, the connector 112 formed as a frame may have a top surface located on the top 68 of the integrated circuit 22, or located on the top 68 and bottom of the integrated circuit 22

Between 70, indicated by dashed lines 122 and 128. The connector 112 formed as a frame may have a bottom surface that is located under the bottom 70 of the integrated circuit 22, or located on the integrated circuit

Between the top 68 and the bottom 70 of 22, indicated by the dashed lines 124 and 130, and can extend to the top surface of the printed circuit board 114, if present. Figure 12C shows a more detailed illustration of the connector 112 formed as a frame .

These three examples of the connector 112 formed as a cover, a frame, or a socket illustrate various examples of the various forms, shapes, and sizes that the connector 112 may have. Note that the descriptions in the above examples are mixed with each other. For example, the description of the cover is mixed with the description of the frame, and the description of the frame is mixed with the description of the socket. Therefore, these examples show that the connector 112 can be located on any side or multiple sides of the integrated circuit 22, and is not limited to the illustration in FIG. 11.

The connector 112 may have (not limited to) any suitable material including plastic and metal, and may have (not limited to) any suitable characteristics including conductive or non-conductive. Preferably, the connector uses a non-conductor , Formed of a plastic material, and carry suitable signal contacts (not shown) and power contacts that operate with the corresponding signal contacts 90 and power contacts 92 carried by the integrated circuit 22, respectively. Alternatively, as shown in FIG. 2 above, the connector 112 may be formed as a circuit for carrying the voltage regulator module 38 and/or the decoupling capacitor 42

02818928.0 The first board. Alternatively, the connector 112 may be formed as a decoupling capacitor 42 itself having an integral capacitor structure. These two alternatives are described in further detail below. Alternatively, the connector 112 may be formed to provide the function of the voltage regulator module 38 and/or the decoupling capacitor 42 without having components that may be regarded as discrete components of a conventional housing.

The connector 112 may have a mechanical device (not shown) that can align the connector 112 with another structure and/or be installed on the other structure, and the other structure includes (not limited to): a circuit board 114 , Another connector (shown in Figure 13 and Figure 14) that forms a cover, socket or frame, conductor 116, etc. These mechanical components may be formed as separate components mounted on the connector 112 or integrally formed with the connector Ό 112. These mechanical components include (not limited to): pins, ridges, posts, pegs, protrusions, etc. extending to the outside of one or more surfaces of the connector 112, and/or extending to the inside of one or more surfaces of the connector 112 Of holes, recesses, grooves, etc. The mechanical part may form the holder itself, such as a snap, a clip, etc., or may cooperate with a separate holder to align with the connector 112 and/or be installed on the connector 112.

As described above, the signal connector 26 and/or the power connector 24 are electrically and mechanically coupled to the connector 112 in this manner, so that the signal connector 26 and/or the power connector 24 and the integrated circuit 22 are preferably connected to each other. / Or alternative position alignment. As described above, the signal connector 26 and/or the power connector 24 may be formed as a conductor 116 or a printed circuit board trace 118.

When the signal connector 26 and the power connector 24 are formed as the conductor 116 and the connector 112', the printed circuit board 114 may not be used at all or may only be used to provide mechanical stability for the connector 112. In this case, the connector 112 can be regarded as a holder for the integrated circuit 22 and the conductor 116, and the conductor 116 transmits the signal and power to the integrated circuit 22. If stored on the printed circuit board to provide mechanical stability to the connector 112, the connector 112 may appear to hang over the circuit board a bit.

The circuit board 114 may be used to determine the wiring to and/or from the integrated circuit 22 for the signal connector 26 and/or the power connector 24 using the conductive traces 118. When the circuit board 114 is used, it is preferable to use the integrated circuit-to-circuit board signal and/or power interface 132 to provide the integrated circuit board 114.

02818928.0 The proper connection between the completed circuit 22 and the circuit board 114. Preferably, the interface 132 is located between the bottom 70 of the integrated circuit 22 and the top of the circuit board 114. The circuit board 114 may have various types of mechanical devices for aligning and/or fixing the integrated circuit 22, the connector 112, and/or the conductor 116, and the mechanical device types include (not limited to) holes, recesses, etc., and Cooperate mechanically with corresponding mechanical devices on the mating structure, or use separate fixers such as pins, screws, bolts, snaps, clips, etc., to align and/or fix the mating structure.

The interface 132 can be used alone or in combination with the connector 112. When the interface 132 is used in combination with the connector 112, the connector 112 is preferably formed as a socket or a frame,

Ό to help maintain and align the interface 132 against the integrated circuit 22. In this case, the interface 132 is located inside the connector 112 formed as a socket or frame, which forms the outside of the connector 112 at the periphery of the interface 132. The interface 132 may be formed as a separate component separated from the integrated circuit 22, or may be integrally formed with the integrated circuit 22 as a whole. When the interface 132 is formed as a separate component separated from the integrated circuit 22, the interface 132 can be separated from the integrated circuit 22 or mounted on the integrated circuit 22. Preferably, the interface 132 is formed as a separate component and separated from the integrated circuit 22. When the interface 132 is integrally formed with the integrated circuit 22, the interface 132 may be formed as the semiconductor substrate 60 shown in FIG. 4B, for example, as a side portion of the semiconductor package 62 shown in FIGS. 4C and 8D, or as shown in FIG.

4D or printed circuit board 64 or 114 shown in FIG. 4E. The interface 132 can adopt various shapes and sizes, and can be formed of various materials. Interface as a whole or as a single component

Various shapes of the 132 may include a circle, a square, a polygon, etc., and the interface 132 may be flat, or may be curved or formed to have a specific shape.

The material properties of the interface 132 may include solid, liquid, paste, gel, or gas.

The material of the interface 132 can have any hardness level, including rigidity, flexibility, and compressibility.

The advantage of the flexible interface 132 is that it can better comply with the manufacturing changes of the integrated circuit package and/or the circuit board 114 and is easier to manufacture. In some applications, it may be desirable to use temperature, pressure, etc. to adjust the material properties of the interface 132 such as the dielectric constant. The interface 132 can be formed into a single-layer or multi-layer material using manufacturing techniques, including (not limited to) a layered build solution, a spraying or vacuum deposition solution, and an extrusion solution.

02818928.0 First class. The interface 132 may be formed of the same material or different materials. In the case of different materials, the first material forms the carrier and the second material forms the signal and/or power path. The second material forming the signal and/or power path can be mounted on the first material by means such as press-fitting, insert molding, over molding, rolling, and the like.

Interface 132, signal contact 90 and/or power contact 92 on integrated circuit 22, and corresponding signal contact and/or power contact on printed circuit board 64 or 114, conductor 116, connector 112, or remote circuit 52 It can be configured in various ways. For example, various configurations of these contacts and interfaces 132 may include (not limited to): contact to interface 132, contact to Ό interface 132 to contact, interface 132 to contact to interface 132, interface 132 to interface 132 , Contact to interface 132 to interface 132 to contact, and contact to interface 132 to contact to interface 132 to contact, etc. Therefore, the interface 132 may be formed on the outer surface of the integrated circuit 22, the printed circuit board 64 or 114, the conductor 116, the connector 112, or the remote circuit 52, or may be formed on the inner layer thereof. Electrically, the interface 132 can support any type of signal transmission between the integrated circuit 22 and the remote circuit 52. The signal transmission types include (not limited to): single-ended serial, single-ended parallel, and differential serial. Line and differential parallel signal transmission. Furthermore, the interface 132 and/or the signal contact 90 and/or the power contact 92 are designed to optimize electrical engineering considerations. The electrical engineering considerations include: inductance, capacitance, crosstalk, propagation delay, skew, and impedance.

In a manner similar to that described for connecting to the circuit board 114 through an interface, the interface 132 can also be selectively used as an interface between the integrated circuit 22 and the conductor 116, the connector 112 and another integrated circuit. 132 is compatible with various types of signal interfaces listed in Table 84 shown in Figs. 7A and 7B. For example, when the interface 132 is compatible with the conductive signal interface, the interface 132 is preferably formed of a non-conductive material for carrying a plurality of discrete conductive segments that are compatible with the conductive signal interface. The position of the contact 90 corresponds and aligns. When the interface 132 is compatible with a capacitive signal interface, the interface 132 is preferably formed of a dielectric material having a suitable dielectric constant and a suitable predetermined thickness. In this case, the signal contact 90 is preferably made of metal to provide one side of the conductive plate necessary for capacitive signal transmission. The other side of the conductive plate (not shown) will be provided on the circuit board 114

02818928.0 first.

When the interface 132 is compatible with an inductive signal interface, the interface 132 is preferably formed of a non-conductive material having a suitable predetermined thickness. In this case, the interface 132 enables a conductive element in the integrated circuit 225 to be shown) and the circuit board The best separation is achieved between another conductive element (not shown) in or on. When the interface 132 is compatible with an optical signal interface, the interface 132 preferably forms an optical transmission channel such as a lens suitable for transmitting optical signals in the form of modulated light waves. On the other hand or in combination with an optical transmission channel, the interface 132 can be used to align and/or focus the optical signal between the integrated circuit 22 and the circuit board 114. When the interface 132 is compatible with a transmission line-type signal interface, the interface 132 preferably forms a transmission line interface or channel for achieving correct impedance matching between the integrated circuit 22 and the circuit board 114. When the interface 132 is compatible with a wireless-type signal interface, the interface 132 preferably forms a radio frequency channel suitable for transmitting radio frequency (RF) signals from the integrated circuit 22 to the circuit board 114.

The advantage of the cooperation between the interface 132 and the package design system 16 is that the operating frequency of the microprocessor can be increased without deteriorating signal integrity. For example, the interface 132 forming the dielectric material and the package design system 16 for forming the conductive plate as the signal contact 90 together provide a capacitive signal interface. In this case, the use of a capacitive signal interface can minimize the resistance caused by the inductance associated with the conductive interconnection between the semiconductor die located inside the microprocessor and the motherboard. High-frequency signal operation can be passed without increasing the impedance of the signal path that compromises signal integrity. Therefore, this configuration can maximize performance and minimize the cost of interconnection technology used to realize high-speed digital signal design.

FIG. 12A shows the connector 112 formed as a cover, where the connector 112 has sides that extend 25 to the outside of the sides 72 and 74 of the integrated circuit 22, has an upper portion located above the top 68 of the integrated circuit 22, and It has a lower part arranged to be flush with the bottom 70 of the integrated circuit 22 or located a little below the bottom 70. Preferably, the connector 112 formed as a cover surrounds all four sides of the integrated circuit 22 (72, 74, with one side facing the outside of the page and one side facing the inside of the page). When the integrated circuit 22 is directly mounted on the printed circuit board 114, the connector 112 30 formed as a cover is advantageous.

02818928.0 FIG. 12B shows a view of the integrated circuit 22 in the connector 112 formed as a socket shown in FIG. 11 according to the preferred embodiment of the present invention. 12B shows the connector 112 formed as a socket, wherein the connector 112 has sides extending to the outside of the sides 72 and 74 of the integrated circuit 22, has a lower portion located below the bottom of the integrated circuit 22, and has a It is flush with the top 68 of the integrated circuit 22 or is located above the top 68 a little bit above. Preferably, the connector 112 formed as a socket surrounds all four sides of the integrated circuit 22 (72, 74,-the side faces out of the page, and the side faces the inside of the page). Preferably, the connector 112 formed as a socket is mounted on the printed circuit board 114 and carries the integrated circuit to the signal and/or power interface 132 of the printed circuit board. When the socket is directly mounted on the printed circuit board 114 and the socket carries the integrated circuit 22, it is advantageous to form the connector 112 as a socket.

FIG. 12C shows a view of the integrated circuit 22 in the connector 112 formed as a frame shown in FIG. 11 according to the preferred embodiment of the present invention. 12C shows the connector 112 formed as a frame 15 frame, wherein the connector 112 has a side IP extending to the outside of each side 72 and 74 of the integrated circuit 22, and has a side IP arranged to be flush with or located at the bottom of the integrated circuit 22 A lower part of a point below the bottom, and an upper part arranged to be flush with the top 68 of the integrated circuit 22 or a point above the top 68. When the integrated circuit 22 is directly mounted on the printed circuit board 114, the connector 112 formed as a frame is advantageous.

:0 FIG. 13 shows a view of the integrated circuit 22 shown in FIG. 11 coupled with the remote circuit 52 located in the connector '112 or on the printed circuit board 114 according to a preferred embodiment of the present invention.

The remote circuit 52 includes a remote circuit signal connector 134 and a remote circuit power connector 136, and has a top 144, a bottom 146, and sides 148 and 150. The connector 140 is provided on one or more sides of the remote circuit 52 . The remote circuit 52 can be connected by a connector

140 load, can also be installed on the printed circuit board 114 ±₀The remote circuit-to-printed circuit board signal and/or power interface 138 provides a path for transmitting signals and/or power between the printed circuit board 114 and the remote circuit 52, respectively. The remote circuit 52, the connector 140, the interface 138, the printed circuit board 114, the remote circuit signal connector 134, and the remote circuit power connector 136 are respectively provided with the aforementioned integrated circuit 22, connector 112, interface 132, and printed circuit board.

02818928.0 p.

114. Similar devices, features, functions and operations of the integrated circuit signal connector 48 and the integrated circuit power connector 46.

In addition, the signal connector 26 formed as a conductor 116 or a printed circuit board trace 118 can be connected to any one or more of the top 68, bottom 70, and sides 72 and 74 of the integrated circuit 22 and the top 144, bottom of the remote circuit 52. Signals are transmitted between 146 and any one or more of the side portions 148 and 150. Preferably, the signal connector 26 is formed as a printed circuit board trace 118 and transmits signals between the bottom 70 of the integrated circuit and the bottom 146 of the remote circuit 52.

The power connector 24 formed as a conductor 116 or a printed circuit board trace 118 may be coupled to any one or more of the top 144, the bottom 146, and the sides 148 and 150 of the remote circuit 52. Preferably, the power connector 24 is formed as a conductor 116 and couples power to the sides 148 and 150 of the remote circuit 52. Note that the power supply 15 connector 24 coupled to the remote circuit 52 is an additional device, which is not shown in FIGS. 1 and 2 for the sake of clarity of these two figures. Generally, an active remote circuit requires power from the power transmission system 12, while a passive remote circuit does not require power from the power transmission system 12.

The integrated circuit 22 and the remote circuit 52 can carry the same type or different types of circuits. The circuit types include (not limited to) a microprocessor, a digital signal processor (DSP), a storage device, an audio-video interface device, and a user The interface device may be an active device and/or a passive device.

The break 142 in the printed circuit board 114 indicates that the printed circuit board 114 of the integrated circuit 22 may be the same as or different from the printed circuit board of the remote circuit 52. When the integrated circuit 22 and the remote circuit 52 are mounted on the same printed circuit board 114, the signal connector 26 and/or the power connector 24 may be implemented by the conductor 116 or the printed circuit board trace 118. When the integrated circuit 22 and the remote circuit 52 are mounted on different printed circuit boards, the signal connector 26 and/or the power connector 24 can be realized through the conductor 116 or through the printed circuit board traces 118 on each printed circuit board, where , The conductor (not shown) forms different prints

02818928.0 Jumper between printed circuit board traces 118 on the first circuit board.

The connector 112 may be integrally formed with the connector 140 as a single connector for the integrated circuit 22 and the remote circuit 52. Alternatively, the connector 112 and the connector 140 may be formed as separate components and then mechanically connected to each other, or used separately. When these components are mechanically connected to each other, either side of the connector 112 can be connected to either side of the connector 140.

The interface 132 may be integrally formed with the interface 138 as a single interface for the integrated circuit 22 and the remote circuit 52. Alternatively, the interface 132 and the interface 138 may be formed as separate components and then mechanically connected to each other, or used separately. When these components are mechanically connected to each other, either side of the interface 132 can be connected to either side of the interface 138.

Although FIG. 13 shows the integrated circuit 22 and the remote circuit 52 close to each other in a side-by-side configuration, FIG. 13 is not limited to this configuration. In fact, the integrated circuit 22 and the remote circuit

52 can have any physical configuration relative to each other. For example, as shown in more detail in FIG. 14, the integrated circuit 22 and the remote circuit 52 may have a stacked configuration. Also, although FIG. 13 shows only two circuits (ie, the integrated circuit 22 and the remote circuit 52), FIG. 13 is not limited to only two circuits. In fact, any number of integrated circuits and/or remote circuits can operate together using the same devices, features, functions, and operations described above between the integrated circuit 22 and the remote circuit 52.

FIG. 14 shows a view of the integrated circuit 22 and the remote circuit 52 shown in FIG. 13 that are coupled together in a stacked configuration according to a preferred embodiment of the present invention. FIG. 14 shows the connector 140 for carrying the remote circuit 52 on or on top of the connector 112 for carrying the integrated circuit 22. The signal connector 26 may be routed to another remote circuit 152 through conductor 116 or through a printed circuit board trace (not shown). FIG. 14 shows various signal connectors 26 and/or power connectors 24 that are possible when the integrated circuit 22 and the remote circuit 52 are coupled together in a stacked configuration. This stacked configuration is advantageous for partner, cluster, or master/slave integrated circuits. These integrated circuits are essentially dedicated to working with each other, but separate

02818928.0 package to optimize the cost and/or performance of each semiconductor package. The partner integrated circuit includes (but is not limited to) a microprocessor and a storage device.

Figure 15, Figure 16, Figure 17, Figure 18 and Figure 19 each show the voltage regulator module 38 and decoupling capacitors arranged in various positions according to the preferred embodiment of the present invention shown in Figure 13 or Figure 14 42 view of integrated circuit 22 and remote circuit 52. In each of these figures, integrated circuit signal connector 46, integrated circuit power connector 48, remote circuit signal connector 134, remote circuit power connector 136, integrated circuit 22, and the top, bottom, and sides of remote circuit 52 Reference number, and each connector 112 and 140

The reference numbers of the six dashed lines of W are not shown in these figures for the sake of clarity.

The signal connector 26 and the power connector 24 are each shown coupled to one side of the integrated circuit 22 and the remote circuit 52 in these five figures for clarity. In fact, as described above, the signal connector 26 and/or the power connector 24 may be coupled to one or more sides of the integrated circuit 22 and/or the remote circuit 15 52.

These five figures introduce new system blocks, including the voltage regulator module 154 and decoupling capacitor 158 that are not shown in FIGS. 1 and 2 for the reasons described in the description of FIG. 13. The introduction of the voltage regulator module 154 and/or the decoupling capacitor 158 provides for communication with the voltage regulator module 38 and decoupling by introducing various alternative paths for transmitting signals and/or power to the integrated circuit 22 and the remote circuit 52. The synergy of capacitor 42. The solid line represents the preferred path, and the dashed line represents the alternative path. This synergy applies to each of these five figures. The synergy uses a similar approach as described above for the integrated circuit 22, the voltage regulator module 38, and the decoupling capacitor 42 involving the remote circuit 52, the voltage regulator module 154, the decoupling capacitor 158, the integrated circuit 22, and the voltage regulator module. 38 and the specification of decoupling capacitor 42. The specifications of the integrated circuit 22 and the remote circuit 52 generally determine whether one or two voltage regulator modules are required or whether one or two decoupling capacitors are required. As mentioned above, the physical proximity of the integrated circuit 22 and the remote circuit 52 to the voltage regulator module and decoupling capacitors are also factors that minimize the impedance and the resulting voltage drop. Therefore, the specifications of the remote circuit 52 30 and the integrated circuit 22 may allow the remote circuit 52 to be shared with the integrated circuit 22

02818928.0 The first voltage regulator module 38 and/or the decoupling capacitor 42. Otherwise, the remote circuit 52 must use its own voltage regulator module 154 and/or decoupling capacitor 158.

For illustration purposes only and for the sake of clarity, the voltage regulator module 38, the decoupling capacitor 42, the voltage regulator module 154, and the decoupling capacitor 158 are in the connector 112 or

The specific part of 140 is shown. As described above with reference to Figure 11, each of these elements can be located in any part of the connector 112 or 140, as shown in Figures 12A, 12B, and 12C, any part including (but not limited to) a cover, a socket And/or frame.

FIG. 15 shows the integrated circuits 22 and 158 respectively having voltage regulator modules 38 and 154 and decoupling capacitors 42 and 158 in the connectors 112 and 140 according to the preferred embodiment of the present invention shown in FIG. 13 or FIG. View of remote circuit 52. As described above with reference to FIG. 2, the power transmission system 12 is coupled with the integrated circuit 22 to supply power to the integrated circuit 22. As described above with reference to Figure 2, the preferred path for high-voltage, low-current power transmission is to use conductor 116 or printed circuit board traces 118 from power supply 34 through power connector 36 to voltage regulator module 38, and then use conductor 116 through The power connector 40 to the decoupling capacitor 42 becomes a low-voltage, high-current power, and then the conductor 116 is used to couple to the integrated circuit 22 via the power connector 44 to become a low-voltage, high-current power. Moreover, as described with reference to FIG. 2, the voltage regulator module 38 can also use the conductor 116 instead of the decoupling capacitor 42 to directly couple with the integrated circuit 22 via the Ϊ0 power connector 54 to form a low-voltage, high-current power supply.

In a manner similar to that described with reference to FIG. 2, the power transmission system 12 is coupled with the remote circuit 52 to supply power to the remote circuit 52. The preferred path for power transmission is to use conductor 116 or printed circuit board trace 118 from power supply 34 through power connector 36 to voltage regulator module 25 to block 154 into high voltage, low current power, and then use conductor 116 through power connector 156 When the decoupling capacitor 158 becomes a low-voltage, high-current power, then the conductor 116 is used to become a low-voltage, high-current power through the power connector 166 to the remote circuit 52. Furthermore, in a manner similar to that described with reference to FIG. 2, the voltage regulator module 154 can also use the conductor 116 instead of the decoupling capacitor 158 to the remote circuit power connector 16 via the voltage regulator module.

It is directly coupled with the remote circuit 52 to become a low voltage, high current electricity.

02818928.0 Alternatively, the voltage regulator module 38 can use the conductor 116 to send low voltage and high current electricity to the decoupling capacitor 158 via the power connector 162, or it can use the conductor 116 instead of the voltage regulator module 154 via the power connector 162 And 160 are sent directly to the remote circuit 52. Alternatively, the decoupling capacitor 42 may use the conductor 116 instead of the voltage regulator module 154 or the decoupling capacitor 158 to directly send the low voltage and high current electricity to the remote circuit 52 via the power connector 164.

Therefore, in FIG. 15, the connector 112 may only carry the voltage regulator module 38, only the decoupling capacitor 42, or both the voltage regulator module 38 and the decoupling capacitor 42. Similarly, the connector 140 may carry neither the voltage regulator module 154 nor the decoupling capacitor 158, that is, only one of the voltage regulator module 154 and the decoupling capacitor 158, or the voltage regulator module 154 and the decoupling capacitor 158. both sides. The specific desired combination depends on various engineering considerations, including (but not limited to): the type of circuit used in the integrated circuit 22 and the remote circuit 52, as shown in Figures 7A and

The signal interface types used shown in Table 84 of 7B, the desired characteristics of the thermal management system 18 described herein, etc.

FIG. 16 shows the integrated circuit 22 and the remote controller respectively having voltage regulator modules 38 and 154 and decoupling capacitors 42 and 158 on conductors 116 and 117 according to a preferred embodiment of the present invention shown in FIG. 13 or FIG. View of circuit 52. As described with reference to FIG. 2, the power transmission system 12 is coupled with the integrated circuit 22 to supply power to the integrated circuit 22.

As described with reference to Figure 2, the preferred path for high-voltage, low-current power transmission is to use conductor 116 from the power supply 34 through the power connector 36 to the voltage regulator module 38, and then use the conductor 116 through the power connector 40 to the decoupling capacitor 42 becomes a low-voltage, high-current electricity, and then the conductor 116 is used to become a low-voltage, high-current electricity through the power connector 44 to the integrated circuit 22.

Moreover, as described with reference to FIG. 2, the voltage regulator module 38 can also use the conductor 116 instead of the decoupling capacitor 42 to directly couple with the integrated circuit 22 via the power connector 54 to form a low-voltage, high-current power.

02818928.0 First, in a manner similar to that described with reference to FIG. 2, the power transmission system 12 is coupled with the remote circuit 52 to supply power to the remote circuit 52. The preferred path for power transmission is to use the conductor 117 from the power supply 34 to the voltage regulator module 154 via the power connector 36 to become high voltage and low current electricity, and then to use the conductor 117 to pass through the power connector 156 to the decoupling capacitor 158 to become a low voltage, The high-current electricity is then used to connect the conductor 117 to the remote circuit 52 via the power connector 166 to become a low-voltage, high-current electricity. Moreover, in a similar manner as described with reference to FIG. 2, the voltage regulator module 154 can also use the conductor 117 instead of the decoupling capacitor 158 to directly couple with the remote circuit 52 via the voltage regulator module to the remote circuit power connector 160 to form a low voltage. , High current electricity.

Alternatively, the voltage regulator module 38 can use conductors 116 and/or 117 to send low voltage and high current electricity to the decoupling capacitor 158 via the power connector 162, or it can use conductors 116 and/or 117 instead of the voltage regulator. Module 154 is sent directly to remote circuit 52 via power connectors 162 and 160.

Alternatively, the decoupling capacitor 42 can use the conductor 116 and/or 117 instead of the voltage regulator module *154 or the decoupling capacitor 158 to directly send the low voltage and high current electricity to the remote circuit 52 via the power connector 164.

Therefore, in FIG. 16, the conductor 116 may only carry the voltage regulator module 38, only the decoupling capacitor 42, or both the voltage regulator module 38 and the decoupling capacitor 42. Similarly, the conductor 117 may carry neither the voltage regulator module 154 nor the decoupling capacitor 158, that is, only one of the voltage regulator module 154 and the decoupling capacitor 158, or both the voltage regulator module 154 and the decoupling capacitor 158 . The specific desired combination depends on various engineering considerations, which include (but are not limited to): the type of circuit used in the integrated circuit 22 and the remote circuit 52, as shown in Table 84 in Figures 7A and 7B The type of signal interface used, the desired characteristics of the thermal management system 18 described herein, etc.

Figure 17 is a diagram showing the preferred embodiments of the present invention shown in Figure 13 or Figure 14 each having

02818928.0 A view of the integrated circuit 22 and the remote circuit 52 of the voltage regulator modules 38 and 154 and decoupling capacitors 42 and 158 on the printed circuit board 114, respectively. As described with reference to FIG. 2, the power transmission system 12 is coupled with the integrated circuit 22 to supply power to the integrated circuit 22. As described with reference to Figure 2, the preferred path for high-voltage, low-current power transmission is to use the printed circuit board trace 118 from the power supply 34 via the power connector 36 to the voltage regulator module 38, and then use the printed circuit board trace 118 via the power supply connector 36 to the voltage regulator module 38. The power connector 40 to the decoupling capacitor 42 becomes a low-voltage, high-current power, and then uses the printed circuit board traces 118 and conductors 116 to the integrated circuit 22 through the power connector 44 to become a low-voltage, high-current power. And as described with reference to FIG. 2, the voltage regulator module 38 can also use printed circuit board traces 118 and conductors 116.

Without using the decoupling capacitor 42, it is directly coupled with the integrated circuit 22 via the power connector 54 to become a low-voltage, high-current power supply.

In a manner similar to that described with reference to FIG. 2, the power transmission system 12 is coupled with the remote circuit 52 to supply power to the remote circuit 52. The preferred path for power transmission is to use printed circuit board traces 118 from the power supply 34 through the power connector 36 to the voltage regulator module 154 to become high-voltage, low-current power, and then use the printed circuit board traces 118 to pass the power connector 156 to the voltage regulator module 154. The decoupling capacitor 158 becomes a low-voltage, high-current circuit, and then uses printed circuit board traces

118 and the conductor 116 are connected to the remote circuit 52 via the power connector 166 to become a low-voltage, high-current electricity. Moreover, in a similar manner as described with reference to FIG. 2, the voltage regulator module 154 can also use the printed circuit board traces 118 and conductors 116 without using the decoupling capacitor 158 to communicate directly with the remote circuit power connector 160 via the voltage regulator module. The remote circuit 52 is coupled into low voltage, high current electricity.

Alternatively, the voltage regulator module 38 can use the printed circuit board traces 118 to send low voltage and high current electricity to the decoupling capacitor 158 via the power connector 162, or it can use the printed circuit board traces 118 and conductors 116 instead of voltage. The regulator module 154 is directly sent to the remote circuit 52 via the power connectors 162 and 160. Alternatively, the decoupling capacitor 42 can use the printed circuit board traces 118 and conductors 116 instead of the voltage regulator module 154 or the decoupling capacitor 158 to send low voltage and high current electricity directly to the remote circuit 52 via the power connector 164.

02818928.0 First, in FIG. 17, the printed circuit board 114 may only carry the voltage regulator module 38, only the decoupling capacitor 42, or both the voltage regulator module 38 and the decoupling capacitor 42. Similarly, the conductor 117 may carry neither the voltage regulator module 154 nor the decoupling capacitor 158, that is, only one of the voltage regulator module 154 and the decoupling capacitor 158, or the voltage regulator module 154 and the decoupling capacitor 158. both sides. The specific desired combination depends on various engineering considerations including (but not limited to); the type of circuit used in the integrated circuit 22 and the remote circuit 52, as shown in Table 84 of Figure 7A and Figure 7B The type of signal interface, the expected characteristics of the thermal management system 18 described herein, etc.

18 is shown in FIG. 13 or FIG. 14 according to the preferred embodiment of the present invention, each having voltage regulator modules 38 and 154 located on conductors 116 and 117 and decoupling capacitors 42 and 42 located in connectors 112 and 140, respectively. 158 view of integrated circuit 22 and remote circuit 15 52. As described with reference to FIG. 2, the power transmission system 12 is coupled with the integrated circuit 22 to supply power to the integrated circuit 22. As described with reference to FIG. 2, the preferred path for high-voltage, low-current power transmission is to use conductor 116 from the power supply 34 through the power connector 36 to the voltage regulator module 38, and then use the conductor 116 through the power connector 40 to the decoupling capacitor 42 becomes a low-voltage, high-current electricity, and then uses the conductor 116 to pass through the power connector 44 to the integrated circuit 22 to become a low-voltage, high-current electricity. Moreover, as described with reference to FIG. 2, the voltage regulator module 38 can also use the conductor 116 instead of the decoupling capacitor 42 to directly couple with the integrated circuit 22 via the power connector 54 to form a low-voltage, high-current power.

In a manner similar to that described with reference to FIG. 2, the power transmission system 12 is coupled with the remote circuit 52 to supply power to the remote circuit 52. The preferred path for power transmission is to use conductors 117 and 116 from the power supply 34 to the voltage regulator module 154 via the power connector 36 to become high voltage and low current electricity, and then use the conductor 117 to pass through the power connector 156 to the decoupling capacitor 158 to become low. Voltage, high current electricity, and then use conductor 117 to remote circuit 52 via power connector 166 to become low voltage, high current electricity. Moreover, in a similar manner as described with reference to FIG. 2, the voltage regulator module 154 can also use the conductor 117 instead of the decoupling capacitor 158.

02818928.0 The power connector 160 of the first to the remote circuit via the voltage regulator module is directly coupled with the remote circuit 52 to become a low-voltage, high-current power supply.

Alternatively, the voltage regulator module 38 can use the conductor 116 to send low voltage and high current electricity to the decoupling capacitor 158 via the power connector 162, or use the conductor 116 instead of the voltage regulator module 154 via the power connectors 162 and 160. Send directly to the remote circuit 52. Alternatively, the decoupling capacitor 42 may use the conductor 116 instead of the voltage regulator module 154 or the decoupling capacitor 158 to directly send the low voltage and high current power to the remote circuit 52 via the power connector 164.

Therefore, in FIG. 18, the conductor 116 carries the voltage regulator module 38 and the connector 112 carries the decoupling capacitor 42. Similarly, the conductor 117 carries the voltage regulator module 154, The connector 140 carries a decoupling capacitor 158« FIG. 19 is shown in FIG. 13 or FIG. 14 according to the preferred embodiment of the present invention, each having voltage regulator modules 38 and 154 on the printed circuit board 114 and respectively located on the connector 112 A view of the integrated circuit 22 and the remote circuit 52 of the decoupling capacitors 42 and 158 within and 140. As described with reference to FIG. 2, the power transmission system 12 is coupled with the integrated circuit 22 to supply power to the integrated circuit 22. As described with reference to FIG. 2, the preferred path for high-voltage, low-current power transmission is to preferably use printed circuit board traces 118 and selectively use conductors 116 from the power supply 34 to the voltage regulator module 38 via the power connector 36, Then preferably use the conductor 116 and selectively use the printed circuit board trace 118 via the power connector 40 to the decoupling capacitor 42 to become a low voltage, high current electricity, and then preferably use the conductor 116 and selectively use the printed circuit board trace 118 The power supply connector 44 to the integrated circuit 22 becomes a low-voltage, high-current power. And as described with reference to FIG. 2, the voltage regulator module 38 can also preferably use the conductor 116 via the power connector 54 and instead of using the printed circuit board traces and the conductor 116 via the power connectors 162 and 44 instead of using the The coupling capacitor 42 is directly coupled with the integrated circuit 22 to form a low-voltage, high-current power supply.

In a manner similar to that described with reference to FIG. 2, the power transmission system 12 is coupled to the remote

02818928.0 The first circuit 52 to supply power to the remote circuit 52. The preferred path for power transmission is to preferably use printed circuit board traces 118 and instead use conductors 116 from the power supply 34 to the voltage regulator module 154 via the power supply connector 36 to become high-voltage, low-current power, and then preferably use conductors 116 and Optionally use printed circuit board traces 118 via power connector 156 to decoupling 5. Capacitor 158 becomes a low voltage, high current power, then preferably use conductor 116 and selectively use printed circuit board traces 118 via power connector 166 The remote circuit 52 becomes low-voltage, high-current electricity. And in a similar manner as described with reference to FIG. 2, the voltage regulator module 154 can also preferably use the conductor 116 and selectively use the printed circuit board trace 118 instead of the decoupling capacitor 158 to the remote circuit via the voltage regulator module. The power supply 10 connector 160 directly couples with the remote circuit 52 to form a low voltage, high current power supply.

Alternatively, the voltage regulator module 38 may preferably use the conductor 116 and selectively use the printed circuit board trace 118 to send low voltage and high current electricity to the decoupling capacitor 158 via the power connector 162, or may preferably use the conductor 116 or alternatively The printed circuit board 15 trace 118 is used instead of the voltage regulator module 154 to be directly sent to the remote circuit 52 via the power connector 162. Alternatively, the decoupling capacitor 42 can preferably use the conductor 116 and selectively use the printed circuit board 118 instead of the voltage regulator module 154 or the decoupling capacitor 158 to directly send the low voltage and high current electricity to the remote circuit 52 via the power connector 164 .

Therefore, in FIG. 19, the printed circuit board 114 carries the voltage regulator module 38 and the connector 112 carries the decoupling capacitor 42. Likewise, the printed circuit board 114 carries the voltage regulator module 154, and the connector 140 carries the decoupling capacitor 158.

In Figure 15, Figure 18 and Figure 19, the decoupling capacitor 42 located in the connector may be 25 using power contacts directly soldered to the top 68 and/or sides 72 and 74 of the integrated circuit 22

92 in the form of a monolithic capacitor or multiple discrete capacitors. The decoupling capacitor 42 receives power from the power connector 24 formed as a conductor 116 via a connector (not shown) mounted on the integrated circuit 22 instead of receiving power from the integrated circuit 22 via the printed circuit board trace 118. In this case, the connector 112 includes: a decoupling capacitor 42, an integrated circuit power connector 46 formed as a power contact 92, which may be used to make the decoupling capacitor

02818928.0 Solder that electrically couples the first device 42 and the power contact 92, and possibly a connector (not shown) that connects the conductor 116 and the decoupling capacitor 42. In this example, the connector 112 represents a collection of discrete components assembled in a specific manner, rather than a conventional overall structure such as a plastic cover.

20 shows a view of the integrated circuit 22 with a thermal management system 18 and an electromagnetic interference (EMI) emission control system 20 according to a preferred embodiment of the present invention shown in FIGS. 11-19. In FIG. 20, for clarity, the power transmission system 12, the signal transmission system 14, the signal connector 26, the power connector 24, the integrated circuit signal connector 48, the integrated circuit power connector 46 and the dashed lines 120, 122, 124, Each of 126, 128, and 130 is not shown in the figure, but is included to form a more detailed design.

The thermal management system 18 includes a first heat sink 200 and optionally a first heat spreader 202 and a first fan 204, each of which is preferably located on the top 68 of the integrated circuit 22. Alternatively, the thermal management system 18 includes a second heat sink 206 and optionally a second heat spreader 208 and a second fan 210, each of which is preferably located under the bottom 70 of the integrated circuit 22.

As shown in FIG. 1, the first heat sink 200 and the second heat sink 206 provide a path for drawing heat away from the integrated circuit 22 via the thermal connector 28. The first heat sink 200 and the second heat sink 206 can be made of any type of material, and preferably are made of metal. The first heat sink 200 and the second heat sink 206 may have one or more points of contact with the integrated circuit 22, the heat spreader 202, and/or the printed circuit board 114. The first heat sink 200 and the second heat sink 206 may have any type of design, and preferably have a plurality of heat sinks that can move air between adjacent heat sinks. Alternatively, the first heat sink 200 and the second heat sink 206 may be formed as heat pipes containing a material that changes state (for example, between liquid and gas) in response to temperature. The first heat sink 200 and the second heat sink 206 may be fixed to the connector 112, the printed circuit board 114, or the conductor 116. The first heat sink 200 and the second heat sink 206 are preferably formed as separate parts, but may also form an integral part.

The first heat spreader 202 and the second heat spreader 208 are provided for

02818928.0 p.

The heat of 22 is conducted to the heat conduction paths of the first heat sink 200 and the second heat sink 206, respectively. The first heat spreader 202 and the second heat spreader 208 can be made of any type of material, preferably made of metal, and selectively made of gel or colloid. Generally, the first heat spreader 202 and the second heat spreader 208 are in direct contact with the integrated circuit 22. The first heat spreader 202 and the second heat spreader 208 are preferably formed as separate parts, but may also form an integral part.

The first fan 204 and the second fan 210 force air to pass through the first radiator 200 and the second radiator 206, respectively, so as to extract heat from the first radiator 200 and the second radiator 206, respectively. The first fan 204 and the second fan fan 210 may have any type of design suitable for pushing and/or pulling air through the first radiator 200 and the second radiator 206, respectively. The first fan 204 and the second fan 210 can receive power via the printed circuit board 114, the connector 112 or the conductor 116. The first fan 204 and the second fan 210 may be aligned with the connector 112, the printed circuit board 114 and/or the conductor 116 and/or fixed to the connector 112, the printed circuit board 114 and/or the conductor 116. The first fan 204 and the second fan 210 are preferably formed as separate parts, but may also form an integral part.

The first heat spreader 202, the first heat sink 200, and the first fan 204 are preferably arranged on the top 68 of the integrated circuit 22 in a stacked configuration to extract heat from the integrated circuit 22. Similarly, the second heat spreader 208, the second heat sink 206, and the second fan 210 are preferably arranged under the bottom 70 of the integrated circuit 22 in a stacked configuration to extract heat from the integrated circuit 22.

As mentioned above, the second heat spreader 208 may also provide the signal and/or power interface 132 of the integrated circuit to the printed circuit board 25. In this case, the integrated circuit to the printed circuit board signal and/or power interface 132 is constructed as described above, and is further constructed to have thermal conductivity characteristics to provide a heat spreader. Therefore, the second heat spreader 208 may also provide an integrated circuit-to-printed circuit board signal and/or power interface 132, and an advantageous aspect of the interface 132 is to provide various functions of the signal and/or power interface function and the heat pipe function.

02818928.0 The second heat spreader 208 conducts heat to the printed circuit board 114 or conducts heat to the second heat sink 206 located at the bottom of the printed circuit board 114 through the printed circuit board 114 using printed circuit board vias, heat pipes, etc. The second fan 210 cools the second radiator 206. The connector 112 and/or the printed circuit board 114 may be one of the first heat spreader 200, the first heat spreader 202, the first fan 204, the second fan 210, the second heat spreader 206, and the second heat spreader 208 Or multiple parties provide suitable alignment and/or installation mechanisms.

Thermal grease (not shown) can be used between the integrated circuit 22 and the first heat spreader 202, between the first heat spreader 202 and the first heat sink 200, the integrated circuit 22 and the second heat spreader. 208, between the second heat spreader 208 and the printed circuit board 114, and/or between the second heat spreader 208 and the second heat sink 206. The thermal grease increases the thermal conductivity between adjacent components.

As described above, the electromagnetic interference emission control system 20 is coupled with the integrated circuit 22 on the electromagnetic interference connector 30 representing the electromagnetic interference emission path 15. As shown in FIG. 20, the electromagnetic interference emission control system 20 can be located on one or more sides of the integrated circuit 22, and preferably located on the four sides 72 and 74 of the integrated circuit 22. The electromagnetic interference emission control system 20 may be formed of any type of suitable conductive material, and the conductive material type includes (but is not limited to) metal, metal-coated plastic, flexible circuit, conductive ink-coated plastic, and the like. The electromagnetic interference emission control system 20 can be rigid or flexible. The electromagnetic interference emission control system 20 can have any suitable form, shape and size. Preferably, the electromagnetic interference emission control system 20 is carried by a connector 112 that provides a suitable alignment and/or installation mechanism. In this case, the electromagnetic interference emission control system 20 can be located on the inner surface of the connector 112, can be embedded in the connector 112, or can be located on the outer surface of the connector 112 to 25. The electromagnetic interference emission control system 20 and the connector 112 are preferably formed as separate parts. These separate parts are aligned and fixed together by insert molding, over molding, press-fitting, snaps, clips, adhesives, etc., or The whole is formed as one.

The electromagnetic interference emission control system 20 can be coupled with the first heat spreader 202 and/or the first heat sink 200 through the electromagnetic interference joints 212 30 and 214, respectively. Similarly, the electromagnetic

02818928.0 The first interference emission control system 20 can be coupled with the second heat spreader 208 and/or the second heat sink 206 through the electromagnetic interference joints 216 and 218, respectively. The electromagnetic interference joints 212, 214, 216, and 218 represent conductive paths for electrically connecting respective components and the electrical interference emission control system 20. Any electromagnetic interference emission directed to the first heat spreader 202 and/or the first heat spreader 200 will be routed to the first heat spreader 202 and/or the first heat spreader 200, respectively, and then through the electromagnetic interference joints 212 and 214 EMI emission control system 20. Therefore, an advantageous aspect of the first heat spreader 202 and/or the first heat sink 200 is to provide electromagnetic interference emission control on the top 68 of the integrated circuit 22. Similarly, any electromagnetic interference emission directed to the second heat spreader 208 and/or the printed circuit board 114 will pass through the second heat spreader 208 and/or the printed circuit board 114, respectively, and then through the electromagnetic interference joint 216 and/or respectively 218 is routed to the electromagnetic interference emission control system 20. Therefore, an advantageous aspect of the second heat spreader 208 and/or the printed circuit board 114 is to provide electromagnetic interference emission control under the bottom 70 of the integrated circuit 22. The electromagnetic interference emission control system 20 is electrically coupled with a suitable ground potential through the electromagnetic interference ground path 220, so that the integrated circuit 22 15 Any undesired electromagnetic interference emission radiated is properly grounded without disturbing other circuits in the area and/or any undesired electromagnetic interference emission radiated toward the integrated circuit 22 is properly grounded without disturbing the integrated circuit 22.

21 shows a cross-sectional view of the integrated circuit 22 formed as a secondary semiconductor package 62 with a vertical semiconductor mold 58, as shown in FIGS. 4C, 5, 8A, 8B, and 9A.

As shown in FIG. 9B, FIG. 9C and FIG. 11, the integrated circuit 22 has a capacitive signal interface on the bottom 70 of the integrated circuit 22 and has power contacts 92 on the sides 72 and 74 of the integrated circuit 22. The package 62 is preferably formed as a low temperature co-fired ceramic ("LTCC") package, which is well known in the art. Using the LTCC package, as shown in FIG. 4C, the semiconductor substrate 60 and the bottom side of the semiconductor package 62 are integrally formed as one body.

The semiconductor substrate 60 carries the signal lead frame 220, the power lead frame 222 and the semiconductor mold 58. The signal lead frame 220 and the power lead frame 222 each extend from the inside of the semiconductor package 62 to the outside of the semiconductor package 62. As shown in FIG. 5, FIG. 9B and FIG. 11, the signal lead frame 220 each has: a signal attenuator 226, which is located in the semiconductor package

02818928.0 is the inner part and disposed on the top of the semiconductor substrate 60; and the signal contact 90 is disposed on the outside of the semiconductor package 62 and disposed on the bottom of the semiconductor package 62. Note that, as described with reference to FIG. 8B, the signal contact 90 is flush with the semiconductor package 62. Preferably, as shown in the table 84 of FIGS. 7A and 7B, the signal contact 90 forms one side of a conductive plate suitable for use with a capacitive signal connector.

Similarly, as shown in FIGS. 5, 9C, and 11, the power lead frames 222 each have: a power attenuator 228 located inside the semiconductor package 62 and disposed on the top of the semiconductor substrate 60; and a power contact 92, which It is located outside the semiconductor package 62 and disposed on the sides 72 and 74 of the semiconductor package 62. Preferably, the power contact 92 is located on the side 72 of the integrated circuit 22. Alternatively, the power contact 92 is located on the side 74 of the integrated circuit 22. Note that, as described with reference to FIG. 8A, the power contact 92 protrudes and is located outside the semiconductor package 62.

The semiconductor mold 58 is mounted on the semiconductor substrate 60 in an upright position, wherein the top 232 of the semiconductor mold 58 with a power attenuator and/or a signal attenuator (not shown) is fhce away from the semiconductor substrate 60.

The signal wiring connector 230 connects the appropriate signal solder joints0 on the top 232 of the semiconductor die 58 with the corresponding signal solder joints 226 provided on the top of the semiconductor substrate 60. Similarly, the power wiring connector 234 connects the appropriate power solder joints on the top 232 of the semiconductor mold 58 with the corresponding power solder joints 228 provided on the top of the semiconductor substrate 60.

The integrated circuit to printed circuit board signal and/or power interface 132 is provided at the bottom 70 of the integrated circuit 22. Preferably, as described above, the interface 132 is formed of a dielectric material with a suitable dielectric constant. Preferably, the interface 132 is formed as a separate component and then installed on the bottom 70 of the integrated circuit 22.

22 shows a cross-sectional view of the integrated circuit 22 formed as a secondary semiconductor package 62 30 with a flip-chip semiconductor die 58, as shown in FIG. 4C, FIG. 5, FIG. 8A, FIG. 8B, and FIG. 9A.

02818928.0 p.

As shown in FIG. 9B, FIG. 9C and FIG. 11, the integrated circuit 22 has a capacitive signal interface at the bottom of the integrated circuit 22 and has power contacts 92 on the sides 72 and 74 of the integrated circuit 22. The integrated circuit 22 in FIG. 22 is the same as the integrated circuit 22 described in FIG. 21, except that the semiconductor die 58 is inverted, or called "flip chip", arranged on the semiconductor base 5 board 60. This is in the semiconductor design The domain is well known. The orientation of the flip chip requires a different method from that of the straight position, which transmits the signal and power to the signal contact 90 and the power contact 92 respectively.

The top 232 of the semiconductor mold 58 facing away from the semiconductor substrate 60 in FIG. 22 faces the semiconductor substrate 60 in FIG. 22. Therefore, in FIG. 22, the top 232 of the integrated circuit 22 in FIG. 21 that can be conventionally referred to as the bottom 232 of the integrated circuit 22 can be conventionally referred to. Using the flip chip orientation in FIG. 22, the power solder joints and/or signal solder joints (not shown) on the bottom 232 of the integrated circuit 22 face the semiconductor substrate 60. The signal pads (not shown) on the bottom 232 of the integrated circuit 22 are electrically coupled with the corresponding signal pads 226 provided on the top of the substrate 60 of the semiconductor 15 using a coupling technique known in the semiconductor manufacturing field.

The second power source lead frame 236 has a first power source solder joint 238 and a second power source solder joint 240 electrically coupled to opposite ends of the second power source lead frame 236. The first power source solder joint 238 and the second power source solder joint 240 are each located in the semiconductor The inside of the package 62 is arranged on the top of the semiconductor 0 substrate 60. The first power solder joint 238 is located outside the semiconductor mold 58 and is exposed to sound through the semiconductor mold 58, and the second power solder joint 240 is located under the semiconductor mold 58. Preferably, the power wiring connector 234 connects the first power solder joint 238 with the corresponding power solder joint 228. Alternatively, the first power solder joint 238 may be integrally formed with the corresponding power solder joint 228. Alternatively, the first power solder joint 238 may be soldered to the corresponding power solder joint 228.

FIG. 23 shows a cross-sectional view of the integrated circuit 22 shown in FIG. 21, as shown in FIG. 4C, FIG. 5, FIG. 8A, FIG. 8B, FIG. 10A, FIG. 10B, FIG. 10C, FIG. 11, FIG. 12B, and FIG. 20, The integrated circuit 22 is carried by a connector 112 formed as a socket and supporting the heat sink 200. The integrated circuit 22 in FIG. 23 is the same as the integrated circuit described in FIG. 21. The additional components shown in Figs. 23 30 include a connector 112 formed as a socket and a heat sink 200.

02818928.0 As shown in FIG. 12B, the integrated circuit 22 is carried by a connector 112 formed as a socket. The integrated circuit to printed circuit board signal and/or power interface 132 is represented by a curve extending from the power contact 90 between the two ends of the bottom side of the connector 112. In FIG. 23, the interface 132 is only capacitively coupled to the signal between the integrated circuit 22 and the printed circuit board 114, because power is sent to the side 72 or 74 of the integrated circuit 22. Preferably, the interface 132 is carried together with the bottom of the connector 112 as a separate component part or as an integral part of the connector 112.

The power is directed to the power contact 92 located on the side 72 or 74 of the integrated circuit 22

Ό sent by the integrated circuit 22. Preferably, power is sent to the power contact 92 located on the side 72 of the integrated circuit 22 through the power connector 24 formed as a conductor 116. Alternatively, power is delivered to the power contact 92 located on the side 74 of the integrated circuit 22 through the power connector 24 formed as the printed circuit board trace 116 on the printed circuit board and the conductor 116 formed as the conductor 116 carried by the connector 116. The connector 112 is electrically coupled with the power contact 92 through a corresponding power contact 242 carried by the connector 112. The power contact 92 carried by the connector 112 is made of a suitable conductive material such as metal, and is in physical and electrical contact with the power contact 92 on the integrated circuit 22.

The heat sink 200 is disposed on the top 68 of the integrated circuit 22 and directly contacts the top 68 of the integrated circuit 22. The heat sink 200 draws heat from the integrated circuit 22. As described with reference to Figure 20 above, the heat sink 200 is aligned and/or fixed in place.

24 shows a cross-sectional view of the integrated circuit 22 formed as a secondary semiconductor package 62 with a vertical semiconductor mold 58, as shown in FIGS. 4C, 5, 8A, 8B, 9A, 25-9B, and 9C As shown in FIG. 11, the integrated circuit 22 has a capacitive signal interface on the bottom 70 of the integrated circuit 22 and a power contact 92 on the top 68 of the integrated circuit. The integrated circuit 22 in FIG. 24 is the same as the integrated circuit described in FIG. 21, except that the power contact 92 is located on the top 68 of the integrated circuit 22.

The power supply lead frame 222 has a power supply that is electrically connected to each end of the power supply lead frame 222

02818928.0 Point 228 and power contact 92. The lead frame 222 is routed through the semiconductor substrate 60 and all the way through the sides 72 and 74 of the semiconductor package 62. The power solder joint 228 is located inside the semiconductor package 62 and arranged on the top of the semiconductor substrate 60. As shown in FIG. 5, FIG. 9A or FIG. 10A, the power contact 92 is located outside the semiconductor package 62 and is provided on the top 68 of the semiconductor package 62. Note that, as described with reference to FIG. 8B, the power contact 92 is flush with the semiconductor package 62. The power wiring connector 234 connects the appropriate power solder joints on the top 232 of the semiconductor mold 58 to the corresponding power solder joints 228.

FIG. 25 shows a secondary semiconductor package 62 formed with a flip-chip semiconductor die 58

Ό cross-sectional view of the integrated circuit 22, as shown in Figure 4C, Figure 5, Figure 8A, Figure 8B, Figure 9A, Figure

As shown in FIG. 9B, FIG. 9C and FIG. 11, the integrated circuit 22 has a capacitive signal interface on the bottom 70 of the integrated circuit 22 and a power contact 92 on the top 68 of the integrated circuit 22. The integrated circuit 22 in FIG. 25 is a combination of the integrated circuit 22 described in FIGS. 22 and 24, except for the position of the power solder joint 228. As described with reference to FIG. 22, the integrated circuit 22 in FIG. 25 has a semiconductor die 58 in the flip-chip orientation; and as described with reference to FIG. 24, the integrated circuit 22 in FIG. 25 has a power supply located on the top 68 of the integrated circuit 22. Contact 92. The power solder joints 22, 8 and the signal solder joint 226 are located under the semiconductor mold 58 and are connected to the corresponding power solder joints (not shown) on the bottom 232 of the semiconductor mold 58 in a conventional manner.

26 shows a cross-sectional view of the integrated circuit 22 formed as a first-level semiconductor package with a flip-chip semiconductor die 58, as shown in FIGS. 4B, 5, 8A, 8B, 10A, 10B, and 10C. As shown in FIGS. 11 and 20, the integrated circuit 22 has a capacitive signal interface on the bottom 70 of the integrated circuit 22 and a power contact 92 on the top 68 of the integrated circuit 22. The integrated circuit 22 in FIG. 26 is similar to the integrated circuit 22 described in FIGS. 22 and 25 except for the type of semiconductor package 62 used. In FIG. 26, as described with reference to FIGS. 22 and 25, the semiconductor mold 58 is mounted on the semiconductor substrate 60 in the flip chip orientation.

FIGS. 22 and 25 each show an LTCC type semiconductor package 62 for packaging the semiconductor mold 58, as described for the first time with reference to FIG. 21. However, FIG. 26 shows a semiconductor package formed as a combination of the packaging material 242 and the heat spreader 202.

02818928.0 The first encapsulation material 242, or "glob top, is a compliant material that has the consistency of liquid, paste or gel and is directly applied to the semiconductor mold 58, which is well known in the field of semiconductor manufacturing of. Preferably, the encapsulating material 242 is applied to the periphery of the semiconductor mold 58 and allowed to extend along the side of the semiconductor mold 58, and to be in contact with the semiconductor substrate

60 contacts. Alternatively, the packaging material 242 may also be applied to the top and sides of the semiconductor mold 58. In this optional case, the application of the encapsulating material 242 causes the semiconductor mold 58 to stick to the semiconductor substrate 60 to completely encapsulate.

The Ό heat spreader 202 is arranged in direct contact with the top surface of the semiconductor mold 58. The heat spreader is preferably formed of a thermally conductive material such as metal. Preferably, the heat spreader 202 relies on the packaging material 242 provided on the periphery of the semiconductor mold 58 and is dried and solidified by the packaging material 242 or is held in place by the adhesive or adhesive properties of the packaging material 242. In this case, the combination of the heat spreader 202 and the application of the packaging material 242 on the periphery of the semiconductor mold 58 will make the semiconductor mold 58 stick to the semiconductor substrate 60 to completely encapsulate. Alternatively, the heat spreader 202 may be aligned with and/or mounted on the semiconductor substrate 60. Alternatively, the heat spreader 202 may be fixed in place by the packaging material 242 provided on the top of the semiconductor mold 58.

,·0 In FIG. 26, the top of the semiconductor substrate 60 carries a power contact 92. In this case, the top of the semiconductor package is denoted by the reference number 68 and includes the top of the heat spreader 202 and the top of the semiconductor substrate 60.

FIG. 27 shows a cross-sectional view of the integrated circuit 22 shown in FIG. 26. As further shown in FIGS. 12B and 25, the integrated circuit 22 is formed by a connector 112 that forms a socket and supports the decoupling capacitor 42 and the heat sink 200. Bearer. The integrated circuit 22 and the semiconductor package 62 in FIG. 27 are the same as the integrated circuit 22 and the semiconductor package 62 described in FIG. 26. The additional components shown in FIG. 27 include a connector 112 formed as a socket, a heat sink 200 and a decoupling capacitor 42.

02818928.0 The first decoupling capacitor 42 includes a first conductive plate 244 and a second conductive plate 246 separated by a dielectric material (not shown) used to form the decoupling capacitor 42, which is well known in the field of capacitor design. The decoupling capacitor 42 is provided on the top 68 of the integrated circuit 22, more specifically, on the top 68 of the heat spreader 202.

The first power connector 256 and the selective second power connector 258 located on the opposite side of the decoupling capacitor 42 can electrically couple the power from the power connector 24 with the decoupling capacitor 42. The power supply 34 transmits power to the first power supply connector 256 through the voltage regulator module 38. The second power connector 258 can also receive power from the power source 34 Ό through the voltage regulator module 38, and can also supply power to the remote circuit 52.

The first power connector 256 includes a first power terminal 255 and a second power terminal 257_oThe second power connector 258 loosens the first power terminal 251 and the second power terminal 253. Preferably, the first power terminal 255 of the first power connector 256 and the first power terminal 251 of the second power connector 15 258 are integrally formed with the second conductive plate 246, for example, by metal stamping, punching or forming. However, it may also be formed as a separate component electrically coupled to the second conductive plate 246 by welding, welding, or the like. Similarly, the second power terminal 257 of the first power connector 256 and the second power terminal 253 of the second power connector 258 are integrally formed with the first conductive plate 244, for example, by metal stamping, punching or forming, but they may also ; 0 is formed as a separate component electrically coupled with the first conductive plate 244, for example, by welding, welding, or the like.

The power connector 24 includes a power line 254 and a ground line 252, which are well known in the art and as mentioned above with reference to FIG. 1. The power line 254 carries a predetermined voltage potential, and the ground line 252 carries a ground potential. The power line 254 transmits power to the decoupling capacitor 42, and the ground line 252 provides a return path from the ground potential of the decoupling capacitor 42. The power cord 254 is electrically coupled with the first power terminal 255 of the first power connector 256 and is electrically coupled with the first power terminal 251 of the second power connector 258. The ground wire 252 is electrically coupled with the second power terminal 257 of the first power connector 256 and is electrically coupled with the second power terminal 253 of the second power connector 258. With these connectors, the first conductive plate 244 carries a predetermined voltage potential, and the second conductive plate 246 carries a ground potential.

02818928.0 The first conductive plate 244 of the first decoupling capacitor 42 includes one or more power supply components 250. The power supply components 250 are preferably formed together with the first conductive plate 244 by, for example, metal stamping, punching or forming, but can also be formed, for example, by The welding, welding, etc. are formed as separate parts and then electrically coupled with the first conductive plate 244. As shown in FIG. 27, the power supply part 250 is in electrical contact with a power supply contact 92 corresponding to the voltage potential on the integrated circuit 22 preferably located on the top of the semiconductor substrate 60 of the secondary semiconductor package 62.

The second conductive plate 246 of the decoupling capacitor 42 includes one or more grounding parts 248, and the grounding parts 248 are preferably connected to the second conductive plate by metal stamping, punching or forming, for example.

246 Formed together, but can also be formed as a separate component by welding, welding, etc., and then electrically coupled with the second conductive plate 246. As shown in FIG. 27, the grounding component 248 is preferably located in the secondary semiconductor package 62 The ground contact 92 corresponding to the ground potential on the integrated circuit 22 on the top of the semiconductor substrate 60 is in electrical contact.

It is preferable that the power supply part 250 and the grounding part 248 are each formed as a compliant spring part, but may also be formed as a rigid part such as a pin, a post, or the like. Preferably, the power supply component 250 and the ground component 248 formed as compliant spring components have legs that are angled away from the semiconductor mold 58 and feet that are turned upward away from the semiconductor substrate 60. Alternatively, the power supply member 250 and the ground member 248 formed as compliant spring members may have arms curled inward in a semicircular or semi-elliptical manner and hands curled inward toward the center of the circle or ellipse. The upturned feet or the inwardly curled hands can achieve solderless connections to make assembly easy and convenient. The advantage of this compliant spring component is to reduce the compressive force on the integrated circuit 22 along the Z axis.

The heat sink 200 is placed on the top 68 of the integrated circuit 22. More specifically, the heat sink 200 is provided on the top 68 of the decoupling capacitor 42. The heat spreader 202 dissipates the uneven heat density on the semiconductor mold 58. The heat sink 200 conducts heat from the semiconductor mold 58 through the heat spreader 202 and/or the decoupling capacitor 42.

02818928.0 It is preferable that the decoupling capacitor 42 has a hole extending through the center of the first conductive plate 244, the second conductive plate 246, and the dielectric material, so that the heat sink 200 can be in direct contact with the heat spreader 202. In this case, although most of the heat generated by the integrated circuit 22 is conducted to the heat sink 200 through the heat spreader 202, some of the heat passes through the decoupling capacitor.

42 is conducted to the heat sink 200. Alternatively, the hole in the decoupling capacitor 42 can be eliminated so that the heat sink 200 can conduct all the heat through the decoupling capacitor 42. Alternatively, the heat sink 200 may have one or more regions that surround at least a part of the periphery of the decoupling capacitor 42 and directly contact the heat spreader 202.

, 0 FIG. 28 shows a system of the integrated circuit 22 formed as a secondary semiconductor package 62

The side perspective assembly view of 10, as shown in Figure 4C, Figure 5, Figure 8A, Figure 8B, Figure 9A, Figure 9B, Figure 9C, Figure 11, Figure 12A, Figure 12B, Figure 19 and Figure 20, the integrated circuit 22 is carried by a connector 112 formed as a two-piece cover and socket, and supporting the decoupling capacitor 42 and the heat sink 200. The connector 112 carries an integrated circuit 22 (not shown in FIG. 28) formed as a secondary semiconductor package 62, a decoupling capacitor 42, and an integrated circuit to printed circuit board signal and/or power interface 132 (not shown in FIG. 28) . Place the connector 112 on the printed circuit board

114 on. The heat sink 200 is arranged on the connector 112. This fan is not shown directly in FIG. 28, but is usually installed on the top of the heat sink 200 denoted by B.

The'.0 connector 112 includes a first power connector 256 and a second power connector 258, which are similar to those shown in FIG. 27. The first power connector 256 is preferably shown as a plug-in card connector.

The second power connector 258 is preferably shown as a pin connector. The system 10 includes one or more holes 260 preferably located at the four corners of the system 10. The hole 260 preferably passes through the connector

112 and decoupling capacitor 42 extend to allow system 10 to be mechanically aligned and secured.

29 is an exploded view of the assembly diagram of the system 10 shown in FIG. 27, as shown from the top to the bottom, the system 10 includes: a heat sink 200, a first power connector 256, a second power connector 25 & connector 112 Top 262, first conductive plate 244, second conductive plate 246, central portion 264 of connector 112, signal contact plate 268, integrated circuit 22, printed circuit board 64, bottom 266 of connector 112, and printed circuit board 114 .

02818928.0 The first heat sink 200 is provided on the top 262 of the connector 112. Top of connector 112

262 has integral molding features suitable for receiving the first power connector 256 and the second power connector 258. The top 262 of the connector 112 has a hole extending through the central area thereof, and the hole is adapted to receive the central portion of the bottom of the heat sink 200. The top 262 of the connector 112 also has four holes 260 at its four corners.

The first conductive plate 244 for carrying the voltage potential includes: the second power terminal 253 of the second power connector 258, the second power terminal 257 of the first power connector 256, and a plurality of power contacts 250. The power supply part 250 extends from each of the four sides of the first conductive plate 244. The second power terminal 253 of the second power connector 258 and the second power terminal 257 of the first power connector 256 are bent upward. The power supply part 250 is bent downward. The first conductive plate 244 also has four holes 260 at its four corners.

The second conductive plate 246 for carrying the ground potential includes: a first power terminal 255 of the first power connector 256, a first power terminal 251 of the second power connector 258, and a grounding component 248. The ground contact 248 extends from each of the four sides of the second conductive plate 246. The first power terminal 255 of the first power connector 256 and the first power terminal 251 of the second power connector 258 are bent upward. The ground member 248 is bent downward. The second conductive plate Ό 246 also has four holes 260 at its four corners.

Preferably, the first power terminal 255 of the first power connector 256 carried together with the second conductive plate 246 and the second power terminal 257 of the first power connector 256 carried together with the first conductive plate 244 are in the first A power supply connector 256 is arranged adjacent to each other at a predetermined interval, but it may have any arrangement. Preferably, the first power terminal 251 of the second power connector 258 carried together with the second conductive plate 246 and the second power terminal 253 of the second power connector 258 carried together with the first conductive plate 244 are in the first The two power connectors 258 are configured to be adjacent to each other, but may have any configuration. Preferably, the power contact 250 carried together with the second conductive plate 246 and the 30 ground contact 248 carried together with the second conductive plate 246 are configured to be adjacent to each other, but they may have any configuration.

02818928.0 The central portion 264 of the first connector 112 has an integral molding device suitable for accommodating the first power connector 256 and the second power connector 258. The integral molding device of the top portion 262 of the connector 112 and the center portion 264 of the connector 112 are mechanically aligned and mated with each other to provide a connector housing for their respective terminals. The connector housing is adapted to accommodate the first power connector 256 and the second power connector 258°. The center portion 264 of the connector 112 and the top portion 262 of the connector 112 are mechanically aligned and matched with each other to provide a housing for the decoupling capacitor 42 , Or referred to as the cover shown in Figure 12A. The central portion 264 of the connector 112 also has four holes 260 at its four corners.

The W signal contact plate 268 carries the first power terminal 251 of the second power connector 258 together with the second conductive plate 246 and the second power terminal of the second power connector 258 carried together with the first conductive plate 244 253 Alignment and fixation. The integrated circuit 22 is mounted on a circuit board 64, or called a built-in board, to form the secondary integrated circuit 22 shown in FIG. 4D, which is well known in the field of integrated circuit manufacturing.

The bottom 266 of the connector 112 formed as the socket shown in FIG. 12B or the frame shown in FIG. 12C carries the signal and/or power interface 132 of the integrated circuit to the printed circuit board. The bottom 266 of the connector 112 is suitable for mechanically aligning and fixing the printed circuit board 64 and the interface 132 to the interface 132, so that the signal contact 90 (not shown) at the bottom of the printed circuit board 64 is preferably located on the interface 132. Align with corresponding signal contacts selectively located on the printed circuit board 114. The bottom 266 of the connector 112 also has four holes 260 at its four corners.

The holes 260 in the four corners of each of the top 262 of the connector 112, the first conductive plate 244, the second conductive plate 246, the central portion 264 of the connector 112, and the bottom 266 of the connector 112 are along each corner. The four common shafts are aligned with each other.

As shown in FIG. 28, the holder extends through five holes aligned with the common axis of each of the four corners to mechanically fix the connector 112 together as a component of the system 10. or

02818928.0 First, the four holes aligned with the four holes in the components of the system 10 can extend through the printed circuit board 114 so that the system 10 can be mounted on the printed circuit board 114. The holder can be of any type, which includes (but is not limited to screws, heat piles, pins, bolts, clips, etc.). The holder can be a separate component or can be integrally formed with a part of the connector 112. Preferably, it is fixed. The holder is formed as four separate screws. Alternatively, the holder is formed as a snap or clip that is integrally formed with at least a part of the connector 112 and mechanically engages a mating device on at least another part of the connector 112. In this alternative, The retainer formed as a snap or clip preferably produces a system component that can be easily assembled and disassembled for repair or reuse, but it can also produce a component of the system 10 that is permanently assembled in a sense, that is: it cannot be disassembled It can be removed without damaging the components of the system 10.

The circuit board 114 carries the connector 112 and the heat sink 200. The circuit board 114 is generally referred to as a motherboard, because it also carries many circuits connected to the integrated circuit 22 through interfaces. The circuit board 114 includes a plurality of conductive contacts (not shown) corresponding to the conductive contacts 90 on the integrated circuit 22 or on the interface 132. The printed circuit board also includes a plurality of printed circuit board traces 118 (not shown in FIG. 29), which connect conductive contacts (not shown) on the printed circuit board with the through interface and integrated circuit Various other circuits connected to 22 are electrically coupled.

:0 Note that FIG. 29 does not show the holes in the central area of the first conductive plate 244 and the second conductive plate 246 of the decoupling capacitor 42 shown in FIG. 27. Also, note that FIG. 29 does not show the heat spreader 202 shown in FIG. 27. The absence of these two components in FIG. 29 indicates the alternative solution described with reference to FIG. 27, where the decoupling capacitor 42 in FIG. 29 performs the function of the heat spreader 202 in FIG. 27, and the heat sink 200 is decoupled from The top of capacitor 42 is directly connected to 25 contacts. The optional scheme will be further described below with reference to FIG. 30 and FIG. 31.

FIG. 30 shows a cross-sectional view of the components of the system 10 shown in FIG. 28 and FIG. 29. The printed circuit board 114 carries the connector 112. As described above, the interface 132 provides a signal interface between the printed circuit board 64 and the printed circuit board 144. The printed circuit board 64 carries the integrated circuit 22. The decoupling capacitor 42 is provided on the integrated circuit 22. 42 decoupling capacitors

02818928.0 has the characteristics of a heat spreader, and it is in direct contact with the top of the integrated circuit 22 in order to diffuse the heat of the integrated circuit 22 in the entire structure of the decoupling capacitor 42. The power supply part 248 and the grounding part 250 used to form the extension leg and the flip-up foot described with reference to FIG. 27 correspond to the power contact 92 (not shown) and the ground contact 92 (not shown) on the top of the printed circuit board 64 ) Make 5 touches. The heat sink 200 is carried on the top of the connector 112. The central area of the heat sink 200 extends through the hole in the top 262 of the connector 112 so as to directly contact the top of the decoupling capacitor 42.

FIG. 31 shows a selective cross-sectional view of the components of the system 10 shown in FIG. 28. The components of the system 10 in FIG. 30 0 are the same as the components of the system 10 in FIG. 31, except that the power contacts 92 are provided on the sides (72 and 74) of the integrated circuit 22, and the power supply part 248 and the grounding part 250 are shown as directed The arms and hands curled inside, and the signal interface 132 form a dielectric material to capacitively couple the signal between the integrated circuit 22 and the printed circuit board 114.

The printed circuit board 114 carries the connector 112. The interface 132 provides a capacitive signal interface between the integrated circuit 22 and the printed circuit board 144. Note that the printed circuit board 64 does not exist in FIG. 31. In this case, the integrated circuit 22 has a set of signal contacts 90 (not shown), forming one side of the respective capacitors, and the printed circuit board 114 has another set of corresponding signal contacts (not shown), forming respective capacitors On the other side. The interface 132 provides a dielectric material with a suitable dielectric constant between the integrated circuit 22 and the corresponding signal contact on the printed circuit board 114 to achieve capacitive signal coupling between the integrated circuit 22 and the printed circuit board 114 .

The decoupling capacitor 42 is provided on the integrated circuit 22. In addition to the rear side (shown) and the front side (not shown), the power supply part 248 and the grounding part 250 for forming the arms and hands curled inward also contact the corresponding power supply contacts of the sides 72 and 74 of the integrated circuit 22. The point 92 is in contact with the ground contact 92. The heat sink 200 is carried on the top of the connector 112 and directly contacts the decoupling capacitor 42.

Figure 32 shows the connector 112 of the present invention, which is in a sense

02818928.0 has two properties, namely: it can be used as a socket with a recess for accommodating the integrated circuit inside, and it can also be used as a cover that can be mounted on the integrated circuit. This type of configuration is suitable for use with the two-level semiconductor package of the type shown in FIGS. 4C, 5, 8A, 8B, 9A, 9B, 9C, 11, 12A, and 12B. In this configuration 5, the connector includes an external device shown as a pair of edge circuit boards or circuit boards 256, 258 for connection with a power source, which can be used as respective first and second power connectors. This configuration is suitable for use in the case where power can be supplied to the integrated circuit package from the side of the integrated circuit package. The connector 112 carries a decoupling capacitor 42 which preferably takes the form of a plate capacitor including different power contacts 248 and ground contacts 250. The connector 112 has a recess or cavity forming a part of the connector 112, and a power contact 248 and a ground contact

250 is provided in a recessed portion on the periphery of the connector 112. The recess has a suitable shape and depth suitable for accommodating the integrated circuit 22, so that the power contact 248 and the ground contact 250 can be paired with the corresponding power or ground contact 92 on the integrated circuit 22 in the manner generally shown in FIG. 34. Accurate and contact.

The connector 112 can also be regarded as the cover schematically shown in FIG. 12A, which is mounted on the top of the integrated circuit 22 shown in FIG. 31. In this case, the decoupling capacitor 42 is provided on the top 68 of the integrated circuit 22, and the power supply part 248 and the contact part 250 are in contact with corresponding contacts 92 provided on each side of the integrated circuit 22. Alternatively, the connector 112 can also be regarded as the socket shown in FIG. 12B. In this case, the connector 112 is shown upright to show the device inside the socket. As a socket, the integrated circuit 22 is assembled into the connector 112 shown in FIG. 23. The decoupling capacitor 42 is provided under the bottom 70 of the integrated circuit 22, and the power contact 248 and the ground contact 250 are in contact with corresponding power contacts 92 provided on each side of the integrated circuit 22. In this case, the signal will be transmitted via the signal conductor through the top 25 68 of the integrated circuit 22, because the decoupling capacitor 42 blocks the signal from passing through the connector

112 to the bottom of the transmission. The first power connector 256 and the second power connector 258 shown as plug-in card connectors connect the voltage potential and the ground potential to the decoupling capacitor 42.

FIG. 33 shows that it is formed to be suitable for the secondary semiconductor package 62 shown in FIG. 4C, FIG. 5, FIG. 8A, FIG. 8B, FIG. 9A, FIG. 9B, FIG. 9C, FIG. 11, FIG. 12A, and FIG. 12B.

02818928.0 The optional connector 112 of the cover used together, and the connector 112 can be regarded as similar to that shown in FIG. 32, the body of the flip-chip connector has different types of power supply parts mating parts. In this embodiment, the external device used to connect to the power supply is provided in the form of two pin holders 256, 258. Each of the two pin holders 256, 258 includes the external device extending from the cover in FIG. 33 Or the upwardly extending conductive pins 255, 257°, this type of configuration can send power from the top to the package. A plurality of conductive capacitor plates are formed in the connector.

FIG. 34 shows another embodiment of the present invention, in which the power transmission system is contained in a cover member (not shown) mounted on the integrated circuit 22. In this embodiment, the power transmission system P includes at least a pair of conductive plates 244, 246, which are similar in size and aligned with each other in the vertical (Z-axis) direction. The two conductive plates are separated by intervening the dielectric layer 300. The dielectric constant and/or thickness of the dielectric layer 300 can be selected to provide a certain type of capacitor for storing sufficient power to prevent normal operation or surge current. Supply integrated circuits. A second insulating layer 302 is provided on the bottom surface of the bottom capacitor plate 246 to insulate the integrated circuit 15 from it. As mentioned above, the power transmission system includes a plurality of contacts 248, 250, the plurality of contacts 248, 250 can include or interweave power and ground (power return) contacts, these contacts preferably use the shown cantilever or The bellows form extends outward from the plates 244, 246 and all the way along the sides of the integrated circuit package, where they engage with contacts 303 formed in the integrated circuit. The two plates 264, 266 and a portion of the contacts 248, 250 are usually encapsulated or molded in an external insulating material such as 0 plastic.

These contacts 248, 250 are formed inside each of the two boards 244, 246, and they are in contact with the integrated circuit package. This embodiment is suitable for use in combination with a heat sink (not shown). Therefore, this embodiment may be provided with an opening 305 that extends through the two plates 244, 25 and 246, the intervening dielectric layer 300 and the lower insulating layer 302. A part of the heat sink may extend through the opening 305 to contact the heating surface of the integrated circuit 22. In some configurations, the thermally conductive component can be used to fit in the opening and extend between the heating surface of the integrated circuit and the heat sink.

35 is a cross-sectional view of FIG. 34, but for the sake of clarity, the lower insulating layer 302 is not shown,

02818928.0 and shows the relationship between the integrated circuit 22, its package 114 and the power transmission system. As shown in FIG. 35, the lower insulating layer 302 is abutted with the top surface 22a of the integrated circuit, and for additional cooling purposes, an additional but smaller opening 306 may be provided. For more clarity, Tuan 42 shows the end of this part. As shown, the contacts 248, 250 are arranged around the perimeter, and this configuration reduces the amount of force required for insertion and removal, where the contacts engage the integrated circuit along a horizontal line of action instead of a vertical line of action.

36 and FIG. 37 show another embodiment of the present invention, which includes a power transmission system Ό capable of supplying a plurality of different voltages to the integrated circuit at various positions of the integrated circuit body. This is achieved by including a plurality of different capacitors in the cover member, and the plurality of different capacitors are formed as respective lower conductive plates 310-313. As best shown in FIG. 37, each of these plates is separated from each other by an intervening space 315, and as shown in the figure, each of the plates includes each contact part 316, which extends outward from each plate. Extend and extend down from each board into place for contact with the contacts of the integrated circuit or integrated circuit package. Like the embodiment discussed in 15 above, the individual plates 310-313 are separated from the top, single or multiple segmented capacitor plates 244 by the intervening dielectric layer 300, so that the lower plates 310-313 of the system are in the vertical direction through the intervening dielectric layer 300. It is separated from the upper plate 244, and separated from each other in the X and Y directions by the air or intervening medium in the space 315. It is also conceivable that the lower plates 310-313 may have corresponding individual top plates associated with them, so that the connector will support four sets of capacitive plate pairs in the embodiment of FIG. 32o.

FIG. 36 shows a group of multiple plates (as well as the upper plate 244 and the intervening dielectric layer 300) embedded or encapsulated in the housing or cover 112, which is also preferably formed of a dielectric material or an electrically insulating material. In this type of structure, the material used to form the cover 112 will fill the intervening space 315 between the capacitor plates 310-313 of the lower part 25. The extended plate contact 316 may also be partially embedded in the cover 112, or may be arranged in a series of grooves 316 formed inside, so as not to excessively restrict the spring action of the contact. FIG. 38 is a cross-sectional view of the power transmission structure of FIG. 37 (and a part of FIG. 34) before being fitted into the cover 112. With this structure, different voltages such as 0.5V, 1.0V, -2.0V, etc. can be sent to different parts of the integrated circuit.

02818928.0 Figure 39 shows a staggered contact configuration that can be used with the power transmission system of the present invention. In FIG. 39, the two conductive plates 244, 246 are shown as being separated by the intervening dielectric layer 300, and the contacts 248, 250 of each plate extend downward from each plate at a nearly right angle to each plate, but the contact 248 and 250 have different contact positions in the vertical direction. As shown in the figure, the contact 248 of the lower plate 246 has a first length, and the contact 250 of the upper plate 244 has a second length. The two lengths are shown to be equal However, the contact arms of the contacts 248 and 250 are configured with different elevation angles. This staggered configuration helps to reduce the force required to insert and remove the cover 112 on the integrated circuit or its package, wherein the number of contacts engaged with the integrated circuit/package is divided into two at the first contact. This configuration can also realize the implementation of first mate and last break of the power transmission structure to reduce the possibility of short circuit and arcing in the connection.

FIG. 40 shows another embodiment of a power transmission system constructed according to the principles of the present invention, in which the power transmission system 375 includes three 15 capacitor plates 318, 319, and 321 separated by interposing dielectric material layers 300, 323. The top and bottom capacitor plates 318, 319 are interconnected together by an interconnection member 320, preferably on their sides as shown. These interconnection points are isolated and separated from the middle or inner capacitor plate 321 by spaces or gaps 322. The group of three contacts 248, 250, 325 are configured to surround the periphery of the power transmission system for contact with corresponding contacts on the integrated circuit or its package. The power transmission system adopting this form and the previous form can be regarded as a kind of module in one aspect because of its structure that can be inserted into the cover and socket parts. The figure shows an exemplary configuration of contacts 248, 250, and 325 with accompanying length, cantilever or bellows arms 360; these arms 360 are bent downward and slightly inward and terminate in the The free end 361 of the inner contact arm 362. Each contact arm preferably has an inwardly angled contact surface 363 for making contact with the side of the integrated circuit/package.

The use of the two outer capacitor plates provided on the sides of the inner capacitor plate in this embodiment has the effect of increasing the total capacitance of the decoupling capacitor due to the increased surface area of the top plate and the bottom plate. In other words, with this embodiment, the capacitance of the same horizontal surface area provided by the connector body (and the current supplied to the integrated circuit) can be increased. In this way, where the designer has a limited amount of space available for the circuit 30 board, or where the integrated circuit is small, you can

02818928.0 First use this structure. In this structure, the capacitor plate is preferably arranged vertically in the order of power-ground-power or ground-power-ground. .

Figure 41 shows the power transmission system contained in the cover 112 mounted on the integrated circuit 22. For clarity, the cover 112 is shown transparent to show how it engages the integrated circuit/package around its periphery.

FIG. 43 shows the outside of the assembled integrated circuit package containing the power transmission structure inside, in which the decoupling capacitor 42 is held on the integrated circuit by the cover member 262. The assembly has a plurality of mounting holes formed in its body portion for mounting components on the circuit board, and also has means 256, 258 for mating with external power supply leads to supply power to the decoupling capacitor 42 .

FIGS. 44 to 50 show another embodiment of the present invention, in which the integrated circuit 132 15 is held in a socket connector 112 which has a decoupling capacitor 42 contained inside. As shown in the figure, the socket connector 112 is rectangular or square in shape, and has a body portion 400 formed by a plurality of side walls 401 that cooperate to define a The central opening of the integrated circuit 132, namely the receiver 402, is accommodated. The receiver 402 may be a through hole, where an integrated circuit is located on a circuit board in contact with a contact or terminal 890 (Figure 46). Decoupling capacitor 42 includes multiple discrete capacitors

403. Each discrete capacitor 403 can send the same voltage or different voltages to appropriate contacts provided on the integrated circuit 132 (not shown). The cover plate 404 encloses and seals the integrated circuit in the socket connector 112. The capacitor 403 receives power from the power supply 405 mounted on the circuit board 406 through the trace path (Figure 45). Including these discrete capacitors in the socket connector will free up space on the circuit board 406 surrounding the integrated circuit 132.

The capacitor 403 is accommodated in an opening 410 such as a groove, or is provided in an opening in the body portion on the side wall 401 of the socket connector. The capacitor may include conventional capacitors or chip capacitors 30 to 505 using conductive leads 411 for connection purposes as shown in FIGS. 44-48. In order to accommodate these leads 411, the side wall 401 of the body part may also include

02818928.0 The channel 412 used to accommodate the leads to keep the socket connector unobtrusive and low space (Figure 48). The side wall 401 of the body portion may have a certain height to form a minute recess for accommodating a heat transfer member such as the heat sink 200. This type of connector can be fixed to the circuit board using a retainer 415 (Figure 50). The capacitor accommodating openings 410 are preferably separated from each other around the periphery of the socket as shown in FIG. 5, and may also be separated at different intervals corresponding to the positions of different power contacts or terminals on the integrated circuit.

Figures 51 to 54 show another embodiment of a power transmission system 500 constructed in accordance with the principles of the present invention. The connector 112 takes the form of a socket 501. The socket 501 has a plurality of 0 formed in its side wall 504. Discrete openings 502, each of the openings 502 accommodates a decoupling capacitor 42 in the form of a chip capacitor 505. A different terminal or lead structure can be used with the first embodiment, and the lead 506 of this structure is shown as a wire formed lead with a common U-shaped structure. The lead is terminated at one end to the ring end 507, and is opposite to each other. The end 508 is terminated with a free tail 509, and the free tail 509 can be soldered to the circuit board. The ring lead 506 passes through the side wall 504 of the socket connector 112 and can be easily molded in place during the manufacture of the socket connector. The ring end 507 is slightly bent upward so that it will be inserted into the socket connector. The bottom of the integrated circuit makes effective electrical contact. The "loopback" nature of this part of the terminal 506 can realize a redundant circuit path to the integrated circuit and also reduce the inductance of the terminal and the entire connector. The lead wire is used as a set of first or "power" terminals. The terminal set uses a .0 pattern or array for containing multiple second, preferably non-power terminals 550 arranged inside the connector socket, and uses To connect the integrated circuit with the circuit board located below. These non-power terminals 550 may include LGA, PGA, BGA, elastic Reed contacts, etc.

The inner carrier frame 510 may be provided as a part of the package, and the inner frame 510 is located in the side wall of the socket connector to form a support for the integrated circuit. In order to accommodate the ring end of the lead 506, the frame 510 may be provided with a recess 515 as shown in the figure. The recess 515 surrounds the ring end 507 and can be deflected under the insertion force of the integrated circuit when inserted into the socket connector opening. The leads 506 can be easily stamped and formed at low cost as part of the entire carrier tape 520 30, and can be formed in directions other than those shown in order to accommodate integrated electronics.

02818928.0 The location of the first road. The inner frame 510 and the side wall 504 can be formed into one body by inserting or over-molding, so that, in fact, the inner frame 510 serves as the base or bottom of the socket connector housing.

FIG. 58 shows another manner in which the discrete capacitor 403 has its terminal, or the lead 44 extends through the groove 430 formed in the side wall 401 of the connector body. In this case, the leads are connected to the terminals, and the side walls 401 surrounding the capacitor accommodating openings 410 can be added with additional materials to these openings 410, or can be configured to facilitate the thermocompression recess bonding of the capacitor 403 and its leads so as to place them in The connector body is held in place. Alternatively, the discrete capacitor 403 can be completely enclosed in the side wall 401 by using additional material to seal the opening 410 as in 440, or by molding the capacitor and leads in place in the connector body.

Finally, FIGS. 56 and 57 are bottom 15 side perspective views of the cover member used in the system shown in FIG. 30, which show the capacitor plates 244, 246 in the assembled state in the outer support members 262, 264 setting.

The present and accompanying drawings respectively illustrate and illustrate many features and characteristics of the preferred embodiments of the present invention. Any feature or characteristic described in any part of this document or shown in any figure may be the same as described in any other part of this document or shown in any other part of the same or different figures. Any combination of features or characteristics. For example, although the above description has been written in terms of power transmission system, it should be realized that the present invention can be used for signal transmission, and the sizes of various capacitor plates are designed to achieve optimal performance.

Although the preferred embodiments of the present invention are illustrated and described above, those skilled in the art should understand that changes and modifications can be made without departing from the spirit of the present invention, and the scope of the present invention is defined by the appended claims.

02818928.0