Method and apparatus for patterning a workpiece

Workpiece composition method and device

Technical field

The present invention generally relates to techniques for obtaining improved images. In particular, it relates to lithography methods using computer-controlled imaging configurations with improved virtual grids, such as spatial light modulators (SLM). The present invention also relates to a workpiece patterning device including this method.

Background technique

Lithography is used in integrated circuits, masks, reticles, flat panel displays, micro-mechanical or micro-optical devices and packaging devices, such as lead frames and MCMs. Lithographic production can include an optical system that images a master pattern from a computer-controlled reticle on the workpiece. Suitable workpieces include an electromagnetic radiation sensitive layer, such as visible or invisible light. An example of this system is described in WO 9945435, which is the same inventor and applicant as the present invention.

The computer-controlled reticle may be, for example, a spatial light modulator (SLM) including a one-dimensional or two-dimensional reflective movable micro-mirror array or matrix, a one-dimensional or two-dimensional transmissive LCD crystal array or matrix, or Other similar programmable one-dimensional or two-dimensional arrays or mechanical elements based on grating effects and interference effects, such as shutters.

Generally, the quality of the pattern can be improved by multiple writing. However, there are several different aspects of pattern quality improved by multiple writing, and not all of them are necessary at the same time. First, it is possible to generate a finer address grid in several passes than in a single pass. Secondly, the multi-pass with offset grid can remove the grid effect due to the limitation of pixel size.

Third, because multi-channels can statistically reduce random errors (such as artifacts in the optical path, interference with exposure doses, beams used for imaging or field misalignment), for example, four-channels can reduce the impact of random dose errors to the original 1/2 (square root of 4). Fourth, systematic errors (such as the drop in the dose at the corners of the pattern to be written, deformation, and curvature of the focal plane) can be reduced by the offset between the writing fields. Fifth, bad pixels can be corrected better through multiple write paths. Sixth, many multi-pass schemes give weakened edges and maintain edge sharpness is the desired performance of the multi-pass scheme.

Different rasterization multi-pass schemes can be designed, but there is a problem of finding a scheme that can improve all the above six aspects at the same time.

Figure 3a shows a known method of generating a virtual grid. A pixel array with 7 rows and 5 columns is shown in FIG. 3a. The pixels in the two leftmost columns are set to the maximum gray value. The two rightmost columns of pixels are set to the minimum gray value. The pixels in the middle column are set to the middle gray value. Fig. 3a is an example of analog modulation of characteristic edge pixels 301 in a single pass in order to generate a virtual grid. All pixels in the middle column are set to the same value.

Figure 3b shows another known method of generating a virtual grid. In this method, the four writing channels 305 are written with half the dose (for example: 100%, 50%, 25%, 12.5%). All pixels in a single pass are set to equal gray level values. The virtual grid is generated by turning on the column of characteristic edge pixels in at least one writing pass. The column of characteristic edge pixels in FIG. 3b is the writing pass at the top and the second writing pass from the bottom on.

Figure 3c shows yet another known method of generating a virtual grid. In this method, all four write paths 305 are written at the same dose. The characteristic edge pixel column 304 in at least one write pass is turned on. FIG. 3c illustrates that the bottom write pass and the second write pass from the bottom are turned on.

Figure 4a shows another known method of generating a virtual grid. In this method, four 401 write paths are written with the same dose offset, and the offset relationship of different write paths with respect to the origin 402 is Shown in Figure 4a. By turning on the edge pixels 403 only in certain passes, one edge of the feature to be written can be accurately located.

Figure 4b shows another known method of generating a virtual grid. This method utilizes an analog modulation combination of characteristic edge pixels and bias paths, which gives a different analog value 404 in each path.

Figure 5a shows a four-pixel write grid in a single pass write strategy. The mark indicated by 501 is placed in the middle of the grid.

Figure 5b shows a known method of biasing different write paths. Here, four passes are used, two of which are offset relative to the other two in two vertical directions parallel to the pixel grid by a distance defined by half the pixel size. By biasing different write paths in the multiple write strategy, imaging defects can be more or less effectively hidden.

Figure 5c shows another known method of biasing different write paths to hide the grid. In this embodiment, all the write paths are offset relative to the others. One write path is only offset in the first direction, the other write path is offset in a second direction perpendicular to the first direction, and one path is simultaneously offset in the first direction and the second direction. The offset in the first direction and the second direction is shown as half the pixel size.

Obviously, better pattern fidelity can be obtained by increasing the number of channels, but the cost also increases. Double the number of channels will double the investment and operating cost of each pattern generator for making the workpiece, and in many cases it is not economically feasible.

Generally, computer-controlled reticles can be used for imaging in various ways. These reticles, such as SLM, include many modulation elements or pixels, and in some instances, millions or more pixels.

In WO 99/45440, which has a co-inventor with the present invention, a pattern generator with improved address resolution is described. In the application, the pixels can be set to several states greater than 2, in which one type of pixel image is within the pattern feature, the other type of pixel image is outside the pattern feature, and the intermediate pixel image is at the boundary of the pattern feature. The intermediate pixel map is generated based on the position of the boundary in the grid, which is finer than the position of the pixel of the SLM projected on the workpiece.

Since the line width of the pattern to be printed on the wafer and the space between the two lines are very small, many requirements are placed on the printing method and the device using the method. Using an SLM that provides an address grid that is too coarse can limit the achievable resolution and accuracy of its application in optical imaging. For example, the production of printed patterns on a workpiece may be limited by its line width and accuracy.

Therefore, there is a need in the art for a method that further fine-tunes the positions of the edges of the image elements generated on the workpiece. Similarly, there is a need to improve the effect of multi-path averaging in this field, that is, reducing the number of paths to improve the fine adjustment of feature edges.

Summary of the invention

From the perspective of the above background, the fine adjustment of the edge positions of the elements in the image generated on the workpiece is the key to achieving the line width in the sub-micron range when using single-pass or multi-pass writing.

The invention is suitable for patterning workpieces based on digital input data files, such as masks, semiconductor wafers, optoelectronic devices, micro-optical devices, magnetic devices, superconducting devices, display devices, and writing of electrical connection structures such as MCMS. The invention has nothing to do with the writing mechanism, and is suitable for laser beams and other electromagnetic radiation beams, electrons or other charged particle beams. The beam can be broadly understood as including, for example, the printing method of the projection area projected by the SLM and the photoelectric tube. Non-traditional writing mechanisms are also included, such as atomic beams, multi-photon processing, entangled photons, near-field effects, direct current exposure from the scanning head, and thermal exposure.

Therefore, an object of the present invention is to provide an improved method for fine-tuning the edges of elements.

In the first embodiment, the present invention provides a method of patterning on a workpiece sensitive to electromagnetic radiation. Electromagnetic radiation is emitted onto a computer-controlled reticle with multiple modulation elements (pixels). Pixels are arranged on the reticle controlled by the computer according to the digital description. A computer-controlled reticle image is generated on the workpiece, wherein the pixels in the computer-controlled reticle are arranged in an alternating state along a part of at least one feature edge to produce a smaller Address grid.

In another embodiment of the present invention, the pixels along at least one feature edge in the computer-controlled reticle belong to a one-dimensional line of pixels.

In yet another embodiment of the present invention, the image is generated in a write pass.

In still another embodiment of the present invention, the image is generated through multiple writing paths.

In still another embodiment of the present invention, the pixels along at least one feature edge in the computer-controlled reticle are arranged differently from the plurality of writing paths.

In another embodiment of the present invention, in the first writing pass, at least one first pixel along the edge of at least one feature is set to a first gray value and is surrounded by pixels set to at least one other gray value. And in at least one other writing pass, at least one second pixel along the edge of the at least one feature is set to the first gray value and is surrounded by a pixel set to at least one other gray value.

In yet another embodiment of the present invention, four write passes produce patterns.

In still another embodiment of the present invention, the pixels set to the first gray value in different writing paths do not overlap.

In another embodiment of the present invention, the surrounding pixels are set to the same gray value.

In still another embodiment of the present invention, the surrounding pixels are set to different gray values.

In still another embodiment of the present invention, the pixels along at least one characteristic edge in the computer-controlled reticle belong to a pixel line with a width of two pixels.

In another embodiment of the present invention, the pixels along at least one feature edge in the computer-controlled reticle belong to a pixel line having a width of three pixels.

In another embodiment of the present invention, the pixels are micromirrors in the SLM.

In yet another embodiment of the present invention, the pixels are transmissive.

Another aspect of the present invention is to provide an improved device for fine-tuning the edges of elements.

In the first embodiment, the present invention provides a device for patterning on a workpiece sensitive to electromagnetic radiation. The device includes a radiation source that emits electromagnetic radiation onto a computer-controlled reticle with multiple modulation elements (pixels), and a projection system that produces an image of the computer-controlled reticle on the workpiece , Wherein the pixels in the computer-controlled reticle are arranged in an alternating state along at least a partial boundary of at least one element to be patterned, so as to fine-tune the elements in the pattern to be formed on the workpiece The position of the edge.

In the first embodiment of the present invention, the pixels along at least one characteristic edge in the computer-controlled reticle belong to a one-dimensional line of pixels.

In another embodiment of the invention, the image is generated in a write pass.

In yet another embodiment of the present invention, the image is generated through multiple writing passes.

In still another embodiment of the present invention, the pixels along at least one feature edge in the computer-controlled reticle are arranged differently in the plurality of writing paths.

In still another embodiment of the present invention, in the first writing pass, at least one first pixel along the edge portion of at least one feature is set to a first gray value and is set to at least one second gray value. Pixels are surrounded, and at least one second pixel along the portion of the characteristic edge in at least one second writing pass is set to the first gray value and is surrounded by at least the second gray value Value in pixels.

In another embodiment of the present invention, the pattern is generated through four write passes.

In another embodiment of the present invention, the pixels set to the first gray scale value in different writing paths do not overlap.

In still another embodiment of the present invention, the pixels set to the first gray value in different writing paths are separated by an interval of at least one pixel.

In still another embodiment of the present invention, the surrounding pixels are set to the same gray value.

In another embodiment of the present invention, the surrounding pixels are set to different gray values.

In another embodiment of the present invention, a part of the pixels along the edge of at least one feature in the computer-controlled reticle belong to a pixel line having a width of two pixels.

In still another embodiment of the present invention, the pixels along at least one characteristic edge in the computer-controlled reticle belong to a pixel line having a width of three pixels.

In still another embodiment of the present invention, the pixels are micromirrors in the SLM.

In another embodiment of the present invention, the computer-controlled reticle is a transmissive SLM.

Another aspect of the present invention is to provide an improved wafer patterned by a finer address grid.

In a first embodiment, the present invention provides a semiconductor wafer including at least one integrated circuit, wherein the at least one integrated circuit is a computer having a plurality of modulation elements (pixels) by emitting electromagnetic radiation into at least one write path. Patterned on a controlled reticle, the pixels in the computer-controlled reticle are set according to a digital description, and an image of the computer-controlled reticle is generated on the wafer, wherein The pixels in the computer-controlled reticle are arranged in an alternating state along a portion of at least one feature edge to generate a smaller address grid.

Another aspect of the present invention is to provide an improved mask, which is patterned by a finer address grid.

The first embodiment of the present invention provides a mask including a pattern to be printed on a workpiece, wherein the substrate of the mask is emitted by electromagnetic radiation onto a computer-controlled reticle with multiple modulation elements (pixels) Is patterned in at least one writing path, the pixels in the computer-controlled reticle are set according to a digital description, and an image of the computer-controlled reticle is generated on the mask substrate, The pixels in the computer-controlled reticle are arranged in an alternating state along a part of at least one feature edge to generate a smaller address grid.

Another aspect of the present invention is to provide an improved method for fine-tuning the edges of the elements to be imaged.

In the first embodiment of the present invention, a method for imaging a pattern on a surface according to a data file description is provided, wherein a plurality of writing paths are provided, and the grids of pixels in at least two paths are offset. The value of the edge pixels in the pass is controlled, and the value of the edge pixels between at least two passes is adjusted by a predetermined rasterization rule to optimize the quality of the edge.

In another embodiment of the present invention, the edge quality is defined as edge roughness.

In yet another embodiment of the present invention, the edge quality is defined as edge sharpness.

In another embodiment of the present invention, the edge quality is defined as critical dimension control (CDC).

In still another embodiment of the present invention, the at least two adjacent edge pixels in at least one pass have unequal values.

In another embodiment of the present invention, the rasterization is non-linear.

In another embodiment of the present invention, each pixel divided into at least two regions performs nonlinear rasterization, wherein the first region has a first weight function and the second region has a second weight function.

Another aspect of the present invention is to provide a method for generating a virtual grid.

In the first embodiment of the present invention, there is provided a method for writing a pattern on a substrate and generating a virtual grid according to a description in a data file, wherein the sequence of characteristic edge pixels is generated in the first writing pass, and The sequence of feature edge pixels is replaced in at least one second writing pass, and the sequence is at least partially superimposed on the substrate.

In another embodiment of the invention, it further includes an action of offsetting a pixel grid in at least two paths.

In yet another embodiment of the invention, it further comprises an action of periodically repeating the sequence of characteristic edge pixels along at least one characteristic edge.

In still another embodiment of the present invention, the sequence of characteristic edge pixels is aperiodic.

Another aspect of the present invention is to provide another method of generating a virtual grid.

In the first embodiment of the present invention, a method for writing a pattern on a substrate and generating a virtual grid according to the description in the data file is provided, wherein the first sequence of characteristic edge pixels is generated in the first writing path, and the characteristic A second sequence of edge pixels is generated in at least one second write pass, and the sequence is at least partially stacked on the substrate.

In another embodiment of the present invention, the first and second sequences are periodic.

In still another embodiment of the present invention, the first and second sequences are aperiodic.

In yet another embodiment of the present invention, the pixels are on/off pixels.

In still another embodiment of the present invention, the pixel is a multi-value pixel.

In another embodiment of the present invention, it further includes an action of offsetting a pixel grid in at least two paths.

In another embodiment of the present invention, the at least one of the characteristic edge pixels is divided into at least two regions with different weight functions for completing nonlinear rasterization.

Description of the drawings

In order to have a more complete understanding of the present invention and its advantages, the present invention will be described below with reference to the accompanying drawings, in which: FIG. 1a shows a first method of rasterizing features using a single write path.

Figure 1b shows a second method of rasterizing features using a single write pass.

Figure 1c shows a third method of rasterizing features using four write passes.

Figure 2a shows a feature that has been rasterized.

Figure 2b shows the exposure dose as a function of a single pixel.

Figure 2c shows the smoothing of the edges.

Figure 3a shows a first embodiment of generating a virtual grid according to the prior art.

Fig. 3b shows a second embodiment of generating a virtual grid according to the prior art.

Fig. 3c shows a third embodiment of generating a virtual grid according to the prior art.

Fig. 4a shows a fourth embodiment of generating a virtual grid according to the prior art.

Fig. 4b shows a fifth embodiment of generating a virtual grid according to the prior art.

Figure 5a shows a first embodiment of generating a path offset according to the prior art.

Figure 5b shows a second embodiment of generating a path offset according to the prior art.

Fig. 5c shows a third embodiment of generating a path offset according to the prior art.

Figure 6a shows a first embodiment of biasing different write paths according to the present invention.

Fig. 6b shows the result of printing a star with the offset according to Fig. 6a.

Figure 6c shows a second embodiment of generating a path offset according to the present invention.

Fig. 6d shows the result of printing a star with the offset according to Fig. 6c.

Figure 7 shows the reference points for using four write paths according to the present invention.

Fig. 8 shows a first embodiment of the four-pass writing rule according to the present invention.

Fig. 9 shows a second embodiment of the four-pass writing rule according to the present invention.

Fig. 10 shows a third embodiment of the four-pass writing rule according to the present invention.

Figure 11a shows a fourth embodiment of the four-pass writing rule according to the present invention.

Fig. 11b shows a fifth embodiment of the four-pass writing rule according to the present invention.

Figures 12a-e show the results of a single-pass feature edge pixel sequence.

FIG. 13 depicts a diagram illustrating the relationship between the virtual grid and the line edge roughness.

Figure 14 shows four write passes with a long characteristic edge pixel period according to the present invention.

FIG. 15 depicts a graph illustrating the simulated edge roughness and the combined roughness of each channel.

Figure 16 depicts the same graph as Figure 13, but the edge roughness is after four passes with shifted edge pixel sequences.

Figure 17 depicts an algorithm for calculating edge pixel values using on-off pixels.

FIG. 18 depicts the same diagram as FIG. 1 but with 65-value pixels.

Figure 19 depicts the combination of two improved virtual grid methods.

Figure 20a shows an example of a multi-pass scheme.

Figure 20b shows another embodiment of a multi-pass scheme.

Figures 21a and 21b show the difference between the two paths when the edge of the input feature moves by one address unit.

Figure 22 shows an example of a multi-pass scheme.

Figures 23a and 23b show graphs illustrating edge roughness.

Figures 24a and 24b show the process of calculating the optimal or near optimal sequence of feature edge pixels.

Figure 25a shows a non-linear rasterization function.

Figure 25b shows the same graph as Figure 20 but with a non-linear rasterization function.

Figure 26a-c shows the completion of non-linear rasterization.

Figs. 27a-c show the weight functions of nonlinear rasterization using the displacement scheme shown in Fig. 7.

Figure 28a-b shows another embodiment of the weight function.

Fig. 29 shows an embodiment of the inventive characteristic edge pattern in a spatial light modulator (SLM).

Figure 30 shows another embodiment of the inventive characteristic edge pattern in a spatial light modulator (SLM).

Figure 31 shows yet another embodiment of the inventive characteristic edge pattern in a spatial light modulator (SLM).

Fig. 32 shows still another embodiment of the inventive characteristic edge pattern in a spatial light modulator (SLM).

Figure 33a shows the first write pass of another embodiment of the inventive feature edge pattern in a spatial light modulator (SLM).

Figure 33b shows a second write pass.

Figure 33c shows a third write pass.

Figure 33d shows a fourth write pass.

Figure 33e shows a table representing the paths shown in Figures 5a to 5d.

Figure 34 shows the pattern generator.

detailed description

Figure 1a shows a feature 102 that has been rasterized. The grid 101 including the pixels 103 is aligned with the origin 104 of the coordinate system. It can be seen from Figure 1a that the mesh is a bit rough. Therefore, the feature 102 cannot be imaged with the required accuracy.

Figure 1b shows the same features as shown in Figure 1a, but here the features are rasterized into a finer grid. The accuracy of rasterization is better to be twice, but there are 4 times more pixels to be written here, which makes this method consume more time than the method shown in Figure 1a.

Fig. 1c shows the same feature shown in Fig. 1a, which has been rasterized to the same grid size but using four channels 105 without offset. If different pathways are imaged at the same dose, different lithographic characteristics such as resist characteristics and time delay may make this imaging method more accurate than the method shown in Figure 1a.

Figure 2a shows the rasterized vertical lines. Fig. 2b shows the ideal exposure 202 of the rasterized line in Fig. 2a. Smoothing by the limited resolution of the exposure beam gives the exposure dose represented by 203 in Figure 2b. Figure 2b shows the smoothing process due to exposure, but chemical diffusion, developer transport, and the limited resolution of the resist or recording medium also bring similar effects. Figure 2c shows a rasterized feature including steps. This imaging feature will eventually result in the pattern shown by the dashed line. The smoothing in step 205 is produced by the limited resolution of the exposure beam according to the method described in FIG. 2b. Pixel 206 will therefore be affected by neighboring pixels.

Figure 6a shows the inventive method of biasing different write paths. In this embodiment, the four write passes are offset relative to each other by a quarter of the pixel size in two vertical directions. What is shown here is the path to be offset in the diagonal direction of the pixel. Usually for N channels, where N is an integer greater than 2, the channels are distributed along the diagonal of the pixel with (pixel size)/N, that is, for three writing channels, the first channel is written at the origin of the coordinates, and the second channel is written at the origin of the coordinates. The path is written at 1/3 of the diagonal of the pixel from the origin of coordinates, and the third path is written at 2/3 of the diagonal of the pixel from the origin of coordinates.

Fig. 6b shows a star written by the bias method shown in Fig. 6a. It can be seen from Figure 6b that there is an unwanted asymmetry on the diagonal. This is because smoothing only occurs in the direction parallel to the pixel side, and deviation from this direction will result in a rough grid effect.

Figure 6c shows another inventive method of biasing different write paths. In this embodiment, the four write paths are distributed in the same number as shown in FIG. 6a but not along a straight line. Here the first path is written at the origin of the coordinate system. The second path is at 1/4 of the pixel size in the X direction and 1/2 of the pixel size in the negative Y direction, where the X and Y directions are parallel to the sides of the rectangular pixel. The third pass is written at 1/2 of the pixel size in the X direction and at 1/4 of the pixel size in the Y direction. The fourth pass is written at 3/4 of the pixel size in the X direction and at 1/4 of the pixel size in the negative Y direction. Through such an offset method, symmetry in two directions parallel to the side of the pixel and two diagonal directions of the pixel can be obtained.

Fig. 6d shows the same star as written according to the method of Fig. 6c. Compared with the star shown in Figure 6b, the symmetry is improved here. Symmetry is achieved in all eight directions by biasing the write path according to the scheme shown in Figure 6c.

FIG. 7 shows the reference points of several pixels in the four paths 701, 702, 703, and 704. The displacement between the channels can be slightly changed by a small part of the pixel size unit, and a more uniform distribution of reference points can be obtained at the cost of uneven division along the horizontal axis and the vertical axis. The details of the rasterization algorithm and the error structure of the pattern generator determine which one is more advantageous. The mirror image of the pattern in Figure 7 and its 90° rotation are also good. The offset method according to Fig. 7 is particularly good for hiding the grid pattern. Of course other numbers of vias can be used, in which case the patterns will look different. The offset between the paths should be selected so that the x and y directions and the two diagonal directions are as symmetric as possible.

Figure 8 shows four write passes with analog or multi-value pixels according to the present invention. A middle column represents a characteristic edge pixel column. It can be seen that the pixels of the column are set to different states. The pixel patterns of the characteristic edge columns of the four channels can be equal or unequal. The fine address grid is completed by the jitter between different gray values.

Figure 9 shows four passes with edge pixels in more than one column according to the present invention. This pixel is multi-valued. Here, multiple edge columns in one write pass can be equal or at least different in one other write pass. The pixels in different edge columns may have different weights, which may be set to be different from each other according to the example of the pattern to be imaged.

Figure 10 shows a multi-pass scheme according to the present invention. Here, for some channels, generally those with high doses, channels with different doses are used to generate a doubled finer address grid to improve the average effect. The passages with the same dose indicated by the same cross-hatched lines in FIG. 10 can shift their exposure fields and/or their pixel grids to improve image uniformity. Because the average effect will be greatly affected by these paths, the write path with a high dose is repeated. Paths with low doses can be mainly used to fine-tune the address grid. A path with a high dose is used for the most significant bits in the address and a path with a low dose is used for the least significant bits in the address.

Figures 11a and 11b show a multi-pass scheme with edge pixels according to the present invention to generate a finer grid and the sequence or distribution of edge pixels in different passes are different. In Figure 11a, different passes are written with substantially the same exposure. For example, in Figure 11b two passes are written at 25% exposure and the other two passes are written at 100% exposure. The sequence period of each pass is 4, giving a combined grid with a pixel size of 1/16. An example of an edge pixel sequence is shown on the right side of the stacking pass in Fig. 11b. The two leftmost patterns can be written with 100% exposure and the two rightmost patterns can be written with 25% exposure.

Figures 12a-e show different edge pixel sequences. The sequence of edge pixels can be periodic or non-periodic. The figure shows a sequence of cycles with different cycles and a final image edge. Figure 12a shows a pixel sequence with a period of 1, that is, all pixels have the same value. Obviously this will produce smooth edges.

Figure 12b depicts a pixel sequence with a period of 2, giving a virtual address grid twice as thin as Figure 12a. The edges are still smooth due to the smoothing effect of the exposure tools and processing. The pixels are simulated as having 16 states, and for example, every second pixel of a characteristic edge can be set to 5/16 and the others to 6/16.

Figure 12c shows a pixel sequence with a period of 3, giving an address grid three times finer, but starting to show line edge roughness (LER). The actual edge roughness will depend on the trade-off between pixel sizes, and the figure shows a typical example.

Figures 12d and 12e show pixel sequences with periods of 4 and 10, respectively. In these two figures, it can be clearly seen that the edge roughness increases as the period of the pixel sequence increases.

FIG. 13 depicts a diagram showing the relationship between the virtual grid and the line edge roughness using the scheme shown in FIG. 12. Both the virtual grid and the edge roughness are related to the pixel size.

Figure 14 shows four passes 1401 with a long edge pixel period. Each path taken out separately will produce a large line edge roughness 1402. By shifting the pattern by a certain number of pixels between the vias and stacking the vias, the line edge roughness 1403 can be significantly reduced.

Figure 15 shows two graphs showing the simulated edge roughness and combined roughness of each channel. The two figures show two different sequences corresponding to different feature edge arrangements. The figure shows that some arrangements are better and others are worse, but the roughness can be greatly reduced for each arrangement. The left image in FIG. 15 shows the displacement of regular pixel edge patterns and the right image shows the stacking of irregular pixel edge patterns.

Figure 16 shows the same graph as Figure 13, but here is the edge roughness after four passes with shifted edge pixel sequences. The graph is simulated based on typical input parameters and can display four-channel sequence lengths up to 16 lengths. A large sequence length may cause a roughness larger than the grid.

Figure 17 shows an algorithm for calculating edge pixel values with binary (on/off) pixels and a sequence period of 5. The feature edge is located at 0.409 units on the pixels in the middle column. The predetermined sequence is 0, 2, 4, 1, 3. The criterion for setting pixels in the feature edge column to an on state is P+(Si/L)>1, where P is the position of the feature edge, si is a single number in the sequence, and L is the length of the sequence.

The basics shown in Fig. 18 are the same as those shown in Fig. 17, but 65-value pixels are used here. In this case, 0.409=16/64+0.009=(16+0.576)/64. Because of the use of multi-value pixels, what we want to know is when to change from 16/64 to 17/64. Therefore P=0.576.

Figure 19 shows a combination of two methods for obtaining a finer address grid. An example is the use of simulated edge pixels in more than one row, as shown in Figure 9, Figure 32, and Figure 33. The effects of pixels in different columns may be different and the columns can be combined in a linear or non-linear way. The use of these two methods can be used in the present invention with a calibration lookup table. In the example of the analog value in the column, the entered data gives a lookup value for each method. The lookup table typically has more output bits than address bits, so a 6-bit address may produce two 8-bit values. This 8-bit value is generated when the edge positions of different numerical combinations are measured and mapped to the input value during calibration. In a simpler example of a single method, the same lookup table structure can be used, but there is only one output for each input.

Figures 20a and 20b show a multi-pass scheme with different edge sequences in different passages and the passages are shifted relative to each other. Figure 20a shows a different sequence of feature edge pixels. Figure 20b shows how the vias are stacked. Because of the displacement between the channels, the dashed lines representing the edge of the feature will be displayed at different positions in the different channels. For each of the last edge positions, there is at least one combination of characteristic edge patterns, all of which are likely to be different, which will result in a substantially smooth edge. The pixels of FIGS. 20a and 20b are on/off pixels.

Figures 21a and 21b show that the path may have been completely reconfigured when the input edge moves by only one address unit. Figure 21a shows two passages at one edge position. Figure 21b shows two identical paths when the input edge has moved one virtual grid unit to the left compared to Figure 21a. A pixel value changes from on (on) to off (off) (in the feature edge column, six pixels in Figure 21a are in the on state and 5 pixels in Figure 21b are in the on state) and then the pixels have been Reconfigure to the best LER and edge sharpness.

Figure 22 shows a sequence with long and unequal cycles giving a virtual grid of pixel size 1/28. The sequence length is 7. For each virtual grid step, one pixel changes from off (off) to on (on). The same sequence can be used again after 7 steps, but the order between the paths is changed or rotated. The sequence does not need to be periodic, it can be found that the aperiodic sequence has basically the same characteristics. Similarly, more or fewer paths and different displacements between paths can be used or no displacement at all.

Figures 23a and 23b show two graphs showing the edge roughness in each pass and four combined passes. Figure 23a shows a bitmap of a feature edge arrangement, and Figure 23b is a bitmap of another feature edge arrangement. There is no low frequency component in Figure 23a.

Figures 24a and 24b show two methods of calculating the best or near best edge pixel sequences for different edge positions. The calculated sequence is performed offline and is used for tabulation in the rasterization process. Figure 24a shows a binary sequence representing edge pixels in different passes. The pixels used are dual-valued pixels. The four-passage uses the invented displacement scheme as described above. The sequence of edge pixels is shown aperiodic. This diagram in Figure 24a is just one of many alternative ways to implement the present invention. Figure 24a shows that one column of pixels in each pass is controlled by a sequence, that is, there are four columns that are controlled in a four pass scheme. Of course, the four-pass scheme can be controlled by other numbers of columns.

Figure 24b shows an algorithm that generates a sequence with good characteristics for each edge position given by the input address grid. The error diffusion algorithm can be used to generate the initial binary sequence. Error diffusion algorithms can be found in textbooks that involve computer graphics. The error diffusion algorithm gives an approximately uniform distribution of 0 and 1. The sequence can be further improved by iterative replacement of short sequences. The displacement protects the average edge position while on the other hand affects the edge roughness evaluated in the imaging mode. A simple imaging mode can first be used to quickly generate candidate sequences. Then, the candidate sequence can be further analyzed/evaluated in a more comprehensive mode, for example through a commercially available lithography simulation program. Once a sequence that reaches an acceptable level is found, the sequence is accepted and the algorithm proceeds to the next edge position.

Figures 25a and 25b show a non-linear rasterization function. Pixels or average columns as a function of the superposition between features and pixel regions in the input data. Fig. 25a shows a graph representing a linear function, a piecewise linear non-linear function, and a smooth non-linear function. All three functions are idealized because in practice they are truncated as step functions. The diagram of Figure 25b is the same as Figure 20, but here the non-linear rasterization function gives better edge sharpness because only two of the passes have edge pixels. Each position of the feature edge can be optimized individually. The virtual grid in Figure 25b is 1/16 of the pixel size. By looking at the pixels of the characteristic edge and using four writing passes, 100% exposure can be used in one pass of the characteristic edge pixels and 0% exposure can be used in the other writing pass of the characteristic edge pixels. For the remaining two paths, a steeper can be used to rasterize the function.

Figures 26a-c show how nonlinear rasterization is done in a supersampled rasterizer. In each pixel, a feature is rasterized on a fine grid, that is, a super-sampling ultra-fine grid. The pixel value is the number of ultra-fine grid points set by the rasterizer. The same weight is applied to each ultrafine grid point, and the rasterization is linear. If a larger weight function is applied to the ultrafine grid point close to the center, a nonlinear rasterization function will result. The weight function of the central square area with higher weight is shown in Fig. 26b. Figure 26c illustrates a continuous weight function with a higher weight at the center than near the edges. Through this supersampling, the rasterization function of the stepper can be completed.

Fig. 27a shows the weight function of nonlinear rasterization using the displacement scheme shown in Fig. 7. FIG. 27a shows the pixel area in the channel 2701, and the channel 2701 overlaps and fills the area four times after the four channels. The rectangular area 2702 with a higher weight function is smaller and fills the area without being superimposed after four passes. The rectangle must be rotated 90 degrees in the two passages of the passage 2703. Supersampling on either of these two area sizes gives the correct pixels representing the input pattern, that is, it is impossible to set small features anywhere so that the area is not accurately reflected by the pixel value. There are other area shapes that have the same characteristics for different superposition factors such as 2 or 8. Because each of the two region shapes gives the correct rasterization, each linear combination of them is also correct.

Figure 27b shows pixels with a super-sampling grid. One weight function is applied to the center rectangle and the other is applied to the remaining pixels.

Figure 27c shows the weight function of Figure 27b in three dimensions. The height and top of the central area can be arbitrarily selected according to the required non-linearity.

Figures 28a and 28b show weight functions similar to those of Figures 27b and 27c, for two passes deflection by half a pixel size in the x direction and half a pixel size in the y direction. The non-linear characteristics can be changed by changing the weight between the rectangular area and the outside of the rectangle, that is, the slope of the non-linear function will be changed.

FIG. 29 shows an exemplary embodiment of the apparatus 1 for patterning on the workpiece 60. The device 1 includes a radiation source 10 for emitting electromagnetic radiation, a first lens assembly 50, a computer-controlled reticle 30, a beam adjuster assembly 20, a spatial filter 70 located in the Fourier plane, and a second lens assembly 40.

The radiation source 10 can emit radiation in the wavelength range from infrared (IR) to extreme ultraviolet (EUV). Infrared (IR) light is limited to 780nm to about 20nm; extreme ultraviolet light (EUV) is limited to 100nm in this application. Down to the range of radiation that can be treated as electromagnetic radiation, that is, using optical elements for reflection and focusing. The radiation emitted by the radiation source 10 is pulsed or continuous. The radiation emitted from the continuous radiation source 10 can form pulsed radiation through a shutter located on the radiation path between the radiation source 10 and the computer-controlled reticle 30. As an example, the radiation source 10, that is, the source of the exposure beam may be a KrF excimer laser with a pulse output of 248 nm, a pulse length of about 10 ns, and a repetition frequency of 1000 Hz. The repetition frequency can be above or below 1000 Hz.

The beam adjuster unit can be a simple lens or a combination of lenses or other optical components. The beam adjuster unit 20 uniformly distributes the radiation emitted from the radiation source 10 on at least a part of the surface of the computer-controlled reticle 30. In the case of a continuous radiation source, the beam of such a source can be scanned on the surface of a computer-controlled reticle.

Between the radiation source 10 and a computer-controlled reticle 30, which may be, for example, a spatial light modulator (SLM), the beam modifier assembly is provided, and the assembly 20 expands and reshapes the light beam so as to irradiate the surface of the SLM uniformly on. In a preferred embodiment using an excimer laser as the source, the beam shape is rectangular, the beam diverges differently in the x-direction and the y-direction, and the radiation intensity in the beam section is often uneven. The beam can have the shape and size of the SLM 30 and be homogenized to transform the rather unpredictable beam profile into a flat illumination with a uniformity of, for example, 1-2%. This can be done in steps: a first beam shaping step, a homogenization step, and a second beam shaping step. The beam is also angularly filtered and shaped, so that the radiation irradiated to each point on the SLM has a controllable angular sub tense.

The optical device of the present invention is similar to the wafer stepper. In the stepper, the light beam is homogenized in a rectangular or prismatic rod with a reflective inner wall that is a light pipe, in which mirror images of many light sources are formed, so that the illumination is a stack of many individual light sources. The homogenization operation can also be performed by splitting or recombining these light beams by refracting, reflecting or diffractive light elements.

Provide SLM 30 with a digital description of the pattern to be printed. The pattern can first be made with a general-purpose commercially available drawing program. Before the pattern file is supplied to the SLM, the pattern file is divided and converted into a format that can be recognized by the SLM.

FIG. 30 shows a spatial light modulator (SLM) 200, which includes a two-dimensional pixel array. In this embodiment, there are 8 rows 3001 and 8 columns 3002, that is, a total of 64 pixels. In practice, an SLM can include several million pixels, but for clarity, an SLM with a few pixels is chosen.

The micromirror pixels may be, for example, 20×20 μm. A projection lens with a reduction rate of 200× makes one pixel on the SLM correspond to 0.1 μm of the image on the workpiece. Each pixel can be controlled at 64 levels, so the 100nm pixel is interpolated into 64, and each interpolation increment is 1.56nm.

The two leftmost columns of pixels 3010, 3011 and the rightmost two columns of pixels 3016, 3017 are set to a dark state, that is, these pixels are in a state where no radiation is generated on the workpiece, which is indicated as " 0". The middle two columns 3013 and 3014 are set to a state called white, that is, these pixels are in a state that will generate maximum radiation on the workpiece, which is represented as "100" in FIG. 30. The pixels in the columns 3010, 3011, 3016, and 3017 are outer characteristic pixels, and the pixels in the columns 3013 and 3014 are inner characteristic pixels. The pixel boundary feature pixels in columns 3012 and 3015. The boundary feature pixels are set in an alternating state along the boundary line of the feature as shown in FIG. 30, which are indicated as 74 and 75 in this example. In this embodiment, each second boundary feature pixel is set to 74 and the rest is set to 75. It can be seen from the same figure that the state of the boundary feature pixels in column 3012 and the boundary feature pixels in column 3015 do not match, that is, the boundary feature pixels indicated by 75 do not belong to the same row. In another embodiment, the boundary feature pixels match each other, that is, the boundary feature pixels represented by the same gray value are located in the same row.

In order to replace each of the second boundary feature pixels to one gray value and the rest to another gray value, each second pair of boundary feature pixels is set to an alternating state. For each pixel whose pixel size is 100nm on the workpiece is controlled to 64 levels, and by setting the boundary feature pixels in the SLM to alternate states, an address grid of 0.78nm can be obtained in one writing step. In FIG. 30, the boundary feature pixels are represented by a single column 3012, 3015.

Setting each boundary feature pixel to a first gray value and setting the remaining pixels to a similar gray value can produce a smoother feature edge. Compared with whether to select a long sequence of alternating states in a single write pass, the similar gray value can be higher or lower.

In an alternative embodiment, as shown in FIG. 31, the boundary feature pixels are represented by two columns. In FIG. 31, the leftmost and rightmost columns 3110, 3117 are respectively set to a dark state, and the pixels in these two columns represent outer feature pixels. The inner feature pixels are shown as two columns 3113 and 3114 in the figure. The boundary feature pixels are represented as 3111, 3112, 3115, and 3116 columns.

In this embodiment, each second pixel of the leftmost boundary characteristic pixel column 3111 and the rightmost boundary characteristic pixel column 3116 is set to "1" gray level and the rest is set to "0" gray level . Here, the pixel of the leftmost boundary feature pixel column 3111 is set to "0" to match the higher value of the remaining boundary feature pixel columns 3112, which is 75 here, and one of the feature edges is jointly generated on the workpiece. The same applies to the two columns 3115 and 3116, which together produce another feature edge on the workpiece, that is, the "0" of the rightmost column 3116 matches the higher value of the pixel in the other boundary feature pixel column 3115, here it is 75; and the most The "1 in the right column 3116 matches the lower value of the pixel in the other boundary feature pixel column 3115, which is 74 here.

In addition, it can be reversed, that is, a feature pixel column with two boundary features produces a feature edge on the workpiece, and the higher alternating state (gray value) in one of these columns may be the other higher alternating of these columns. The state (gray value) matches.

Instead of extending the boundary characteristic pixel column to the outer characteristic pixel column, the column may extend into the inner characteristic pixel column as shown in FIG. 32. In FIG. 32, columns 3210, 3211, 3216, and 3217 represent outer characteristic pixel columns. Columns 3212, 3213, 3214, and 3215 represent boundary feature pixel columns. Here, because the line to be written is only represented as 4 columns and the two columns represent the two edges of the line, there is no inner feature pixel column. It can be seen from FIG. 32 that all the higher alternating values match each other, that is, "100" in columns 3213 and 3214 matches "75" in columns 3212 and 3215. In addition, the higher values in the outermost boundary characteristic pixel columns 3212 and 3215 may be matched with the lower values of the innermost boundary characteristic pixel columns 3213 and 3214.

Figure 33 shows another embodiment of an inventive feature edge pattern in a spatial light modulator (SLM). Here, the three columns represent boundary feature pixels. The leftmost and rightmost columns 3310 and 3317 are respectively set to a dark state and the pixels in these two columns represent outer feature pixels. The boundary feature pixels are represented in the columns 3311, 3312, 3313, 3314, 3315, and 3316. In FIG. 33, the inner characteristic pixels are not shown.

In this embodiment, each second pixel in the leftmost boundary characteristic pixel column 3311 and the rightmost boundary characteristic pixel column 3316 is set to a gray level of "1" and the rest are set to gray level "0". Degree level. Here, the pixels in the leftmost boundary feature pixel column 3311 are set to "0" and they match the higher gray values of the pixels in the boundary feature pixel columns 3312, 3313, 3314, and 3315. The grayscale value of 0 matches the grayscale value 75 in columns 3312 and 3315 in this embodiment, and the remaining pixels in columns 3312 and 3315 are set to 74. The grayscale value of 0 matches the grayscale value 75 in columns 3313 and 3315 in this embodiment. The gray value of 100 in 3314 matches, where the remaining pixels in columns 3313 and 3314 are set to a gray value of 99. The columns 3311, 3312, 3313, 3314, 3315, 3316, and 3317 collectively produce linear characteristic edges.

Figure 34a shows the first of the four write passes used to generate straight lines with a fine address grid. The pixels in columns 3410, 3411, 3416, and 3417 are set to a grayscale value of 0. The pixels in columns 3413 and 3414 are set to a grayscale value of 100. According to the previous language used in the foregoing embodiment, the columns 3410, 3411, 3416, and 3417 are outer feature pixel columns, while using the same language, the columns 3413 and 3414 are inner feature pixel columns. Columns 3412 and 3415 are boundary feature pixel columns. In the first writing pass, all pixels in the boundary feature pixel column are set to the first gray value except at least one pixel is set to the second gray value. In this embodiment, as shown in FIG. 34a, seven of the eight pixels in the corresponding column are set to a gray value of 75. One pixel in column 3412 is set to a grayscale value of 74 and one pixel in column 3415 is set to a grayscale value of 74. Here, the gray values 75 in column 3412 and column 3415 match each other, that is, they are exactly opposite to each other. However, in an optional embodiment, the second gray value may be unequal in the two boundary feature pixel columns and may not be exactly opposite to each other.

Figure 34b shows the second write pass of the four write passes used to generate straight lines. The only difference between FIG. 34b and FIG. 34a is that the second gray values of the boundary feature pixel columns 3412 and 3415 are moved from the third position from the top in FIG. 34a to the top position in FIG. 34b.

Figure 34c shows the third write pass of the four write passes used to generate straight lines. The only difference between Fig. 34b and Fig. 34c is that the second gray values of the boundary feature pixel columns 3412 and 3415 are moved from the top position of Fig. 34b to the fifth position from the top of Fig. 34c.

Figure 34d shows the fourth write pass of the four write passes used to generate straight lines. The only difference between FIG. 34d and FIG. 34c is that the second gray value of the boundary feature pixel columns 3412 and 3415 is moved from the fifth position from the top in FIG. 34c to the bottom position in FIG. 34d.

When the first, second, third, and fourth write paths are stacked, the effect of the second gray value is substantially the same as the low gray value of the boundary feature pixel columns 3412 and 3415 in FIG. 1 .

Figure 34e shows a write pass scheme in an embodiment with four write passes and a pixel sequence length of 8 pixels. The first column, the second column, the third column, and the fourth column respectively represent a boundary feature pixel column in the first, second, third, and fourth write paths. As shown in FIG. 34e, in the leftmost column, the pixels in the boundary feature pixel column of the first write pass are first individually set as a gray value sequence. At least one of the eight pixels in the sequence has a gray value different from the other. With the write path scheme shown in FIG. 34e, the at least one pixel that is different from other pixels will move around the boundary feature pixel column and generate a finer address grid when the corresponding write paths are stacked on top of each other.

Alternatively, the number of pixels in the sequence may be any number other than the illustrated 8, such as 6, 12, 14, and 16 pixels. The present invention is not limited to one write path or four write paths as shown in the figure, but any number of write paths, such as 2, 3, and 5 may be used.