Transistor and making method thereof

Transistor and its manufacturing method

The invention relates to a thin film transistor (TFT) and a manufacturing method thereof. The thin film transistor according to the present invention can be made on an insulating substrate such as glass, or on a substrate made of crystalline silicon. In particular, the present invention relates to a thin film transistor manufactured through process steps such as crystallization and thermal annealing activation.

Recently, an insulated gate type semiconductor device including an insulating substrate and provided with a thin film active layer (sometimes referred to as an active region) thereon has been effectively studied. In particular, great efforts have been made in the study of thin-film insulated gate transistors, which are commonly referred to as thin-film transistors (TFTs). Multiple TFTs are made on a transparent insulating substrate, mainly to use them to control the matrix to drive each pixel or drive circuit of the display device. According to the material and state of the semiconductor used in the TFT, TFTs can be classified into amorphous silicon TFTs and crystalline silicon TFTs.

Among the many TFTs mentioned above, the manufacture of amorphous TFTs does not have to undergo high-temperature processes. Amorphous TFTs have long been put into practical use, because when they are fabricated on a large-area substrate, their yield is high. Generally, an inverted ladder type (also called a bottom gate type) amorphous silicon TFT is used in actual amorphous silicon TFTs. The gate electrode of this type of amorphous silicon TFT is arranged under the active area.

The process steps for manufacturing an existing TFT include: forming a gate electrode on a substrate; forming an amorphous silicon film and an active layer as a gate insulating film; and forming an N-type crystal fine-grained film on the amorphous silicon film. Silicon film to set source and drain regions. However, since the etching rate of the N-type silicon film and the amorphous silicon film provided as the substrate are almost the same, this process requires additional steps, such as providing an etching stop layer and the like.

As a measure to overcome the above-mentioned problems, a method for directly implanting high-speed ions into an amorphous silicon film to form a source and a drain using an ion doping process is provided.

However, this method is still unsatisfactory, because the crystallinity of the ion implanted region produced by it is obviously damaged. The conductivity of these regions is low, so they are not yet suitable for practical use. It has also been proposed to anneal these regions with laser beams and similar light energy to increase their crystallinity. However, this method is not suitable for mass production.

The currently practically useful method is the method of crystallizing amorphous silicon by heating. However, this method requires annealing at a temperature of 600°C or above. Therefore, this process is unpopular due to the problem of the substrate. More specifically, the alkali-free glass substrates generally used for amorphous silicon TFTs begin to deform at 600°C or lower (for example, the softening point of Corning#7059 glass substrate is 593°C). Annealing at 600°C will shrink or deform the glass substrate.

Moreover, annealing at 600°C will damage the characteristics of amorphous silicon previously produced at low temperatures. More specifically, the active region is also subjected to crystallization at 600°C, and the advantageous characteristics are completely lost, that is, the amorphous silicon TFT no longer has its characteristic of low leakage current. This problem requires the crystallization process to be carried out at a lower temperature (preferably at a temperature of 50°C or lower than the deformation temperature of the glass).

Generally, semiconductors in an amorphous state have low electric field mobility. Therefore, they cannot be used for TFTs that require high-speed operation. Moreover, the electric field mobility of P-type amorphous silicon is extremely low. This makes P-channel TFT (PMOS TFT) manufacturing impractical. It is inferred from this that a complementary MOS circuit cannot be obtained, because a combination of P-channel TFT and N-channel TFT (NMOS TFT) is necessary to realize CMOS.

Compared with amorphous semiconductors, crystalline semiconductors have higher electric field mobility and are therefore suitable for high-speed operation TFTs. The advantage of crystalline silicon is that it is easy to make CMOS circuits, because not only NMOS TFT but also PMOS TFT can be obtained from crystalline silicon. Therefore, a liquid crystal display with an active matrix drive called a monolithic structure is proposed. Not only the active matrix part but also the peripheral circuits (such as the driving circuit) are composed of CMOS crystal TFTs. For these reasons, research and development of TFTs using crystalline silicon have recently become more active.

Crystalline silicon can be obtained by irradiating amorphous silicon with laser or strong light of equal light intensity. However, this process is not suitable for mass production; and it is unstable because the laser output itself is unstable and because the process is too short.

A practical process for crystallization of amorphous silicon recently is to use heat treatment, that is, thermal crystallization. This process can produce crystalline silicon of uniform quality regardless of the batch size. However, there are still problems with this process, which need to be resolved.

Generally, thermal crystallization requires long-term annealing at about 600°C, or annealing at temperatures as high as 1000°C, or even higher. The latter process narrows the choice of substrate materials, because it cannot be applied to substrates other than quartz substrates, and the aforementioned processing has other problems.

Specifically, the process of using a cheap alkali-free glass substrate (such as Corning#7059 glass substrate) to manufacture TFT includes: depositing a layer of amorphous silicon film on the substrate; Crystallize the amorphous silicon film for 24 hours or longer; deposit a layer of gate insulating film; form the gate electrode; introduce impurities (by ion implantation or ion doping); Annealing for hours or longer activates the doped impurities; forms an interlayer insulator; and forms source and drain regions.

Among the above-mentioned process steps, it is found that the activation of the doped impurities is the most problematic in the sixth step. Most alkali-free glass will deform near 600°C (for example, the softening temperature of Corning#7059 glass is 593°C). This means that the shrinkage of the substrate must be considered in this step. In the second step, the annealing step, shrinkage of the substrate is not a problem because the pattern has not yet been formed on the substrate. However, in the sixth step, the circuit pattern has been formed on the substrate. If the substrate shrinks, mask alignment cannot be performed in the next steps. This obviously reduces the yield. This requires the sixth step to be carried out at a lower temperature, preferably at a temperature lower than the glass deformation temperature by 50°C or lower.

As mentioned earlier, the use of lasers can reduce the process temperature. However, the reliability of this process is poor because not only the laser is unstable, but also because there is a gap between the part irradiated by the laser (source and drain region) and the part not irradiated by the laser (the active region, that is, the region under the gate electrode). The temperature rise is different and the stress is generated.

Therefore, it is difficult to use a laser to manufacture TFTs, and no other effective measures have been found to overcome these problems. The present invention provides a solution to the above-mentioned difficulties. That is, the purpose of the present invention is to propose a process that overcomes the above-mentioned problems and is suitable for mass production.

As a result of extensive research by the present inventors, it was found that the crystallization of a substantially amorphous silicon film can be accelerated by adding a small amount of catalytic material. According to this method, crystallization can be completed in a relatively short time at a lower temperature. Preferred catalytic materials include some pure metals, namely: nickel (Ni), iron (Fe), cobalt (Co) and platinum (Pt), or a compound such as the silicide of the elements listed herein. Specifically, the process according to the present invention includes forming a material containing catalytic elements in the shape of thin films, particles, agglomerates, etc., on or under and in contact with an amorphous silicon film, and at an appropriate temperature, Generally at 580°C or lower, preferably at 550°C or lower, the formed material is thermally annealed to crystallize it. Another method is that it is not necessary to form a material containing a catalytic element in contact with the amorphous silicon film, and instead, the catalytic element is doped into the amorphous silicon film by a method such as ion implantation.

Of course, increasing the annealing temperature can shorten the crystallization cycle. Furthermore, as the concentration of nickel, iron, cobalt, or platinum increases, the period of crystallization becomes shorter and the temperature of crystallization becomes lower. Through in-depth research, the present inventors found that the concentration of at least one of the above-mentioned catalytic elements can accelerate crystallization at a concentration above 1×1017 cm-3, and its concentration is preferably 5×1018 cm-3 or higher.

However, the catalytic materials listed above are not good for silicon. Therefore, it is best to control its concentration to the lowest possible level. Through research, the inventors found that the preferred range of the total concentration is 1×1020 cm-3 or lower. In particular, in the active layer, the concentration of the catalytic material must be controlled to 1×1018 cm-3 or less, preferably lower than 1×1017 cm-3, and more preferably lower than 1×1016 cm-3.

Fig. 1(A)-1(E) schematically shows a sequential structural cross-sectional view obtained by the process of an embodiment of the present invention (Example 1); Fig. 2(A)-2(E) schematically shows according to the present invention A sequential structural cross-sectional view obtained by the process of another embodiment of the invention (Example 2); Figures 3(A)-3(E) schematically show the process according to another embodiment of the present invention (Example 3) The obtained sequential structural sectional views; and FIGS. 4(A)-4(E) schematically show sequential structural sectional views obtained by the process of still another embodiment (Example 4) of the present invention.

As mentioned above, the inventors of the present invention have paid attention to the role of catalytic elements and found that these elements can be used to overcome the problems in the prior art processes. A process for fabricating a TFT according to an embodiment of the present invention includes: forming a gate electrode; depositing a gate insulating film; depositing an amorphous silicon film; and introducing impurities into the amorphous silicon film by ion implantation or ion doping Inside;

A material film containing a catalytic element is formed on the silicon film; heat treatment at 550° C. or below is not longer than 8 hours to activate the doped impurities; and source and drain electrodes are formed.

A process according to another embodiment of the present invention includes: forming a gate electrode; depositing a gate insulating film; depositing an amorphous silicon film; introducing impurities into the amorphous silicon film by ion implantation or ion doping; Catalytic elements are introduced into the silicon film by ion implantation or ion doping; heat treatment at 550°C or lower for no longer than 8 hours to activate the doped impurities; and source and drain electrodes are formed.

In the above process steps, the order of the fourth step and the subsequent step is interchangeable. That is, the doping step may be performed before or after the step of introducing the catalytic element. The introduction of catalytic elements into the source and drain regions significantly accelerates the crystallization of these two regions. Therefore, a temperature of 550°C or below is sufficient to complete the activation, and it is generally performed at a temperature of 500°C or lower. Annealing for 8 hours or less, generally 4 hours or less is sufficient. In particular, it has been found that when a catalytic element is introduced into a silicon film by ion implantation or ion doping, crystallization proceeds extremely rapidly because the element is found to be uniformly distributed in the silicon film.

In impurity doping, a mask can be used to dope the catalytic element into the silicon film. In a self-aligned way, the mask can be obtained by illuminating from behind the gate electrode.

Another process for fabricating a TFT according to another embodiment of the present invention includes: depositing a layer of amorphous silicon film; heating the amorphous silicon film at 600°C or above for 24 hours or longer to crystallize it Depositing a layer of gate insulating film; forming a gate electrode; introducing impurities into the amorphous silicon film by ion implantation or ion doping; depositing a film containing a catalytic element on the silicon film; at 600 °C or The following heat treatment is not longer than 8 hours to activate the doped impurities; form an interlayer insulator; and form source and drain electrodes.

Another process for fabricating a TFT according to an embodiment of the present invention includes: depositing a layer of amorphous silicon film; heating the amorphous silicon film at 600°C or above for 24 hours or longer to crystallize it; Deposit a layer of gate insulating film; form a gate electrode; use ion implantation or ion doping to introduce impurities into the amorphous silicon film; use ion implantation or ion doping to introduce a catalytic element into the silicon film; at or below 600°C The heat treatment is not longer than 8 hours to activate the doped impurities; form an interlayer insulator; and form source and drain electrodes.

In the above process steps, the order of the fifth step and the next step can be reversed. That is, the doping step may be performed before or after the step of introducing the catalytic element. The introduction of catalytic elements into the source and drain regions significantly accelerates the crystallization of these two regions. Therefore, activation is sufficient at 600°C or below, generally 550°C or below. For annealing, 8 hours or less, generally 4 hours or less is sufficient. In particular, when the catalytic element was introduced into the silicon film by ion implantation or ion doping, it was found that the crystallization proceeded extremely rapidly because the element was found to be uniformly distributed in the silicon film.

The process of the present invention is characterized in that the process includes adding a catalytic element that is unfavorable to silicon, but the concentration in the active region is suppressed to an extremely low level of 1×1018 cm-3 or below. That is, all the aforementioned processes include providing a mask or gate electrode for the active region during doping. Therefore, the catalytic element will not directly contact or be injected into the active area. The reliability and characteristics of the TFT are not impaired. In particular, the concentration of Ni doped into the impurity region is 10 times or more than that of the active region, and then the annealing temperature and time are preferably set to activate the impurity region while maintaining the amorphous state. Because annealing is completed under thermal equilibrium, the temperature difference that occurs during laser annealing will not be encountered.

Hereinafter, the present invention will be described in more detail with reference to non-limiting embodiments. However, it should be understood that this is not a limitation of the present invention. Example 1 Fig. 1 shows a step-by-step structural sectional view obtained by a process according to an embodiment of the present invention. Referring to FIG. 1, a tantalum film with a thickness of 3000-8000 Å is formed on Corning #7059 glass substrate 1, and a pattern is formed to form a gate electrode 2. Then, the surface of the tantalum film is anodized to form an anodized film 3 having a thickness of 1000-3000 Å, for example, 2000 Å. Then, a silicon nitride film 4 with a thickness of 1000-5000 angstroms, for example 1500 angstroms, is deposited by plasma CVD. Then, plasma CVD is used to deposit an intrinsic (I-type) amorphous silicon film with a thickness of 200-1500 Ȧ, for example, 500 Ȧ. The final amorphous silicon film is patterned to obtain a semiconductor region 5, as shown in FIG. 1(A).

The surface of the obtained substrate is covered with photoresist and exposed from the back of the substrate to form a mask 6 consistent with the gate electrode pattern, as shown in FIG. 1(B).

With ion doping, phosphorus is implanted into the semiconductor region 5 as an impurity using the mask 6 obtained. Phosphine (PH3) is used as the doping gas for ion doping, the acceleration voltage used is 60-90KV, such as 80KV, and the dose used is in the range of 1×1015-8×1015cm-2. In this case, the dosage of phosphorus is 2×1015 cm-2. In this way, N-type impurity regions 7a and 7b are formed as shown in FIG. 1(C).

Then, the mask 6 is used to implant nickel ions by ion doping. The dose used is 2×1013-2×1014cm-2, more specifically, for example, 5×1013cm-2. As a result, it was found that the concentration of nickel in the N-type impurity regions 26a and 26b was approximately 5×1018 cm-3. In this way, the structure shown in Figure 1(D) is obtained.

Then, the resultant structure is annealed at 500°C for 4 hours in a hydrogen atmosphere containing hydrogen with a partial pressure of preferably 0.1-1 atm. Activate impurities in this way. Because nickel ions have been injected into the impurity regions in advance, it was found that the crystallization in these regions was accelerated due to the catalytic effect of nickel on the crystallization. This activates the impurity regions 7a and 7b.

Subsequently, a 3000 Å thick silicon oxide film 8 is deposited by plasma CVD as an interlayer insulator, and contact holes are formed thereon to serve as the source and drain regions of the TFT. A multilayer film of metal-containing materials such as titanium nitride and aluminum is used. Create electrodes with interconnections 9a and 9b. This completes a complete thin film transistor, as shown in Figure 1(E).

A secondary ion mass spectrometer (SIMS) was used to measure the nickel concentration in the impurity region and the active region of the TFT prepared by the above process. The measured nickel concentration in the impurity region is 1×1018-5×1018cm-3. This is in clear contrast with the active area concentration of 1×1016 cm-3 lower than the detection limit. Example 2 Fig. 2 shows a cross-sectional view of each step structure obtained by an embodiment of the present invention. Referring to FIG. 2, a tantalum film having a thickness of 3000-8000 Ȧ, for example 5000 Ȧ, is formed on a Corning #7059 glass substrate 11, and a gate electrode 12 is patterned. Then, an anodic oxidation method is used to form an anodic oxide film with a thickness of 1000-3000 angstroms, for example 2000 angstroms, on the surface of the tantalum film. Then, a silicon nitride film 14 having a thickness of 1000-5000 angstroms, for example, 1500 angstroms, is deposited by the plasma CVD method. Next, an intrinsic (I-type) amorphous silicon film with a thickness of 200-1500 angstroms, for example, 500 angstroms in this example, is deposited thereon by plasma CVD. The obtained amorphous silicon film is patterned to obtain a semiconductor region 15, as shown in FIG. 2(A).

A layer of photoresist is coated on the surface of the resultant substrate, and exposed from the back surface of the substrate to form a mask 16 consistent with the gate electrode pattern shown in FIG.

By the ion doping method, the obtained mask 16 is used to implant the semiconductor region 15 with phosphorus as an impurity. Phosphine (PH3) is used as the doping gas to complete ion doping, the acceleration voltage added is 60-90KV, such as 80KV, and the dose is 1×1015-8×1015cm-2. In this case, the dosage of phosphorus is 2×1015cm-2. In this way, N-type impurity regions 17a and 17b are formed as shown in FIG. 2(C).

Then, a layer of nickel silicide film (expressed as NiSix in chemical formula, where X is 0.4-2.5 such as 2.0) 18 with a thickness of 5-200 Ȧ, such as 20 Ȧ, is deposited on the entire surface by a sputtering method. Since the resulting film was as thin as about 20 angstroms, it looked like agglomerates rather than a continuous film. The appearance of the film is not so important in this example. In this way, the structure shown in Figure 2(D) is obtained.

Then, the obtained structure is annealed in a hydrogen-containing atmosphere at a temperature of 450° C. for 4 hours, and the partial pressure of hydrogen is preferably 0.1-1 atm. In this way, impurities are activated. Because the nickel silicide film 18 is deposited in advance, it diffuses nickel atoms and acts as a catalyst for the crystallization of the N-type impurity regions 17a and 17b. This accelerates the crystallization of these regions and activates the impurity regions 17a and 17b.

Subsequently, a 3000 Å thick silicon oxide film 19 is deposited by plasma CVD as an interlayer insulator, and contact holes are formed thereon, so as to be the source and drain regions of the TFT, using metal-containing materials such as titanium nitride and aluminum. Layer the film to establish electrodes with interconnections 20a and 20b. This completes a complete thin film transistor, as shown in Figure 2(E).

A secondary ion mass spectrometer (SIMS) was used to measure the nickel concentration in the impurity region and the active region of the TFT prepared by the above process. The measured nickel concentration in the impurity region is 1×1018-3×1018. This is in sharp contrast with the active area concentration in the range of 1×1016-5×1016. Example 3 Fig. 3 shows a cross-sectional view of each step structure produced by the process of another embodiment of the present invention. Referring to FIG. 3, a 2000 Å thick silicon oxide film 111 is formed on a Corning #7059 glass substrate 110 by a sputtering method as a base film. Then, an intrinsic (I-type) amorphous silicon film having a thickness of 500-1500 angstroms, for example, 1500 angstroms, is deposited thereon by plasma CVD. Then, annealing was performed at 600°C for 48 hours in a nitrogen atmosphere to crystallize the amorphous silicon film. After annealing, the silicon film is patterned to form island-shaped silicon regions 112, and a 1000 Å thick silicon oxide film 113 is deposited thereon as a gate insulating film by sputtering. The sputtering process is performed in an atmosphere containing oxygen and argon using silicon oxide as a sputtering target, and the ratio of argon to oxygen is not higher than 0.5, for example, 0.1 or less. During the process, the temperature of the substrate is maintained at 200-400°C, for example, 350°C.

Then, a silicon film with a thickness of 6000-8000 Å, for example, 6000 Å, with a phosphorus content of 0.1-2% is deposited by low-pressure CVD. The step of depositing the silicon oxide film is preferably carried out continuously with the step of depositing the silicon film. The resulting silicon film is patterned to form a gate electrode 114, as shown in FIG. 3(A).

Then, plasma doping is used, and the gate electrode is used as a mask to introduce phosphorus as an impurity into the silicon region. Phosphine (PH3) is used as the doping gas for doping, the acceleration voltage used is 60-90KV, for example 80KV, and the dose used is 1×1015-8×1015cm-2. The dosage of phosphorus doped in this embodiment is 2×1015 cm-2. In this way, N-type impurity regions 115a and 115b are formed as shown in FIG. 3(B).

The silicon oxide film 113 on the impurity region is etched to expose the impurity region 115, and a nickel silicide film (represented by the chemical formula NiSix) is deposited on the entire surface by a sputtering method with a thickness of 5-200 Å, such as 20 Å, where X is 0.4 -2.5, for example 2.0)116. Since the resulting film is about 20 angstroms thin, it looks like agglomerates, not like a continuous film. In this case, the appearance of the film is not so important. In this way, the structure shown in Figure 3(c) is obtained.

Then, the resultant structure was annealed at 500°C for 4 hours in a nitrogen atmosphere to activate the impurities. Since nickel diffuses into the N-type impurity regions 115a and 115b from the nickel silicide film deposited thereon in advance, it is found that annealing accelerates the occurrence of crystallization. In this way, the impurity regions 115a and 115b are activated. The resulting structure is shown in Figure 3(D).

Then, a 6000 Å thick silicon oxide film 117 is deposited by plasma CVD as an interlayer insulating layer, and contact holes are formed thereon. A metal-containing material, such as a multilayer film of titanium nitride and aluminum, is used as the source and drain of the TFT. The region forms electrodes with interconnections 118a and 118b. Finally, the resulting structure was annealed at 350°C for 30 minutes in a hydrogen atmosphere of 1 atm. This completes a complete thin film transistor, as shown in Figure 3(E).

A secondary ion mass spectrometer (SIMS) was used to measure the nickel concentration in the source and drain regions and the active region of the TFT prepared by the above process. It is found that the nickel concentration of the source and drain regions is 1×1018-5×1018cm-3. This is in sharp contrast with the concentration of the active area which is 1×1016cm-3 lower than the detection limit. Example 4 Fig. 4 shows the surface diagram of each step structure prepared by the process of another embodiment of the present invention. Referring to FIG. 4, on a Corning #7059 glass substrate 29, a 2000 Å thick silicon oxide film is formed as a base film by sputtering. Then, a layer of intrinsic (I type) amorphous silicon film is deposited on it by plasma CVD, the thickness of which is in the range of 500-1500 angstroms, for example, 1500 angstroms. Then, annealing was performed at 600°C for 48 hours in a nitrogen atmosphere to crystallize the amorphous silicon film. After annealing, the silicon film is patterned to form an island-shaped silicon film 22.

Then, plasma CVD is used to deposit a 1000 Å silicon oxide film 23 as a gate insulating film using tetraethoxysilane (TEOS; Si(OC2H5)4) and oxygen as raw materials. Therefore, trichloroethylene is added to the original gas material. Before the film deposition begins, oxygen gas is supplied to the reaction chamber at a flow rate of 400SCCM (standard cubic centimeter per minute). When the total pressure is maintained at 5Pa, the substrate temperature is 300°C, and 150W RF power is applied, the reaction chamber Plasma is generated inside. Maintain this state for 10 minutes. Then, oxygen, TEOS and trichloroethylene were introduced into the reaction chamber at flow rates of 300 SCCM, 15 SCCM and 2 SCCM respectively, and a silicon oxide film was deposited. During the film deposition, the substrate temperature, RF power, and total pressure were maintained at 300°C, 75W, and 5Pa, respectively. When the film deposition is completed, hydrogen gas with a pressure of 100 Torr is introduced into the reaction chamber to complete hydrogen annealing at 350° C. for 35 minutes.

Subsequently, a sputtering method is used to deposit a tantalum film with a thickness of 3000-8000 angstroms, for example 6000 angstroms. Titanium, tungsten, molybdenum or silicon can be used instead of tantalum. However, the film must have sufficiently high heat resistance to withstand the subsequent activation treatment. The two-step deposition steps of the silicon oxide film 23 and the tantalum film are preferably performed continuously. The tantalum film is patterned to form the gate electrode 24 of the TFT. The surface of the tantalum film is then anodized to form an oxide layer 25 on the surface. The anodization is carried out in a glycol solution containing 1-5% tartaric acid. Thus, a 2000 Å thick oxide layer is obtained, as shown in Figure 4(A).

Plasma doping is performed using the gate electrode as a mask, and phosphorus is injected into the silicon region as an impurity. Phosphine (PH3) is used as the doping gas for the doping process, and the acceleration voltage used is 80KV. In this example, phosphorus was incorporated in a dose of 2×1015 cm-2. In this way, N-type impurity regions 26a and 26b are formed. It can be seen that the impurity region 26 established in this case deviates from the gate electrode 24, as shown in FIG. 4(B).

Then, ion doping is used to implant nickel ions using the gate electrode as a mask. The dose used to introduce nickel is in the range of 2×1013-2×1014 cm-2, for example, 5×1013 cm-2 more specifically. As a result, it was found that the concentration of nickel in the N-type impurity regions 26a and 26b was approximately 5×1018m-3. Thus, the structure shown in Fig. 4(C) is obtained.

The resulting structure was then annealed at 500°C for 4 hours in a nitrogen atmosphere to activate the impurities. Since nickel ions were previously implanted into the N-type impurity regions 26a and 26b, it was found that the catalytic effect of nickel on crystallization accelerates the progress of recrystallization in these regions. Thus, the impurity regions 26a and 26b are activated. The resulting structure is shown in Figure 4(D).

Subsequently, TEOS was used as a raw material, a 2000 Å thick silicon oxide film 27 was deposited as an interlayer insulator by plasma CVD, contact holes were formed thereon, and a multilayer film containing metal materials such as titanium nitride and aluminum was used as the source of the TFT. And the drain region form an electrode with interconnections 28a and 28b. Thus, a complete semiconductor circuit is completed, as shown in Figure 4(E).

It is found that the thin film transistor fabricated in this way has a field-effect mobility in the range of 70-100cm2/Vs when the gate voltage is 10V. When a voltage of -20V is applied to the gate, the threshold voltage is 2.5-4.0V and the leakage current is 10-13A or lower.

In the present invention, by activating the doped impurities at a temperature as low as 500 DEG C in a short period of 4 hours, the production volume of thin film transistors is increased. Therefore, the present invention provides a method for solving the problems of the prior art; since the high temperature process performed at 600° C. or above has encountered the serious problem of the deformation of the glass substrate, the crystallization is realized at such a low temperature. This avoids shrinkage and bending of the glass substrate.

The advantages of the present invention listed above also include the ability to process large-area substrates at one time. More specifically, a large-area substrate is cut into a plurality of semiconductor circuits (such as matrix circuits). Therefore, the individual cost of the circuit can be significantly reduced. When applied to the production of liquid crystal displays, the process according to the present invention can increase productivity and improve the performance of the display. It can be seen from the above that the present invention can be widely used in industrial production.

Although the present invention has been described in detail with reference to specific embodiments, those skilled in the art should understand that various changes and modifications can be made without departing from the spirit and scope of the present invention.