Device isolating process flow for ARS system

Device isolation process flow for ARS system

Technical field

The technical field relates to atomic resolution storage (ARS) systems, and in particular, to device isolation process flow for ARS systems.

Background technique

The ARS system provides a small device with a storage density greater than 1 megabit per square inch (1000 gigabits). The ARS technology is based on advanced atom probe microscopes, in which a probe field emitter tip as small as a single atom is used to scan the surface of the material to produce images with an accuracy of a few nanometers. Probe storage technology can use an array of atomic-level probe field emitters to read and write data to points on the storage medium.

The ARS system generally includes three bonded silicon (Si) wafers, namely the tip wafer, also called the launch wafer, the rotor wafer, also called the mover wafer, and the stator wafer. These wafers are bonded together using wafer bonding techniques well known in the art.

Figure 1 illustrates the prior art ARS system, in which all diodes share a common electrode. The spire wafer 110 includes a plurality of field emitter spires 114. The phase change layer 123, which can be used as a storage medium to store data bits, is deposited on the substrate rotor wafer (120), also known as the mover wafer. The substrate rotor wafer 120 is a highly doped silicon substrate, which may be an n-type substrate or a p-type substrate. The cover layer 160 is coated on the phase change layer 123 to protect the phase change layer 123 and prevent the material from evaporating when heated. The cover layer 160 also changes the surface state of the phase change layer 123. The electron beam focusing electrode 113 causes the focused electron beam 116 to locally change the phase of the local dielectric film. As shown in FIG. 1, the rotor wafer 120 can move in the x and y directions, so that data bits can be written to and read from the storage medium.

The ARS storage medium uses pn junction diodes, that is, the devices used to read data bits are buried in the top active silicon layer. In the prior art ARS system, the diodes share a common electrode (not shown), which may increase the crosstalk between devices, resulting in higher electrical noise.

Summary of the invention

The method for device isolation of the ARS system includes: forming an insulating layer between a wafer substrate and a top active silicon layer, the wafer substrate being, for example, a rotor wafer; and forming a phase change layer on top of the active silicon layer; Depositing and patterning on the phase change layer, and selectively etching the mask layer; using the mask layer as a mask to etch the top active silicon layer until the insulating layer. As a result, the diodes, that is, the devices buried in the top active silicon layer, are electrically isolated from each other to improve the signal-to-noise ratio of the ARS system.

In an embodiment of the device isolation process flow, the insulating layer is formed by implanting oxygen ions under the top active silicon layer on the wafer substrate and heating the oxygen to generate oxide.

In another embodiment of the device isolation process flow, the insulating layer is formed by epitaxially growing silicon on the rotor wafer substrate using anti-doping material and heating the anti-doping material.

The device isolation process is to insert the device isolation into the process flow of the ARS system, so the diodes can be electrically insulated from each other to improve the signal-to-noise ratio. In addition, since extremely harsh processing is performed before depositing the phase change layer that stores the data bits, the processing damage of the phase change layer is minimized.

Description of the drawings

The preferred embodiment of the device isolation process will be described in detail with reference to the following drawings. Similar numbers in the figures represent similar elements: Figure 1 shows a prior art ARS system with non-isolated devices; Figure 2(a) and 2(b) shows a typical ARS system; Figure 3 shows an exemplary ARS system with isolation devices; Figure 4(a)-4(f) shows an exemplary ARS system device isolation process flow; 5(a)-5(c) show another method for device isolation of the ARS system; FIG. 6 is a flowchart illustrating an exemplary device isolation process flow of the ARS system.

detailed description

Figures 2(a) and 2(b) illustrate an exemplary ARS system 200. The ARS system 200 has a high data storage capacity, up to 1000 gigabits per square inch. The ARS system 200 is small, sturdy, and easy to carry. In addition, the ARS system 200 has low power consumption because, generally, when the ARS system 200 does not need to operate, it does not consume power. Referring to Figure 2(a), the ARS system 200 includes three bonded silicon wafers, namely the tip wafer 210, which is referred to as the first wafer in this specification; the rotor wafer, which is generally also called the mover wafer, is referred to in this specification This is the second chip; and the stator chip 230. The rotor wafer 220 has a general thickness of 100 μm and is a highly doped silicon substrate, which can be an n-type or p-type substrate. The wafers 210, 220, and 230 are bonded together using wafer bonding technology, as shown in FIG. 2(a). The wafer bonding technology is well known in the art.

Each wafer-to-wafer bonding requires the use of an ultra-high vacuum (UHV) sealing member 202 to seal a high-vacuum inner cavity. It helps to maintain the internal environment of the ARS chip. Wafer-to- wafer bonding also requires low-resistance electrical connections. For example, as shown in FIG. 2(a), the conductive electrode on the stator side of the rotor wafer 220 may be coupled with the conductive electrode on the rotor side of the stator wafer 230. The conductive electrode on the dielectric side of the rotor wafer 220 may be connected to a complementary metal oxide semiconductor (CMOS) circuit 232 located in the stator wafer 230. The apex electronic circuit 212 located in the stator chip 230 controls the field emitter apex 214 (see FIG. 2(b)). The field emitter apex is required to be connected to the storage medium 222 in the ARS system 200. The storage medium 222 includes a medium recording unit 224 (see FIG. 2(b)) to store data bits in the ARS system 200.

The read/write (R/W) electronic circuit containing the CMOS circuit 232 is also located in the stator chip 230 under the conductive electrode 234(b). The R/W electronic circuit can control the reading or writing of data bits in the storage medium 222.

Through the wafer through hole 226, the R/W electrical signal (not shown) can be transmitted from the CMOS circuit 232 in the stator wafer 230 to the conductive electrode on the dielectric side of the rotor wafer 220 and the tip electronic circuit 212 in the tip wafer 210.

Figure 2(b) illustrates the operation of the ARS system 200. A single field emitter tip 214 generates an electron beam 216, which is drawn from the metal of the field emitter tip 214 with a high electric field. By heating the micro data points and changing the physical state and phase of the points, the electron beam is focused and used to write data bits into the storage medium. The electron beam 216 can also be used to determine the state (value) of the data bits in the storage medium 222. The emitter spire array 218 is an array of field emitter spires 214, and the storage medium 222 under it moves with nanometer precision. The suspension spring 240 shown in FIG. 2(b) can fix the rotor wafer 220 between the field emitter apex 214 and the stator wafer 230, and move the data bit relative to the field emitter apex 214, thereby making each field emitter apex 214 Access multiple data bits.

For the operation of the ARS system 200, the rotor wafer 220 and the stator wafer 230 need to be processed, that is, conductive electrodes are deposited for nanometer precision positioning control. An example of the ARS system 200 process flow is in the US patent application of Lee et al., titled "Process flow of bonding ARS mover wafer using selenized wafer after processing the medium side of the rotor wafer" and "Before processing the medium side of the rotor wafer" , The process flow of using selenide wafers to bond ARS movers is described in ", they were submitted on the same day, and they are listed here for reference.

Device isolation process flow. Device isolation is inserted in the process flow of the ARS system 200 to make the diode, that is, the small electronic device buried in the phase change layer 323 (described later) and the top active silicon layer 330 (described later) ) And the electronic devices on the surface of the rotor wafer 220 may be electrically insulated from each other. As a result, the signal-to-noise ratio is improved. In addition, since the phase change layer is subjected to the most severe treatment before depositing the phase change layer that stores the data bits, the damage to the phase change layer processing is minimized.

Figure 3 describes a typical ARS system with isolation devices. The tip wafer 210, also called an emitter wafer, may include a plurality of field emitter tips 214. The tip emitter 214 may be replaced by a flat emitter. An insulating layer 350, such as a buried oxide layer 350(a) (described later) or an anti-doped semi-insulating silicon layer 350(b) (described later), can be active silicon on the top of the rotor wafer 220 The layer 330 is formed below. The phase change layer 323 that can be used as the storage medium 222 for storing data bits can be deposited on top of the top active silicon layer 330. The top active silicon layer 330 and the phase change layer 323 together form a heterogeneous pn junction diode 370 for electrically reading or writing data bits on the phase change layer 323. When two different materials with different conductivity types, such as active silicon and phase change materials, form a junction and cause current to flow in one direction, a heterojunction pn diode 370 (heterojunction pn) is generally formed. diode). The cover layer 360 may cover the phase change layer 323 to protect the phase change layer 323 and prevent the material from evaporating when heated. The cover layer 360 can also improve the state of the surface of the phase change layer 323. The rotor wafer 220 can be moved in the x and y directions to write to or read data bits from the storage medium 222.

The device isolation process can electrically insulate multiple heterogeneous pn junction diodes 370 from each other, so each isolated diode 370 is coupled to each field emitter tip 214. By moving the diode 370 in the x and y directions, multiple data bits can be written on a single isolated diode 370, thus reducing the chance of crosstalk between different diodes 370. With the reduction of electrical signal interference, the signal-to-noise ratio of the ARS system 200 is greatly improved. The signal-to-noise ratio refers to the signal corresponding to the data bit being read.

Figures 4(a)-4(f) illustrate the typical device isolation process flow of the ARS system 200. FIG. 4(a) illustrates the oxygen ion implantation under the top active silicon layer 330(a) on the rotor wafer 220. After the oxygen is implanted, an isolation oxide layer 350(a) can be formed by heat treatment. The oxide layer 350(a) can electrically insulate the top active silicon layer 330(a) and the rotor wafer 220, so that the flow of electrons between the two can be prevented.

Referring to FIG. 4(b), the phase change layer 323(a) can be formed by depositing a thin film of the phase change material by thermal evaporation. The phase change material can be transformed from amorphous to crystalline material. The atomic lattice of amorphous materials is generally already disordered and does not have long-range order. On the other hand, the crystalline material has a periodic arrangement of a long-range ordered atomic lattice. If the crystalline material is ion implanted, that is, ions with energy are injected into the crystalline material, the implanted ions will destroy the lattice structure of the crystalline material. Therefore, crystalline materials may lose long-range order and become amorphous materials. The phase change layer 323(a) can record data bits in the form of amorphous dots with a crystalline background. The protective cover layer 360 can be arbitrarily covered on the phase change layer 323(a) to protect the surface of the phase change layer and prevent the material from evaporating when heated.

Referring to FIG. 4(c), a mask layer 410, such as an SiO2 layer or a photoresist material (PR) layer, may be deposited on the phase change layer 323(a). The mask layer 410 may be patterned by, for example, photolithography, and a predetermined portion of the mask layer 410 may be etched.

Referring to FIG. 4(d), the exposed portion of the phase change layer 323(a) corresponding to the removed portion of the mask layer 410 may be etched by a dry method or a wet method. Dry etching is directional and anisotropic etching, for example, using plasma, that is, a mixture of discharged gas, electrons, and neutral atoms. Therefore, dry etching can be widely used to transfer fine patterns. Wet etching uses wet chemical reagents, such as acids and alkalis, so the orientation is not good. The profile of wet etching is isotropic, so wet etching is not suitable for transferring submicron fine patterns.

Figure 4(e) shows the next step, etching the top active silicon layer 330(a) until the insulating oxide layer 350(a). Due to the better pattern transfer capability of dry etching, the dry etching technique is generally used to define the top active silicon layer 330(a). Therefore, the heterogeneous pn junction diode 370, that is, the device buried in the top active silicon layer 330(a) and the phase change layer 323(a), are electrically insulated from each other to increase the signal-to-noise ratio of the ARS system 200.

Referring to FIG. 4(f), the mask layer 410 may be removed. In order to achieve the purpose of protection, the protective cover layer 360 may be optionally coated on the phase change layer 323(a).

5(a)-5(c) show another embodiment of the ARS system 200 device isolation process flow. Instead of implanting oxygen ions through the rotor wafer 220 of a highly doped silicon substrate, in order to form an electrical insulating layer, the implanted ions may be counter-doped to form a semi-insulating silicon layer 350(b).

First, the epitaxial process is used to grow crystalline silicon on a silicon substrate. During the growth of crystalline silicon, the type of silicon, that is, n-type or p-type, can be controlled by adding dopant materials. Between the rotor wafer 220 and the top active silicon layer 330(b), a semi-insulating silicon layer 350(b) may be formed along with the counter-doped epitaxial silicon layer. This process of forming an inverted pn junction diode is called "junction isolation."

Because epitaxial silicon can be grown at, for example, 600-650° C. and a production speed of 0.5 μm/min, the thermal accumulation of the epitaxial growth step is not fatal to the thermal CMOS circuit in the stator wafer 230. In addition, the doping concentration of the top active silicon layer 330(b) can be individually optimized for the rotor wafer 220 to obtain the best device performance.

Referring to FIG. 5(a), p-type doped silicon can be epitaxially grown on a counter-doped, that is, n-type, silicon rotor wafer 220 substrate. The p-type silicon dopant is activated by heat treatment to form a p-type semi-insulating silicon layer 350 (b). Alternatively, an n-type semi-insulating silicon layer may be epitaxially grown on the p-type silicon rotor wafer 220 substrate.

Secondly, as shown in Figure 5(b), n-type doped silicon can be epitaxially grown on top of the p-type dopant. The n-type silicon dopant activated by heat treatment can form the n-type top active silicon layer 330(b). Alternatively, in order to form the p-type top active silicon layer, p-type doped silicon is grown on the n-type silicon dopant.

Referring to FIG. 5(c), the p-type phase change layer 323(b) can be formed by depositing a phase change material on the n-type top active silicon layer 330(b). Alternatively, an n-type phase change layer may be formed on the p-type top active silicon layer. Optionally, a protective cover layer 360 is deposited on the phase change layer 323(b).

Similar to Figures 4(c)-4(f) (not shown in Figure 5), the mask layer 410, such as a hard mask SiO2 layer or a soft mask photoresist material (PR) layer, can be deposited on the phase Above the variable layer 323(b). The mask layer 410 may be patterned by, for example, photolithography, and a predetermined portion of the mask layer 410 may be etched. Then, the exposed portion of the phase change layer 323(b) corresponding to the cleared portion of the mask layer 410 may be etched by a dry method or a wet method.

Second, the top active silicon layer 330(b) can be etched up to the semi-insulating silicon layer 350(b). Therefore, the heterogeneous pn junction diode 370, that is, the devices buried in the top active silicon layer 330(b) and the phase change layer 323(b) are electrically insulated from each other, so as to improve the signal-to-noise ratio of the ARS system 200. Finally, the mask layer 410 can be removed, and the protective cover layer 360 can optionally be coated on the phase change layer 323(b) and the top active silicon layer 330(b) to play a protective role.

FIG. 6 is a flowchart showing the device isolation process flow of the ARS system 100. Step 610 involves performing oxygen ion implantation or anti-doping implantation under the active silicon layer 330 on the rotor wafer substrate 220, and then performing heat treatment to form the insulating layer 350 (step 612). Subsequently, by depositing a phase change material on the top active silicon layer 330, a phase change layer 323 may be formed (step 614). Optionally, the protective cover layer 360 may be coated on the phase change layer 323 to play a protective role.

Next, a mask layer 410, such as a hard mask SiO2 layer or a soft mask photoresist material (PR) layer, may be deposited on the phase change layer 323 (step 616). The mask layer 410 (step 618) is patterned by photolithography and a predetermined portion of the mask layer 410 can be etched (step 620). Then, the exposed portion of the phase change layer 323 corresponding to the etched portion of the mask layer 410 may be etched by a dry or wet process (step 626). In step 624, the top active silicon layer 330 can be etched up to the insulating layer 350. Finally, the mask layer 410 can be removed (step 626), and the protective mask layer 360 can optionally be deposited on the phase change layer 323 , Plays a protective role (step 628).

Exemplary embodiments have been used to describe the device isolation process flow. Those skilled in the art will realize that many improvements should be obvious according to these teachings. Therefore, this application is intended to cover any variations thereof.