Multiple edge through silicon vias and related systems, methods, and devices

Multiple edge through silicon vias and related systems, methods and devices

[0001] Divisional application related information

[0002] This application is a divisional application. The parent application is an invention patent application with an application date of August 3, 2020, application number 202010769221.0, and invention name "Multiple edge silicon vias and related systems, methods and devices".

[0003] PRIORITY CLAIM

[0004] This application claims the benefit of the filing date of U.S. patent application serial number 16/577,243, filed on September 20, 2019, entitled "A Plurality of Edge Through-Silicon Vias and Related Systems, Methods, and Devices."

Technical Field

[0005] The present disclosure relates generally to identifying a minimum acceptable through silicon via (TSV) distance from a side edge of a chip stack, and more particularly to identifying a minimum acceptable TSV distance in a memory device.

Background Art

[0006] A three-dimensional integrated circuit can be formed by stacking semiconductor chips having electronic circuit systems formed therein or thereon. These stacked semiconductor chips can be vertically interconnected. For example, the stacked semiconductor chips can be interconnected using TSVs.

Summary of the invention

[0007] In some embodiments, an electronic device includes a chip stack, a first TSV, and a second TSV. The chip stack includes one or more side edges at the perimeter of the chip stack. A through silicon via region (TSV region) of the chip stack is located within a predetermined distance from the one or more side edges. The first TSV is located within the TSV region of the chip stack at a first distance from the one or more side edges. The second TSV is located within the TSV region of the chip stack at a second distance from the one or more side edges. The second distance is shorter than the first distance.

[0008] In some embodiments, a method for determining a minimum acceptable TSV distance from one or more side edges of a chip stack includes performing a conductivity test on a first TSV positioned at a first distance from the one or more side edges of the chip stack; performing the conductivity test on a second TSV positioned at a second distance from the one or more side edges, the second distance being shorter than the first distance; and identifying the minimum acceptable TSV distance from the one or more side edges as the first distance in response to determining that: the first TSV passed the conductivity test, the second TSV failed the conductivity test, and no other TSV farther from the one or more side edges than the first TSV failed the conductivity test.

[0009] In some embodiments, a memory device includes a chip stack, a plurality of TSVs, and a control circuit system. The chip stack includes a logic die and a plurality of core dies stacked on the logic die. The plurality of TSVs are positioned at different distances from one or more side edges of the chip stack. An ordered sequence is associated with the plurality of TSVs from the TSV farthest from the one or more side edges to the TSV closest to the one or more side edges. The control circuit system is located on or in the logic die. The control circuit system is configured to perform a conductive

The invention relates to a method for performing a conductivity test on a plurality of TSVs; identifying a TSV of the plurality of TSVs that is the last consecutive TSV in the ordered sequence to pass the conductivity test without a preceding TSV in the ordered sequence failing the conductivity test; and determining that a minimum acceptable TSV distance from the one or more side edges is the same as a distance from the identified TSV to the one or more side edges.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] While the present disclosure concludes with claims that particularly point out and distinctly claim specific embodiments, the various features and advantages of embodiments within the scope of the present disclosure may be more readily ascertained from the following description when read in conjunction with the accompanying drawings, in which:

[0011] FIG. 1 is a top view of an electronic device according to some embodiments;

[0012] FIG. 2 is a cross-sectional view of a portion of the electronic device of FIG. 1 , the cross section being taken at cross section 2 of FIG. 1 ;

[0013] FIG. 3 is a flow chart illustrating a method of determining a minimum acceptable TSV distance from one or more side edges of a chip stack according to some embodiments;

[0014] FIG. 4 is a cross-sectional view of a chip stack according to some embodiments;

[0015] FIG. 5 is a flow chart illustrating a method of performing a conductivity test according to some embodiments;

[0016] FIG. 6 is a top view of a chip stack according to some embodiments;

[0017] FIG. 7 is a top view of the chip stack of FIG. 6 illustrating an example of signal management according to some embodiments;

FIG. 8 is a schematic diagram of a multiplexing circuit according to some embodiments;

FIG. 9 is a block diagram of an example of a logic die of the electronic device 100 of FIG. 1 ;

[0020] FIG. 10 is a block diagram of a high bandwidth memory HBM+ system according to some embodiments; and

[0021] Figure 11 is a block diagram of a computing system according to some embodiments.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description, and in which specific examples of embodiments of the present disclosure are shown by way of illustration. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other embodiments implemented herein may be utilized, and structural, material and process changes may be made without departing from the scope of the present disclosure.

[0023] The illustrations presented herein are not intended to be actual views of any particular method, system, device or structure, but are merely idealized representations for describing embodiments of the present disclosure. In some cases, similar structures or components in the various drawings may retain the same or similar reference numerals for the convenience of the reader; however, the similarity of the reference numerals does not necessarily mean that the structures or components are identical in size, composition, configuration or any other properties.

[0024] The following description may contain examples that help enable one of ordinary skill in the art to practice the disclosed embodiments. The use of the terms "exemplary," "by way of example," and "for example" means that the relevant description is illustrative, and although the scope of the present disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of the present disclosure to specific components, steps, features, functions, etc.

[0025] It should be readily understood that the components of the embodiments as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following description of the various embodiments is not intended to limit the scope of the present disclosure, but merely to represent the various embodiments. Although various aspects of the embodiments may be presented in the accompanying drawings, unless otherwise specified,

The drawings are not necessarily drawn to scale.

[0026] In addition, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Components, circuits, and functions may be shown in the form of block diagrams to avoid obscuring the present disclosure in unnecessary detail. On the contrary, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. In addition, the logical partitions between block definitions and various blocks are examples of specific embodiments. It is obvious to those of ordinary skill in the art that the present disclosure can be practiced by many other partition solutions. In most cases, details about timing considerations, etc. have been omitted, where such details are unnecessary for obtaining a complete understanding of the present disclosure and such details are within the capabilities of those of ordinary skill in the relevant art.

Those skilled in the art will appreciate that any of a variety of techniques and technologies may be used to represent information and signals. To make representation and description clear, some drawings may show signals as single signals. Those skilled in the art will appreciate that signals may represent a bus of signals, wherein the bus may have various bit widths and the present disclosure may be implemented on any number of data signals comprising a single data signal.

The various illustrative logic blocks, modules and circuits described in conjunction with the embodiments disclosed herein can be implemented or executed with the following: a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component or any combination thereof designed to perform the functions described herein. A general-purpose processor (which may also be referred to as a host processor or simply as a host in this article) may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of a computing device, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general-purpose computer comprising a processor is considered a special-purpose computer, and a general-purpose computer is configured to perform a computing instruction (e.g., software code) related to an embodiment of the present disclosure.

Embodiment can be described according to the process that is depicted as flow chart (flowchart or flow diagram) structure diagram or block diagram.Although flow chart can describe operational action as sequential process, many actions in these actions can be performed in another order, in parallel or substantially simultaneously.In addition, the order of action can be rearranged.Process can correspond to method, thread, function, process, subroutine, subprogram, other structure or its combination.In addition, the method disclosed herein can be implemented with hardware, software or both.If implemented with software, function can be stored in or transferred to computer readable medium as one or more instructions or codes.Computer readable medium includes both computer storage medium and communication medium, and communication medium includes any medium that promotes to transmit computer program from one place to another place.

Unless such restrictions are clearly defined, any reference to an element as "first", "second", etc., used herein does not limit the quantity or order of those elements. On the contrary, these designations can be used as a convenient method to distinguish two or more elements or element instances in this article. Therefore, reference to a first element and a second element does not mean that only two elements can be used or that the first element must precede the second element in some way. In addition, unless otherwise stated, a group of elements may include one or more elements.

The term "substantially" used herein with respect to a given parameter, property or condition means and encompasses the extent to which one of ordinary skill in the art will understand that a given parameter, property or condition is met with a small degree of difference (e.g., a difference within an acceptable tolerance). For example, depending on the particular parameter, property or condition being substantially met, the parameter, property or condition may be at least 90% met, at least 95% met, or even at least 99% met.

The term "chip" as used herein refers to a semiconductor wafer (e.g., a silicon wafer) having

An electronic circuit system formed therein or thereon. Examples of chips include memory logic chips, memory core chips, central processing unit chips, and other electronic device chips.

[0033] In some embodiments, an electronic device includes a chip stack, a first TSV, and a second TSV. The chip stack includes one or more side edges at the perimeter of the chip stack. A through silicon via region (TSV region) of the chip stack is located within a predetermined distance from the one or more side edges. The first TSV is located within the TSV region of the chip stack at a first distance from the one or more side edges. The second TSV is located within the TSV region of the chip stack at a second distance from the one or more side edges. The second distance is shorter than the first distance.

[0034] In some embodiments, a method for determining a minimum acceptable TSV distance from one or more side edges of a chip stack includes performing a conductivity test on a first TSV positioned at a first distance from the one or more side edges of the chip stack; performing the conductivity test on a second TSV positioned at a second distance from the one or more side edges, the second distance being shorter than the first distance; and identifying the minimum acceptable TSV distance from the one or more side edges as the first distance in response to determining that: the first TSV passed the conductivity test, the second TSV failed the conductivity test, and no other TSV farther from the one or more side edges than the first TSV failed the conductivity test.

[0035] In some embodiments, a memory device includes a chip stack, a plurality of TSVs, and a control circuit system. The chip stack includes a logic die and a plurality of core dies stacked on the logic die. The plurality of TSVs are positioned at different distances from one or more side edges of the chip stack. An ordered sequence is associated with the plurality of TSVs from the TSV farthest from the one or more side edges to the TSV closest to the one or more side edges. The control circuit system is located on or in the logic die. The control circuit system is configured to perform a conductivity test on each of the plurality of TSVs; identify a TSV in the plurality of TSVs that is the last consecutive TSV in the ordered sequence that passes the conductivity test when no preceding TSV in the ordered sequence fails the conductivity test; and determine that the minimum acceptable TSV distance from the one or more side edges is the same as the distance from the identified TSV to the one or more side edges.

FIG. 1 is a top view of an electronic device 100 according to some embodiments. The electronic device 100 includes a chip stack 102, the chip stack including one or more side edges 108, a TSV region 106 of the chip stack 102, the one or more side edges being located at the perimeter of the chip stack 102, and the TSV region being located within a predetermined distance D (e.g., 230 micrometers (μm)) from the one or more side edges 108. The TSV region 106 is defined by the side edges 108 and the TSV region boundary 104 shown in FIG. The electronic device 100 also includes TSVs 110 positioned at various distances from the side edges 108.

FIG. 2 is a cross-sectional view of a portion of the electronic device 100 of FIG. 1 , the cross section being taken at the cross section 2 of FIG. 1 . Referring to FIG. 1 and FIG. 2 together, the electronic device 100 includes a plurality of chips. For example, the chip stack 102 includes a chip 214, a chip 216, a chip 218, a chip 220, and a chip 222. It should be noted that the chip stack 102 may include any number of chips greater than or equal to two chips.

[0038] One of the chips in chip stack 102 includes control circuitry 224 therein or thereon. A chip including control circuitry 224 may sometimes be referred to herein as a "control chip". In some embodiments, bottom chip 214 in chip stack 102 may include control circuitry 224 as in the example shown in FIG. 2. In some embodiments, top chip (e.g., chip 222) may include control circuitry 224. As a specific non-limiting example, chip 214 may include a logic die of a memory device, chip 216, chip 218, chip 220, and chip 222 may include memory core chips, and control circuitry 224 may include direct access (DA) control circuitry.

[0039] The chip stack 102 further includes a TSV 110 within the TSV region 106 of the chip stack 102, wherein the TSV includes a TSV

1 and 2 illustrate six TSVs 110, the electronic device 100 may include any number of TSVs greater than or equal to two TSVs. Each of the TSVs 110 is positioned at a different distance from the side edge 108 of the chip stack 102. For example, TSV 202 is positioned at a distance D1 from the side edge 108; TSV 204 is positioned at a distance D2 from the side edge 108; TSV 206 is positioned at a distance D2 from the side edge 108; TSV 208 is positioned at a distance D4 from the side edge 108; TSV 210 is positioned at a distance D5 from the side edge 108; and TSV 212 is positioned at a distance D6 from the side edge 108.

In the case where TSVs 110 are arranged at different distances from side edge 108, control circuit system 224 is configured to perform a conductivity test on each TSV in TSVs 110 and use the results of the conductivity test to identify the minimum acceptable TSV distance from side edge 108. In other words, control circuit system 224 is configured to use the results of the conductivity test to identify the limit of well-formed TSVs that can be formed. If a first conductivity test of a first TSV in TSVs 110 shows no problems, and a second conductivity test of a second TSV in TSVs 110 that is arranged adjacent to the first TSV in TSVs 110 shows an open circuit, then the limit can be determined to be the distance to the first TSV in TSVs 110. In other words, the control circuit system 224 is configured to perform a conductivity test on the TSVs 110 and identify a minimum acceptable TSV distance from the side edge 108 as a first distance corresponding to a first TSV in the TSVs 110 in response to determining that the first TSV in the TSVs 110 passed the conductivity test, a second TSV in the TSVs 110 that is adjacent to the first TSV in the TSVs 110 failed the conductivity test, and no other TSVs 110 that are farther from the side edge than the first TSV in the TSVs 110 failed the conductivity test.

[0041] In other words, the ordered sequence may be associated with TSVs 110 from the TSV farthest from side edge 108 (TSV 202) to the TSV closest to side edge 108 (TSV 212). Control circuit system 224 is configured to perform a conductivity test on each TSV in TSVs 110, identifying the TSV in TSVs 110 as the last consecutive TSV in the ordered sequence that passes the conductivity test without the preceding TSV in the ordered sequence failing the conductivity test. Control circuit system 224 is further configured to determine that the minimum acceptable TSV distance from side edge 108 is the same as the distance from the identified TSV to side edge 108.

As a specific non-limiting example, control circuitry 224 may perform a conductivity test on each of TSVs 110, resulting in no problems in TSVs 202, 204, 206, and 208 and an open circuit in TSVs 210 and 212. In this example, the minimum acceptable TSV distance, or the limit at which a well-formed TSV may be formed, may be determined to be a distance D4 of TSV 208 from side edge 108.

Compared to using a single TSV, using multiple TSVs 110 to determine the minimum acceptable TSV distance allows for evaluating multiple different distances (e.g., D1, D2, D3, D4, D5, and D6) from the side edge 108 instead of a single distance. In the case of using only a single TSV, it can only be determined whether the distance of the single TSV from the side edge 108 is acceptable or unacceptable without providing the granularity provided by multiple TSVs.

FIG. 3 is a flow chart illustrating a method 300 for determining a minimum acceptable TSV distance from one or more side edges of a chip stack according to some embodiments. In operation 302, the method 300 performs a conductivity test on a first TSV located at a first distance from the one or more side edges of the chip stack. Details of an example of a conductivity test are provided below in FIG. 4 and FIG. 5.

In operation 304, the method 300 performs a conductivity test on a second TSV located at a second distance from the one or more side edges. The second distance is shorter than the first distance. In operation 306, the method 300 identifies a minimum acceptable TSV distance from the one or more side edges as a first distance in response to determining that the first TSV passes the conductivity test, the second TSV fails the conductivity test, and no other TSVs farther from the one or more side edges than the first TSV fail the conductivity test.

[0046] FIG. 4 is a cross-sectional view of a chip stack 400 according to some embodiments. The chip stack 400 includes a chip stack

The chip stack 400 includes a control chip 402 at the bottom of the chip stack 400, an end chip 410 at the top of the chip stack 400, and intermediate chips (chip 404, chip 406, and chip 408) located between the control chip 402 and the end chip 410. The chip stack 400 also includes a TSV 4300 that traverses the chip stack 400. The TSV 430 includes a first end 434 close to the control chip 402 and a second end 432 close to the end chip 410.

The control chip 402 includes a control circuit system 412 similar to the control circuit system 224 of FIG. 2 . The control chip 402 also includes a switch 418 and a detection circuit system 428. The switch 418 is operably coupled between the first test voltage potential 414 and the first end 434 of the TSV 430. The control input of the switch 418 is operably coupled to the control circuit system 412 to enable the control circuit system 412 to open and close the switch 418. The switch 418 is configured to selectively operably couple the first end 434 of the TSV 430 to the first test voltage potential 414 and electrically isolate the first end from the first test voltage potential in response to control of the control circuit system 412. The detection circuit system 428 is configured to detect the voltage potential of the first end 434 of the TSV 430. The detection circuit system 428 is operably coupled to the control circuit system 412 to provide the detected voltage potential of the first end 434 of the TSV 430 to the control circuit system 412.

The end chip 410 includes a switch 426 operably coupled between the second test voltage potential 416 and the second end 432 of the TSV 430. The control input of the switch 426 is operably coupled to the control circuit system 412 to enable the control circuit system 412 to open and close the switch 426. The switch 418 is configured to selectively operably couple the second end 432 of the TSV 430 to the second test voltage potential 416 and electrically isolate the second end from the second test voltage potential in response to control of the control circuit system 412.

The intermediate chips, namely, chip 404, chip 406, and chip 408, include switches, switch 420, switch 422, and switch 424, respectively, operably coupled between the second test voltage potential 416 and the TSV 430. The control inputs of switch 420, chip 406, and chip 408 are operably coupled to the control circuit system 412 to enable the control circuit system 412 to open and close the switches 420, switch 422, and switch 424. The switches, namely, switch 420, switch 422, and switch 424, are configured to selectively operably couple the TSV 430 to the second test voltage potential 416 at its respective position along the TSV 430 in response to control of the control circuit system 412 and electrically isolate the TSV 430 from the second test voltage potential.

Spiral TSVs may be used to transmit signals (eg, signals controlling switches 420 , 422 , 424 , and 426 ) between the control chip 402 and other chips (chip 404 , chip 406 , chip 408 , and end chip 410 ) of the chip stack 400 .

[0051] The control circuit system 412 is configured to perform a conductivity test on the second end 432. An example of the conductivity test is discussed below with reference to FIG. 5. Although only one TSV 430 is shown in FIG. 4, it should be understood that the chip stack 400 may include multiple TSVs, such as the electronic device 100 of FIGS. 1 and 2, and similar conductivity tests may be performed on each of the TSVs. [0052] FIG. 5 is a flow chart illustrating a method 500 for performing a conductivity test according to some embodiments. Referring to FIGS. 4 and 5 together, in operation 502, the method 500 precharges the first end 434 of the TSV 430 to a first test voltage potential 414. In some embodiments, precharging the first end 434 of the TSV 430 to the first test voltage potential 414 includes activating a switch 418 operably coupled between the first end 434 of the TSV 430 and the first test voltage potential 414 until the first end 434 of the TSV 430 is charged to the first test voltage potential 414.

In operation 504, the method 500 discharges the second end 432 of the TSV 430 opposite the first end 434 to the second test voltage potential 416. In some embodiments, pre-discharging the second end 432 of the TSV 430 to the second test voltage potential 416 includes activating a switch 426 operably coupled between the second end 432 of the TSV 430 and the second test voltage potential 416 until the second end 432 of the TSV 430 is discharged to the second test voltage potential 416.

[0054] In operation 506, the method 500 detects a voltage potential at the first end 434 of the TSV 430. In some embodiments

4. In operation 504, detecting the voltage potential at the first end 434 of the TSV 430 includes detecting the voltage potential using the detection circuit system 428. If the conductivity of the TSV 430 is good, discharging the second end 432 of the TSV 430 to the second test voltage potential 416 in operation 504 will discharge the entire TSV 430 from the second end 432 to the first end 434 to the second test voltage potential 416. Therefore, if the conductivity of the TSV 430 is good, the voltage potential detected at the first end 434 of the TSV 430 after the discharge in operation 504 will be at the second test voltage potential 416. On the other hand, if the conductivity of the TSV 430 is poor (e.g., an open circuit is not well formed at a connection point between dies or at a point of the TSV 430 itself), the voltage potential detected at the first end 434 of the TSV 430 after the discharge in operation 504 will not be at the second test voltage potential 416. For example, the voltage potential at the first end 434 may remain at the first test voltage potential 414 and end at some other voltage potential between the first test voltage potential 414 and the second test voltage potential 416 .

In operation 508, the method 500 determines that the TSV 430 passes the conductivity test in response to detecting the second test voltage potential 416 at the first end 434 of the TSV 430. In operation 510, the method 500 determines that the TSV 430 fails the conductivity test in response to detecting the first test voltage potential 414 at the first end 434 of the TSV 430.

If it is determined that TSV 430 fails the conductivity test, method 500 may be repeated for each of the middle chips (chip 404, chip 406, and chip 408) in the middle chips of chip stack 400 instead of end chip 410 to identify the location of the failure in TSV 430. For example, if TSV 430 fails at the connection between chip 404 and chip 406, TSV 430 will pass the conductivity test between chip 404 and control chip 402, but TSV 430 will fail the conductivity test between control chip 402 and each of chips 406, chip 408, and end chip 410.

[0057] FIG6 is a top view of a chip stack 600 according to some embodiments. The chip stack 600 may be similar to the electronic device 100 of FIGS. 1 and 2, and similar to the chip stack 400 of FIG. Chip stack 600 includes several sets of edge TSVs (edge TSV 604, edge TSV 620, edge TSV 628, edge TSV 630, edge TSV 632, edge TSV 634, edge TSV 638), VDD/VSS/VPP TSVs (VDD/VSS/VPP TSV 608, VDD/VSS/VPP TSV 610, VDD/VSS/VPP TSV 612, VDD/VSS/VPP TSV 614), and VDD/VSS TSVs 640 including VDD/VSS/VPP edge TSVs (VDD/VSS/VPP edge TSV 606, VDD/VSS/VPP edge TSV 618, VDD/VSS/VPP edge TSV 624, VDD/VSS/VPP edge TSV 622). TSV 640 includes VDD/VSS edge TSV 626 and VDD/VSS edge TSV 616 .

[0058] In the case where various groups of TSVs are arranged at the side edges 602 of the chip stack 600, a restricted area or minimum acceptable TSV distance for placing TSVs at the edge region (e.g., TSV region 106 of FIG. 1) may be determined (e.g., using method 300 of FIG. 3 and method 500 of FIG. 5). In some embodiments, this minimum acceptable TSV distance may be determined globally (e.g., by selecting the largest minimum acceptable TSV distance among the minimum acceptable TSV distances for each edge TSV group in the edge TSV group including edge TSVs, VDD/VSS edge TSVs, and VDD/VSS/VPP edge TSVs). However, the minimum acceptable TSV distance may be determined independently for each of the side edges 602 of the chip stack 600 by placing a test TSV along each of the side edges 602. Therefore, in some embodiments, the minimum acceptable TSV distance may be determined independently for each of the side edges 602 of the chip stack 600. In some embodiments, a minimum acceptable TSV distance may be determined for each set of edge TSVs including edge TSVs, VDD/VSS edge TSVs, and VDD/VSS/VPP edge TSVs.

As a specific non-limiting example, the edge TSV 630 may include TSVs at each of 70 μm, 110 μm, 150 μm, and 190 μm from the side edge 602, as shown in the exploded view 642 of the edge TSV 630. In this example, it can be determined that the TSVs at 110 μm, 150 μm, and 190 μm pass the conductivity test, while the TSV at 70 μm fails the conductivity test. Therefore, 110 μm may be selected as the minimum acceptable TSV distance of the edge TSV 630, the side edge of the chip stack 600 close to the edge TSV 630, or the entire chip stack 600.

[0060] As another specific non-limiting example, the VDD/VSS edge TSV 626 may include two TSVs at each of 70 μm, 110 μm, 150 μm, and 190 μm from the side edge 602, as shown in the exploded view 644 of the VDD/VSS edge TSV 626. In this example, it can be determined that the TSVs at 110 μm, 150 μm, and 190 μm pass the conductivity test, while at least one of the TSVs at 70 μm fails the conductivity test. Therefore, 110 μm may be selected as the minimum acceptable TSV distance of the VDD/VSS edge TSV 626, the side edge of the chip stack 600 close to the VDD/VSS edge TSV 626, or the entire chip stack 600.

[0061] In some embodiments, looking at the power sources that provide the power rail voltages, increasing the number of TSVs for the power rail voltages (e.g., VSS, VDD, VPP, etc.) may reduce the impedance of the chip stack 600. Using the embodiments disclosed herein, it can be determined how many additional TSVs can be placed near the side edge 602 for each set of VDD/VSS/VPP TSVs and VDD/VSS TSVs, thereby reducing impedance compared to previously known systems.

FIG. 7 is a top view of the chip stack 600 of FIG. 6 showing an example of signal management according to some embodiments. In the upper left quarter 706 of the chip stack 600, from the perspective of the chip stack 600 in the top view 6, some signal management for outputting the results of the conductivity test is shown. For example, the chip stack 600 may include (e.g., in a control chip) a local multiplexer (e.g., local multiplexer 702, local multiplexer 704) configured to deliver the results of the conductivity test from each of the TSVs in each TSV group in the TSV group. In FIG. 7, the local multiplexer 702 multiplexes the results from the edge TSV 604 and the edge TSV 620, and the local multiplexer 704 multiplexes the results of the VDD/VSS edge TSV 616 and the output of the local multiplexer 702. Thus, local multiplexer 704 can selectively provide results from edge TSV 620, edge TSV 604, or VDD/VSS edge TSV 616 in response to control applied to these edges (e.g., provided by control circuitry). Although not shown, chip stack 600 can include additional local multiplexers configured to multiplex results from conductivity tests of other edge TSVs (e.g., edge TSV 628, edge TSV 629, and edge TSV 630). 630 , VDD/VSS/VPP edge TSV 624 , VDD/VSS edge TSV 626 , VDD/VSS/VPP edge TSV 622 , edge TSV 632 , edge TSV 634 , edge TSV 636 , edge TSV 638 , VDD/VSS/VPP edge TSV 618 , VDD/VSS/VPP edge TSV 606 ).

[0063] In some embodiments, the results of the conductivity test may be output sequentially (e.g., continuously, one at a time on a single bus). In some embodiments, the results of the conductivity test may be output in parallel (e.g., simultaneously on enough test buses to carry all the results at once). In some embodiments, some intermediate multiplexing may occur. For example, the number of buses that transmit the results of the conductivity test may be less than the number of results of the conductivity test, and each bus in the bus transmits a series of different parts of the results in a row.

8 is a schematic diagram of a multiplexing circuit 800 according to some embodiments. The multiplexing circuit 800 may be used to multiplex TSV conductivity test results (e.g., TSV conductivity test results 816, TSV conductivity test results 818) from edge TSVs (e.g., edge TSVs of FIGS. 6 and 7, VDD/VSS edge TSVs, VDD/VSS/VPP edge TSVs) to a global output 814. The multiplexing circuit 800 includes local multiplexers (e.g., local multiplexer 804, local multiplexer 806, local multiplexer 808, local multiplexer 810), which are configured to multiplex TSV conductivity test results 816 and TSV conductivity test results 818 to local outputs 812, some of which can be analog (e.g., to indicate the detected voltage potential on the TSV), and some of which can be digital (e.g., to indicate whether the corresponding TSV passes or fails the conductivity test). The multiplexing circuit 800 also includes a global multiplexer 802, which is configured to multiplex the local outputs 812 into the global output 814.

Each of the multiplexers (global multiplexer 802, local multiplexer 804, local multiplexer 806, local multiplexer 808, local multiplexer 810) is configured to respond to a selection signal SEL.

One of the multiplexer inputs is selectively output. Thus, depending on the value of the select signal SEL, any one of the TSV conductivity test results 816 or the TSV conductivity test results 818 may be provided at the global output 814. The control circuit system (e.g., the control circuit system 224, the control circuit system 412) may be configured to provide the select signal SEL and receive the global output 814.

In some embodiments, local multiplexer 804, local multiplexer 806, local multiplexer 808, and/or local multiplexer 810 may be configured to receive signals not related to the conductivity test (e.g., signals related to other types of tests). Thus, multiplexing circuit 800 may be configured to selectively output any of TSV conductivity test results 816 or TSV conductivity test results 818 or other signals related to other tests to global output 814.

9 is a block diagram of an example of a logic die 900 of the electronic device 100 of FIG. 1. The logic die 900 includes an AWORD/DWORD interface 904, a P1500 interface 906, and a direct access interface, DA interface 908. The logic die 900 also includes a command address data control circuit 902 operatively coupled to the AWORD/DWORD interface 904, a P1500 control circuit 916 operatively coupled to the P1500 interface 906 through a multiplexer 910, and a DA control circuit 914 operatively coupled to the DA interface 908. The command address data control circuit 902 is configured to control the operation of the AWORD/DWORD interface 904, the P1500 control circuit 916 is configured to control the operation of the P1500 interface 906, and the DA control circuit 914 is configured to control the operation of the DA interface 908. Each of the command address data control circuit 902, the P1500 control circuit 916, and the DA control circuit 914 is configured to communicate directly with the DRAM die (e.g., the DRAM die 1006 of FIG. 10 ). The P1500 control circuit 916 and the DA control circuit 914 are also configured to communicate indirectly with the DRAM die (e.g., the DRAM die 1006 of FIG. 10 ) through the built-in self-test BIST 912. In addition, The P1500 control circuit 916 and the DA control circuit 914 are configured to perform hybrid communication with a DRAM die (eg, DRAM die 1006 of FIG. 10 ), wherein the hybrid communication includes both direct and indirect communication (through BIST 912 ) with the DRAM die (eg, DRAM die 1006 of FIG. 10 ).

[0068] The AWORD/DWORD interface 904 is an interface for providing address/command (AWORD) and data (DWORD) for normal operation of the high bandwidth memory (HBM 1002 of FIG. 10). By way of non-limiting example, the AWORD/DWORD interface 904 is configured to be used as an interface for conducting operation signals (e.g., commands, address signals, DQ input/output data signals, etc.). The AWORD/DWORD interface 904 includes an AWORD/DWORD port 918.

[0069] The P1500 interface 906 is an interface for test operations specified by JEDEC. The P1500 interface 906 includes a P1500 port 922. The number of P1500 ports 922 specified by JEDEC is fifteen P1500 ports 922. The P1500 test interface is a test interface between an embedded core and a system chip that can be used to test core interoperability. The functions and circuits (e.g., P1500 control circuit 916) of the P1500 interface between various different HBMs can be relatively similar because JEDEC closely regulates the P1500 interface 906.

DA interface 908 is an interface for other operations (e.g., primarily test operations). For other test operations, DA interface 908 is not defined (manufacturer/user specific). Some of these test operations may include method 300 of FIG. 3 , method 500 of FIG. 5 , other test operations discussed herein, or any combination thereof. Thus, DA control circuit 914 may implement control circuit systems discussed herein (e.g., control circuit systems 224, control circuit systems 412).

[0071] The basic role of the DA interface 908 is to verify the function of the HBM (e.g., the electronic device 100 of FIG. 1 ) without using other interfaces (e.g., the AWORD/DWORD interface 904 or the P1500 interface 906). The DA interface 908 includes DA ports 920. At least some of the DA ports 920 have test pads 924. The number of DA ports 920 is sixty DA ports 920. The functions and circuits (e.g., the DA control circuit 914) of the DA interface 908 may be relatively different from one HBM to another because the functions and circuits of the DA interface 908 are not as closely regulated as the functions and circuits of the P1500 interface 906. For example, JEDEC defines the DA port 920 as follows:

The number and placement of the uBumps of port 920. However, the port assignment and usage of DA interface 908 may vary from one HBM to another.

Various arrows indicating signal directions are shown in FIG9 . It should be noted that address/command signals and corresponding test signals are driven in one direction from outside the logic die 900 to the DRAM die 1006 ( FIG10 ). On the other hand, data signals and corresponding test signals are driven in two directions (i.e., driven to and from the DRAM die 1006 of FIG10 ).

10 is a block diagram of a high bandwidth memory HBM+ system 1000 according to some embodiments. The HBM+ system 1000 includes an HBM 1002 and a processing unit 1004 (e.g., a central processing unit or CPU, a graphics processing unit or GPU, an accelerated processing unit or APU, etc.) operably coupled to the HBM 1002. The HBM 1002 includes a dynamic random access memory die, a DRAM die 1006, and a logic die 1008. The logic die 1008 includes a processor 1010 and a near memory controller NMC 1012. The processing unit 1004 includes a far memory controller FMC 1014.

[0074] The NMC 1012 and the FMC 1014 are configured to function as a memory controller master._OThe FMC 1014 includes a disconnected HBM memory controller, and the NMC 1012 includes an on-HBM memory controller located on a logic die 1008 of the HBM 1002. The logic die 1008 may be a control chip (e.g., the control chip 402 of FIG. 4). By way of non-limiting example, the logic die 1008 may correspond to a bottom layer of the 3D stacked memory as the HBM 1002, while the DRAM die 1006 may correspond to one of the upper layers of the HBM 1002. The logic die 1008 may control the DRAM die 1006 using the NMC 1012, which may be instructed by the processor 1010 to control the DRAM die 1006. It should be noted that one or both of the NMC 1012 and the FMC 1014 may be represented by a general memory controller. The logic die 1008 may include the logic die 900 of FIG. 9.

11 is a block diagram of a computing system 1100 according to some embodiments. The computing system 1100 includes one or more processors 1104, one or more non-volatile data storage devices 1110, one or more input devices 1106, and one or more output devices 1108, the one or more processors being operably coupled to one or more memory devices 1102. In some embodiments, the computing system 1100 includes a personal computer (PC), such as a desktop computer, a laptop computer, a tablet computer, a mobile computer (e.g., a smart phone, a personal digital assistant (PDA)), etc., a network server, or other computer devices.

[0076] In some embodiments, the one or more processors 1104 may include a central processing unit (CPU) or other processors configured to control the computing system 1100. In some embodiments, the one or more memory devices 1102 include random access memory (RAM), such as volatile data storage (e.g., dynamic RAM (DRAM), static RAM (SRAM), etc.). In some embodiments, the one or more non-volatile data storage devices 1110 include a hard disk drive, a solid state drive, a flash memory, an erasable programmable read-only memory (EPROM), other non-volatile data storage devices, or any combination thereof. In some embodiments, the one or more input devices 1106 include a keyboard 1112, a pointing device 1114 (e.g., a mouse, a trackpad, etc.), a microphone 1116, a keypad 1118, a scanner 1120, a camera 1122, other input devices, or any combination thereof. In some embodiments, the one or more output devices 1108 include an electronic display 1124, a speaker 1126, a printer 1128, other output devices, or any combination thereof.

[0077] In some embodiments, the one or more memory devices 1102 include an HBM system such as the HBM+ system 1000 of FIG. 10. In some embodiments, the one or more memory devices 1102 include a chip stack (e.g., the chip stack 102 of FIG. 1, the chip stack 400 of FIG. 4, the chip stack 600 of FIG. 6), the chip stack including the logic die 900 of FIG. 9. [0078] As used in the present disclosure, the term "module" or "component" may refer to a specific hardware implementation that is configured to perform the actions of a module or component and/or software object or to execute a software routine that may be stored on or executed by general hardware of a computing system. In some embodiments, the different components, modules,

Engines and services can be implemented as objects or processes that execute on a computing system (e.g., as separate threads). Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and/or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are possible and contemplated.

[0079] As used in the present disclosure, the term "combination" relating to a plurality of elements may include any subcombination of a combination of all elements or a variety of different subcombinations of some of the elements. For example, the phrase "A, B, C, D, or a combination thereof" may refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0080] The terms used in this disclosure and especially in the appended claims (e.g., the bodies of the appended claims) are generally intended to be "open" terms (e.g., the term "including" should be understood as "including but not limited to," the term "having" should be understood as "having at least," the term "includes" should be understood as "including but not limited to," etc.).

[0081] In addition, if a specific number of introduced claim statements is intended, such intent will be explicitly stated in the claim, and in the absence of such a statement, such intent is absent. For example, to aid understanding, the following appended claims may contain introductory phrases "at least one" and "one or more" to introduce claim statements. However, the use of such phrases should not be interpreted as implying that a claim statement introduced by the indefinite article "a, an" will limit any particular claim containing such introduced claim statements to an embodiment containing only one such statement, even when the same claim contains the introductory phrases "one or more" or "at least one" and indefinite articles such as "one, a kind" (for example, "a" and/or "a kind" should be interpreted as meaning "at least one" or "one or more"); the same is true for the use of definite articles used to introduce claim statements.

[0082] In addition, even if a specific number of an introduced claim statement is explicitly stated, one skilled in the art will recognize that such a statement should be interpreted to mean at least the stated number (e.g., an unmodified statement of "two statements" without other modifiers means at least two statements, or two or more statements). Moreover, in those cases where a convention similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, such construction is generally intended to include only A, only B, only C, A and B, A and C, B and C, or A, B and C, etc.

[0083] Further, any separating word or phrase presenting two or more alternative terms, whether in the claims or drawings, should be understood to include the possibility of one of the terms, any one of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "-B" or "A and B".

Although the disclosure has been described herein with respect to some of the embodiments shown, it will be appreciated and understood by those of ordinary skill in the art that the present invention is not limited thereto. On the contrary, without departing from the scope of the present invention as claimed hereinafter and its legal equivalents, many additions, deletions and modifications may be made to the embodiments shown and described. In addition, features from one embodiment may be combined with features of another embodiment while still being encompassed within the scope of the present invention as contemplated by the inventor.