Memory device and operating method thereof

Storage device and its operation method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the rights and interests of Korean Patent Application No. 10 2020-0059971 filed at the Korean Intellectual Property Office on May 19, 2020, the entire disclosure of which is incorporated herein by reference.

Technical field

[0003] The inventive concept relates to a storage device, and more specifically, to a storage device including an interface circuit that performs data conversion according to an endian format.

Background technique

[0004] Applications such as higher performance and/or graphics algorithms are data-intensive and/or computationally intensive. Machine learning applications such as neural networks will include a large number of operations, which have a large number of computing and storage requirements. Therefore, machine learning applications require computing systems with large-scale computing and storage capabilities to train or learn different data sets more accurately. In order to perform certain computing operations of the computing system as internal processing, processor in-memory (PIM) type processor devices are being developed. Through the internal processing of the storage device, the computing operation load of the computing system can be reduced.

[0005] High-bandwidth memory (HBM) is a high-performance random access memory (RAM) interface for 3D stacked dynamic random access memory (DRAM). HBM can be used for memory-centric computationally intensive neural networks or other artificial intelligence (AI). This is due to the increase in the size of the training data set, the increase in model parameters, and the increase in intermediate processing results. In addition, the HBM is configured to perform the PIM function, and may include processing elements (PE) that perform internal processing (for example, arithmetic calculations such as addition and multiplication and logical calculations such as exclusive OR (XOR)).

[0006] The HBM can send and receive data through a data bus based on a command from a host using the HBM. The data bus may include, for example, a 64-bit bus. On the data bus, bytes are regarded as atomic units, and the data bus may be divided into byte-wide lanes. However, the endianness of the bus used by the data bus in the host may be different from the endianness of the bus used by the HBM. For example, the host can use a big-endian bus, and the HBM can use a little-endian bus.

Summary of the invention

[0007] The inventive concept provides data conversion between different bus endian formats for data immutability.

[0008] The inventive concept provides a storage device including an interface circuit for data conversion according to different endian formats.

[0009] According to an aspect of the inventive concept, there is provided a storage device, including: a storage bank; a processing element (PE), the PE coupled to the storage bank and configured to perform calculation processing; a serializer /Deserializer (SERDES) area, the SERDES area includes SERDES, the SERDES is configured to perform an operation of parallelizing a serial data stream received from a host device outside the storage device, and from the The operation of serializing the parallel data stream output by the memory bank or the PE; and an interface circuit including a data transmission path related to the memory bank, the PE, and the SERDES, and is configured such that The storage device can be based on the data set according to the endian format of the host device

The control signal performs data conversion in the data transmission path.

[0010] According to another aspect of the inventive concept, there is provided a storage device including: a memory bank; a serializer/deserializer (SERDES) area, the SERDES area includes SERDES, the SERDES is configured to perform The operation of parallelizing the serial data stream received from the host device outside the storage device, and the operation of serializing the parallel data stream output from the memory bank; and an interface circuit, the interface circuit including and The storage body and the data transmission path related to the SERDES, the interface circuit is coupled to the SERDES area, and is configured to enable the storage device to be based on a control set according to the endian format of the host device The signal performs data conversion in the data transmission path.

[0011] According to another aspect of the inventive concept, there is provided a method of operating a storage device including an interface circuit configured to adjust the endian format between a host device and the storage device, so The method includes: receiving a serial data stream in a first endian format from the host device; parallelizing the serial data stream into first data; and converting the serial data stream into a first data stream based on a control signal The second endian format of the storage device, or the parallelized first data is converted into the second endian format, and the conversion is performed by the interface circuit.

Description of the drawings

[0012] An example embodiment of the inventive concept will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: [0013] FIG. 1 is a block diagram illustrating data conversion according to an example embodiment of the inventive concept;

[0014] FIG. 2 is a block diagram of a system with data conversion according to an example embodiment of the inventive concept;

[0015] FIG. 3 is a block diagram illustrating an interface circuit according to an example embodiment of the inventive concept;

[0016] FIG. 4 is a circuit diagram that implements the data converter (data to data (D2D) multiplexer (MUX)) of FIG. 3;

[0017] FIGS. 5A to 5c are circuit diagrams for implementing the D2D MUX of FIG. 3;

[0018] FIG. 6 is a diagram illustrating a storage device according to an example embodiment of the inventive concept;

[0019] FIG. 7 is a diagram showing the arrangement of D2D MUX in a storage device according to an example embodiment of the inventive concept; [0020] FIG. 8 is a diagram showing the arrangement of a D2D MUX in a storage device according to an example embodiment of the inventive concept [0021] FIG. 9 is a diagram showing the arrangement of D2D MUX in a storage device according to an example embodiment of the inventive concept; [0022] FIG. 10 is a diagram showing the arrangement according to the inventive concept A diagram of the arrangement of the D2D MUX in the storage device of the exemplary embodiment;

[0023] FIG. 11 is a diagram illustrating the arrangement of a D2D MUX in a storage device according to an example embodiment of the inventive concept;

[0024] FIG. 12 is a diagram illustrating the arrangement of a D2D MUX in a storage device according to an example embodiment of the inventive concept; and

[0025] FIG. 13 is a diagram illustrating the operation of the D2D MUX of FIG. 12.

Detailed ways

[0026] FIG. 1 is a block diagram illustrating data conversion according to an example embodiment of the inventive concept.

[0027] Referring to FIG. 1, two types of bus endianness including a big-endian bus 110 and a little-endian bus 120 are shown. For example, suppose that 64-bit data is sent through the data bus 230 (Figure 2). For simplicity of description, FIG. 1 shows a configuration of 64-bit (ie, 8 bytes) data, but it is not limited to this, and other configurations are possible. The 64-bit data corresponds to the size of the data sent from the host device (or the CPU 210), which will be described with reference to FIGS. 2 and 7. 8 bytes of data

The quotes can be hexadecimal codes 0x0 to 0x7 respectively.

[0028] In the data bus structure, the first byte of 0x0 index can be placed on the rightmost byte or digit, and the 8th byte of 0x7 index can be placed on the leftmost byte or digit. For ease of description, the following example is described: each byte in the 8-byte data may include 1 byte with 0x0A code point or 1 byte with 0x0B code point, that is, with 0x0A code point, Any one of the 2 bytes of the 0x0B code bit. In some example embodiments of the inventive concept, 2 bytes will be described as the data conversion unit 130.

[0029] In the big-endian bus 110, 2 bytes with 0x0A code points and 0x0B code points are placed starting from the digits on the right side of the data conversion unit 130, that is, the 0x0A code points are placed in the 0x0 index, and the 0x0B code is placed The bits are placed in the 0x1 index. Similarly, the 0x0A code bit is placed in the 0x2 index, and the 0x0B code bit is placed in the 0x3 index. The 0x0A code bit is placed in the 0x4 index, the 0x0B code bit is placed in the 0x5 index, the 0x0A code bit is placed in the 0x6 index, and the 0x0B code bit is placed in the 0x7 index.

[0030] In the little-endian bus 120, 2 bytes with 0x0A code points and 0x0B code points are placed starting from the digit on the left of the data conversion unit 130. For example, the 0x0A code point is placed in the 0x1 index, and the 0x0B code is placed The bits are placed in the 0x0 index. Similarly, the 0x0A code point is placed in the 0x3 index, and the 0x0B code point is placed in the 0x2 index. The 0x0A code bit is placed in the 0x5 index, the 0x0B code bit is placed in the 0x4 index, the 0x0A code bit is placed in the 0x7 index, and the 0x0B code bit is placed in the 0x6 index.

[0031] In an environment where the big-endian bus 110 and the little-endian bus 120 are mixed, data conversion 140 is required to make the endianness consistent. When the host uses the big-endian bus 110 for processing and the storage device connected to the processor uses the little-endian bus 120, the storage device performs data conversion 140 in a software manner. This is because the processor processes data in its own big-endian bus 110 format. When the storage device performs data conversion 140, a series of shifts and exchanges are required. Such software operations consume a large amount of storage space and time, which will cause the performance of the storage device to decrease. Therefore, when the storage device can use hardware to perform the data conversion 140 and there may be such a device (hardware), it will be beneficial to improve the performance of the storage device.

[0032] FIG. 2 is a block diagram of a system 200 with data conversion according to an example embodiment of the inventive concept.

[0033] Referring to FIG. 2, in the system 200, the host device 210 and the storage device 220 can communicate with each other using various protocols, for example, such as Peripheral Component Interconnect Rapid (PCI-E), Advanced Technology Attachment (ATA), serial The interface protocol of ATA (SATA), Parallel ATA (PATA) or Serial Connected SCSI (SAS). In addition, various other interface protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE), etc. can be applied to the host device 210 and the storage device 220 Agreement between.

[0034] The data transmission between the host device 210 and the storage device 220 is performed in the form of data signals (ie, data bits), and the data signals are driven in a parallel channel 240 of the data bus 230. The host device 210 may generate data bits and send the data bits to the storage device 220 through the data bus 230. The host device 210 is a functional block that performs computer operations in the system 200, and may correspond to a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), or an application processor (AP). Herein, the host device 210 may be referred to as a CPU 210.

[0035] The CPU 210 may be configured to execute instructions or software executable by one or more machines, firmware, or various combinations thereof. The CPU 210 may include any number of processor cores. For example, the CPU 210 may include a single core or multiple cores such as dual cores, quad cores, six cores, and so on. Although the system 200 including one CPU 210 is shown in FIG. 2, according to some example embodiments, the system 200 may include a plurality of CPUs.

[0036] The data bus 230 may be a bidirectional data bus, and in some example embodiments, the storage device 220 may

The data bits are generated and sent to the host device 200 through the data bus 230. The data bus 230 may include parallel conductive lines called channels 240, the ends of which are coupled to the legs of the host device 210 and the storage device 220, respectively. The term "pin" broadly refers to an electrical interconnection with an integrated circuit, and may include, for example, a pad or another electrical contact on the integrated circuit. The data bus 230 may include any number of channels 240, and may include, for example, 2, 4, 8, 16, 32, or 64 channels.

[0037] The channel 240 may configure an independent interface between the CPU 210 and the storage device 220. For example, when the storage device 220 is implemented in HBM, each of the DRAM dies 621 to 624 (FIG. 6) stacked in the HBM may include 2 channels, and each channel (for example, CH6 in FIG. 6) may include 2 dummy channels (for example, CH6a and CH6b in FIG. 6), and each dummy channel can include 64 wires. Therefore, each of the HBM DRAM dies 621 to 624 may include 4 dummy channels and include 256 wires. The data bus 230 may be coupled to the eight channels 240 through the organization associated with the HBM architecture.

[0038] The expressions "connected" and/or "coupled" and their derivatives may be used to describe some examples. These terms are not necessarily synonyms for each other. For example, a description using the terms "connected" and/or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. In addition, the terms "connected" and/or "coupled" can also mean that two or more elements do not directly contact each other, but still cooperate or interact with each other.

[0039] The data bus 230 may be coupled to transmit data bits to the interface circuit 222, which is one of the hardware components of the storage device 220. The interface circuit 222 may receive data from the data bus 230, and perform data conversion on the received data according to the big-endian format of the host device 210. Various data paths may be included in the storage device 220, and the interface circuit 222 may perform data conversion based on a control signal BE_SEL in a predetermined or desired path.

[0040] The control signal BE_SEL may be provided in the mode register set (MRS) 224 of the storage device 220. When an MRS command is issued from the CPU 210, the MRS 224 can be programmed with the appropriate bit value of the address bus provided to the storage interface. In the MRS 224, multiple operation options, various functions, features, and modes of the storage device 220 can be set. In the inventive concept, the MRS 224 may include a special control signal BE_SEL, whether its setting is changed to the big endian format. For example, when it is instructed to change to the big endian format, the MRS 224 may provide a logic high level control signal BE_SEL.

[0041] According to some example embodiments, a non-volatile storage device (for example, an anti-fuse) in the storage device 220 may be used to provide the control signal BE_SEL. An anti-fuse is a resistance fuse device: the resistance fuse device has the opposite resistance characteristics of the fuse device, and has a higher resistance value in the unprogrammed state, and has a higher resistance value in the programmed state. Low resistance value. For example, when programming the anti-fuse, the control signal BE_SEL can indicate a change to the big-endian format.

[0042] FIG. 3 is a block diagram illustrating an interface circuit 222 according to some example embodiments of the inventive concept.

2 and 3, the interface circuit 222 may include a data converter 330 connected between the first data bus 310 and the second data bus 320. The first data bus 310 refers to the data line D_BUS[15:0] coupled to the CPU 210, and the second data bus 320 refers to the data line DQ[0:15] coupled to the storage device 220.

[0044] According to the control signals BE_SEL and BE_SELB, the data converter 330 selectively reconfigures the endian format of the second data bus 320 according to the specific endian format of the first data bus 310, and performs transmission. In response to the control signals BE_SEL and BE_SELB, the data converter 330 can reconfigure the endian format of the second data bus 320 to the big-endian format when the first data bus 310 is in the big-endian format, and when the first data bus 310 is in the big-endian format, When the data bus 310 is in the little-endian format, the endian format of the second data bus 320 is reconfigured to the little-endian format.

[0045] The control signal BE_SEL can determine whether the data converter 330 (reconfigures the endian format of the second data bus 320) to the big endian format. The control signal BE_SELB is the logic level of the control signal BE_SEL

Opposite signal.

[0046] The first data bus 310 may include lines D_BUS0 to D_BUS7 for transmitting the first byte 311 and lines D_BUS8 to D_BUS15 for transmitting the second byte 312, and the second data bus 320 may include lines DQ0 to D_BUS15 for transmitting the first byte 321. The DQ7 line and the DQ8 to DQ15 lines that transmit the second byte 322. When the first data bus 310 is in the little-endian format and the control signal BE_SEL does not indicate the reconfiguration to the big-endian format, the data converter 330 can transfer the first byte 311 of the first data bus 310 to the second data The first byte 321 of the bus 320 and the second byte 312 of the first data bus 310 are transferred to the second byte 322 of the second data bus 320. In addition, the data converter 330 may transfer the first byte 321 of the second data bus 320 to the first byte 311 of the first data bus 310, and transfer the second byte 322 of the second data bus 320 to the first byte 311 of the first data bus 310. The second byte 312 of the data bus 310.

[0047] When the first data bus 310 is in the big-endian format and the control signal BE_SEL indicates to be reconfigured to the big-endian format, the data converter 330 may reconfigure and reconfigure the first byte 311 of the first data bus 310. The second byte 322 is transmitted to the second data bus 320, and the second byte 312 of the first data bus 310 can be reconfigured and transmitted to the first byte 321 of the second data bus 320. In addition, the data converter 330 can reconfigure and transfer the first byte 321 of the second data bus 320 to the second byte 312 of the first data bus 310, and can transfer the second byte 322 of the second data bus 320 It is reconfigured and transmitted to the first byte 311 of the first data bus 310.

[0048] The data converter 330 performs the function of selectively exchanging the first byte 311 and the second byte 312 of the first data bus 310 and the first byte 321 and the second byte 322 of the second data bus 320, This function can actually be physically implemented in the form of a data-to-data multiplexer (D2D MUX). Hereinafter, for convenience of description, the data converter 330 will be referred to as D2D MUX, and will be described as D2D MUX 330. In addition, suppose that the first data bus 310 transmits data in big-endian format, and the second data bus 320 transmits data in little-endian format, and the logic high of the control signal BE_SEL controls the D2D MUX 330 to be reconfigured as big-endian. Order format.

[0049] FIG. 4 is a circuit diagram that implements the D2D MUX 330 of FIG. 3.

[0050] Referring to FIGS. 3 and 4, the D2D MUX 330 may include 16 transmission gate circuits 40. The transmission gate circuit 40 is divided into one bit line of the first byte 311 of the first data bus 310, one bit line of the second byte 312 of the first data bus 310, and the first word of the second data bus 320. One bit line of section 321 or second byte 322. For example, the transmission gate circuit 40 may include a first transmission gate 41 connected between the D_BUS0 line and the DQ0 line, and a second transmission gate 42 connected between the D_BUS8 line and the DQ0 line. In response to the logic low level of the control signal BE_SEL, the first transmission gate 41 connects the D_BUS0 line to the UDQ0 line, and in response to the logic high level of the control signal BE_SEL, the second transmission gate 42 connects the D_BUS8 line to the DQ0 line. The other transmission gate circuits 40 operate similarly.

[0051] Therefore, when the control signal BE_SEL is at a logic low level, the D2D MUX 330 transfers the first byte 311 of the first data bus 310 to the first byte 321 of the second data bus 320, and transfers the first data bus 310 to the first byte 321 of the second data bus 320. The second byte 312 of the second data bus 320 is transferred to the second byte 322 of the second data bus 320, the first byte 321 of the second data bus 320 is transferred to the first byte 311 of the first data bus 310, and the second The second byte 322 of the data bus 320 is transferred to the second byte 312 of the first data bus 310. When the control signal BIG_SEL is at a logic high level, the D2D MUX 330 reconfigures and transmits the second byte 312 of the first data bus 310 to the first byte 321 of the second data bus 320, and transfers the second byte 312 of the first data bus 310 to the first byte 321 of the second data bus 320. One byte 311 is reconfigured and transmitted to the second byte 322 of the second data bus 320, and the second byte 322 of the second data bus 320 is reconfigured and transmitted to the first byte 311 of the first data bus 310, And the first byte 321 of the second data bus 320 is reconfigured and transmitted to the second byte 312 of the first data bus 310.

[0052] FIGS. 5A to 5c are circuit diagrams for implementing the D2D MUX 330 of FIG. 3. The D2D MUX330 of FIG. 5A may include FIG. 5B

And Figure 5C.

[0053] Referring to FIGS. 3 and 5B, the D2D MUX 330 may include 16 first multiplexers 51. The first multiplexer 51 is divided into one bit line of the first byte 311 of the first data bus 310, one bit line of the second byte 312 of the first data bus 310, and the second data bus 320, respectively. One bit line of the first byte 321 or the second byte 322. For example, the first multiplexer 51 is connected between the D_BUS0 line, the D_BUS8 line, and the DQ0 line to transmit the bit of the D_BUS0 line to the DQ0 line in response to the logic low level of the control signal BE_SEL, and respond to the control signal The logic high of BE_SEL transfers the bits of the D_BUS8 line to the DQ0 line. The other first multiplexers 51 operate similarly.

[0054] Correspondingly, when the control signal BE_SEL is at a logic low level, the D2D MUX 330 transfers the first byte 311 of the first data bus 310 to the first byte 321 of the second data bus 320, and transfers the first data The second byte 312 of the bus 310 is transferred to the second byte 322 of the second data bus 320. When the control signal BE_SEL is at a logic high level, the D2D MUX 330 reconfigures and transmits the second byte 312 of the first data bus 310 to the second byte 321 of the second data bus 320, and transfers the The first byte 311 is reconfigured and transferred to the second byte 322 of the second data bus 320.

[0055] Referring to FIGS. 3 and 5C, the D2D MUX 330 may include 16 second multiplexers 52. The second multiplexer 52 is divided into one bit line of the first byte 321 of the second data bus 320, one bit line of the second byte 322 of the second data bus 320, and the first data bus 310. One bit line of the first byte 311 or the second byte 312. For example, the second multiplexer 52 is connected between the DQ0 line, the DQ8 line, and the D_BUS0 line, and in response to the logic low level of the control signal BE_SEL, transmits the bit of the DQ0 line to the D_BUS0 line, and responds to the control signal BE_SEL The logic high level of the DQ8 line will be transferred to the D_BUS0 line. The other second multiplexers 52 operate similarly.

[0056] Correspondingly, when the control signal BE_SEL is at a logic low level, the D2D MUX 330 transfers the first byte 321 of the second data bus 320 to the first byte 311 of the first data bus 310, and transfers the second data The second byte 322 of the bus 320 is transferred to the second byte 312 of the first data bus 310. When the control signal BE_SEL is at a logic high level, the D2D MUX 330 reconfigures and transmits the second byte 322 of the second data bus 320 to the first byte 311 of the first data bus 310, and transfers the second byte 322 of the second data bus 320 The first byte 321 is reconfigured and transferred to the second byte 322 of the second data bus 320.

[0057] FIG. 6 is a diagram illustrating a storage device 220 according to some example embodiments of the inventive concept.

2 and 6, the storage device 220 may be an HBM, which includes a plurality of channels CH1 to CH8 having interfaces independent of each other. The memory device 220 may include a plurality of dies including a buffer die 610 and at least one DRAM die 620 stacked on the buffer die 610. For example, the first DRAM die 621 may include a first channel CH1 and a third channel CH3, the second DRAM die 622 may include a second channel CH2 and a fourth channel CH4, and the third DRAM die 623 may include a fifth channel CH5. As with the seventh channel CH7, the fourth DRAM die 624 may include the sixth channel CH6 and the eighth channel CH8.

[0059] The buffer die 610 may communicate with the CPU 210 through conductive elements (for example, bumps or solder balls) formed on the outer surface of the storage device 220. The buffer die 610 may receive commands, addresses, and data from the CPU 210 and provide the received commands, addresses, and data to at least one channel of the DRAM die 620. In addition, the buffer die 610 may provide data output from the channel of at least one DRAM die 620 to the CPU 210.

[0060] The storage device 220 may include a plurality of through silicon vias (TSV) 630 penetrating the first to fourth DRAM dies 621 to 624. When the channels CH1 to CH8 all have a 128-bit bandwidth, TSV 630 can include a 1024-bit data input and output configuration. Each of the channels CH1 to CH8 can be set separately from left to right. For example, in the fourth DRAM die 624, the sixth channel CH6 is divided into dummy channels CH6a and CH6b, and the eighth channel CH8 can be divided into dummy channels. Channels CH8a and CH8b. TSV 630 can

It can be set between the dummy channels CH6a and CH6b of the sixth channel CH6 and between the dummy channels CH8a and CH8b of the eighth channel CH8.

[0061] The buffer die 610 may include a TSV area 612, a serializer/deserializer (SERDES) area 614, and/or an HBM physical layer interface (ie, an HBM PHY area 616). The TSV area 612 is formed therein for and The area of TSV 630 where at least one DRAM die 620 communicates.

[0062] The SERDES area 614 is an area where the SERDES interface of the Joint Electronic Equipment Engineering Committee (JEDEC) standard is provided as the processing throughput of the CPU 210 increases and the demand for memory bandwidth increases. The SERDES area 614 may include a serializer/deserializer (SERDES). The SERDES may include a SERDES transmitter part, a SERDES receiver part, and/or a controller part. The SERDES transmitter part may include a parallel-serial circuit and a transmitter, which can receive parallel data streams and serialize the received parallel data streams. The SERDES receiver part may include a receiver amplifier, an equalizer, a clock and data recovery (CDR) circuit, and a serial-parallel circuit, which receives the serial data stream and parallelizes the received serial data stream. The controller part may include registers such as an error detection circuit, an error correction circuit, and a first in first out (FIFO). [0063] The HBM PHY area 616 may include a physical or electrical layer and a logical layer, which are provided for signals, frequencies, timing, driving, detailed operating parameters, and functions required for effective communication between the CPU 210 and the storage device 220. The HBM PHY area 616 can perform memory interface connections, such as selecting rows and columns corresponding to the memory cells, writing data to the memory cells, or reading and writing data. HBM The PHY area 616 may support the features of the HBM protocol of the JEDEC standard. For example, the HBM PHY area 616 can perform 64-bit data communication with the CPU 210.

[0064] FIG. 7 is a diagram illustrating the arrangement of the D2D MUX 330a in the storage device 220a according to some example embodiments of the inventive concept. Hereinafter, the subscripts attached to the reference numerals (for example, a in 220a and a in 330a) are used to distinguish a plurality of circuits having the same function.

6 and 7, in the storage device 220a, the D2D MUX 330a may be disposed between the HBM PHY area 616 and the SERDES area 614. The HBM PHY area 616 may receive 64-bit input data from the CPU 210 and divide the received 64-bit input data into byte widths to transmit the divided 64-bit input data to the D2D MUX 330a. The D2D MUX 330a may respond to the control signal BE_SEL , Based on data transfer or conversion operation, perform data conversion on 64-bit input data in 2-byte units, and output 64-bit output data. The D2D MUX 330a may be implemented as the D2D MUX 330 of FIGS. 4 and 5A to 5c described above, and the 64-bit input data may be divided into 8 bytes and carried on the first data bus 310, and 64-bit The output data may be divided into 8 bytes and carried on the second data bus 320.

[0066] The D2D MUX 330a can reconfigure and transmit the first byte of the first data bus 310 to the second byte of the second data bus 320 according to the logic high control signal BE_SEL, and transfer the first data bus 310 The second byte of is reconfigured and transferred to the first byte of the second data bus 320, similar to the data conversion 140 shown in FIG. 1. Similarly, the D2D MUX 330a can reconfigure and transfer the third byte of the first data bus 310 to the fourth byte of the second data bus 320, and reconfigure and transfer the fourth byte of the first data bus 310 to The third byte of the second data bus 320, the fifth byte of the first data bus 310 is reconfigured and transferred to the sixth byte of the second data bus 320, and the sixth byte of the first data bus 310 is reconfigured Configure and transfer to the fifth byte of the second data bus 320, reconfigure and transfer the seventh byte of the first data bus 310 to the eighth byte of the second data bus 320, and transfer the The eighth byte is reconfigured and transferred to the seventh byte of the second data bus 320. That is, the D2D MUX 330a can exchange 2 bytes between the first data bus 310 and the second data bus 320 according to the logic high level control signal BE_SEL.

[0067] The D2D MUX 330a may change the unchanged data from the first data according to the logic low level control signal BE_SEL

The first byte to the eighth byte of the bus 310 are transferred to the first byte to the eighth byte of the second data bus 320.

[0068] After the data conversion is performed by the D2D MUX 330a, the second data bus 320 may be coupled to the SERDES area 6140. The SERDES area 614 may continuously receive the 64-bit data of the second data bus 320, and connect the 64-bit data through the serial-parallel circuit. Bit data is converted and output as 256-bit parallel data. The 256-bit parallel data output from the SERDES area 614 can be provided to at least one DRAM die 620 through the TSV area 612.

[0069] FIG. 8 is a diagram illustrating the arrangement of the D2D MUX 330b in the storage device 220b according to some example embodiments of the inventive concept. The D2D MUX 330b of FIG. 8 is different from the D2D MUX 330a of FIG. 7 in that the D2D MUX 330b is disposed between the SERDES area 614 and the TSV area 612. Hereinafter, the difference between FIG. 7 and FIG. 8 will be described.

6 and 8, consecutively received 64-bit input data from the CPU 210 to the HBM PHY area 616 may be provided to the SERDES area 614 and converted into 256-bit parallel data. The 256-bit parallel data output from the SERDES area 614 can be transmitted to the D2D MUX 330b through the first data bus 310. The D2D MUX 330b can respond to the control signal BE_SEL to perform the data transfer or conversion operation in units of 2 bytes to the 256-bit input data. The data conversion is performed, and 256-bit output data is output through the second data bus 320. The D2D MUX 330b may be implemented as the D2D MUX 330 of FIGS. 4 and 5A to 5c described above, and the 256-bit input data may be divided into 16 bytes and carried on the first data bus 310, and the 256-bit The output data may be divided into 16 bytes and carried on the second data bus 320.

[0071] The D2D MUX 330b can exchange between the two bytes of the first data bus 310 and the second data bus 320 according to the logic high control signal BE_SEL, that is, between the first byte and the second byte , Between the third and fourth bytes, between the fifth and sixth bytes, between the seventh and eighth bytes, between the ninth and tenth bytes Between the eleventh and twelfth bytes, between the thirteenth and fourteenth bytes, and between the fifteenth and sixteenth bytes.

[0072] The D2D MUX 330b can transfer unchanged data from the first byte to the sixteenth byte of the first data bus 310 to the first byte to the second data bus 320 according to the logic low level control signal BE_SEL. The sixteenth byte.

[0073] After the D2D MUX 330b performs data bus conversion, the second data bus 320 may be coupled to the TSV area 612.

[0074] Since the D2D MUX 330a of FIG. 7 is coupled to the HBM PHY area 616 that communicates according to the operating speed of the CPU 210 (for example, 1.2 GHz), the high-frequency operation suitable for the high-speed operation of the HBM PHY area 616 may be required. Data bus conversion. In contrast, because the D2DMUX 330b of FIG. 8 performs data bus conversion on the 256-bit parallel data processed with high-speed operations in the HBM PHY area 616 and the SERDES area 614, the low frequency is relatively lower than that of the D2D MUX 330a of FIG. The data bus conversion of the operation can satisfy D2D MUX 330b of FIG. 8.

[0075] The D2D MUX 330a of FIG. 7 performs data bus conversion on the 64-bit data of the first data bus 310 and the second data bus 320, while the D2D MUX 330b of FIG. 8 performs data bus conversion on the first data bus 310 and the second data bus 320. 256-bit data performs data bus conversion. Since the size of the D2D MUX 330a of FIG. 7 is relatively smaller than the size of the D2D MUX 330b of FIG. 8, the D2D MUX 330a of FIG. 7 is advantageous in terms of area.

[0076] FIG. 9 is a diagram illustrating the arrangement of the D2D MUX 330c in the storage device 220c according to some example embodiments of the inventive concept. When describing the configuration and operation of the storage device 220c of FIG. 9, the configuration may correspond to at least one DRAM die 620 in the HBM of FIG. 6. Many hardware configurations are shown to describe at least one DRAM die 620, but it is not limited to this, and other configurations are also possible.

[0077] Referring to FIGS. 2, 6 and 9, the following examples are shown: at least one DRAM die 620 of the storage device 220c may

The first to fourth banks BANK0 to BANK3 defined as one bank group BG are included, and the first to fourth banks BANK0 to BANK3 share one bank group input/output line I/O. The bank group I/O BGIO can transfer data in two directions between the CPU 210 and the bank group BG. In order to simplify the drawing, the bank group I/O BGIO and the bank local I/OBLIO are shown as one signal line, but may actually be implemented as multiple signal lines.

[0078] The processing element (PE) 906 may be set corresponding to two or more banks, may be set corresponding to the first bank BANK0 and the second bank BANK1, and may be set corresponding to the third bank BANK2 and the second bank BANK1. The four memory banks BANK3 are set correspondingly. The PE 906 is a conceptual component that performs PIM functions, and can be defined to include various other components related to arithmetic calculation and/or logical calculation processing. For example, the PE 906 may include components that perform various functions, such as a controller that controls all operations of calculation processing, an instruction memory (or instruction queue) that stores instructions, and/or instruction decoding.

[0079] The sense amplifier 901, the write driver 902, and/or the bank group input/output gating circuit (hereinafter referred to as the BGIO gating circuit 903) may be coupled to the first bank BANK0 correspondingly. In addition, the sense amplifier 901 and the write driver 902 may be arranged on the bank local I/O BLIO, and the BGIO gating circuit 903 may be arranged to select the data transfer direction of the bank local I/O BLIO. In FIG. 9, an example is shown in which the BGIO gating circuit 903 is provided in the path of data transmission through the write driver 902, but the BGIO gating circuit 903 is not necessarily limited to this. As another example, the BGIO gating circuit 903 may be arranged in a path through which the sense amplifier 901 outputs data.

[0080] The first PE input/output (PEIO) gating circuit 904 may be provided corresponding to the first bank BANK0, and the second PEIO gating circuit 905 may be provided corresponding to the second bank BANK1. The first PEIO gating circuit 904 and the second PEIO gating circuit 905 may be arranged to control the movement path of data in the storage operation and the calculation processing operation. In the storage operation, the first PEIO gating circuit 904 can electrically connect the bank local I/O BLIO to the bank group I/O BGIO to send and receive data between the CPU 210 and the first bank BANK0, and Data can be transmitted and received between the CPU 210 and the second bank BANK1 through the second PEIO gating circuit 905. At the same time, during the calculation process, the first PEIO gating circuit 904 and the second PEIO gating circuit 905 resist and disconnect the bank local I/O BLIO and the bank group I/O BGIO, so as to communicate between the CPU 210 and the PE 906. Or send and receive data between the PE 906 and the first bank BANK0 and the second bank BANK1.

[0081] The PE 906 may be provided corresponding to the first bank BANK0 and the second bank BANK1. The PE 906 may perform calculation processing by using at least one of the data provided from the CPU 210, the data read from the first bank BANK0 and the second bank BANK1, and the information stored in the register provided in the PE 906 . In some example embodiments, when the PE 906 performs calculation processing using data from the first bank BANK0, the second PEIO gating circuit 905 provided corresponding to the second bank BANK1 can block the bank group I/O BGIO Electrical connection with the bank local I/O BLIO corresponding to the second bank BANK1. In some example embodiments, when the PE906 is shared with the first bank BANK0 and the second bank BANK1, the result of the calculation process using the data of any one bank may be stored in another bank. As an example, the data read from the first bank BANK0 may be provided to the PE 906 as an operand, and the calculation result of the PE 906 may be stored in the second bank BANK1.

[0082] The bank group I/O BGIO may be coupled to the D2D MUX 330c through the data bus driver 907, and the D2D MUX 330c may be coupled to the TSV 630. The data transmitted to the TSV 630 of the at least one DRAM die 620 can be transmitted to the D2D MUX 330c through the first data bus 310. The D2D MUX 330c can respond to the control signal BE_SEL, based on the data transfer or conversion operation, to 256 in units of 2 bytes. Bit input data performs data bus conversion, and 256-bit output data is output through the second data bus 320.

[0083] The D2D MUX 330c may be implemented as the D2DMUX 330 of FIGS. 4 and 5A to 5c described above, and 256

The bit input data may be divided into 16 bytes and carried on the first data bus 310, and the 256-bit output data may be divided into 16 bytes and carried on the second data bus 320. The D2D MUX 330c can exchange two bytes among the 256 bits and 16 bytes of the first data bus 310 and the second data bus 320 according to the logic high level control signal BE_SEL, that is, between the first byte and the second data bus 320. Between the second byte, between the third byte and the fourth byte, between the fifth byte and the sixth byte, between the seventh byte and the eighth byte, and between the ninth byte Between the section and the tenth byte, between the eleventh and twelfth bytes, between the thirteenth and fourteenth bytes, and between the fifteenth and sixteenth bytes Between bytes. The D2D MUX 330c can transfer the unchanged data from the first byte to the sixteenth byte of the first data bus 310 to the first byte to the sixteenth byte of the second data bus 320 according to the logic low level control signal BE_SEL. byte.

[0084] After the D2D MUX 330c performs data bus conversion, the second data bus 320 may be coupled to the bank group I/O BGIO through the data bus driver 907.

[0085] The DRAM die configuration shown in FIG. 9 is provided as an example, but is not necessarily an actual DRAM die configuration. In addition, the DRAM die configuration shown in FIG. 9 does not indicate or imply limitations on the inventive concept.

[0086] FIG. 10 is a diagram illustrating the arrangement of the D2D MUX 330d in the storage device 220d according to some example embodiments of the inventive concept. The storage device 220d of FIG. 10 is different from the storage device 220c of FIG. 9 in that the PEs are arranged corresponding to the first to fourth banks BANK0 to BANK3, respectively. Hereinafter, the difference between FIG. 9 and FIG. 10 will be described.

10, the first PE 906a and the second PE 906b are individually arranged in correspondence with the first bank BANK0 and the second bank BANK1, respectively. The first PEIO gating circuit 904a may be arranged to control the connection of the bank group I/O BGIO and the bank local I/O BLIO of the first bank BANK0, and the second PEIO gating circuit 905b may be arranged to control the bank. The connection of the bank I/O BGIO and the bank local I/O BLIO of the second bank BANK1. The D2D MUX 330d may be connected between the first PE 906a and the first PEIO gating circuit 904a, and between the second PE 906b and the second PEIO gating circuit 905b. The data transmitted from the first PE 906a and the second PE 906b can be transmitted to the D2D MUX 330d through the first data bus 310. The D2D MUX 330d can respond to the control signal BE_SEL, based on the data transfer or conversion operation, to 256 bits in units of 2 bytes. The input data performs data bus conversion, and the 256-bit output data is output to the first PEIO gating circuit 904a and the second PEIO gating circuit 905b through the second data bus 320.

[0088] The D2D MUX 330d may be implemented as the D2DMUX 330 of FIGS. 4 and 5A to 5c described above, and the 256-bit input data may be divided into 16 bytes and carried on the first data bus 310, and The 256-bit output data can be divided into 16 bytes and carried on the second data bus 320. The D2D MUX 330d can exchange two bytes out of the 256 bits and 16 bytes of the first data bus 310 and the second data bus 320 according to the logic high control signal BE_SEL, that is, between the first byte and the second data bus 320. Between the second byte, between the third byte and the fourth byte, between the fifth byte and the sixth byte, between the seventh byte and the eighth byte, and between the ninth byte Between the section and the tenth byte, between the eleventh and twelfth bytes, between the thirteenth and fourteenth bytes, and between the fifteenth and sixteenth bytes Between bytes. The D2D MUX 330d can transfer unchanged data from the first byte to the sixteenth byte of the first data bus 310 to the first byte to the sixteenth byte of the second data bus 320 according to the logic low level control signal BE_SEL. byte.

[0089] FIG. 11 is a diagram illustrating the arrangement of the D2D MUX 330e in the storage device 220e according to some example embodiments of the inventive concept. The storage device 220e of FIG. 11 is an independent type of double data rate (DDR) DRAM, and may include a PE that performs a PIM function.

2 and 11, in the storage device 220e, the D2D MUX 330e may be disposed between the SERDES area 614a and the bank BANK. The DDR PHY area 616a can receive 4-bit input data from the CPU 210 and transmit the 4-bit input data to the SERDES area 614. The DDR PHY area 616a can support the features of the HBM protocol of the JEDEC standard. SERDES area

The 614a can continuously receive the 4-bit data of the CPU 210 transmitted through the DDR PHY area 616a, and convert the 4-bit data through the serial-parallel circuit and output it as 32-bit parallel data. The 32-bit parallel data output from the SERDES area 614a can be divided into byte widths and transmitted to the D2D MUX 330e through the first data bus 310. The D2D MUX 330e can respond to the control signal BE_SEL, based on the data transfer or conversion operation, with 2 bytes Perform data conversion on 32-bit input data for units, and output 32-bit output data.

[0091] The D2D MUX 330e may be implemented as the D2DMUX 330 of FIGS. 4 and 5A to 5c described above, and the 32-bit input data is divided into 4 bytes and carried on the first data bus 310, and 32 The bit output data may be divided into 4 bytes and carried on the second data bus 320. The D2D MUX 330e can exchange two bytes out of the 32 bits and 4 bytes of the first data bus 310 and the second data bus 320 according to the logic high control signal BE_SEL, that is, between the first byte and the second data bus 320. Between the second byte and between the third byte and the fourth byte. The D2D MUX330e can transfer unchanged data from the first byte to the fourth byte of the first data bus 310 to the first byte to the fourth byte of the second data bus 320 according to the logic low level control signal BE_SEL.

[0092] After the data bus conversion is performed by the D2D MUX 330e, the second data bus 320 may be coupled to the bank BANK.

[0093] FIG. 12 is a diagram illustrating the arrangement of the D2D MUX 330f in the storage device 220f according to some example embodiments of the inventive concept. The difference between the D2D MUX 330f of FIG. 12 and the D2D MUX 330e of FIG. 11 is that the D2D MUX 330f is disposed between the DDR PHY area 616b and the SERDES area 614b. Hereinafter, the difference between FIG. 11 and FIG. 12 will be described.

2 and 12, in the storage device 220f, the DDR PHY area 616b may receive 4-bit input data from the CPU 210, and transmit the 4-bit input data to the D2D MUX 330f through the first data bus 310. For example, in the first data bus 310 in big-endian format, the first address refers to the most significant (for example, the leftmost) bit of the first data bus 310, and the increasing addresses refer to It is the increasingly less significant bits (increasingly less significant bits). In contrast, in the second data bus 320 in little-endian format, the same first address refers to the least significant (for example, the rightmost) bit of the second data bus 320, and the incremented address refers to It is increasingly more significant bits.

[0095] As shown in FIG. 13, the D2D MUX 330f may perform a bit transfer or bit conversion operation on the 4-bit input data of the first data bus 310 in response to the control signal BE_SEL. The D2D MUX 330f can perform bit swap 1301 according to the logic high level control signal BE_SEL, so that the b3-b2-b1-b0 bits of the first data bus 310 can be converted into b0-b1-b2-b3 bits and output to the second Data bus 320. In contrast, the D2D MUX 330f can perform bit transfer 1302 according to the logic low level control signal BE_SEL, so that the b3-b2-b1-b0 bit of the first data bus 310 can be unchanged and used as the b3-b2-b1-b0 bit Output to the second data bus 320.

[0096] After the data bus conversion is performed by the D2D MUX 330f, the second data bus 320 may be coupled to the SERDES area 614b. The SERDES area 614b may continuously receive the 4-bit data of the second data bus 320, and connect the serial-parallel circuit 4-bit data is converted and output as 32-bit parallel data. The 32-bit parallel data output from the SERDES area 614b can be transferred to the bank BANK.

[0097] As described above, the data converter 330 may be implemented in hardware (as shown but not limited to the examples shown in FIGS. 4 to 5c), as well as in an equivalent hardware implementation.

[0098] Any remaining elements disclosed above may include or be implemented in processing circuits such as: hardware including logic circuits; hardware/software combinations such as processors that execute software; or combinations thereof. For example, the processing circuit is more

Specifically, it may include but not limited to central processing unit (CPU), arithmetic logic unit (ALU), digital signal processor, microcomputer, field programmable gate array (FPGA), system on chip (SoC), programmable logic unit, micro Processor, application specific integrated circuit (ASIC), etc.

[0099] Although the inventive concept has been specifically shown and described with reference to the exemplary embodiments of the inventive concept, it will be understood that various forms and details may be made without departing from the spirit and scope of the appended claims. Kind of change.