Display panel, manufacturing method of display panel and display device

Display panel, display panel manufacturing method, and display device technical field

[0001] This application relates to the field of display technology, and in particular to a display panel, a method for manufacturing the display panel, and a display device.

Background technique

[0002] Due to the advantages of large area, high integration, high resolution, and low power consumption, TFT-LCD (Thin Film Transistor-Liquid Crystal Display) devices, as the foundation of a new generation of display devices, have received more and more attention. More and more attention.

[0003] In the related art, the pixel unit of the TFT-LCD display panel includes a transistor, a pixel electrode, and a common electrode. Wherein, the pixel electrode can be connected to the transistor through the via structure, and when the pixel electrode is connected to the transistor, it is easy to cause poor connection due to factors such as poor contact between the pixel electrode and the hole wall of the via structure, and then cause poor display of the display panel.

Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a display panel, a manufacturing method of the display panel, and a display device, so as to reduce the probability of display failure of the display panel. The specific technical solutions are as follows:

[0005] An embodiment of the first aspect of the present application provides a display panel, the display panel including:

[0006] a base substrate and a plurality of pixel units located on the base substrate and arranged in a matrix, at least one pixel unit includes a transistor and a pixel electrode connected to the transistor;

[0007] A first insulating layer, where the first insulating layer is located on a side of the transistor away from the base substrate;

[0008] A second insulating layer, the second insulating layer is located on the side of the first insulating layer away from the transistor, the second insulating layer is provided with a first via hole, and the pixel electrode passes through the The first via hole is connected to the transistor, and the first via hole includes a first hole section penetrating the first insulating layer and a second hole section penetrating the second insulating layer. The second insulating layer Covering at least part of the hole wall of the first hole section.

[0009] In some embodiments, at least one transistor includes a first metal layer, a gate insulating layer, a second metal layer, and an active layer on one side of the base substrate, and the first metal layer includes a gate, The second metal layer includes a source electrode and a drain electrode, and the pixel electrode is connected to the drain electrode through the first via hole.

[0010] In some embodiments, the second insulating layer completely covers the hole wall of the first hole section, and the second insulating layer is in contact with the drain.

[0011] In some embodiments, at least one pixel unit further includes a common electrode disposed opposite to the pixel electrode, a second via hole is provided on the second insulating layer, and the common electrode passes through the second via hole. Connected to the gate.

[0012] In some embodiments, the second via hole includes a third hole section penetrating the first insulating layer, a fourth hole section penetrating the second insulating layer, and a first hole section penetrating the gate insulating layer. A five-hole section, and the second insulating layer covers the hole walls of the third hole section and the fifth hole section.

[0013] In some embodiments, at least part of the common electrode of the pixel unit is connected.

[0014] In some embodiments, the common electrode and the pixel electrode are both transparent metal oxide electrodes.

[0015] In some embodiments, the material of the first insulating layer includes silicon nitride, and the material of the second insulating layer includes

Resin.

[0016] A second aspect of the embodiments of the present application provides a manufacturing method of a display panel, and the manufacturing method of the display panel includes:

[0017] Provide a base substrate;

[0018] forming a transistor on one side of the base substrate;

[0019] forming a first insulating layer on the side of the transistor away from the base substrate;

[0020] forming a second insulating layer on the side of the first insulating layer away from the transistor;

[0021] forming a first via hole on the second insulating layer, the first via hole including a first hole section penetrating the first insulating layer and a second hole section penetrating the second insulating layer;

[0022] Using a preset temperature to heat the second insulating layer so that the second insulating layer flows and covers at least part of the hole wall of the first hole section;

[0023] A pixel electrode is formed, and the pixel electrode is connected to the transistor through the first via hole.

[0024] In some embodiments, the preset temperature is 200 degrees Celsius to 250 degrees Celsius.

[0025] A third aspect of the embodiments of the present application provides a display device, which is characterized in that the display device includes any of the above-mentioned display panels.

[0026] The beneficial effects of the embodiments of the present application:

[0027] The embodiments of the present application provide a display panel, a method for manufacturing a display panel, and a display device. In the display panel, the display panel includes a base substrate and a plurality of pixel units located on the base substrate. The pixel unit includes a transistor and a pixel electrode connected to the transistor. The display panel further includes a first insulating layer on the transistor of the pixel unit and a second insulating layer on the first insulating layer. Wherein, the second insulating layer is provided with a first via hole, so that the pixel electrode can be connected to the transistor through the second via hole. The first via hole includes a first hole section and a second hole section respectively penetrating the first insulating layer and the second insulating layer, and the second insulating layer covers at least a part of the hole wall of the first hole section. In the display panel provided by the embodiment of the present application, the second hole section penetrates the second insulating layer, and the second insulating layer covers at least part of the hole wall of the first hole section, so that the second insulating layer at least partially covers the first hole section The connection between the second hole section and the second hole section makes the hole wall of the first via hole relatively smooth. Based on this, when the pixel electrode is connected to the transistor of the pixel unit through the first via hole, the pixel electrode can more closely fit the wall of the first via hole, thereby reducing the probability of poor contact between the pixel electrode and the wall of the first via hole. Therefore, the probability of poor connection between the pixel electrode and the transistor is reduced, and the probability of poor display of the display panel is reduced.

[0028] Of course, the implementation of any product or method of the present application does not necessarily need to achieve all the advantages described above at the same time.

Description of the drawings

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, in the following description The drawings are only some embodiments of the present application, and for those of ordinary skill in the art, other embodiments can be obtained based on these drawings.

[0030] FIG. 1 is a schematic diagram of a structure of a display panel in the related art;

[0031] FIG. 2 is a schematic diagram of a structure of a display panel in some embodiments of the application;

[0032] FIG. 3 is a cross-sectional view along the AA direction in FIG. 2;

[0033] FIG. 4 is another cross-sectional view along the AA direction in FIG. 2;

[0034] FIG. 5 is another cross-sectional view along the AA direction in FIG. 2;

[0035] FIG. 6 is a flowchart of a manufacturing method of a display panel in some embodiments of the application.

[0036] Reference signs: 100-display panel; 200-light-emitting layer; 210-organic light-emitting layer; 300-liquid crystal layer; 1-substrate; 2-pixel unit; 21-transistor; 211-first metal layer; 2111-gate; 212-gate insulating layer; 213-second metal layer; 2131-source; 2132-drain; 214-active layer; 22-pixel electrode; 23-common electrode; 3-first insulation Layer; 4- second insulating layer; 5- first via; 51- first hole section; 52- second hole section; 6- second via; 61- third hole section; 62- fourth hole section ; 63-Fifth hole section.

Detailed ways

[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all implementations. example. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art based on this application fall within the protection scope of this application.

[0038] It should be noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or intervening layers may be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or there may be more than one intervening layer or element. In addition, it can also be understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or more than one intervening layer may also be present. Or components. Similar reference numerals indicate similar elements throughout.

[0039] In the related art, as shown in FIG. 1, the display panel includes a base substrate 1'and a pixel unit 2'located on the base substrate 1'. The pixel unit 2'includes a transistor 21' and a transistor 21' connected to it. Pixel electrode 22'. The display panel further includes a first insulating layer 3'located on the transistor 21' and a second insulating layer 4'located on the first insulating layer 3', the second insulating layer 4'is provided with a via structure 5', and a pixel electrode 22' is connected to the transistor 21' through the via structure 5'. In the related art, since the materials of the first insulating layer 3'and the second insulating layer can be different, when forming the via structure 5', the via structure 5'can be formed on the second insulating layer by first using techniques such as exposure and development. Then, the first insulating layer 3'is processed by etching or the like to form the first hole section 51' of the via structure 5', thereby forming the via structure 5'. After the first insulating layer is etched, as shown in FIG. 1, the first insulating layer 3'may form a chamfered surface at the first hole section 51', that is, the hole wall of the first hole section 51' is different from The hole wall of the second hole section 52' is located on the same plane. Based on this, when the pixel electrode 22' is connected to the transistor 21' through the via structure 5', the hole wall of the pixel electrode 22' and the first hole section 51' is easy to produce The poor contact results in poor connection between the pixel electrode 22' and the transistor 21', resulting in poor display of the display panel.

[0040] Therefore, in order to reduce the probability of display failure of the display panel, the embodiments of the present application provide a display panel, a manufacturing method of the display panel, and a display device. The manufacturing method of the panel and the display device will be described in detail. Among them, the display panel includes but not limited to OLED (Organic Light-Emitting Diode, organic electroluminescence display panel), QLED (Quantum Dot Light Emitting Diodes, quantum dot electroluminescence display panel), quantum dot photoluminescence display panel and TFT -LCD (Thin Film Transistor-Liquid Crystal Display) etc.

[0041] As shown in FIGS. 2 and 3, an embodiment of the first aspect of the present application provides a display panel 100, which includes a base substrate 1, a plurality of pixel units 2, and a first insulating layer 3. And second insulating layer 4. Among them, a plurality of pixel units 2 are located on the base substrate 1 and arranged in a matrix. At least one pixel unit 2 includes a transistor 21 and an image connected to the transistor 21.

Prime22. Element electrode 22. The first insulating layer 3 is located on the side of the transistor 21 away from the base substrate 1. The second insulating layer 4 is located on the side of the first insulating layer 3 away from the transistor 21. The second insulating layer 4 is provided with a first via hole 5, and the pixel electrode 22 is connected to the transistor 21 through the first via hole 5. The hole 5 includes a first hole section 51 penetrating the first insulating layer 3 and a second hole section 52 penetrating the second insulating layer 4, and the second insulating layer 4 covers at least part of the hole wall of the first hole section 51.

[0042] In the display panel 100 provided by the embodiment of the present application, the second insulating layer 4 is provided with a first via hole 5, so that the pixel electrode 22 of the pixel unit 2 can be connected to the transistor 21 through the first via hole 5. The first via hole 5 includes a first hole section 51 and a second hole section 52 respectively penetrating the first insulating layer 3 and the second insulating layer 4, and the second insulating layer 4 covers at least part of the hole wall of the first hole section 51. The second hole section 52 penetrates the second insulating layer 4, and the second insulating layer 4 covers at least part of the hole wall of the first hole section 51, which makes the second insulating layer 4 at least partially cover the first hole section 51 and the first hole section 51. The junction of the two hole sections 52 makes the hole wall of the first via 5 relatively smooth. Based on this, when the pixel electrode 22 is connected to the transistor 21 of the pixel unit 2 through the first via hole 5, the pixel electrode 22 can more closely fit the wall of the first via hole 5, thereby reducing the pixel electrode 22 and the first via hole. The probability of poor contact of the hole wall of 5 further reduces the probability of poor connection between the pixel electrode 22 and the transistor 21, and reduces the probability of poor display of the display panel 100.

[0043] Among them, the base substrate 1 may be a rigid base substrate, such as a glass substrate. The base substrate 1 may also be a flexible base substrate, such as a polyimide substrate, which is not specifically limited in the embodiment of the present application.

[0044] Further, the material of the first insulating layer 3 includes silicon nitride (SiNx), and the material of the second insulating layer 4 includes resin. Wherein, since the materials of the first insulating layer 3 and the second insulating layer 4 can be different, when forming the first via 5 on the second insulating layer 4, it is necessary to first form the first via 5 on the second insulating layer 4. The second hole section 52, and then a first hole section 51 is further formed on the first insulating layer 3, thereby forming the first via hole 5. Specifically, taking the material of the first insulating layer 3 as SiNx and the material of the second insulating layer 4 as resin as an example, when the first via hole 5 is formed on the second insulating layer 4, the second insulating layer 4 is first exposed and developed in the second A second hole section 52 penetrating the second insulating layer 4 is formed on the insulating layer 4, and then a first hole section 51 penetrating the first insulating layer 3 is continuously formed on the first insulating layer 3 by dry etching. Since the material of the second insulating layer 4 is resin, after the first via hole 5 is formed, the second insulating layer 4 is heated at a high temperature of 200 degrees Celsius to 250 degrees Celsius, so that the second insulating layer 4 flows and covers the etching of SiNx Edge, even if the second insulating layer 4 flows to cover the hole wall of the first hole section 51 and the connection between the first hole section 51 and the second hole section 52. Then, the second insulating layer 4 is cured under the action of high temperature. Based on this, a relatively smooth transition is formed at the first hole section 51 and the second hole section 52, so that the hole wall of the first via hole 5 is smoother. In a specific embodiment, The second insulating layer 4 is heated at a high temperature of 230 degrees Celsius.

[0045] In some embodiments, as shown in FIG. 3, at least one transistor 21 includes a first metal layer 211, a gate insulating layer 212, a second metal layer 213, and an active layer 214 on one side of the base substrate 1. The first metal layer 211 includes the gate 2111, the second metal layer 213 includes the source 2131 and the drain 2132, and the pixel electrode 22 is connected to the drain 2132 through the first via 5.

[0046] In the embodiment of the present application, the pixel electrode 22 is disposed on the second insulating layer 4, and the pixel electrode 22 is connected to the drain 2132 in the transistor 21 through the first via hole 5. Wherein, the materials of the first metal layer 211 and the second metal layer 213 may include metal materials such as copper, aluminum, and silver, or alloy materials containing the foregoing metal materials. The material of the gate insulating layer 212 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or may include polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or Organic insulating materials such as phenolic resin. Further, the gate 2111 may have a laminated structure having a copper layer and a molybdenum-niobium layer, and the molybdenum-niobium layer is used to protect the copper layer. In addition, both the source electrode 2131 and the drain electrode 2132 may also include a copper layer and a molybdenum-niobium layer for protecting the copper layer. Similarly, the molybdenum-niobium layer has a protective effect on the copper layer to prevent the copper layer from being corroded.

[0047] In some embodiments, the second insulating layer 4 completely covers the hole wall of the first hole section 51, and the second insulating layer 4 and the drain electrode

2132 contacts.

[0048] In the embodiment of the present application, as shown in FIG. 3, the second insulating layer 4 may extend from the junction of the first hole section 51 and the second hole section 52 toward the drain 2132, until the second insulating layer 4 extends to The drain 2132 covers a part of the surface of the drain 2132. Based on this, the second insulating layer 4 completely covers the connection between the first hole section 51 and the second hole section 52 and the hole wall of the first hole section 51, which makes the hole wall of the first via hole 5 covered by the second insulating layer 4 Covering to form a whole makes the hole wall of the first via hole 5 smoother. When the pixel electrode 22 is connected to the transistor 21 of the pixel unit 2 through the first via hole 5, the pixel electrode 22 can be more closely attached to the hole wall of the first via hole 5, and the hole between the pixel electrode 22 and the first via hole 5 is further reduced. The probability of poor contact of the wall further reduces the probability of poor connection between the pixel electrode 22 and the transistor 21, and reduces the probability of poor display of the display panel 100.

[0049] In some embodiments, as shown in FIG. 3, at least one pixel unit 2 further includes a common electrode 23 disposed opposite to the pixel electrode 22, a second via hole 6 is provided on the second insulating layer 4, and the common electrode 23 passes through The second via hole 6 is connected to the gate 2111. [0050] In the embodiment of the present application, the common electrode 23 may be disposed on the first insulating layer 3, the pixel electrode 22 may be disposed on the second insulating layer 4, and the pixel electrode 22 and the common electrode 23 may pass through the second insulating layer 4. Separately, the first via hole 5 is provided through the first insulating layer 3 and the second insulating layer 4, so that a part of the structure of the pixel electrode 22 can extend into the first via hole 5 so as to pass through the first via hole 5. The drain 2132 under an insulating layer 3 is connected. The second via hole 6 is provided through the first insulating layer 3, the second insulating layer 4, and the gate insulating layer 212, so that the common electrode 23 can extend into the second via hole 6 so as to be located in the gate insulating layer through the second via hole 6 The gate 2111 under the layer 212 is connected.

[0051] In some embodiments, the second via hole 6 includes a third hole section 61 penetrating the first insulating layer 3, a fourth hole section 62 penetrating the second insulating layer 4, and a fifth hole penetrating the gate insulating layer 212 Section 63, the second insulating layer 4 covers the hole walls of the third hole section 61 and the fifth hole section 63.

[0052] In the embodiment of the present application, the second insulating layer 4 covers at least part of the hole walls of the third hole section 61 and the fifth hole section 63, so that the second insulating layer 4 at least partially covers the third hole section 61 and the first hole section 61. The connection of the four hole section 62 and the connection of the fourth hole section 62 and the fifth hole section 63 make the hole wall of the second via hole 6 relatively smooth. Based on this, when the common electrode 23 is connected to the gate 2111 of the transistor 21 through the second via 6, the common electrode 23 can more closely fit the wall of the second via 6, thereby reducing the common electrode 23 and the second via. The probability of poor contact of the hole wall of 6 further reduces the probability of poor connection between the common electrode 23 and the transistor 21, and reduces the probability of poor display of the display panel 100.

[0053] Further, as shown in FIG. 3, the second insulating layer 4 may completely cover the hole walls of the third hole section 61 and the fifth hole section 63, and the second insulating layer 4 may extend toward the gate 2111 until it is in contact with the gate. Pole 2111 contact. The second insulating layer 4 completely covers the hole walls of the third hole section 61 and the fifth hole section 63, so that the hole wall of the second via hole 6 is completely covered by the second insulating layer 4 to form a whole, so that the second via hole The hole wall of 6 is more gentle. Based on this, when the common electrode 23 is connected to the gate 2111 through the second via hole 6, the common electrode 23 can be more closely attached to the wall of the second via hole 6, reducing the problem of poor overlap between the common electrode 23 and the gate 2111. The probability further reduces the probability of poor display of the display panel 100.

[0054] Wherein, the first via hole 5 and the second via hole 6 can be formed at the same time. After the first via hole 5 and the second via hole 6 are formed, the second insulating layer 4 is processed at a high temperature of 200 degrees Celsius to 250 degrees Celsius. Heating, so that the second insulating layer 4 can flow and cover the first hole section 51 of the first via hole 5, the third hole section 61 and the fifth hole section 63 of the second via hole 6, and then the second insulating layer 4 is at a high temperature Under the action of curing.

[0055] In some embodiments, at least part of the common electrode 23 of the pixel unit 2 is connected.

[0056] In the embodiment of the present application, the plurality of pixel units 2 located on the base substrate 1 are distributed in a matrix. Among them, some of the pixel units 2 can be multiple pixel units 2 located in the same row, and some of the pixel units 2 can also be multiple image units located in different rows.

Whiteunit 2. That is, the common electrodes 23 of a plurality of pixel units 2 located in the same row can be connected to form an integrated structure, and the common electrodes 23 of pixel units 2 located in different rows can also be connected to form an integrated structure. The common electrodes 23 of part of the pixel units 2 are connected to form an integral structure, so that the common electrodes 23 of the plurality of pixel units 2 have an equal potential, thereby improving the display effect of the display panel 100.

[0057] Further, the common electrodes 23 of all the pixel units 2 of the display panel 100 are connected, so that the common electrodes 23 of all the pixel units 2 have the same potential, which further improves the display effect of the display panel 100.

[0058] The common electrodes 23 of the multiple pixel units 2 may be directly connected, and the common electrodes 23 of the multiple pixel units 2 may also be connected through auxiliary electrode lines. Specifically, when the common electrode 23 of a plurality of pixel units 2 is connected by an auxiliary electrode line, the common electrode 23 of the pixel unit 2 is connected to one end of the auxiliary electrode line through a via structure, and the pixel unit adjacent to the pixel unit 2 The common electrode 23 of 2 is connected to the other end of the auxiliary electrode line through a via structure, thereby connecting the common electrodes 23 of two adjacent pixel units 2. Wherein, the material of the auxiliary electrode wire may include metal materials such as copper, aluminum, silver, or an alloy material containing the foregoing metal materials, and the material of the auxiliary electrode wire may also be a transparent metal oxide or the like.

[0059] In some embodiments, the common electrode 23 and the pixel electrode 22 are both transparent metal oxide electrodes. That is, the materials of the common electrode 23 and the pixel electrode 22 are both transparent metal oxides, such as IZO (indium zinc oxide), ITO (indium tin oxide), and the like. The material of the common electrode 23 and the pixel electrode 22 is transparent metal oxide, which reduces the light blocking rate of the common electrode 23 and the pixel electrode 22, and improves the light transmittance of the display panel 100.

[0060] In some embodiments, the materials of the common electrode 23 and the pixel electrode 22 may also include metal materials such as copper, aluminum, and silver, or alloy materials containing the foregoing metal materials.

[0061] In the embodiment of the present application, when the display panel 100 is an organic light-emitting display panel, as shown in FIG. The light-emitting layer 200 on the side. The transistor 21 is used to drive the light emitting layer 200 to emit light. The pixel electrode 22 may be an anode layer in the light-emitting layer 200, the common electrode 23 may be a cathode layer in the light-emitting layer 200, and an organic light-emitting layer 210 for emitting light is also provided between the pixel electrode 22 and the common electrode 23.

[0062] When the display panel 100 is a thin film transistor liquid crystal display panel, as shown in FIG. The liquid crystal layer 300 on one side of the substrate 1 and the transistor 21 are used to drive the liquid crystal in the liquid crystal layer 300 to undergo directional deflection.

[0063] The embodiment of the second aspect of the present application provides a method for manufacturing a display panel. As shown in FIG. 6, the method includes the following steps:

[0064] Step S601, providing a base substrate.

[0065] Step S602, forming a transistor on one side of the base substrate.

[0066] In step S603, a first insulating layer is formed on a side of the transistor away from the base substrate.

[0067] In step S604, a second insulating layer is formed on a side of the first insulating layer away from the transistor.

[0068] Step S605, forming a first via hole on the second insulating layer, the first via hole including a first hole section penetrating the first insulating layer and a second hole section penetrating the second insulating layer.

[0069] The specific process of forming the first via hole may be: forming a second hole section penetrating the second insulating layer on the second insulating layer by exposure and development, and then performing dry etching on the second insulating layer. The first insulating layer under the insulating layer is etched to form a first hole section penetrating the first insulating layer on the first insulating layer, thereby forming a first via hole.

[0070] Step S606, heating the second insulating layer at a preset temperature so that the second insulating layer flows and covers at least part of the hole wall of the first hole section.

[0071] Further, the preset temperature is 200 degrees Celsius to 250 degrees Celsius. In an example, the preset temperature may be 230 degrees Celsius.

[0072] In step S607, a pixel electrode is formed, and the pixel electrode is connected to the transistor through the first via hole.

[0073] According to the manufacturing method of the display panel of the embodiment of the present disclosure, the second hole section penetrates the second insulating layer, and the second insulating layer covers at least part of the hole wall of the first hole section, so that the second insulating layer at least partially covers The connection between the first hole section and the second hole section is arranged so that the hole wall of the first via hole is relatively smooth. Based on this, when the pixel electrode is connected to the transistor of the pixel unit through the first via hole, the pixel electrode can more closely fit the wall of the first via hole, thereby reducing the probability of poor contact between the pixel electrode and the wall of the first via hole. Therefore, the probability of poor connection between the pixel electrode and the transistor is reduced, and the probability of poor display of the display panel is reduced.

[0074] Further, step S605 can be refined to form a first via hole and a second via hole on the second insulating layer, the first via hole includes a first hole section penetrating the first insulating layer and a second insulating layer penetrating through the first hole section. The second hole section of the layer, the second via hole includes a third hole section penetrating the first insulating layer, a fourth hole section penetrating the second insulating layer, and a fifth hole section penetrating the gate insulating layer of the transistor.

[0075] Further, step S606 can be refined as: heating the second insulating layer at a preset temperature, causing the second insulating layer to flow and cover at least part of the hole wall of the first hole section, and causing the second insulating layer to flow and cover Part of the hole wall of the third hole section and the fifth hole section.

[0076] Further, the above manufacturing method further includes: forming a common electrode, and the common electrode is connected to the transistor through the second via hole.

[0077] In the embodiment of the present application, the second insulating layer covers at least part of the hole walls of the third hole section and the fifth hole section, so that the second insulating layer at least partially covers the connection between the third hole section and the fourth hole section. And the connection between the fourth hole section and the fifth hole section, which makes the hole wall of the second via relatively smooth. Based on this, when the common electrode is connected to the gate of the transistor through the second via hole, the common electrode can more closely fit the wall of the second via hole, thereby reducing the probability of poor contact between the common electrode and the wall of the second via hole. Therefore, the probability of poor connection between the common electrode and the transistor is reduced, and the probability of poor display of the display panel is reduced.

[0078] The embodiment of the third aspect of the present disclosure provides a display device, and the display device includes the display panel 100 in any of the foregoing embodiments. Among them, display devices include, but are not limited to, mobile phones, tablet computers, monitors, televisions, painting screens, advertising screens, electronic paper, etc. Since the display device includes the above-mentioned display panel 100, the display device has all the advantages of the above-mentioned display panel 100, such as a low probability of occurrence of display failure.

[0079] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these entities. Or there is any such actual relationship or sequence between operations. Moreover, the terms "include", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes those that are not explicitly listed Other elements of, or also include elements inherent to this process, method, article or equipment. If there are no more restrictions, the element defined by the sentence "including a..." does not exclude the existence of other identical elements in the process, method, article, or equipment that includes the element.

[0080] The above descriptions are only preferred embodiments of the present application, and are not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application are all included in the protection scope of this application.