Display

Display device

Technical field

The present invention relates to a light-emitting element using an EL (Electroluminescence) element or LED (Light Emitting Diode) element that emits light by passing a driving current through an organic semiconductor film, and a thin film transistor (hereinafter referred to as TFT) Active matrix type display device. In more detail, it relates to an optimization technique for improving the layout of the display characteristics.

Background technique

An active matrix type display device using a current control type light emitting element such as an EL element or an LED element has been proposed. Since the light-emitting elements used in this type of display device emit light by themselves, unlike the liquid crystal display device, a backlight is not required, and in addition, it has advantages such as less dependence on the viewing angle.

FIG. 22 shows a block diagram of an active matrix type display device using a charge injection type organic thin film EL element, as an example of such a display device. In the display device 1A shown in the figure, a plurality of scan lines gate, a plurality of data lines sig extending in a direction crossing the extending direction of these scan lines gate, and these data lines sig are formed on a transparent substrate. The parallel multiple common power supply lines com and the pixels 7 corresponding to the intersections of the data line sig and the scan line gate. With respect to the data line sig, a data-side drive circuit 3 including a shift register, a level shifter, a video line, and analog switches is formed. With respect to the scanning lines, a scanning side drive circuit 4 including a shift register and a level shifter is constituted. In addition, each pixel 7 constitutes a first TFT 20 that supplies a scanning signal to the gate electrode through a scanning line, a holding capacitor cap that holds the image signal supplied from the data line sig through the first TFT 20, and a diagram holding the holding capacitor cap. The second TFT 30 for supplying the image signal to the gate electrode and the light emitting element 40 through which the driving current flows from the common power supply line com when the second TFT 30 is electrically connected to the common power supply line com.

That is, as shown in FIG. 23(A) and (B), two island-shaped semiconductor films are used to form the first TFT 20 and the second TFT 30 in any pixel 7, and the first TFT 20 and the second TFT 30 are formed through the contact hole of the first interlayer insulating film 51. The relay electrode 35 is electrically connected to the source-drain region of the second TFT 30, and the pixel electrode 41 is electrically connected to the relay electrode 35 through the contact hole of the second interlayer insulating film 52. On the upper layer side of the pixel electrode 41, a hole injection layer 42, an organic semiconductor film 43, and a counter electrode op are laminated. Here, the opposing electrode op is formed across the data line sig and the like and spread over the plurality of pixels 7. Furthermore, the common power supply line com is electrically connected to the source-drain region of the second TFT 30 through a contact hole.

In contrast, in the first TFT 20, the potential holding electrode st that is electrically connected to the source-drain region is electrically connected to the extended portion 310 of the gate electrode 31. With respect to the extended portion 310, the semiconductor film 400 is opposed to the gate insulating film 50 on the lower layer side. The semiconductor film 400 is made conductive by the impurities introduced therein, so the extended portion 310 and the gate insulating film 50 are formed togetherUpholding capacitance cap. Here, the common power supply line com is electrically connected to the semiconductor film 400 through the contact hole of the first interlayer insulating film 51. Therefore, since the holding capacitor cap holds the image signal supplied from the data line sig through the first TFT 20, even if the first TFT 20 is turned off, the gate electrode 31 of the second TFT 30 is held at a potential corresponding to the image signal. Therefore, since the driving current continues to flow into the light emitting element 40 from the common power supply line com, the light emitting element 40 continues to emit light.

However, in the above-mentioned display device 1A, compared with the liquid crystal display device, since the second TFT 30 and the common power supply line com are necessary, the pixels 7 are narrowed, and there is a problem that the display quality cannot be improved.

Therefore, the subject of the present invention is to provide a display device in which the layout of the pixels formed on the substrate and the common power supply line com is improved, and the light-emitting area of the pixels is expanded, thereby improving the display quality.

Summary of the invention

In order to solve the above-mentioned problems, in the present invention, the display device has on the substrate: a plurality of scan lines; a plurality of data lines extending in a direction intersecting the extending direction of the scan line; and a plurality of common lines parallel to the data line. Power supply line; and pixels formed in a matrix by the data line and the scan line, each of the pixels has: a first thin film transistor on the first gate electrode that receives a scan signal through the scan line; keeps passing The first thin film transistor has a holding capacitor for the image signal supplied from the data line; a second thin film transistor that receives the image signal held by the holding capacitor on the second gate electrode; and a light-emitting element having an organic A semiconductor film in which the organic semiconductor film is formed between the pixel electrode formed in each of the above-mentioned pixels and the layer of the counter electrode opposite to the pixel electrode, and the above-mentioned pixel electrode is supplied with the above-mentioned common power through the second thin-film transistor When the wires are electrically connected, they emit light by driving current flowing between the pixel electrode and the opposing electrode. The display device is characterized in that pixels are arranged on both sides of the common power supply line, and the driving current is The pixel passes through the common power supply line, and the data line passes through the side opposite to the common power supply line for the pixel.

That is, in the present invention, since a data line, a pixel group connected to it, a common power supply line, a pixel group connected to it, and a data line that supplies pixel signals to the pixel group are taken as one unit, They are arranged repeatedly in the extending direction of the scanning line, so one common power supply line is used to drive the pixels in two columns. Therefore, since the formation area of the common power supply line can be narrowed compared with the case where the common power supply line is formed in each of the pixel groups in one column, the light-emitting area of the pixels can be expanded accordingly. As a result, display performance such as brightness and contrast can be improved.

When configured in this manner, for example, between two pixels arranged so as to sandwich the common power supply line, it is preferable that the first thin film transistor, the second thin film transistor, and the light-emitting element share the common power supply line. The power supply line is centrally arranged in line symmetry.

In the present invention, it is preferable that the pitch of the center of the formation region of the organic semiconductor film is made equal between any pixels adjacent in the extending direction of the scanning line. If constructed in this way, it is convenient to eject the material of the organic semiconductor film from the inkjet head to form the organic semiconductor film. That is, since the center pitch of the formation area of the organic semiconductor film is equal, the material of the organic semiconductor film may be ejected from the inkjet head at equal intervals. As a result, the movement control mechanism of the inkjet head becomes simple, and the position accuracy is also improved.

In addition, it is preferable that the formation area of the organic semiconductor film is surrounded by a bank layer composed of an insulating film thicker than the organic semiconductor film, and the bank layer is formed so as to cover with the same width dimension. The above-mentioned data line and the above-mentioned common power supply line. With this configuration, the bank layer prevents the organic semiconductor film from overflowing around when the organic semiconductor film is formed by the inkjet method, so that the organic semiconductor film can be formed in a predetermined area. In addition, since the bank layer covers the data line and the common power supply line with the same width dimension, the center of the organic semiconductor film formation region is formed between any pixels adjacent in the extending direction of the scanning line. It is suitable in terms of equal spacing. Here, the opposing electrode is formed at least substantially on the entire surface of the pixel area, or is formed in a stripe shape over a wide area, and it is in a state facing the data line. Therefore, in the original state, a large parasitic capacitance is generated with respect to the data line. However, in the present invention, since the bank layer is interposed between the data line and the counter electrode, it is possible to prevent the capacitance formed between the counter electrode and the counter electrode from parasitising the data line. As a result, since the load on the data-side drive circuit can be reduced, it is possible to reduce power consumption or increase the speed of display operation.

In the present invention, it is preferable to form a wiring layer at a position corresponding to the two data lines passing through the common power supply line on the opposite side with respect to the pixel. If two data lines are in parallel, there is a concern that crosstalk (crosstalk) occurs between these data lines. However, in the present invention, since another wiring layer is passed between the two data lines, the above-mentioned crosstalk can be prevented by placing such a wiring layer at a fixed potential during at least one horizontal scanning period of the image.

At this time, among the plurality of data lines, it is preferable that the image signal is sampled at the same timing between two adjacent data lines. With this configuration, since the potential changes during sampling between the two data lines occur simultaneously, it is possible to more reliably prevent the occurrence of crosstalk between these data lines.

In the present invention, it is preferable that a plurality of pixels between the driving current passing pixel and the same common power supply line include substantially the same number of driving currents for driving the light-emitting element using polarity inversion. Kind of pixels.

If configured in this way, the drive current flowing from the common power supply line to the pixels and the drive current flowing from the pixels to the common power supply line are cancelled out, and the drive current flowing to the common power supply line can be reduced. Therefore, since the common power supply line can be made thinner accordingly, the display area relative to the screen shape can be expanded. In addition, it is possible to eliminate brightness unevenness due to the difference in drive current.

For example, it is configured such that the polarity of the driving current in each pixel in the extending direction of the data line is the same, and the polarity of the driving current in each pixel in the extending direction of the scanning line is per pixel. Or inverted every 2 pixels. Alternatively, it may be constructed in such a way that the polarity of the driving current in each pixel in the extending direction of the scanning line is the same, and the polarity of the driving current in each pixel in the extending direction of the data line is equal to 1 Inverted every 2 pixels or every 2 pixels. In these forms, when the polarity of the driving current is inverted every two pixels, the pixels to which the driving current of the same polarity flows, because the pairing can be made between adjacent pixels. The counter electrode becomes common, so the number of gaps in the counter electrode can be reduced. That is, the resistance value of the counter electrode through which a large current flows is not increased, and the polarity can be reversed.

In addition, it may be configured such that the polarity of the driving current in each pixel is reversed for each pixel in either the direction in which the scanning line extends or the direction in which the data line extends.

Description of the drawings

FIG. 1 is an explanatory diagram schematically showing a display device to which the present invention is applied and a formation area of a bank layer formed therein.

Fig. 2 is a block diagram showing the basic structure of a display device to which the present invention is applied.

Fig. 3 is an enlarged plan view showing the pixels of the display device according to the first embodiment of the present invention.

Fig. 4 is a cross-sectional view taken along the line AA' in Fig. 3.

Fig. 5 is a cross-sectional view taken along the line BB' of Fig. 3.

Fig. 6(A) is a cross-sectional view taken along the line CC' of Fig. 3, and Fig. 6(B) is a cross-sectional view of a structure in which the formation area of the bank layer is not expanded before covering the relay electrode.

FIG. 7 is a graph showing the IV characteristics of the light-emitting element used in the display device shown in FIG. 1.

FIG. 8 is a process cross-sectional view showing a method of manufacturing a display device to which the present invention is applied.

FIG. 9 is a block diagram showing a modified example of the display device shown in FIG. 1.

FIG. 10(A) is a cross-sectional view showing a dummy wiring layer formed in the display device shown in FIG. 9, and FIG. 10(B) is a plan view thereof.

Fig. 11 is a block diagram showing a modification of the display device shown in Fig. 3.

FIG. 12(A) is an enlarged plan view of pixels formed in the display device shown in FIG. 11, and FIG. 12(B) is a cross-sectional view thereof.

FIG. 13 is an equivalent circuit diagram showing the structure of two pixels in which the drive current is inverted in the display device according to the second embodiment of the present invention.

Fig. 14 is a waveform diagram of each signal for driving one of the two pixels shown in Fig. 13.

FIG. 15 is a waveform diagram of each signal used to drive the other pixel of the two pixels shown in FIG. 13.

FIG. 16 is a cross-sectional view showing the structure of a light-emitting element constructed in two pixels shown in FIG. 13.

FIG. 17 is an explanatory diagram showing the arrangement of pixels in the display device shown in FIG. 13.

Fig. 18 is an explanatory diagram showing the arrangement of pixels in a display device according to the third embodiment of the present invention.

Fig. 19 is an explanatory diagram showing the arrangement of pixels in a display device according to the fourth embodiment of the present invention.

Fig. 20 is an explanatory diagram showing the arrangement of pixels in a display device according to the fifth embodiment of the present invention.

Fig. 21 is an explanatory diagram showing the arrangement of pixels in a display device according to the sixth embodiment of the present invention.

Fig. 22 is a block diagram of a conventional display device.

FIG. 23(A) is an enlarged plan view of pixels formed in the display device shown in FIG. 22, and FIG. 23(B) is a cross-sectional view thereof.

[Description of Symbols] 1 display device 2 display section 3 data side drive circuit 4 scan side drive circuit 5 inspection circuit 6 mounting pads 7, 7A, 7B pixels 10 transparent substrate 20 first TFT 21 gate electrode of the first TFT 30 second TFT 31 Gate electrodes 40, 40A, 40B of the second TFT Light emitting element 41 Pixel electrode 42 Hole injection layer 43 Organic semiconductor film

45 thin aluminum electrode containing lithium 46ITO film 50 gate color fringe film 51 first interlayer insulating film 52 second interlayer insulating film DA dummy wiring layer bank bank cap holding capacitor cline capacitor line com common power supply line gate, gateA , GateB scanning lines op, opA, opB opposing electrodes sig, sigA, sigB data lines st, stA, stB potential holding electrodes specific embodiments of the present invention will be described with reference to the accompanying drawings.

[Embodiment 1] (Overall structure of active matrix substrate) FIG. 1 is a block diagram schematically showing the overall layout of a display device, and FIG. 2 is an equivalent circuit diagram of an active matrix constructed therein.

As shown in the figure, in the display device 1 of this form, the central part of the transparent substrate 10 as the base serves as the display portion 2. In the outer peripheral portion of the transparent substrate 10, a data-side driving circuit 3 and an inspection circuit 5 outputting image signals are formed at both ends of the data line sig, and a scanning-side driving circuit 4 outputting a scanning signal is formed at both ends of the scanning line gate. In these driving circuits 3 and 4, an N-type TFT and a P-type TFT constitute a complementary TFT, and the complementary TFT constitutes a shift register, a level shifter, an analog switch, and the like. Furthermore, on the transparent substrate 10, between the data-side drive circuit 3 and the outer peripheral area is formed a mounting pad 6 as a terminal group for inputting image signals, various potentials, and pulse signals.

(Arrangement of common power supply lines and pixels) In the display device 1, the same as the active matrix substrate of the liquid crystal display device, a plurality of scanning lines gate are formed on the transparent substrate 10 and the scanning lines are formed on the transparent substrate 10 and cross the extension direction of the scanning line gate. A plurality of data lines sig extending in the direction, as shown in FIG. 2, these data lines sig and scanning lines gate constitute pixels 7 formed in a matrix.

Each of these pixels 7 constitutes a first TFT 20 that supplies a scanning signal to the gate electrode 21 (first gate electrode) via the scanning line gate. One of the source-drain regions of the TFT 20 is electrically connected to the data line sig, and the other is electrically connected to the potential holding electrode st. The capacitance line cline is arranged in parallel with respect to the scanning line gate, and a holding capacitance cap is formed between the capacitance line cline and the potential holding electrode st. Therefore, if the first TFT 20 is selected by the scanning signal and the first TFT 20 is turned on, the image signal is written into the holding capacitor cap from the data line sig through the first TFT 20.

The gate electrode 31 (second gate electrode) of the second TFT 30 is electrically connected to the potential holding electrode st. One of the source-drain regions of the TFT 30 is conductively connected to the common power supply line com, and the other is conductively connected to an electrode (a pixel electrode described later) of the light-emitting element 40. The common power supply line com is maintained at a constant potential. Therefore, when the second TFT 30 is turned on, the current of the common power supply line com flows to the light-emitting element 40 through the TFT, so that the light-emitting element 40 emits light.

In this form, a plurality of pixels 7 are arranged on both sides of the common power supply line com, and a drive current is supplied between the pixel 7 and the common power supply line. The two data lines sig pass to the pixel 7 The opposite side of the above-mentioned common power supply line. That is, a data line sig, a pixel group connected to it, a common power supply line com, a pixel group connected to it, and a data line sig that supplies a pixel signal to the pixel group are taken as one unit, and they are The scanning lines gate are repeatedly arranged in the extending direction, and a common power supply line com is used to supply driving current to the pixels 7 in the two columns. Therefore, in the present embodiment, between the two pixels 7 arranged to sandwich the common power supply line com, the first TFT 20, the second TFT 30, and the light-emitting element 40 are arranged in line symmetry with the common power supply line com as the center. The conductive connection between these elements and each wiring layer becomes easy.

In this way, in this form, since one common power supply line com is used to drive the pixels of two columns, the common power supply line is compared with the case where the common power supply line com is formed in each pixel group of one column. The number of com is only 1/2, and there is no need to ensure a gap between the common power supply line com and the data line sig formed between the same layer. Therefore, since the wiring area can be narrowed on the transparent substrate 10, the ratio of the light-emitting area in each pixel area can be increased accordingly, and the display performance such as brightness and contrast can be improved.

Furthermore, since the two columns of pixels are connected to one common power supply line com in this way, the data line sig is in a state of paralleling every two, and as a result, images are supplied to the pixel groups of each column. signal.

(Pixel Structure) The structure of each pixel 7 of the display device 1 configured in this manner will be described in detail with reference to FIGS. 3 to 6(A).

3 is an enlarged plan view showing three pixels 7 among a plurality of pixels 7 formed in the display device 1 of the present embodiment, and FIGS. 4, 5, and 6(A) are respectively A-A The cross-sectional view of the'line, the cross-sectional view of the line B-B', and the cross-sectional view of the line C-C'.

First, as shown in FIG. 4, at a position corresponding to the line AA' in FIG. 3, an island-shaped silicon for forming the first TFT 20 is formed in each of the pixels 7 on the transparent substrate 10. The film 200 has a gate insulating film 50 formed on its surface. In addition, a gate electrode 21 (a part of the scanning line gate) is formed on the surface of the gate insulating film 50, and source-drain regions 22 and 23 are formed in a self-aligned manner with respect to the gate electrode 21. A first interlayer insulating film 51 is formed on the surface side of the gate insulating film 50, and the data line sig and the potential holding electrode st are electrically connected to the source through contact holes 61 and 62 formed in the interlayer insulating film. Drain area 22,23 on.

A capacitor line cline is formed in the same layer as the scanning line gate or gate electrode 21 (between the gate insulating film 50 and the first interlayer insulating film 51) so as to be parallel to the scanning line gate in each pixel 7. The extended portion st1 of the sustain electrode st overlaps the capacitor line cline through the first interlayer insulating film 51. Therefore, the capacitance line cline and the extended portion st1 of the potential holding electrode st constitute a holding capacitance cap with the first interlayer insulating film 51 as an electrolyte membrane. Furthermore, a second interlayer insulating film 52 is formed on the surface side of the potential holding electrode st and the data line sig.

As shown in FIG. 5, at a position corresponding to BB' in FIG. 3, the surfaces of the first interlayer insulating film 51 and the second interlayer insulating film 52 formed on the transparent substrate 10 are The data line sig corresponding to the pixel 7 is in a state of two parallel.

As shown in FIG. 6(A), at a position corresponding to CC' in FIG. 3, an island-shaped silicon film 300 for forming the second TFT 30 is formed, and a gate insulating film 50 is formed on the surface thereof. , So that it straddles the two pixels 7 sandwiching the common power supply line com on the transparent substrate 10. On the surface of the gate insulating film 50, a gate electrode 31 is formed in each of the pixels 7 so as to sandwich the common power supply line com to form a source-drain in a self-aligned manner on the gate electrode 31. District 32, 33. A first interlayer insulating film 51 is formed on the surface side of the gate insulating film 50, and the relay electrode 35 is electrically connected to the source-drain region 32 through a contact hole 63 formed in the interlayer insulating film. On the other hand, the common power supply line com passes through the contact hole 64 of the first interlayer insulating film 51, and conducts conductivity with the portion at the center of the silicon film 300 that becomes the common source-drain region 33 in the two pixels 7 connection. A second interlayer insulating film 52 is formed on the surface side of the common power supply line com and the relay electrode 35. On the surface side of the second interlayer insulating film 52, a pixel electrode 41 made of an ITO film is formed. The pixel electrode 41 is electrically connected to the relay electrode 35 through a contact hole 65 formed in the second interlayer insulating film 52, and is electrically connected to the source-drain of the second TFT 30 through the relay electrode 35 District 82.

Here, the pixel electrode 41 constitutes one electrode of the light-emitting element 40. That is, the hole injection layer 42 and the organic semiconductor film 43 are laminated on the surface of the pixel electrode 41, and then on the surface of the organic semiconductor film 43, a counter electrode op composed of a metal film of aluminum, calcium, etc. containing lithium is formed. . The opposing electrode op is a common electrode formed at least on the pixel area or in a stripe shape, and it maintains a constant potential.

In the light-emitting element 40 configured in this manner, the opposing electrode op and the pixel electrode 41 are applied with voltages as positive and negative electrodes, respectively. As shown in FIG. 7, organic flow passes through the region where the applied voltage exceeds the threshold voltage Vth. The current (drive current) of the semiconductor film 43 sharply increases. As a result, the light-emitting element 40 emits light as an electroluminescence element or an LED element, and the light of the light-emitting element 40 is reflected by the counter electrode op, passes through the transparent pixel electrode 41 and the transparent substrate 10 and is emitted.

Since the driving current for performing such light emission flows through the current path constituted by the counter electrode op, the organic semiconductor film 43, the hole injection layer 42, the pixel electrode 41, the second TFT 30, and the common power supply line com, if the second TFT 30 changes In the off state, no current flows. In the display device 1 of this embodiment, when the first TFT 20 is selected by the scanning signal and the first TFT 20 is turned on, the image signal is written from the data line sig through the first TFT 20 to the holding capacitor cap. Therefore, even if the first TFT 20 is turned off, the gate electrode of the second TFT 30 maintains a potential corresponding to the image signal due to the holding capacitor cap, so the second TFT 30 is in the original on state. Therefore, the driving current continues to flow into the light-emitting element 40, and the pixel is in the original lighting state. This state is maintained until new image data is written into the holding capacitor cap and the second TFT 30 is turned off.

(Method of Manufacturing Display Device) In the method of manufacturing the display device 1 configured in this manner, the steps up to the step of manufacturing the first TFT 20 and the second TFT 30 on the transparent substrate 10 and the step of manufacturing the active matrix substrate of the liquid crystal display device 1 They are almost the same, so the outline will be described with reference to FIG.

FIG. 8 is a process cross-sectional view schematically showing a process of forming each component part of the display device 1.

That is, as shown in FIG. 8(A), for the transparent substrate 10, TEOS (tetraethoxysilane) and oxygen gas are used as the raw material gas, and the thickness is about 2000-5000 angstroms by the plasma CVD method as needed. A base protective film (not shown in the figure) composed of a silicon oxide film. Next, the temperature of the substrate is set to approximately 350° C., and a semiconductor film 100 composed of an amorphous silicon film with a thickness of approximately 300 to 700 angstroms is formed on the surface of the base protective film by a plasma CVD method. Next, the semiconductor film 100 made of an amorphous silicon film is continuously subjected to a crystallization process such as laser annealing or a solid phase growth method to crystallize the semiconductor film 100 into a polycrystalline silicon film. In the laser annealing method, for example, an excimer laser is used, and a line beam with a beam shape having a long side dimension of 400 mm is used, and its output intensity is, for example, 200 mJ/cm 2. Regarding the line beam, the line beam is scanned so that a portion corresponding to 90% of the peak value of the laser intensity in the short-side dimension direction overlaps in each area.

Next, as shown in FIG. 8(B), the semiconductor film 100 is patterned and etched to form island-shaped semiconductor films 200 and 300. For the surface, TEOS (tetraethoxysilane) and oxygen gas are used as raw materials. Gas, a gate insulating film 50 composed of a silicon oxide film or a silicon nitride film with a thickness of about 600 to 1500 angstroms is formed by a plasma CVD method.

Next, as shown in FIG. 8(C), after a conductive film composed of a metal film of aluminum, tantalum, molybdenum, titanium, tungsten, etc., is formed by a sputtering method, pattern etching is performed to form a part of the scan line gate The gate electrodes 21,31. In this step, the capacitor line cline is also formed. Furthermore, 310 in the figure is an extension of the gate electrode 31.

In this state, a high concentration of phosphorus ions or boron ions are implanted to form source-drain regions 22, 23, 32, 33 in the silicon thin films 200, 300 for the gate electrodes 21, 31 in a self-aligned manner. In addition, the portions where no impurities are introduced become channel regions 27 and 37.

Next, as shown in FIG. 8(D), after the first interlayer insulating film 51 is formed, contact holes 61, 62, 63, 64, 69 are formed, the data line sig is formed, and the capacitor line cline and the gate are overlapped. The potential holding electrode st of the extension portion st1 on the extension portion 310 of the electrode 31, the common power supply line com and the relay electrode 35. As a result, the potential holding electrode st is electrically connected to the gate electrode 31 through the contact hole 69 and the extension portion 310. In this way, the first TFT 20 and the second TFT 30 are formed. In addition, a holding capacitance cap is formed by the capacitance line cline and the extended portion st1 of the potential holding electrode st.

Next, as shown in FIG. 8(E), a second interlayer insulating film 52 is formed. In this interlayer insulating film, a contact hole 65 is formed in a portion corresponding to the relay electrode 35. Next, after the ITO film is formed on the entire surface of the second interlayer insulating film 52, pattern etching is performed to form the pixel electrode 41 electrically connected to the source-drain region of the second TFT 30 through the contact hole 65. .

Next, as shown in FIG. 8(F), after a black resist layer is formed on the surface side of the second interlayer insulating film 52, the resist is left to surround the space where the light emitting element 40 should be formed. The region of the hole injection layer 42 and the organic semiconductor film 43 forms a bank layer bank. Here, regardless of whether it is a case where the organic semiconductor film 43 is formed independently in each pixel or a case where it is formed in a stripe shape along the data line sig, the bank layer bank is formed into a shape corresponding to it. , The manufacturing methods related to this form can be applied.

Next, the liquid material (precursor) constituting the hole injection layer 42 is ejected from the inkjet head IJ to the inner region of the bank layer bank, and the hole injection layer 42 is formed in the inner region of the bank layer bank. Similarly, the liquid material (precursor) constituting the organic semiconductor film 43 is ejected from the inkjet head IJ to the inner region of the bank layer bank, and the organic semiconductor film 43 is formed in the inner region of the bank layer bank. Here, since the bank layer bank is made of resist, it is water-repellent. In contrast, since the precursor of the organic semiconductor film 43 mainly uses a hydrophilic solvent, the coating area of the organic semiconductor film 43 is reliably determined by the bank layer bank and does not overflow into adjacent pixels.

In the case where the organic semiconductor film 43 and the hole injection layer 42 are formed by the inkjet method in this way, in order to improve the operation efficiency and the accuracy of the injection position, in this embodiment, as shown in FIG. The pitch P between the centers of the regions where the organic semiconductor film 43 is formed is made equal between any pixels 7 adjacent in the extending direction. Therefore, as indicated by the arrow Q, since the material of the organic semiconductor film 43 can be ejected from the inkjet head IJ at equal intervals along the extending direction of the scanning line gate, there is an advantage of high operating efficiency. In addition, the movement control mechanism of the inkjet head IJ becomes simple, and at the same time the accuracy of the pouring position is improved.

After that, as shown in FIG. 8(G), a counter electrode op is formed on the surface side of the transparent substrate 10. Here, the counter electrode op is formed at least on the entire surface of the pixel area or in a stripe shape. However, when the counter electrode op is formed in a stripe shape, after a metal film is formed on the entire surface of the transparent substrate 10 , It is patterned and etched into strips.

Furthermore, since the bank layer bank is made of black resist, it is left as it is, and as described below, it is used as a black matrix BM and an insulating layer for reducing parasitic capacitance.

TFTs are also formed in the data-side driver circuit 3 and the scanning-side driver circuit 4 shown in FIG. 1, but these TFTs can be performed by using all or part of the process of forming the TFT in the pixel 7 described above. Therefore, as a result, the TFT constituting the driving circuit is also formed in the same interlayer as the TFT of the pixel 7.

In addition, with regard to the above-mentioned first TFT 20 and second TFT 30, both of them are N-type, both are P-type, one is N-type and the other is P-type. A combination of these types can also be used to form a TFT by a well-known method, so the description is omitted.

(Formation area of bank layer) In this embodiment, the above-mentioned bank layer bank is formed for the entire peripheral area of the transparent substrate 10 shown in FIG. 1 (the formation area is hatched). Therefore, both the data side drive circuit 3 and the scan side drive circuit 4 are covered by the bank layer bank. Therefore, even if the opposing electrode op overlaps the formation regions of these driving circuits, the bank layer bank is interposed between the wiring layer of the driving circuit and the opposing electrode op. Therefore, since capacitance can be prevented from being parasitic in the driving circuits 3 and 4, the load of the driving circuits 3 and 4 can be reduced, and the power consumption can be reduced or the display operation speed can be improved.

In addition, in this form, as shown in FIGS. 3 to 5, a bank layer bank is formed so as to overlap the data line sig. Therefore, since the bank layer bank is interposed between the data line sig and the counter electrode op, it is possible to prevent the capacitance from being parasitic in the data line sig. As a result, since the load of the data-side drive circuit 3 can be reduced, it is possible to reduce power consumption or increase the speed of the display operation.

Here, unlike the data line sig, a large current for driving the light emitting element 40 flows to the common power supply line com, and a driving current is supplied to the pixels in the two columns. Therefore, regarding the common power supply line com, the line width is set to be wider than the line width of the data line sig, so that the resistance value per unit length of the common power supply line com is smaller than the resistance value per unit length of the data line sig. Under such design conditions, in this form, the bank layer bank is formed so as to overlap the common power supply line com. When the formation area of the organic semiconductor film 43 is determined, the width of the bank layer bank formed therein is overlapped with The width dimension of the bank layer bank on the two data lines sig is the same. Therefore, as described above, it is suitable for the organic semiconductor film to be formed between any pixels 7 adjacent in the extending direction of the scanning line gate. 43 is a structure in which the pitch P between the centers of the forming area is equal.

Furthermore, in this embodiment, as shown in FIGS. 3, 4, and 6(A), in the formation region of the pixel electrode 41, in the region where the formation region of the first TFT 20 and the formation region of the second TFT 30 overlap The embankment layer bank is also formed. That is, as shown in FIG. 6(B), if the bank layer bank is not formed in the region overlapping with the relay electrode 35, for example, even if the driving current flows between the opposing electrode op, the organic semiconductor film 43 emits light. Since this light is also sandwiched by the relay electrode 35 and the counter electrode op and is not emitted, it does not contribute to the display. The drive current flowing in such a portion that does not contribute to the display can be said to be an ineffective current from the perspective of display. In this aspect, since the bank layer bank is formed in the portion where such invalid current should flow, the driving current is prevented from flowing there, and therefore, useless current can be prevented from flowing into the common power supply line com. Therefore, the common power supply line com can be narrowed accordingly.

In addition, if the bank layer bank made of black resist is left as described above, the bank layer bank functions as a black matrix, and the display quality such as brightness and contrast can be improved. That is, in the display device 1 related to this aspect, since the counter electrode op is formed on the entire surface of the transparent substrate 10 on the surface side, or is formed in a stripe shape over a wide area, it is reflected by the counter electrode op The light makes the contrast drop. In this embodiment, the black resist is used to form the bank layer bank with the function of suppressing parasitic capacitance while determining the organic semiconductor film 43. Therefore, the bank layer bank also functions as a black matrix, which shields from The reflected light of the opposing electrode op has the advantage of high contrast. In addition, since the bank layer bank can be used to determine the light-emitting area in a self-aligned manner, there is no need to use the bank layer bank as the black matrix but another metal layer as the black matrix, which becomes a problem with the light-emitting area. Align the margin.

[Improved example of the above aspect] In the above aspect, the pixels 7 are arranged on both sides of the common power supply line com, and the driving current flows between the pixel 7 and the common power supply line com, and the two data lines sig are in parallel. Pass through the side opposite to the above-mentioned common power supply line com with respect to the pixel 7. Therefore, there is a concern that crosstalk occurs between the two data lines sig. Therefore, in this embodiment, as shown in FIGS. 9 and 10 (A), (B), the dummy wiring layer DA is formed at a position corresponding to between the two data lines sig. As the dummy wiring layer DA, for example, an ITO film DA1 formed at the same time as the pixel electrode 41 can be used. In addition, as the dummy wiring layer DA, an extension portion DA2 from the capacitor line cline may be formed between the two data lines sig. Both of these can also be used as the dummy wiring layer DA.

If configured in this way, a different wiring layer DA is passed between the two parallel data lines sig. Therefore, by placing such wiring layers DA (DA1, DA2) in at least one horizontal scanning period of the image Built in a fixed potential to prevent the above-mentioned crosstalk. That is, since the film thickness of the first interlayer insulating film 51 and the second interlayer insulating film 52 is approximately 1 micrometer, and the interval between the two data lines sig is approximately 2 micrometers or more, they are connected to each data line sig and the dummy wiring. Compared with the capacitance formed between the layers DA (DA1, DA2), the capacitance formed between the two data lines sig is sufficiently small and can be ignored. Therefore, since the high frequency signal leaking from the data line sig is absorbed by the dummy wiring layers DA1 and DA2, the crosstalk between the two data lines sig can be prevented.

In addition, among the plurality of data lines sig, it is preferable to sample the image signal at the same timing between two adjacent data lines sig. With this configuration, since the potential changes during sampling between the two data lines sig occur at the same time, it is possible to more reliably prevent crosstalk between the two data lines sig.

[Another configuration example of the holding capacitor] In the above-mentioned form, the capacitor line cline is formed in the holding capacitor cap. However, as explained in the prior art, the polysilicon used to constitute the TFT may also be used. The film constitutes the holding capacitor cap.

In addition, as shown in FIG. 11, a holding capacitance cap may be formed between the common power supply line com and the potential holding electrode st. At this time, as shown in FIGS. 12(A) and (B), the extended portion 310 of the gate electrode 31 for conductively connecting the potential holding electrode st and the gate electrode 31 is extended to the lower layer side of the common power supply line com, The first interlayer insulating film 51 located between the extension portion 310 and the common power supply line com is used as a dielectric film to constitute a holding capacitor cap.

[Embodiment 2] In Embodiment 1 described above, the light-emitting element 40 is driven by the driving current of the same polarity in any pixel 7, but as explained below, it can also be configured such that the driving current is The plurality of pixels 7 passing between the pixel 7 and the same common power supply line com include two types of pixels 7 in which the light-emitting elements 40 are driven by the driving current with the polarity inverted in the same number.

An example of such a configuration will be described with reference to FIGS. 13 to 17. FIG. 13 is a block diagram of a configuration in which two types of pixels of the light-emitting element 40 are driven by a driving current with a polarity inverted. 14 and 15 are respectively explanatory diagrams of the scanning signal, the image signal, the potential of the common power supply line, and the potential of the potential holding electrode when the light-emitting element 40 is driven with a driving current with a polarity inverted.

As shown in FIG. 13, in any of the present form and the following form, when the light-emitting element 40 is driven by the drive current i with the polarity inverted, as indicated by the arrow E, the drive current changes from the common In the pixel 7A through which the power supply line com flows, the n-channel type is used to constitute the first TFT 20. As indicated by the arrow F, in the pixel 7B where the driving current flows to the common power supply line com, the p-channel type is used to constitute the first TFT 20. 1TFT20. Therefore, scanning lines gateA and gateB are formed in each of these two types of pixels 7A and 7B. In addition, in this embodiment, the p-channel type is used to form the second TFT 30 of the pixel 7A, and the n-channel type is used to form the second TFT 30 of the pixel 7B. In any of the pixels 7A and 7B, the first TFT 20 and The conductivity type of the second TFT 30 is reversed. Therefore, regarding the image signals respectively supplied through the data line sigA corresponding to the pixel 7A and the data line sigB corresponding to the pixel 7B, the polarities are also reversed as described below.

Furthermore, in each of the pixels 7A and 7B, since the light-emitting element 40 is driven by the drive current i whose polarity is reversed, as described below, the potential of the opposing electrode op is measured by the common power supply line com. When the potential is used as a reference, it must also be configured as reverse polarity. Therefore, regarding the counter electrode op, the structure is such that the pixels 7A and 7B through which the drive current i of the same polarity flows are connected to each other, and a predetermined potential is applied to each of them.

Therefore, in each of FIGS. 14 and 15, for the pixels 7A and 7B, the waveforms of the scanning signals supplied through the scanning lines gateA and gateB, the waveforms of the image signals supplied through the data lines sigA and sigB, and the corresponding The potential of the set electrode op and the potential of the potential holding electrodes stA and stB are expressed on the basis of the potential of the common power supply line com, and each signal is set between the pixels 7A and 7B to be either during the on period or the off period. The period becomes reverse polarity.

In addition, as shown in FIGS. 16(A) and (B), the respective pixels 7A and 7B constitute light-emitting elements 40A and 40B having different structures. That is, in the light-emitting element 40A formed in the pixel 7A, a pixel electrode 41 made of an ITO film, a hole injection layer 42, an organic semiconductor film 43, and a counter electrode are laminated in the following order from the lower layer side to the upper layer side. opA. In contrast, in the light-emitting element 40B formed in the pixel 7B, a pixel electrode 41 made of an ITO film and a light-transmitting aluminum electrode containing lithium are laminated in the following order from the lower layer side to the upper layer side. 45. Organic semiconductor layer 43, hole injection layer 42, ITO film layer 46, counter electrode opB. Therefore, even if a driving current of opposite polarity flows between the light-emitting elements 40A and 40B, since the structure of the electrode layer directly in contact with the hole injection layer 42 and the organic semiconductor layer 43 is the same, the light-emitting elements 40A, 40B The luminous characteristics are the same.

When forming these two types of light-emitting elements 40A and 40B, since both the organic semiconductor film 43 and the hole injection layer 42 are formed on the inner side of the bank layer bank by the inkjet method, the manufacturing process does not occur even if the vertical positions are reversed. Becomes complicated. In addition, in the light-emitting element 40B, compared with the light-emitting element 40A, an aluminum electrode 45 containing lithium and an ITO film 46 are added which are thinner than the light-transmitting element. However, even if the aluminum electrode 45 containing lithium becomes an object The structure laminated in the same region of the element electrode 41 does not hinder display, and even if the ITO film layer 46 has a structure laminated in the same region as the counter electrode opB, it does not hinder display. Therefore, the aluminum electrode 45 containing lithium and the pixel electrode 41 may be patterned separately, but the same resist mask may also be used for pattern etching together. Similarly, the ITO film layer 46 and the opposing electrode opB may be patterned separately, but the same resist mask may also be used for pattern etching. Of course, it is also possible to form the aluminum electrode 45 containing lithium and the ITO film layer 46 only in the inner region of the bank layer bank.

In this way, the light-emitting elements 40A, 40B can be driven by the driving current with the polarity inverted in each of the pixels 7A, 7B. On this basis, the two types of pixels 7A, 7B described above are arranged as shown in FIG. . In this figure, the pixel with a sign (-) corresponds to the pixel 7A described in Figs. 13, 14, and 16, and the pixel with a sign (+) corresponds to the pixel in Figs. 13, 15 Pixel 7B as described in Fig. 16. Furthermore, in FIG. 17, illustration of the scan lines gateA and gateB and the data lines sigA and sigB is omitted.

As shown in FIG. 17, in this form, the polarity of the driving current in each pixel in the extending direction of the data lines sigA and sigB is the same, and in each pixel in the extending direction of the scanning lines gateA and gateB The polarity of the driving current is reversed for each pixel. In addition, as shown by the one-dot chain line respectively corresponding to the formation areas of the opposing electrodes opA and opB for each pixel, any opposing electrodes opA and opB are constructed in such a way that driving currents of the same polarity are passed through The pixels 7A and 7B are connected to each other. That is, the opposing electrodes opA and opB are respectively formed in strips along the extending direction of the data lines sigA and sigB. When the potential of the common power supply line com is used as a reference, a negative potential and a positive potential are applied to each of the opposing electrodes opA and opB. Potential.

Therefore, as a result, the drive current i in the directions shown by the arrows E and F in FIG. 13 flows between the pixels 7A and 7B and the common power supply line com, respectively. Therefore, since the current flowing through the common power supply line com is substantially canceled between the drive currents i of different polarities, the current flowing through the common power supply line com can be reduced. Therefore, since the common power supply line com can be made thinner accordingly, the ratio of the light-emitting area of the pixel area in the pixels 7A and 7B can be increased, and the display performance such as brightness and contrast can be improved.

[Embodiment 3] Furthermore, from the viewpoint of arranging the pixels so that the driving current flows between the pixel and the same common power supply line com with the opposite polarity, each pixel may be as shown in the figure. Configure as shown in 18. In addition, in this embodiment, since the structure of each pixel 7A, 7B is the same as that of the second embodiment, the description is omitted. In Fig. 18 and the following description of Fig. 19 to Fig. 21 for explaining the various modes, use The symbol (-) indicates that it corresponds to the pixel 7A described in FIGS. 13, 14, and 16, and the symbol (+) indicates that it corresponds to the pixel 7B described in FIG. 13, FIG. 15, and FIG. 16.

As shown in FIG. 18, in this form, the polarity of the driving current in each pixel 7A, 7B in the extending direction of the data lines sigA, sigB is the same, and the driving current in the extending direction of the scanning lines gateA, gateB is the same. In the direction, the polarity of the driving current in each pixel 7A, 7B is reversed every two pixels.

When constructed in this manner, as a result, the drive current i in the directions shown by arrows E and F in FIG. 13 flows between the pixels 7A and 7B and the common power supply line com, respectively. Therefore, since the current flowing through the common power supply line com is canceled between the drive currents i of different polarities, the drive current flowing through the common power supply line com can be reduced. Therefore, since the common power supply line com can be made thinner accordingly, the ratio of the light-emitting area of the pixel area in the pixels 7A and 7B can be increased, and the display performance such as brightness and contrast can be improved. In addition, in this embodiment, since the polarity of the driving current is inverted every two pixels in the extending direction of the scanning lines gateA and gateB, even between pixels driven by the driving current of the same polarity Alternatively, the common counter electrodes opA and opB may be formed in stripes for two adjacent columns of pixels. Therefore, the number of counter electrodes opA and opB can be reduced to 1/2. In addition, compared with the stripes of each pixel, the resistance of the opposing electrodes opA and opB can be reduced, so that the influence of the voltage drop of the opposing electrodes opA and opB can be reduced.

[Embodiment 4] In addition, from the viewpoint of arranging the pixels so that the driving current flows between the pixel and the same common power supply line com with the opposite polarity, each pixel can also be arranged as shown in FIG. 19 Configure it as shown in.

As shown in FIG. 19, in this form, the polarity of the driving current in each pixel 7A, 7B is the same in the extending direction of the scanning lines gateA, gateB, and the extending direction of the data lines sigA, sigB is the same. In the direction, the polarity of the driving current in each pixel 7A, 7B is reversed every pixel.

In the case of configuring in this way, as in the second or third embodiment, the current flowing through the common power supply line com is canceled between the drive currents of different polarities, so that the amount of current flowing through the common power supply line com can be reduced. Drive current. Therefore, since the common power supply line com can be made thinner accordingly, the ratio of the light-emitting area of the pixel area in the pixels 7A and 7B can be increased, and the display performance such as brightness and contrast can be improved.

[Embodiment 5] In addition, from the viewpoint of arranging the pixels so that the driving current flows between the pixel and the same common power supply line com with the opposite polarity, each pixel can also be arranged as shown in Fig. 20 Configure it as shown in.

As shown in FIG. 20, in this form, the polarity of the driving current in each pixel 7A, 7B in the extending direction of the scanning lines gateA, gateB is the same, and the polarity of the driving current in the extending direction of the data lines sigA, sigB is the same. In the direction, the polarity of the driving current in each pixel 7A, 7B is reversed every two pixels.

In the case of configuring in this manner, as in the third embodiment, since the current flowing through the common power supply line com is canceled between drive currents of different polarities, the drive current flowing through the common power supply line com can be reduced. Therefore, since the common power supply line com can be made thinner accordingly, the ratio of the light-emitting area of the pixel area in the pixels 7A and 7B can be increased, and the display performance such as brightness and contrast can be improved. In addition, in this embodiment, since the polarity of the driving current is inverted every two pixels in the extending direction of the scanning lines gateA and gateB, even between pixels driven by the driving current of the same polarity Alternatively, the common counter electrodes opA and opB may be formed in stripes for two adjacent columns of pixels. Therefore, the number of counter electrodes opA and opB can be reduced to 1/2. In addition, compared with the stripes of each pixel, the resistance of the opposing electrodes opA and opB can be reduced, so that the influence of the voltage drop of the opposing electrodes opA and opB can be reduced.

[Embodiment 6] In addition, from the viewpoint of arranging the pixels so that the driving current flows between the pixel and the same common power supply line com with the opposite polarity, each pixel can also be arranged as shown in FIG. 21 Configure it as shown in.

As shown in FIG. 21, in the present embodiment, the polarity of the drive current in each pixel 7A, 7B in either the extending direction of the scanning lines gateA, gateB and the extending direction of the data lines sigA, sigB is It is inverted every 1 pixel.

In the case of configuring in this way, as in Embodiments 2 to 4, the current flowing through the common power supply line com is canceled between the drive currents of different polarities, so that the amount of current flowing through the common power supply line com can be reduced. Drive current. Therefore, since the common power supply line com can be made thinner accordingly, the ratio of the light-emitting area of the pixel area in the pixels 7A and 7B can be increased, and the display performance such as brightness and contrast can be improved.

If the pixels 7A and 7B are arranged in this way, the strip-shaped counter electrodes opA and opB cannot correspond to them. However, in spite of this, the counter electrodes opA and opB are formed in each pixel 7A and 7B. The wiring layer only needs to connect the opposing electrodes opA and opB to each other.

The possibility of utilization of the invention As explained above, in the display device related to the present invention, since the pixels are arranged on both sides of the common power supply line, the driving current passes between the pixel and the common power supply line. Therefore, one common power supply line can be used for the pixels in the two columns. Therefore, since the formation area of the common power supply line can be narrowed compared with the case where the common power supply line is formed for each pixel group, it is possible to increase the ratio of the light-emitting area in the pixel and improve the display performance such as brightness and contrast. .

In addition, in the case where a plurality of pixels through which a driving current passes between the pixel and the same common power supply line includes two types of pixels in which the above-mentioned light-emitting element is driven by a driving current whose polarity is reversed, because In one common power supply line, the driving current flowing from the common power supply line to the light-emitting element and the driving current flowing from the light-emitting element to the common power supply line in the opposite direction cancel out, so the driving current flowing to the common power supply line can be reduced. Therefore, since the common power supply line can be made thinner accordingly, the ratio of the light-emitting area in the pixel can be increased, and the display performance such as brightness and contrast can be improved.