A programmable gate array containing a programmable computing unit

Programmable gate array technology field containing programmable computing unit

[0001] The present invention relates to the field of integrated circuits, and more specifically, to programmable gate arrays.

Background technique

[0002] Programmable gate arrays belong to semi-custom integrated circuits, that is, through back-end process or on-site programming, the customization of logic circuits is realized. US Patent 4,870,302 discloses a programmable gate array. It contains multiple programmable logic units (conf igurab 1 e logic element, or conf igurable logic block) and programmable interconnect (configurable interconnect, or programmable interconnect). Among them, the programmable logic unit can selectively realize shift, logical negation, AND (logical AND), OR (logical sum), NOR (and negation), NAND (NAND), X0R (exclusive OR) under the control of the setting signal. ), + (arithmetic addition),-(arithmetic subtraction) and other functions; programmable connection can selectively realize the connection and disconnection between two interconnection lines under the control of the setting signal.

[0003] At present, many applications involve the calculation of complex functions. Complex functions generally contain multiple independent variables, which are a combination of basic functions. The basic function contains one or a few independent variables, examples of which include transcendental functions, such as exponential (exp), logarithm (log), trigonometric function (sina, cos), etc. In order to ensure the execution speed, high-performance applications require hardware to implement complex functions. In the existing programmable gate array, complex functions are implemented by solidifying the computing unit. These solidified computing units are part of the hard block, and their circuits have been solidified and cannot be reconfigured. Obviously, curing the computing unit will limit the further application of programmable gate arrays. In order to overcome this difficulty, the present invention promotes the concept of programmable gate circuit to make the solidified computing unit programmable. Specifically, in addition to programmable logic units, programmable gates also contain programmable computing units. The programmable calculation unit can selectively implement any one of a variety of functions.

Summary of the invention

[0004] The main purpose of the present invention is to promote the application of programmable gate circuits in the field of complex calculations.

[0005] Another object of the present invention is to provide a programmable gate circuit whose logic function can be customized, and its calculation function can also be customized.

[0006] Another object of the present invention is to provide a programmable gate array with more flexible and powerful computing capabilities.

[0007] Another object of the present invention is to provide a programmable gate array with a smaller chip area and lower cost.

[0008] In order to achieve these and other objectives, the present invention proposes a programmable gate array. It is a monolithic chip and contains multiple programmable computing units, multiple programmable logic units and multiple programmable connections. They are all horizontally integrated in the same chip, that is, these units are distributed side by side in the same semiconductor On the substrate.

[000] Each programmable computing unit contains at least one writable storage array, and the writable storage array stores a look-up table (LUT) of a basic function. The use of programmable computing unit is divided into two phases: setting phase and computing phase. In the setting stage, the LUT of the basic function is loaded into the writable storage array according to the user's needs; in the calculation stage, the value of the function is obtained by looking up the LUT. Due to the use of a writable storage array, even the same batch of chips can implement different functions. Moreover, for a programmable gate array based on a multi-time programming memory (MTP) array, since the MTP array can be loaded with LUTs of different functions at different time periods, the programmable gate array can realize reconfigurable calculations.

[0010] In addition, each programmable logic unit selectively implements a logic operation from a logic operation library, and each

Programmable connections selectively implement a connection from a connection library. In the process of implementing a complex function, the complex function is first decomposed into multiple basic functions. Then set the corresponding programmable calculation unit for each basic function to realize the corresponding basic function. Finally, by setting up programmable logic units and programmable connections, the required complex functions are realized.

[0011] Correspondingly, the present invention proposes a programmable gate array (400), which is characterized by containing: a plurality of programmable computing units (100, 100AA-100AD), the programmable computing unit (100) contains a writable Storage array (110), the writable storage array (110) stores at least a partial look-up table (LUT) of a basic function; a plurality of programmable logic units (200, 200AA-200AD), the programmable logic unit (200) from A logic operation library selectively implements a logic operation; multiple programmable connections (300) that selectively couple the programmable calculation unit (100AA-100AD) and the programmable logic unit (200AA-200AD); through The programmable calculation unit (100AA-100AD)>the programmable logic unit (200AA200AD) and the programmable connection (300) are programmed to implement a complex function, which is a combination of the basic functions.

[0012] The present invention also provides a programmable gate array (400), which is characterized by comprising: a semiconductor substrate (0); a plurality of programmable calculation units (100, 100AA-100AD), the programmable calculation unit ( 100) Contains a writable storage array (110) that stores at least a partial look-up table (LUT) of a basic function; a plurality of programmable logic units (200, 200AA-200AD), the programmable The logic unit (200) selectively implements a logic operation from a logic operation library; multiple programmable computing units (100AA-100AD) and the programmable logic unit (200AA-200AD) are selectively coupled Connection (300); a complex function is realized by programming the programmable calculation unit (100AA-100AD), the programmable logic unit (200AA-200AD) and the programmable connection (300), and the complex function is the A combination of basic functions; the writable memory array (110) contains a first transistor (Otl), the programmable logic unit (200) contains a second transistor (0t2), the first and second transistors (Otl, 0t2) are formed in the semiconductor substrate (0).

Description of the drawings

[0013] FIG. 1 is a symbol of a programmable computing unit.

[0014] FIG. 2 is a layout diagram of a substrate circuit of a programmable computing unit.

[0015] FIG. 3 is a layout diagram of a programmable gate array.

[0016] FIG. 4 shows two life cycles of a reconfigurable gate array.

[0017] FIG. 5A discloses a connection library realized by a programmable connection; FIG. 5B discloses a logic operation library realized by a programmable logic unit.

[0018] FIG. 6 is a layout diagram of a specific implementation of the programmable gate array.

[0019] FIG. 7 is a cross-sectional view of a programmable gate array chip.

[0020] Note that these drawings are only schematic drawings, and they are not drawn to scale. For the sake of conspicuousness and convenience, some sizes and structures in the figure may be enlarged or reduced. In different embodiments, the same symbols generally indicate corresponding or similar structures.

Detailed ways

[0021] FIG. 1 is a symbol of a programmable computing unit 100. The input terminal IN includes input data 115, the output terminal OUT includes output data 135, and the setting terminal CFG includes a setting signal 125. When the setting signal 125 is "write", the LUT of the required basic function is written in the programmable calculation unit 100. When the setting signal 125 is "read", the value in the LUT is read from the programmable calculation unit 100. FIG. 2 is a circuit layout diagram of a programmable computing unit 100. In this embodiment, the UT is stored in at least one

A writable storage array 110. The circuit also includes peripheral circuits of the writable memory array 110: X decoder 15 and Y decoder (including readout circuit) 17 and so on. The writable storage array 110 may be RAM or ROM. Examples of RAM include SRAM, DRAM, etc.; examples of ROM include OTP (one time programming), MTP (multiple programming), etc. Among them, MTP includes EPROM, EEPROM, flash memory and so on.

[0022] FIG. 3 shows a programmable gate array 400. It contains regularly arranged programmable modules 400A.400B and so on. Each programmable module (such as 400A) contains multiple programmable computing units (such as 100AA-100AD) and multiple programmable logic units (such as 200AA-200AD). There are multiple programmable channels 320 and 340 between the programmable computing unit (such as 100AA-100AD) and the programmable logic unit (such as 200AA200AD); between the programmable module 400A and the programmable module 400B, there are also multiple Programmable channels 310, 330, 350. Programmable channels 310-350 contain multiple programmable connections 300. For professionals familiar with the field, in addition to programmable channels, designs such as sea-of-gates can also be used.

[0023] FIG. 4 shows two usage cycles 620 and 660 of the reconfigurable gate array 400. The first use cycle 620 is divided into two phases: a setting phase 610 and a calculation phase 630. In the setting stage 610, a LUT related to a basic function is loaded into the MTP array 110 according to user needs; in the calculation stage 630, the corresponding LUT is searched in the MTP array 110 to obtain the value of the function. Similarly, the second usage period 660 also contains the same setting phase 650 and calculation phase 670. Reconfigurable computing is particularly suitable for SIMD (Single Instruction Multiple Data Stream) data processing. Once the LUT is loaded into the MTP array 110 in the setup phase 610, a large amount of data can be sent to the programmable computing unit 100 for processing, and a higher processing speed can be obtained. There are many application examples of SIMD, such as the same operation or vector operation of multiple pixels in image processing, and massively parallel computing used in scientific computing. In addition, the programmable gate array can also streamline the calculation in its programmable calculation unit to further improve the throughput rate.

[0024] FIG. 5A discloses a connection library that can be implemented by the programmable connection 300. The programmable connection 300 is similar to the programmable connection disclosed in US Patent 4,870,302. It uses a connection method of the following connection library: a) the interconnection line 302/304 is connected, the interconnection line 306/308 is connected, but the 302/304 and 306/308 are not connected; b) the interconnection line 302/304/ 306/308 are all connected; c) the interconnection lines 306/308 are connected, the interconnection lines 302, 304 are not connected, nor are they connected to 306/308; d) the interconnection line 302/304 is connected, and the interconnection lines 306, 306 are not connected, nor Connected with 302/304; e) The interconnection lines 302, 304, 306, 306 are not connected. In this text, the symbol "/" between two interconnecting lines indicates that the two interconnecting lines are connected, and the symbol "," between two interconnecting lines indicates that the two interconnecting lines are not connected.

[0025] FIG. 5B discloses a logic operation library that the programmable logic unit 200 can implement. The input A and B are input data 210 and 220, and the output C is output data 230. The programmable logic unit 200 is similar to the programmable logic unit disclosed in US Patent 4,870,302. It can implement at least one of the following logical operation libraries: C=A, A logical negation, A shift, AND(A, B), OR(A,B), NAND(A,B), NOR(A ,B), XOR(A,B), arithmetic plus A+B, arithmetic minus AB, etc. The programmable logic unit 200 may also contain sequential circuit elements such as registers and flip-flops to practice operations such as pipelines.

[0026] FIG. 6 is a specific implementation of a programmable gate array 400, which is used to implement a complex function: e=a'sin(b)+c'cos(d). In the programmable channels 310-350, the programmable connection 300 uses the representation in Fig. 5A: a programmable connection with a dot at a cross point indicates a cross-line connection, and a programmable connection without a dot at the cross point indicates that the cross-line is disconnected and disconnected. The open programmable connection means that the disconnected interconnection line is divided into two interconnection segments that are not connected to each other. In this embodiment, the programmable calculation unit 100AA is set to log (), and its calculation result log (a) is sent to the first input of the programmable logic unit 200AA. The programmable calculation unit 100AB is set to log [sin ()], and its calculation result log [sin (b)] is sent to the second input of the programmable logic unit 200AA. The programmable logic unit 200AA is set to "arithmetic addition", and its calculation result log (a) + log [sin (b)] is sent to the programmable calculation unit 100BA. The programmable calculation unit 100BA is set to exp (), and its calculation The result exp {log (a) +log[sin (b) ]}=a'sin is sent to the first input of the programmable logic unit 200BA. Similarly,

With appropriate settings, the results Leos (d) of the programmable calculation units 100AC, 100AD, the programmable logic unit 200AC, and the programmable calculation unit 100BC are sent to the second input of the programmable logic unit 200BA. The programmable logic unit 200BA is set to "arithmetic addition", awin(b) and c'cos(d) are added here, and the final result is sent to the output e. Obviously, by changing the settings, the programmable gate array 400 can also implement other complex functions.

[0027] FIG. 7 is a cross-sectional view of a programmable gate array 400 chip, which is a monolithic chip and contains regularly arranged programmable modules 400A and the like. The programmable module 400A includes a programmable calculation unit 100AA and a programmable logic unit 200AA. The writable memory array 110 in the programmable computing unit 100AA is based on the first type of transistor 0tl, which is suitable for completing the storage function. The logic circuit in the programmable logic unit 200AA is based on the second type of transistor 0t2, which is suitable for completing logic functions. Both types of transistors 0tl and 0t2 are formed in the same single crystal semiconductor substrate 0, and they are coupled to each other through an interconnection line 0i. Since the programmable computing unit 100AA and the programmable logic unit 200AA are based on transistors 0tl and 0t2, they can be formed through a traditional CMOS process without the need to develop new processes. Therefore, the programmable gate array (400) proposed by the present invention has better advantages. Short development cycle and excellent manufacturability. Moreover, since the transistor 0tl is a single crystal transistor, the writable memory array 110 in the programmable computing unit 100AA has a faster reading speed, which is suitable for the realization of high-performance computing.

[0028] In this example, field programmable gate array (FPGA) is used as an example. In FPGA, the wafer will complete all processes (including all programmable computing units, programmable logic units and programmable connections). At the programming site, you can define the function of the FPGA by setting up a programmable connection. The above-mentioned FPGA example can be easily extended to traditional programmable gate arrays. In the traditional programmable gate array, the wafer is only half completed, that is, only the programmable computing unit and the programmable logic unit are completed in wafer production, but the programmable connection is not completed. When the function of the chip is determined, the programmable channels 310-350 are customized through the back-end process.

[0029] It should be understood that without departing from the spirit and scope of the present invention, the form and details of the present invention can be modified, which does not prevent them from applying the spirit of the present invention. Therefore, the present invention should not be restricted in any way except in accordance with the spirit of the appended claims.