Multi-faced molded semiconductor package and related methods

Multi-sided molded semiconductor packaging and related methods technical field

[0001] Aspects of this document relate generally to semiconductor packaging, such as chip-scale packaging and flip-chip packaging. A more specific embodiment relates to a semiconductor package covered by a molding compound.

Background technique

[0002] Reducing the size of semiconductor packages has long been expected in the industry because it brings economic and technical benefits as a whole. The reduction in the size of the semiconductor package generally leads to an increased risk of damage to the semiconductor die and package during manufacturing. The protective cover or molding generally covers a part of the semiconductor package to protect the semiconductor from the environment, electrostatic discharge, surge, and the like.

Summary of the invention

[0003] An embodiment of a method of forming a semiconductor package may include forming a plurality of electrical contacts on the first side of the wafer, applying a photoresist layer to the first side of the wafer, and patterning the photoresist layer , And use a photoresist layer to etch multiple grooves in the first side of the wafer. The method may include applying a first molding compound into the plurality of grooves and above the first side of the wafer, and cutting a second side lip of the wafer opposite to the first side of the wafer to the first side of the wafer The plurality of grooves formed in one side apply one of the second molding compound and the laminating resin to the second side of the wafer, and cut the wafer into a plurality of semiconductor packages. The six sides of each semiconductor package may be covered by one of the first molding compound, the second molding compound, and the laminate resin.

[0004] The implementation of the method of forming a semiconductor package may include one, all, or any of the following: [0005] The first molding compound may be applied using one of a printer molding technique and a compression molding technique .

[0006] The periphery of the first side of the die within the package may be substantially one of an octagonal shape and a rectangle with rounded corners.

[0007] The plurality of grooves may be etched in the first side of the wafer using a photoresist layer and one of polyimide, polybenzoxanthene, and phenolic resin.

[0008] The plurality of grooves may be etched in the first side of the wafer using a photoresist layer and a passivation mask.

[0009] One of the solder resist layer, the passivation layer, the intermediate layer and the combination of the solder resist layer, the passivation layer and the intermediate layer may be coupled to the first side of the wafer and may be covered by the first molding compound.

[0010] The plurality of packages may be cut using an etching process.

[0011] An embodiment of a method of forming a semiconductor package may include forming a metal layer on the first side of the wafer, applying a first photoresist layer on the metal layer, patterning the first photoresist layer, and using The first photoresist layer forms electrical contacts coupled to the metal layer, the first photoresist layer is removed, the metal layer is etched, and a plurality of grooves are etched in the first side of the wafer. The method may include applying a first molding compound into the plurality of grooves, above the electrical contacts, and above the first side of the wafer, exposing the electrical contacts through the first molding compound by lip cutting the first molding compound , Lip the second side of the wafer opposite to the first side of the wafer to the plurality of grooves formed in the first side of the wafer, and apply one of the second molding compound and the laminating resin To the second side of the wafer, and dicing the wafer into multiple semiconductor packages. Each semiconductor package may be covered on the first side, second side, third side, fourth side, fifth side, and first side of each semiconductor package by one of the first molding compound, the second molding compound, and the laminating resin. On six sides.

[0012] The implementation of the method of forming a semiconductor package may include one, all, or any of the following:

[0013] The first side of the die within each semiconductor package may include a perimeter that is one of an octagonal shape and a rectangle with rounded edges.

[0014] The first molding compound may be anchored to the side walls of the plurality of grooves through a plurality of ridges formed in the side walls of the plurality of grooves.

[0015] The plurality of grooves may be formed using a deep reactive ion etching technique during the etching of the plurality of grooves.

[0016] One of polyimide, polybenzoxanthene, and phenolic resin may be used to etch the plurality of grooves in the first side of the wafer.

[0017] The plurality of grooves may be etched in the first side of the wafer using a passivation mask.

[0018] One of the solder resist layer, the passivation layer, the intermediate layer and the combination of the solder resist layer, the passivation layer and the intermediate layer may be coupled to the first side of the wafer and may be covered by the first molding compound.

[0019] Embodiments of a semiconductor package may include a die having a first side, a second side, a third side, a fourth side, a fifth side, and a sixth side, the first side of the die including a plurality of electrical contacts point. The package may include a first molding compound covering the first side of the die, the second side of the die, the third side of the die, the fourth side of the die, and the fifth side of the die, wherein the plurality of The electrical contacts extend through a plurality of openings in the first molding compound. The package may include one of a second molding compound and a laminate resin covering the sixth side of the die, wherein there is no die chipping on the first side of the die after the dicing of the die.

[0020] The implementation of the method of forming a semiconductor package may include one, all, or any of the following:

[0021] The sixth side may be opposite to the first side.

[0022] The periphery of the first side of the die may include one of an octagonal shape and a rounded rectangle.

[0023] The first molding compound may be anchored to the second side of the die through a plurality of ridges formed in the second side of the die, the third side of the die, the fourth side of the die, and the fifth side of the die. Side, the third side of the die, the fourth side of the die, and the fifth side of the die.

[0024] The plurality of electrical contacts may include one of a combination of wedge, gold, and aluminum, and a combination of tin, silver, and copper.

[0025] The package may include one of a solder resist layer, a passivation layer, an intermediate layer, and a combination of the solder resist layer, the passivation layer and the intermediate layer, which is coupled to the first side of the wafer and covered by the first molding compound. By.

[0026] For those of ordinary skill in the art, the above and other aspects, features, and advantages will be apparent through specific implementations, drawings, and claims.

Description of the drawings

[0027] In the following, various embodiments will be described with reference to the accompanying drawings, in which similar reference numerals indicate similar elements, and:

[0028] FIG. 1 is a cross-sectional side view of a semiconductor package;

[0029] FIG. 2 is a top view of the semiconductor package;

[0030] FIG. 3 is a first process flow showing the formation of a semiconductor package;

[0031] FIG. 4 is a top view of a semiconductor wafer in which a plurality of grooves are cut;

[0032] FIG. 5 is a top view of a semiconductor wafer with a plurality of grooves etched therein;

[0033] FIG. 6 is a top view of a second embodiment of a semiconductor wafer with a plurality of grooves etched therein;

[0034] FIG. 7 is a top view of a third embodiment of a semiconductor wafer with a plurality of grooves etched therein;

[0035] FIG. 8 is a cross-sectional view of a portion of a wafer with a molding applied thereon;

[0036] FIG. 8A is an enlarged cross-sectional view of the joint between the molded part and the side wall of the groove formed in the die;

[0037] FIG. 9 is a second process flow showing the formation of a semiconductor package;

[0038] FIG. 10 is a third process flow showing a part of the formation of a semiconductor package.

[0039] FIG. 11 shows a first alternative for forming grooves in the third process flow.

[0040] FIG. 12 shows a second alternative for forming grooves in the third process flow;

[0041] FIG. 13 shows a third alternative for forming grooves in the third process flow;

[0042] FIG. 14 shows a fourth alternative for forming grooves in the third process flow; and

[0043] FIG. 15 is a fourth process flow showing the formation of a semiconductor package.

Detailed ways

[0044] The present disclosure, its aspects, and implementations are not limited to the specific components, assembly procedures, or method elements disclosed herein. Many additional components, assembly procedures, and/or method elements known in the art that are consistent with the intended semiconductor package will obviously be able to be used with the specific embodiments of the present disclosure. Therefore, for example, although specific embodiments are disclosed in the present invention, such embodiments and implementation components may include any shape, size, size, size, or size, and size, or shape, and size, or shape, or size, or shape, size, shape, or size, shape, size, or size, shape, size, and shape that are known in the art for such semiconductor packages and implementation components and methods that conform to the intended operations and methods. Style, type, model, version, measurement, concentration, material, quantity, method element, procedure, etc.

[0045] Referring to FIG. 1, a cross-sectional side view of the semiconductor package is shown. The semiconductor package includes a die 2, which includes a first side 4, a second side 6, a third side 8 opposite to the second side 6, a fourth side, and a fifth side opposite to the fourth side (fourth side And the fifth side are both inside and outside the drawing surface in this view) and the sixth side 10 opposite to the first side 4. In various embodiments, the second side 6 of the die 2, the third side 8 of the die, the fourth side of the die, and/or the fifth side of the die may include grooves therein.

[0046] In various embodiments, one or more electrical contacts 12 are coupled to the first side 4 of the die 2. In various embodiments, the electrical contact is a metal, and by way of non-limiting example, may be copper, silver, gold, wedge, titanium, aluminum, any combination or alloy thereof, or another metal. In still other embodiments, the electrical contact 12 may not be metallic, but may be another conductive material.

[0047] In various embodiments, the first molding compound 14 covers the first, second, third, fourth, and fifth sides of the die. In various embodiments, by way of non-limiting example, the molding compound may be epoxy molding compound, acrylic molding compound, or another type of material that can physically support the die and provide protection against the ingress of contaminants . In various embodiments, the laminating resin or the second molding compound covers the sixth side 10 of the die.

[0048] The electrical contacts 12 each extend through a corresponding plurality of openings in the first molding compound 14. In various embodiments, as shown in FIG. 1, the electrical contacts 12 extend beyond the surface of the molded part 14, while in other embodiments, the electrical contacts are at the same level or flush with the surface of the molding compound 14.

[0049] In various embodiments, there will be no nicks or cracks on the side of the die, especially on the semiconductor device side of the die. This is done by using etching techniques (rather than conventional sawing techniques) to form the second, third, fourth, and fifth sides of each die. This article will more fully disclose this method in conjunction with the discussion in Figure 3.

[0050] In addition, the first molding compound may be anchored to the second, third, fourth, and fifth sides of the die. In various embodiments, the anchoring effect is the result of the interaction of the molding compound with multiple ridges formed along the second, third, fourth, and fifth sides of the die. This article will more fully disclose the anchoring effect in conjunction with the discussion in FIG. 3.

[0051] Referring to FIG. 2, a top view of the semiconductor package is shown. It can be clearly seen in FIG. 2 that the molding compound 14 surrounds the periphery of each electrical contact 12 (shaded area in FIG. 2) so that the entire first side (and every other side) of the die is not exposed.

[0052] Referring to FIG. 3, a first process flow is shown, which shows the formation of a semiconductor package. In each

In one embodiment, the method for preparing a semiconductor package includes providing a wafer 16, which may contain any specific type of substrate material, including by way of non-limiting examples silicon, sapphire, ruby, iron, glass, or Any other semiconductor wafer substrate type. In various embodiments, the metal layer 18 is formed on the first side 28 of the wafer 16 and may be formed using sputtering techniques. In other embodiments, the metal layer 18 is formed using other techniques, such as electroplating, electroless plating, chemical vapor deposition, and other methods of depositing metal layers, by way of non-limiting example. In certain embodiments, the metal layer is a titanium/copper variety layer, while in other embodiments, by way of non-limiting example, the metal layer may include copper, titanium, gold, wedge, aluminum, silver, or any of them. Combination or alloy.

[0053] In various embodiments, the first photoresist layer 20 is formed and patterned over the metal layer 18. One or more electrical contacts 22 may be formed on the metal layer 18 and within the photoresist layer 20. In various embodiments, this can be done using various electroplating or electroless plating techniques, but deposition and etching techniques can be employed in various embodiments. The electrical contact 22 may be any type of electrical contact (bump, bolt, etc.) previously disclosed herein. In various embodiments, the first photoresist layer 20 is removed through an ashing or solvent dissolution process, and the metal layer 18 may be etched away after the electrical contacts are formed.

[0054] In various embodiments, the second photoresist layer 24 is formed and patterned over the wafer 16. In various embodiments, as shown in FIG. 3, the second patterned photoresist layer 24 does not cover the electrical contacts 22. In other embodiments, the second photoresist layer is formed conformally over the electrical contacts along with the wafer. Referring to FIG. 9, a second process flow is shown, which shows the formation of a semiconductor package. In this process flow, the second photoresist layer 68 is formed as a conformal layer over the electrical contacts 70. Except for this difference, the process shown in FIG. 9 includes the same process steps as the process shown in FIG. 3.

[0055] Referring back to FIG. 3, in various embodiments, the method includes etching a plurality of grooves 26 in the first side 28 of the wafer 16 using a second patterned photoresist layer. In various embodiments, the width of the groove may be between about 50 and about 150 microns wide, while in other embodiments, the width of the groove may be less than about 50 microns or greater than about 150 microns. In various embodiments, the depth of the plurality of grooves 26 may extend between about 25 and 200 microns in the wafer, while in other embodiments, the depth of the plurality of grooves 26 may be less than about 25 microns. Micrometers or greater than about 200 micrometers.

[0056] In various embodiments, by way of non-limiting example, plasma etching, deep reactive ion etching, or wet chemical etching may be used to form the plurality of grooves. In various embodiments, a process sold under the trade name BOSCH® by Robert Bosch GmbH, Stuttgart Germany ("Bosch Process") can be used on the first side of wafer 16 A plurality of grooves 26 are formed in 28.

[0057] Referring now to FIG. 4, a top view of a conventional semiconductor wafer is shown in which a plurality of saw cuts surround the plurality of dies. Using a saw to cut grooves in a semiconductor wafer will always produce nicks and cracks on the device side of the die and in the sidewalls 34 of the groove 30. If the cracks and notches propagate into the device part of the semiconductor die, the existence of the cracks and notches may affect the reliability of the semiconductor package. Since the sawing process involves the friction of the rotating blade on the surface of the die, chipping and cracking can only be processed by sawing variables (wafer feed speed, blade kerf width, cutting depth, multiple saw cuts, blade material, etc.) Manage it, but it cannot be eliminated. In addition, since the sawing process relies on passing the wafer under the blade, conventional sawing techniques usually produce only square and rectangular sized dies.

[0058] Referring to FIG. 5, a top view of a semiconductor wafer with a plurality of grooves etched therein is shown. Different from the appearance of the die processed using the conventional sawing method shown in FIG. 4, the plurality of grooves 36 in the wafer 38 formed using the etching technique have edges and sidewalls 40 in which no cracks or notches are shown therein. . Since there are no cracks and notches, it is possible to improve the reliability of the resulting semiconductor package by using etching technology to form multiple grooves in the semiconductor wafer.

[0059] In addition, the use of etching techniques to form multiple grooves in the wafer allows different shapes of the perimeter of the die to be produced. In various embodiments, the second photoresist layer described with respect to FIG. 3 may be patterned in a certain manner, so that a large amount of photoresist layer is formed.

The grooves will not form the die with a rectangular perimeter. For example, referring to FIG. 6, there is shown a top view of a second embodiment of a semiconductor wafer having a plurality of grooves etched therein. In various embodiments, a plurality of grooves 42 may be formed in the wafer 44. The plurality of grooves 42 may form the final die 46 with an octagonal periphery. Referring to FIG. 7, there is shown a top view of a third embodiment of a semiconductor wafer in which a plurality of grooves are etched. In various embodiments, a plurality of grooves 48 may be formed in the wafer 50. The plurality of grooves 48 may form the final die 52 with a rounded rectangular periphery. In other embodiments, multiple grooves may be formed in the wafer that form the final die with any other closed geometric perimeter.

[0060] Referring back to FIG. 3, in various embodiments, the plurality of grooves 26 formed have two substantially parallel side walls that extend substantially straight to the wafer 16 The first side 28. In other embodiments, two or more stepped grooves are formed in the first side 28 of the wafer 16. Each stepped groove can be formed in the following manner: a first groove is generated in the wafer, and then a second narrow groove is formed in each first groove.

[0061] Referring to FIG. 3, an embodiment of a method for forming a semiconductor package includes applying a first molding compound 54 into the plurality of recesses 26 and above the first side of the wafer. In various embodiments, as shown in FIG. 3, the first molding compound 54 may cover the electrical contacts 22. In other embodiments, the first molding compound 54 may not completely cover the electrical contacts 22. By way of non-limiting example, the first molding compound is applied using liquid dispensing technology, transfer molding technology, E[] brush molding technology, or compression molding technology. The molding compound may be epoxy molding compound, acrylic molding compound, or another type of molding compound disclosed herein.

[0062] In various embodiments, the first molding compound 54 may be anchored to the plurality of side walls 56 of the plurality of grooves 26. Referring now to FIG. 8, there is shown a cross-sectional view of a portion of the wafer on which the molding is applied. Referring now to FIG. 8A, an enlarged cross-sectional view of the joint between the molded part and the side wall of the groove formed in the die is shown. In various embodiments, a plurality of ridges 58 may be formed in the sidewall 56 of each groove in the plurality of grooves. In a particular embodiment, the height of each ridge extending from the sidewall is substantially 0.2 microns high, and the pitch is substantially one micron. Therefore, in embodiments where the groove is 150 microns deep, each sidewall of the groove may be substantially 150 microns. In other embodiments, the grooves may be higher or lower than 0.2 microns, and may have a pitch greater than or less than one micron. The ridge may anchor the first molding compound 54 to the side walls 56 of the plurality of grooves. In various embodiments that use the Bosch process to etch the plurality of grooves, the etching process can etch the plurality of grooves while etching the plurality of grooves through a deposition/etch cycle of deep reactive ion etching. A ridge is formed in the center, thereby increasing the adhesion between the first molding compound and the side wall of each groove.

[0063] Referring back to FIG. 3, in various embodiments where the first molding compound 54 covers the electrical contacts 22, the electrical contacts 22 may be exposed by lip cutting the first molding compound. In various embodiments, the second side 60 of the wafer 16 may be lip cut to the plurality of grooves 26 formed in the first side 28 of the wafer 16. In this way, the individual dies of the semiconductor wafer are limited to each other in various embodiments. By way of non-limiting example, mechanical polishing technology, chemical etching technology, a combination of mechanical polishing and chemical etching technology or any other technology can be used. The lip cutting technique comes to lip the second side 60 of the wafer 16.

[0064] In various embodiments, a second molding compound 62 or laminating resin may be applied to the second side 60 of the wafer 16. In the embodiment where the second molding compound is applied, the molding compound may be any type of molding compound disclosed herein, and may be applied using any technique disclosed herein.

[0065] In various embodiments, as shown in the process flow shown in FIG. 3, the second side 60 of the wafer 16 is lip-cut and the first molding compound 54 is lip-cut to expose the electricity before applying the second molding compound. Contact 22. In other embodiments, the first molding compound 54 may be lip-cut to expose the electrical contacts 22 after lip-cutting the second side 60 of the wafer 16 and applying the second molding compound.

[0066] The method for preparing a semiconductor package includes cutting the wafer 16 into a plurality of semiconductor packages 64. The wafer 16 can be diced by cutting or etching through the wafer 16 where the plurality of grooves 26 are initially formed. By way of non-limiting example, it can be achieved by using saws, lasers, water jets, plasma etching, deep reactive ion etching or chemical etching.

In various embodiments, the Bosch process may be used to cut the wafer 16 and the method for cutting the wafer may include using a thinner film than that used to form the plurality of grooves 26. The notch or etching cuts damage to the wafer so that the first molding compound will cover each side of each cut die 66 in each semiconductor package 64. Specifically, in certain embodiments, the width of the saw used to cut each semiconductor package may be between 20 and 40 microns thick. The semiconductor die in the semiconductor package may be covered on all six sides of the semiconductor die by molding compound or laminate resin.

[0067] In various embodiments, the first side of the die within each semiconductor package may include a perimeter, by way of non-limiting example, the perimeter is rectangular, octagonal, rectangular with rounded edges, or Any other closed geometric shapes.

[0068] Referring now to FIG. 10, a third process flow is shown, which shows a part of the formation of a semiconductor package. In various embodiments, the method for forming a semiconductor package includes providing a wafer 72, which may be any type of wafer substrate disclosed herein. In various embodiments, one or more metal pads 74 may be coupled to the first side 76 of the wafer 72. By way of non-limiting example, the metal pad may include aluminum, copper, wedge, silver, gold, titanium, or any combination or alloy thereof.

[0069] In various embodiments, the first passivation layer 78 may be coupled to a portion of the first side 76 of the wafer 72. The first passivation layer 78 may be a silicon dioxide passivation layer in various embodiments, but it may be any of a variety of other types of layers, including silicon nitride, silicon nitride, Polyimide or another polymer or deposition material. In various embodiments, the second passivation layer 80 may be coupled to a portion of the first side 76 of the wafer 72. The second passivation layer 80 may be a silicon nitride passivation layer. The second passivation layer may include the same material as the first passivation layer or a different material.

[0070] In various embodiments, the third layer 82 may be coupled to a portion of the first side 76 of the wafer 72. The third layer may be polyimide, polybenzoxanthene, phenolic resin, or a combination of polyimide, polybenzoxanthene, and phenolic resin. In various embodiments, a metal variety layer 84 may be formed above the third layer and above the first side 76 of the wafer 72. The metal variety layer 84 can be any type of metal layer disclosed herein. In various embodiments, the metal variety layer 84 may directly contact a portion of the first side 76 of the wafer 72. In various embodiments, the method includes forming a first photoresist layer 86 over the metal variety layer 84 and patterning the first photoresist layer.

[0071] In various embodiments, the method includes forming an electrical contact 88 coupled to the metal variety layer 84 and within the first photoresist layer 86. The electrical contact 88 may be any type of electrical contact disclosed herein. In various embodiments, the electrical contact 88 may include a first layer 90 and a second layer 92. In various embodiments, the first layer 90 may include copper, and the second layer 92 may include tin, silver, or a combination of tin and silver. In various embodiments, the method of forming a semiconductor package includes removing the first photoresist layer 86 after forming the electrical contacts and etching away portions of the metal variety layer 84 that are not covered by the electrical contacts.

[0072] In various embodiments, a method of forming a semiconductor package includes forming a second photoresist layer 94 over the first side 76 of the wafer 72 and patterning the second photoresist layer. In various embodiments, the second photoresist layer covers the electrical contacts 88, while in other embodiments, the second photoresist layer 94 does not cover the electrical contacts 88. The second photoresist layer 94 can be used to etch a plurality of grooves 96 in the wafer 72. The method includes removing the second photoresist layer 94 after etching the plurality of grooves in the wafer.

[0073] The first molding compound can be applied to the plurality of grooves and over the first side 76 of the wafer 72 in the same manner as the first molding compound in FIG. 3. The remaining part of the method for forming a semiconductor package as shown in FIG. 10 may include exposing electrical contacts by lip cutting, lip cutting the backside of the wafer to the plurality of grooves, and applying a second molding compound or laminating Resin is applied to the backside of the wafer, and the wafer is cut into multiple semiconductor packages. These parts forming the semiconductor package may be the same as or similar to the corresponding parts used to form the semiconductor package shown in FIG. 3 and previously disclosed herein.

[0074] In various embodiments, this is illustrated by FIG. The semiconductor package prepared by the method shown may include one or more metal pads, one or more passivation layers, polyimide, phenolic resin, and polybenzoxanthene between the semiconductor die and the first molding compound.

And any combination of them.

[0075] Referring to FIGS. 11-14, an alternative method for forming a plurality of grooves in the process shown in FIG. 10 is shown. Referring to FIG. 11, there is shown a method of using a patterned photoresist layer and one of polyimide, polybenzoxanthene, and phenolic resin in combination with an etching process to form a plurality of grooves. In various embodiments, the patterned photoresist layer 98 may be over the mask 100 and include a patterned polyimide layer, a patterned polybenzoxanthene layer, or a patterned phenolic resin layer. The mask 100 may be above the wafer 102. Any etching process disclosed herein can be used to form the groove 104 in the wafer 102 using a patterned photoresist layer and a mask.

[0076] Referring to FIG. 12, there is shown a method of forming a plurality of grooves using one of polyimide, polybenzoxanthene, and phenolic resin in combination with any of the etching processes disclosed herein. This method can be the same as the method shown in FIG. 11, except that the method shown in FIG. 12 does not include a patterned photoresist layer for forming the groove 106 in the wafer 108.

[0077] Referring to FIG. 13, a method of forming a plurality of grooves using a patterned photoresist layer and a passivation mask is shown. In various embodiments, the patterned photoresist layer 110 may be above the passivation mask 112. The passivation mask 112 may include any passivation layer disclosed herein. The passivation mask 112 may be above the wafer 114. The groove 116 may be formed in the wafer 114 using the patterned photoresist layer 110 and the passivation mask 112 and any etching process disclosed herein.

[0078] Referring to FIG. 14, a method of forming a plurality of grooves using a passivation mask in combination with any etching method disclosed herein is shown. This method may be the same as the method shown in FIG. 13, except that the method shown in FIG. 14 does not include a patterned photoresist layer for forming the groove 116 in the wafer 118.

[0079] Referring to FIG. 15, a fourth process flow is shown, which shows the formation of a semiconductor package. The method for forming a semiconductor package shown in FIG. 15 includes providing a wafer 120. In various embodiments, the intermediate layer 122 may be coupled to the first side 124 of the wafer 120. In various embodiments, the passivation layer 128 may be coupled to the wafer 120. The passivation layer may be any type of passivation layer disclosed herein.

[0080] In various embodiments, one or more electrical contacts 126 may be coupled to the wafer 120. In various embodiments, these electrical contacts include bumps 130. These electrical contacts may include the first metal layer 132 coupled to the bump 130. The first metal layer can include any metal disclosed herein. In a particular embodiment, the first metal layer includes wedge and gold. The electrical contact 128 may include a second metal layer 134 coupled to the first metal layer 132. The second metal layer 134 may include any metal disclosed herein. In a particular embodiment, the second metal layer 134 includes aluminum. In various embodiments, the solder resist layer 136 may be coupled above the wafer 120. In other embodiments, no solder resist layer is included.

[0081] In various embodiments, the passivation layer 128 may be patterned and may directly contact a portion of the wafer 120. In such embodiments, the patterned passivation layer or mask can be used to etch the plurality of grooves 138 in the first side 124 of the wafer 120 using any of the etching processes disclosed herein. The plurality of grooves may be etched using any method disclosed herein, and may be any type of grooves previously disclosed herein.

[0082] In various embodiments, the first molding compound 140 is applied to the plurality of grooves 138 and above the first wafer 120. The first molding compound 140 may be any molding compound disclosed herein, and may be applied using any technique disclosed herein. In various embodiments, the first molding compound 140 does not completely cover the electrical contacts 126, as shown in FIG. 15. In other embodiments, the first molding compound does not completely cover the electrical contacts 126. In embodiments where the first molding compound 140 does not completely cover the electrical contacts 126, the first molding compound may be lip-cut to expose the electrical contacts 126.

[0083] In various embodiments, the second side 142 opposite the first side 124 of the wafer 120 may be ground to the plurality of grooves using any of the lip cutting methods disclosed herein. The second molding compound 144 or laminating resin may then be applied to the second side 142 of the wafer 120.

[0084] The wafer 120 may then be diced into a plurality of semiconductor packages 146. Any of the techniques disclosed herein can be used to cut the round of the semiconductor die 148 with the semiconductor package 146 so that all six sides can be covered with molding compound. In other embodiments, the sixth side of the die 150 may be covered by a laminate resin.

[0085] In various embodiments, the semiconductor package formed by the method shown in FIG. 15 may include a solder resist layer, a passivation layer, and an intermediate layer that are coupled to the first side of the wafer and covered by the first molding compound. , Or a combination of solder mask, passivation layer and intermediate layer.

[0086] An embodiment of a method of forming a semiconductor package may include applying a first molding compound into the plurality of grooves and over the first side of the wafer. The first molding compound may be applied using one of printing press molding technology and compression molding technology.

[0087] The periphery of the first side of the die within the package may be substantially octagonal or rectangular with rounded corners.

[0088] An embodiment of the method of forming a semiconductor package may include forming a metal layer on the first side of the wafer, applying a first photoresist layer on the metal layer, patterning the first photoresist layer, and using The first photoresist layer forms electrical contacts coupled to the metal layer, the first photoresist layer is removed, the metal layer is etched, and a plurality of grooves are etched in the first side of the wafer.

[0089] A deep reactive ion etching technique may be used to form the plurality of grooves during the etching of the plurality of grooves.

[0090] One of polyimide, polybenzoxanthene, and phenolic resin may be used to etch the plurality of grooves in the first side of the wafer.

[0091] The plurality of grooves may be etched in the first side of the wafer using a passivation mask.

[0092] The solder resist layer, passivation layer, intermediate layer, or a combination of the solder resist layer, passivation layer, and intermediate layer may be coupled to the first side of the wafer and may be covered by the first molding compound.

[0093] Embodiments of a semiconductor package may include a die having a first side, a second side, a third side, a fourth side, a fifth side, and a sixth side, the first side of the die including a plurality of electrical contacts point. The sixth side may be opposite to the first side.

[0094] The periphery of the first side of the die may include one of an octagonal shape and a rounded rectangle.

[0095] The plurality of electrical contacts may include one of a combination of wedge, gold, and aluminum, and a combination of tin, silver, and copper.

[0096] In the above description, where specific implementations of semiconductor packages and implementation of components, subcomponents, methods, and submethods are mentioned, it should be obvious that various modifications can be made without departing from their essence, and these implementations The manners, implementation components, sub-components, methods, and sub-methods can be applied to other semiconductor packages.