Wideband FFT channelizer

Broadband Fast Fourier Transform Channel Splitter

FIELD OF THE INVENTION The present invention relates generally to wireless communication networks (such as cellular and personal communication systems (PCS)) and more specifically to a new and improved transceiver device, the receiver part of which includes a wideband, fast Fourier transform based (FFT) channel splitter to extract multiple channels from the digitized intermediate frequency (IF) signal, and includes a set of digital sampling rate converters to adjust the best sampling timing for each channel, and its transmitter part Includes a wideband, inverse FFT-based combiner to combine multiple digitized baseband channels into a single IF signal for transmission.

Background of the Invention In order to provide multi-channel voice and data communications over a wide geographic area, wireless (e.g., cellular) communication service providers currently install transceiver base stations in protected and maintainable facilities (e.g., buildings) . Because of the large amount of hardware currently used to implement signal processing equipment for a single cellular channel, each base station generally needs to be configured to provide multi-channel communication capabilities for only a very limited portion of the spectrum provided to service providers. A typical base station may include three to five equipment racks, accommodating multiple sets of independent receiver and transmitter signal processing components in order to specify the total number of channels (e.g., 400-30kHz) within the available bandwidth (e.g., 12MHz) Part of the service (for example, 48). The receiver part of a typical one of the multiple (for example, 48) narrowband (30kHz) channel units of the base station is schematically illustrated in FIG. 1 as including a set of dedicated signal processing components, including a front-end or down-conversion part 10, an intermediate frequency (IF) part 20 and baseband part 30.

The front-end part 10 is composed of a low noise amplifier 11 connected to an antenna 12 at a transceiver site, a radio frequency to intermediate frequency (RF-IF) down conversion mixer 13 and a related IF local oscillator 15. The IF section 20 is composed of a bandpass filter 21 connected to the output of the mixer 13, an amplifier 23, an IF-baseband mixer 25, and a related baseband local oscillator 27. The center of the band pass filter 21 is on a corresponding one of the 400-30 kHz sub-parts of the 12 MHz wide cellular voice/data communication frequency band, and the bandwidth is 100 kHz, which is schematically illustrated in the multi-channel spectrum distribution diagram of FIG. 2.

The baseband part 30 includes a low-pass (anti-aliasing) filter 31, an analog-to-digital (AD) converter 33, a digital signal processing unit 35 used as a demodulator and error corrector, and a related telephone (for example, T1 carrier) unit 37, The processed channel signal is connected to the auxiliary telephone system equipment through this unit. The sampling rate of the AD converter 33 is typically on the order of 75K samples/sec. The narrowband channel signal digitized by the AD converter 33 is demodulated by a digital signal processing (DSP) unit 35, and the voice/data signal therein is restored for use in the telephone carrier unit 37. (Connect a similar dedicated signal processing transmitter part as a supplement to the receiver part to receive the digital feed from the telephone system equipment and output an up-converted RF signal to the antenna at the transceiver site.) For a typical In the urban service area, in order to optimize the service coverage within the entire bandwidth (for example, 12MHz) provided to the service provider, and to ensure interference-free coverage between the scattered transceiver sites where the base station is located, cellular transceivers The geographical distribution of sites is customarily located in hexagonal meshes adjacent to each other (seven meshes form a group). Therefore, each cell has its own multiple base stations with limited capacity, serving a different subset of the available 400 channels, so that the frequency allocation and allocation in the corresponding cell can be specified over a wide geographic area. The division between adjacent cell groups is to effectively prevent mutual interference between any channels of the network.

It is easy to understand that because each channel has components scattered on multiple equipment racks, such as those components that make up a typical channel receiver section described above with reference to Figure 1, so geographically select, install, and maintain such components. The cost and manpower used by the equipment are not trivial. Indeed, no matter in the sense of the location or the available bandwidth coverage that the corresponding transceiver site can provide, service providers hope to use more flexible equipment. This is especially true in non-urban areas, where the desired cellular coverage may be concentrated along the highway. The limited capacity of the general 48-channel transceiver site is not enough, and it is not necessarily easy to provide the required equipment here. Relatively large, safe and protective structure.

Although broadband transmitters have been used in some other applications in the past, there may be several reasons why they have not found widespread application in multi-channel systems such as cellular and other PCS systems. One is related to the fact that each received channel signal is a digitally encoded signal including a series of symbols. In such a case, the recovery algorithm used by the digital signal processor 35 typically requires that the samples provided by the AD converter 33 be extracted at or near the peak amplitude time of each symbol in order to maximize the probability of correct detection of each symbol. .

In the prior art system as described above, it is quite simple to synchronize the local clock to the optimal sampling time. This is because each channel is processed separately, so the output of the channel signal of the AD converter 33 represents information from only one channel. Therefore, the local receiver clock can be synchronized using common phase-locked loop (PLL) technology to generate a clock gating pulse for the AD converter 33 synchronized to the symbol rate.

However, if the system uses a wideband front end, for example, the low-pass filter 31 covers the bandwidth occupied by several channels, then signals from multiple channels will appear in the output of the AD converter 33. In a typical cellular or other PCS system, the channel signals do not need to be synchronized with each other. Therefore, there is no unique optimal sampling time, and the conventional phase-locking technique cannot be used to synchronize the AD converter 33.

In addition, even if the sampling rate of multi-digital channel signals can be independently controlled, this rate is generally not guaranteed to be an integral multiple of the symbol rate. This exacerbates the problem of properly synchronizing symbol sampling in each digital channel signal, because even a small difference in the digital symbol rate will quickly accumulate in the duration of even a short-term channel signal, so Make the sampling timing deviate again.

Summary of the Invention According to the present invention, the limited channel capacity and the considerable hardware requirements related to the signal processing structure currently used by multi-channel wireless communication service providers, as well as the sampling rate synchronization problem described above, are improved by a new kind of improvement The relatively compact multi-channel transceiver device can be effectively avoided, making it possible to considerably reduce the size and hardware complexity of the transceiver site of the wireless (voice and data) communication network.

Therefore, the transceiver can be easily installed on a variety of installation sites, such as the ceiling of an office building or on a pole of an electrical facility, and has the ability to provide multi-channel communication services that span the entire channel capacity provided by the service provider (for example, greater than 100 channels) instead of a subset of the available channels.

Therefore, the transceiver device of the present invention includes a receiver part with a wideband discrete Fourier transform (DFT) channel splitter, processes digitized received signals of multiple channels, and includes a transmitter part including a wideband inverse DFT combiner, Process multiple digitized transmit channel signals. According to a preferred embodiment, the DFT channel splitter and the DFT combiner can be, but not limited to, be implemented with a fast Fourier transform (FFT), because when the size of the transform is a power of two, the fast Fourier transform is a discrete Fourier transform. An effective algorithm for transformation.

The job of the multi-channel receiver unit is to receive multiple input communication channel signals and output digital signals representing the content of the multiple input communication channel signals. A DFT-based channel splitter unit is connected to receive the digital signal output by the multi-channel receiver unit and output corresponding digital channel signals representing the contents of the corresponding communication channels received by the multi-channel receiver unit.

The digital channel signal output by the DFT-based channel splitter is then fed into a set of sampling rate converters, and each corresponding communication channel has a sampling rate converter. The rate converter works by determining the digital channel signal value interpolated at the time position where the best sample is generated for each channel, that is, the output sample provided by the digital channel splitter using this rate is not an integer multiple of the symbol rate.

In a preferred embodiment, each rate converter is implemented with a decimated, linear-phase, low-pass digital filter, such as a finite impulse response (FIR) filter, where the filter coefficients of each channel pass in each digital channel The sampling phase difference is determined during the leading part of the signal to be selected separately.

Then the corresponding interpolated digital channel output is provided to the first plurality of digital signal processor units, and each digital channel signal output output by the channel splitter has a corresponding digital signal processor unit associated with it. The digital signal processor unit processes (for example, demodulates) the corresponding digital channel signal, and then provides the processed digital channel signal at the corresponding output port for distribution to the auxiliary voice/data network.

On the transmitting side, the transceiver includes a second set of digital signal processor units, which are respectively associated with corresponding ones of the multiple incoming (voice/data) communication signals to be transmitted on different channels, and its job is to process multiple Input the corresponding ones of the communication signals and provide these several processed communication channel signals at the corresponding output ports for use by the inverse DFT processing synthesizer unit. The inverse DFT-based synthesizer unit is connected to receive the communication channel signal processed by the second plurality of digital signal processor units and output a synthesized signal representing the content of the communication channel signal processed by the second plurality of digital signal processor units.

Then the multi-channel transmitter unit transmits a multi-frequency communication channel signal according to the composite signal output by the combiner unit based on the discrete Fourier transform.

More specifically, according to the present invention, the DFT-based channel splitter and combiner used on the transmit and receive channels uses convolution and deconvolution filters, and can be used with overlap and addition filter units or polyphase filtering. Unit to achieve.

According to the first embodiment of the present invention, the wideband channel splitter uses an overlap and add filter structure to generate digital channel signals together with the FFT processor. In this embodiment, the digitized data samples output by the high-speed AD converter in the broadband receiver are first provided to the overlap and add unit. When the received data samples are fed into an input rate buffer, an amplitude monitoring unit monitors the data in order to provide gain control to the input signal and ensure full utilization of the dynamic range of the AD converter. (For this purpose, the output of the amplitude monitoring unit is fed back to the broadband receiver to control the attenuator in front of the AD converter.) When the rate buffer contains a complete "block" composed of M data samples, it sends to the control unit Signal to start processing the block. The number of data samples in a block, M, is equal to the decimation rate of the channel splitter, which is given by the nearest integer obtained by dividing the input sampling rate by twice the complex channel sampling rate.

When the input sampling rate is large (on the order of 30MHz), a half-bandwidth filter can also be used to reduce the data clock rate. The half-bandwidth filter performs data real-to-complex conversion, and decimates the data and clock rate at 2. It is necessary to reduce the clock to realize the filtering structure with the current integrated circuit. If the input clock rate is quite low, or when the processing power provided by the future technology increases, the half-bandwidth filter may not be necessary.

M samples are moved out of the rate buffer into the half-band filter at a rate higher than the input sampling clock rate in groups according to the clock tick, so as to adapt to the size of the FFT processor that requires N samples, where N is greater than M. This means that the overlap and add filter must operate at a clock rate higher than half the input sampling rate.

The complex data value from the half-bandwidth filter enters the shift register used in the overlap and add filter in clock tick. The overlap and add filter is a real-valued low-pass filter with a cutoff frequency of half the channel bandwidth. The basic structure of the overlap and add filter is similar to a finite impulse response (FIR) filter. However, the filter of the present invention is different from a general FIR filter in that a long delay line unit between the feedback multiplexer and the filter tap is used.

More specifically, the shift register in the overlap and add filter is preferably implemented with a group of cascaded delay memory cells and interleaved with a "feedback" multiplexer. The corresponding tap or filter stage consists of a pair of serially connected memory sections, a feedback multiplexer, a coefficient memory and a coefficient multiplier. Each coefficient memory stores a corresponding set of filter coefficients, the number of which corresponds to the size of the FFT processor to which the output of the overlap and add filter is to be sent.

In an exemplary embodiment of the channel splitter filter structure, four overlap and add filter tap stages can be used. The multiplier outputs of the corresponding tap stages are added together. In a memory section, the length of the input memory stage is equal to the decimation rate M; the length of the output memory stage means that the filter "overlap" is equal to NM, where N is the size of the FFT processor.

In order for the FFT processor to process each block of M input samples, N clock signals are required to provide a sufficient number of data samples to the FFT processor for FFT processing. Among the first M of the N clock signals, M samples pass through the rate buffer and half-bandwidth filter and pass through the memory stage of the filter according to the clock tick. The latter is actually a shift register. During this time period, the data is shifted from left to right through each memory section of the shift register. For the remaining NM samples of the N data samples, the data is not shifted out of the rate buffer memory in the clock tick, and no data is shifted through the input memory of each tap stage. In other words, the data is not shifted through the shift register, only the output memory still works on the clock tick. This clock relationship of the output memory is the mechanism used to make the required overlap-add operation effective.

When the corresponding coefficient-weighted data samples generated by the filter tap stage are added, an N-sampled, aliased, and convolved output data sequence is generated at the output of the overlap and add filter. This data sequence is stored in random access memory (RAM), ready to be used in the FFT processor.

In order to maintain throughput at a high processing rate, the FFT processor generally includes multiple FFT engines, which are programmed with an appropriate FFT size, which is related to the signal processing parameters of interest. Implementing the FFT processor with multiple FFT machines guarantees data throughput, because the processing time of a single engine is generally longer than the time required for the collection and processing of N samples.

According to a practical embodiment, the FFT machine can use a 4-base (block floating point) algorithm whose FFT size is a power of four. For a 512-point FFT processor, all 512 bins are generated by using two 256-point FFTs using a 2-base butterfly operation with frequency decimation applied. For a 512-point FFT, samples are read from RAM and provided to the arithmetic logic unit (ALU), which adds consecutive pairs of even data samples and subtracts consecutive pairs of odd data samples. For the processing of even data samples, the sum value output by the ALU is directly provided to the FFT processor engine. In order to generate a 512-point FFT odd number (bin), when the odd number (bin) data sample is read from the RAM, the difference between the data samples provided by the ALU is multiplied by the numerical control oscillator and the modulator by WNn, and the clock beats Enter the FFT processor.

Since the FFT machine uses block floating point operations (outputting a four-bit scale factor along with the complex FFT data), a scaling logic circuit is used to control the barrel shift circuit, and the output of the FFT machine is connected to the shift circuit. When the data is read from the FFT machine, the barrel shift circuit adjusts it according to the scale factor to ensure that the continuous FFT is calibrated according to the same scale. The output of the barrel shift circuit is connected to the output RAM. The output of the FFT processor must be multiplied by a complex exponent, WN-kmM, where m is the decimation rate, k is the number of FFT points (bin), and M is the number of FFT (blocks). The overlap-add embodiment of the channel splitter uses the following identity to perform equivalent operations: x[(nr)N]=FFT(WN-rk*X[k]) where x[n] is the FFT input sequence, x[( nr)N] is the result of x[n] modulo N cyclically shifted r times. This cyclic shift addresses the dual-port output RAM by accessing the processed data value in the order in which the FFT input data sequence is cyclically shifted.

Therefore, the FFT outputs several digital channel signals, and each digital channel signal includes a series of samples of the signal related to a particular channel. When the FFT processed data of each channel (frequency point (bin)) has been written into the output RAM, a following time division multiplexing (TDM) bus interface circuit determines that the data is on the TDM bus, so it can be provided to the bus on the bus. Digital signal processor, which is used for interpolation, subsequent demodulation, and extraction of voice or data from channel data. The data on the TDM bus is preferably divided into multiple time slots. The bus connected to the processor is synchronized to the TDM bus through a conventional framing signal, so the processor will know the correct time slot to read data from.

Before demodulating and extracting live sound and/or data from each channel signal, the digital signal processor first processes each digital channel signal that has passed through a rate converter composed of a linear phase, interpolated low-pass digital filter. By appropriately decimating the output of the interpolated digital filter, the rate converter adjusts the effective timing of the sampled value in each digital channel signal. Interpolation and decimation filters preferably use multi-rate digital signal processing techniques to minimize the total number of necessary arithmetic functions.

The corresponding rate converter associated with each input channel signal determines the value of the interpolated digital signal corresponding to the best sample for that channel. Specifically, each rate converter provides samples of the corresponding digital channel signal at or near the location of the peak symbol amplitude. Algorithmically, the function of the rate converter is equivalent to generating the zero-filling extension corresponding to the output of the corresponding FFT channel, using a low-pass, linear phase, and finite impulse response (FIR) filter to filter the zero-filled signal, and then extracting FIR The output signal of the filter so that only the samples at the amplitude of the symbol closest to the peak are selected.

However, in fact, not every such equivalent operation has to be performed on an algorithm. The present invention takes advantage of certain multi-rate signal processing techniques to reduce the number of operations required to obtain the same result. Specifically, the rate converter is composed of a low-pass filter having one of several sets of possible filter coefficients. Various sets of effective filter coefficients represent various possible phase shifts of interpolating low-pass filters operating on zero-filled digital channel signals. The specific set of filter coefficients that produces the best output signal phase is determined before filtering out the actual data from the digital channel signal. For example, when the expected value of the received digital channel signal is known in advance, this task is typically completed during the preamble of the digital channel signal. This allows the use of a correlator to determine the energy of each output signal detected by the FIR filter for each possible phase shift. The optimal phase shift of the filter is therefore the one with the largest relevant power level.

Therefore, each rate converter also includes a filter phase selection mechanism. When it is detected that the leading part of the corresponding digital channel signal is currently being received, this mechanism will filter the result of the received channel signal with every possible interpolation low-pass filter. It compares with the device to determine which of the possible low-pass filter coefficient sets produces the greatest probability of correctly detecting the symbol in the data portion of the digital channel signal.

Optionally, the rate converter can also perform sampling rate difference adjustment to act on the necessary difference between the sampling rate provided by the discrete Fourier transform and the optimal sampling rate expected by the demodulator. In order to make necessary sampling timing adjustments, the time for sampling to pass through the interpolating low-pass filter is precisely controlled by an output sampling counter operating at a desired output sampling rate. This output sampling counter provides a sampling index number, which is then multiplied by the sampling rate adjustment factor. The result of this multiplication is used to control which input sample the interpolation filter is currently processing, and to adjust the index of the specific filter coefficient set used at any given instant in time. In this way, it is possible to adapt to any difference between the desired sampling rate of the input digital channel signal and the output digital channel signal. The interpolated digital channel output signal from the channel splitter is then provided to the demodulator function performed by the digital signal processor.

As a complement to the above-mentioned wideband channel splitter with overlap and addition filter structure, the signal processing structure of the multi-channel combiner uses a customized TDM bus to collect data on a large number of channels at a relatively high data rate. Because the total data rate from all channels generally exceeds the bus bandwidth of the standard bus protocol (for example, VMEbustm).

Determine the source of the channel-divided (voice/data) signal on the TDM bus is the DSP processor, which formats (for example, according to cellular standards) and modulates the voice or data signal from the auxiliary telephone network, thus providing a Decomposed signal of baseband. Each data source specifies one or more time slots, and a single multi-sample is transmitted in the time slot when requested by the combiner. Two sources cannot allocate the same time slot. The time slot is allocated by the system controller during system initialization (in an independent central processing unit (CPU) of VMEbustm). The system controller also programs the combiner to specify all time slots containing valid data.

The samples from each DSP processor are provided to the TDM bus via a request for control signals from the TDM bus controller and related buffers/drivers. This sample is written into an input (RAM) buffer. The TDM bus controller synchronizes the addressing of the RAM buffer to the framing signal of the TDM bus, thus ensuring that each channel is written to the appropriate address of the dual-port RAM. When the combiner has collected data from all channels in operation, the TDM bus controller connects the control signal to the FFT control logic unit, and causes the FFT control logic unit to start FFT processing.

As the complement of the forward FFT processor function of the overlap-add channel splitter, the overlap-add combiner performs inverse FFT processing. From the point of view of practical applications, the generation of inverse FFT is implemented using forward FFT. The size of the FFT processor is configured to a power of 2 greater than the number of channels to be synthesized. In order to ensure throughput, the FFT processor includes multiple FFT machines, which are programmed with appropriate FFT sizes related to the signal processing parameters of interest. Implementing the FFT processor with multiple machines guarantees data throughput, because the processing time of a single machine is generally longer than the time required for the collection and processing of N samples.

A prescribed (comparatively limited) number of bin zeros are sequentially written into an FFT machine. For the subsequent bins, the data is read from the input dual-port RAM of the active channel. If the channel is not an active channel, the control logic unit writes zeros into the bin. The identification of these active channels is programmed into the control logic unit during system initialization. For the remaining (relatively limited) number of bins, write zeros.

In order to use the forward FFT to generate the inverse FFT, use the following notation: x[n]=K*FFT(X[((-k))K), where x[n] is the inverse FFT of x[k], and n is the sample K is the number of FFT bins, K is the FFT size, and X[((-k))K] is equal to the reverse order of the sequence x[k], modulo K. By generating a mirror image of the input data to the FFT about point (bin) 0, the forward FFT becomes an inverse FFT scaled by the FFT size. When writing data to the FFT machine, the FFT control logic unit addresses the input RAM in reverse order.

In the overlap-add channel splitter, in order to generate a 512-point FFT in the combiner structure, the FFT machine uses a radix-4 (block floating point) algorithm whose FFT size is a power of four. Using the radix-2 time-domain decimation butterfly algorithm, the N/2-point FFT is generated from the even and odd samples of the 512-point input sequence. The multiplication of odd-sampled FFT data values is realized by a numerically controlled oscillator and modulator (NCOM). In order to process the first 256 bins of the 512-point FFT, the output of the first half of the dual-port RAM is added to the output of the second half of the RAM through an ALU. For the last 256 bins, half of the outputs of the two RAMs are subtracted from each other. In order to tolerate the propagation delay through NCOM and ensure that the appropriate sample pairs are processed by the ALU, a set of delay registers are connected in the output channel from the RAM to the ALU.

The combiner algorithm requires the input sequence of the inverse FFT to be multiplied by a complex exponent, WKkmR, where k is the number of input frequency points (bin), K is the size of the inverse FFT, m is the number of inverse FFTs, and R is the interpolation rate of the combiner, And Wk=ej*2*π/K.

Using a mathematical identity, this multiplication operation can be performed by the cyclic shift of the output samples of the inverse FFT, that is: x[((nr))k] = inverse FFT(W-rk*X[k]), where r is equal to -mR. By looping the inverse FFT output sampling -mR times, a complex exponential phase shift is produced. This kind of cycle is realized by FFT output addressing logic.

Because the FFT machine uses a floating-point block algorithm to generate FFT, the algorithm provides a scale factor according to the characteristics of the input data. A barrel shift circuit is connected to the input channel of the signal stream to the ALU to adjust the FFT data to the same scale. In order to properly calibrate the data for subsequent processing.

Similar to the channel splitter, the overlap and add filter of the combiner includes multiple filter tap stages. The FFT size and the number of stages set the total length of the filter. The filter is designed as a real low-pass filter with a cut-off frequency equal to half of the channel bandwidth. The corresponding stage of the filter consists of one or two of a pair of delay memory cells of the shift register, feedback multiplexer, coefficient memory, multiplier and internal adder. Each coefficient memory stores a corresponding set of N filter (weighting) coefficients, the number of which corresponds to the size of the FFT processor. The output from the FFT processor of the ALU is distributed to the multipliers of all filter stages and multiplied by the coefficients of each stage at the same time. The output of a tap-stage multiplier is summed with the accumulated data and shifted by the delay memory in the tap-stage adder for use in the next stage of the filter.

The first tap stage of the filter does not need to be input to the delay memory section, because zeros are moved into the first filter stage first. The length of each delay memory is determined by the filter interpolation rate, which is defined according to the channel and output sampling rate. The filter interpolation rate, R, is the closest integer to the quotient of the output and channel sampling rate: R=round (output sampling rate/channel sampling rate) The length of each output delay memory section is R, and each input delay The length of the memory section, which is the overlap of the filters, is NR.

The interpolation rate R also specifies the signal processing rate required by the overlap and add filter. In order to ensure the pass rate, the minimum clock rate necessary for the filter to process data is given as follows: filter processing rate=output rate*N/R.

For every N samples output by the inverse FFT processor, the overlap and add filter outputs R samples. For the first R samples of each inverse FFT, the first input port through the multiplexer is selected. During this period of time, all data is input in clock ticks, and the summation generated by the adder in the last stage of the filter is input to a half-bandwidth filter. For the remaining NR samples, the second port of each multiplexer is selected, and the output of the internal adder of the corresponding stage is fed back to their delay memory section. During this time, the input memory part is not shifted, and the data from the adder in the last stage does not enter the half-bandwidth filter according to the clock cycle. As with the overlap and add filters in the channel splitter, the feedback of the last NR samples provides the overlap of the filters.

The half-bandwidth filter is configured as an integrated circuit that provides complex-to-real conversion, doubling the output sampling rate. Although the entire combiner can be implemented as a complete real system, this requires all sampling rates, processing rates, and FFT sizes to be doubled, increasing complexity and cost. The rate buffer is connected to the output of the half bandwidth filter to accommodate the continuous data stream from the combiner. The data stored in the rate buffer is connected to the output data link through the output drive unit for the DA converter on the transmitting side of the transceiver station. The half-full mark of the rate buffer is provided to the control logic circuit through the control signal line, and an instruction is sent to the TDM bus interface unit when data is requested. When the amount of data stored in the rate buffer drops below half of the capacity, the flag becomes invalid, informing the TDM bus interface to request channel data from its active channel to maintain a continuous output data stream.

As in the overlap and channel splitter structure, a corresponding oscillator is provided for each required output sampling rate. To include another set of logic circuits to generate additional clock signals used by the combiner. The clock output of the high-rate oscillator is divided by a counter to generate the necessary filter processing clock, TDM bus clock, and FFT machine system clock.

The second embodiment of the broadband channel splitter of the present invention is configured as a polyphase filter structure. As in the overlap-add channel splitter embodiment, the FFT-based polyphase filter array decomposition (channel splitter) system structure receives the real-time wideband IF (intermediate frequency) signal, performs frequency conversion, and divides it into multiple individual narrow The baseband decomposes the signal. The polyphase filter channel splitter provides fully programmable control of system parameters through the standard VMEbustm interface (specified by the Institute of Electrical and Electronic Engineers (IEEE), standard Std 1014-1987) and will be distributed in custom, time division multiplexing (TDM) ) Data channelization on the data bus.

In the multi-belief channel splitter structure, the input sampling rate is an integer multiple of the channel sampling rate, which means that the channel sampling rate must be a multiple of the channel bandwidth. The channelized data is divided into decomposed baseband signals by the channel splitter. The input of the channel splitter is interfaced with the digital data output link of the AD converter from the uplink broadband digital receiver. The input sampling clock rate is determined by the number of channels received and the bandwidth of these channels. As with the overlap and add embodiment, the amplitude monitoring logic circuit monitors the input data to provide automatic gain control of the input signal and ensure that the entire dynamic range of the AD converter in the receiver can be utilized.

The input sample enters the half-bandwidth filter according to the clock beat, and the input data is converted from real number to complex number. The half-bandwidth filter also extracts the data by two, halving the clock rate of the data. Then the complex data samples are fed into the shift register of the polyphase filter, in particular, into the delay memory forming part of the shift register in the first filter stage according to the clock cycle. The length of each delay memory is equal to the size of the FFT in the channel splitter. The output of each delay memory is provided to a coefficient multiplier, which operates at a rate I times the clock rate of the shift register, where I is an oversampling factor of 2. This means that each sample at the output of the delay memory is multiplied by a filter coefficient of 2 (I=2) before entering the next delay memory in a clock tick.

In the exemplary embodiment of the polyphase filter structure, four filter stages are used. The FFT size, oversampling factor, and number of stages constitute the total length of the filter. The N filter coefficients are stored in the coefficient RAM of each filter tap stage. When writing to the coefficient RAM, the filter coefficients are decimated by the number of taps (for example, four). The output of the corresponding coefficients and the data multiplier are summed and written into the dual-port RAM for use in the FFT processor of the multi-channel splitter.

The FFT processor of the multi-beam channel splitter has the same configuration as the FFT processor of the above-mentioned overlap and add channel splitter and operates in the same manner in fact. Once the FFT processed data of each channel (frequency point (bin)) is written into the output RAM, the FFT control logic unit informs the following TDM bus interface circuit to put the data on the TDM bus so that it can be used for the following numbers on the bus Signal processor, which is used to demodulate and extract live sounds or data from channel data. The multi-channel splitter can also be configured to write the data of one or more channels into a test memory, allowing the CPU on the VMEbustm to collect and analyze the channel data without having to interface with a custom TDM bus.

The signal processing structure of the polyphase combiner is complementary to the above-mentioned wideband channel splitter with a polyphase filter structure. It also allows real-time processing of multiple digital voice or data signals, frequency conversion and synthesis of signals into IF (intermediate frequency) The output sampling rate also provides fully programmable control of system parameters through the VMEbustm interface and channelizes the data collected on a custom, time-division multiplexed (TDM) data bus.

The front end (FFT processor) of the polyphase combiner is the same as in the above-mentioned overlap and add structure, but uses a different filter structure, in which the adder is not internally combined with the filter of the overlapped adder combiner. The corresponding delay memory is cascaded. The filter structure of the multi-phase combiner corresponds to that used in the multi-channel splitter. The output of the polyphase filter is connected to the half-bandwidth filter to provide the conversion of complex numbers to real data, doubling the output sampling rate. The output from the half-bandwidth filter to the output data link is provided to the DA converter on the transmitting side of the transceiver site.

Of course, even if the convolution filter is implemented using a polyphase structure, the above-mentioned interpolation filter must still be used in order to achieve the best sampling of the generated digital channel signal.

Brief Description of the Drawings Fig. 1 illustrates the receiver part of the channel unit of a conventional cellular communication base station; Fig. 2 is a multi-channel spectrum distribution diagram of four hundred (400) 30kHz sub-parts of a 12MHz wide voice/data communication frequency band; Fig. 3 Illustrates the broadband multi-channel transceiver device according to the present invention; FIG. 4A illustrates the channel splitter part of the multi-channel transceiver device; FIG. 4B illustrates the combiner portion of the multi-channel transceiver device; FIG. 5A is a diagram Illustrates the configuration of the overlap and addition embodiment of the convolution filter that can be used in the channel splitter device of FIG. 4A according to the first embodiment of the present invention;

FIG. 5B illustrates the configuration of the Fast Fourier Transform (FFT) that can be used with the overlap and add filter of FIG. 5A for the channel splitter; FIG. 6 is performed with the overlap and add channel splitter of FIG. 5A The functional diagram related to the signal processing mechanism; Fig. 7 illustrates an interpolation filter, which together with the convolution filter and FFT constitute a component of the channel splitter of Fig. 4A; Figs. 8A and 8B show exemplary digital channel signals x( n), the output signal z(n) of the exemplary rate converter, and several discrete time lines of the time domain response of the exemplary interpolation filter h(n); Figure 9 works with the interpolation filter shown in Figure 7 A functional diagram of a preferred embodiment of the filter index selector; Fig. 10 is a time-domain curve of a string of symbols expected to be received in each channel, and the symbol string is composed of a frame including a preamble part and a data part; Fig. 11A and 11B is a discrete time line representing the relative timing relationship between the digital channel signal x(n) and the interpolated channel signal z(n), divided into two cases of approximately one sample per symbol and two samples per symbol as desired.

Figure 12 is a functional diagram of the interpolation filter mechanism and the filter clock generator circuit used when the sampling rate of x(n) is not an exact integer multiple of the sampling rate of z(n); Figure 13 illustrates that it can be used to keep Sampling phase tracking function with proper timing relationship with interpolation filter.

FIG. 14A illustrates the signal processing structure of the multi-channel overlap and addition deconvolution filter. The filter forms a part of the combiner in FIG. 4B, and the function is the complement of the overlap and addition convolution filter in FIG. 5A; Fig. 14B illustrates the inverse fast Fourier transform processor forming part of the combiner in Fig. 4B, which is the complement of the FFT processor in Fig. 5B; Figs. 15A and 15B respectively illustrate the use of multiple processors according to another embodiment of the present invention. The configuration of the channel splitter of the phase convolution filter; FIGS. 16A and 16B respectively illustrate the configuration of the combiner using the inverse FFT and the polyphase deconvolution filter according to the second embodiment of the present invention; and Fig. 17 is a functional diagram related to the signal processing mechanism performed by the multi-phase implementation of the overlap and add combiner of Fig. 14B.

Detailed description Before describing in detail the broadband multi-channel transceiver specially improved according to the present invention, it should be noted that the present invention mainly focuses on novel combinations of commercially available communication and signal processing circuits and components, rather than their own particularly detailed structure. Therefore, the structure, control, and arrangement of these conventional circuits and components are illustrated with relatively easy-to-understand block diagrams, and only specific details related to the present invention are shown, so as not to benefit from the benefits of this description. Structural details that are very obvious to those skilled in the art make this disclosure unclear. Therefore, the block diagram in the figure does not necessarily represent the mechanical structure arrangement of the exemplary system, but mainly attempts to represent the main structural elements of the system in the form of convenient functional groups, so that the present invention can be understood more easily.

Referring now to FIG. 3, the transceiver device of the present invention is schematically illustrated as including a receiver part 100 and a transmitter part 200. The receiver part 100 is connected between the antenna 38 and the broadband receiver 101 capable of receiving any channel provided by the communication service provider. As a non-limiting example, the wideband receiver 101 may include a WJ-9104 receiver, manufactured by Watkins-Johnson, 700 Quince Orchard Road, Gaithersburg Maryland 20878-1794.

First, the relevant wireless spectrum is described, for example, a 12-megahertz (MHz) band including four hundred (400) channels, each of which is 30 kilohertz (kHz) wide. It should be noted, however, that the present invention is not limited to use with such or any other communication system parameters. The values given here are just to provide an illustrative example. Moreover, the term "wideband" is not limited to a specific spectrum range, and it should be understood that it means at least the entire useful part of the spectrum (for example, 12 MHz) covering the communication range that the system can operate. On the other hand, narrowband means only a part of the frequency spectrum, for example, the width of a single channel (for example, 30 kHz).

The output of the broadband receiver 101 is a down-converted, multi-channel (baseband) signal, including the content of all 30 kHz voice/data channels currently operable in the relevant communication system or network. This multi-channel baseband signal is connected to a high-speed AD converter 103, such as Model AD9032 AD converter, manufactured by Analog Devices, one Technology Way, Norwood, Massachusetts 02062-9106. Advantageously, the current commercial AD converters, such as those mentioned above, have sufficiently high dynamic range and sampling rate capabilities (for example, the sampling rate can be on the order of 25 megasamples per second (Msps)), It is possible to make downstream digital signal processing (DSP) components-including Discrete Fourier Transform (DFT) channel splitter 111, which will be described below with reference to Figures 4A-B-to process the signals of any of the 400 30kHz channels of the system and to do so The signal is output to the corresponding channel link connected to the telephone network carrier interface (for example, T1 carrier digital interface).

The fast Fourier transform (FFT) channel splitter 111 processes the output of the AD converter 103, which is connected to it through a digital in-phase/quadrature (I/Q) converter 107. The I/Q converter 107 outputs corresponding I and Q channel (ie, complex number) digitally formatted signals through the I and Q links 107I and 107Q, respectively. Then the FFT channel splitter 111 extracts the corresponding narrowband channel signal representing the content of the corresponding (30 kHz) communication channel received by the broadband receiver 101 from the composite digitized multi-channel (I/Q) signal. The corresponding channel signal is connected to the corresponding digital receiver processing unit 113-1,..., 113-N through N output links (for example, N=400 in this example), and each unit demodulates and executes the modulation signal The embedded error correction processing is the same as the conventional transceiver unit in Figure 1. Therefore, each digital receiver processing unit 113 may include a Texas Instruments TMS320C50 digital signal processor, manufactured by Texas Instruments, Post Office Box 655303, Dallas, Texas 75265. The demodulated signal obtained by the digital receiver processing unit 113 is connected to the telephone carrier interface (for example, the T1 carrier digital interface) of the following telephone network (not shown) through the corresponding channel links 115-1,..., 115-N.

The transmitter part 200 includes a second group of multiple digital signal processing units, specifically transmitter signal processing units 121-1,...,121-N. These units are connected to receive different narrowbands from the telephone network through the multi-channel network. (30kHz) Frequency channel transmits corresponding digital voice/data communication signals among multiple channels. Similar to the receiver digital signal processing unit 113 in the receiver part 100, the corresponding transmitter digital signal processing unit 121 may include a TMS320C50 digital signal processor manufactured by Texas Instruments. The transmitter signal processing unit 121 modulates corresponding ones of the multiple incoming communication signals and performs error correction processing before transmission, and provides the processed narrowband communication channel signals to the corresponding output ports 123-1,..., On 123-N. From the output ports 123-1,..., 123-N of the transmitter signal processing unit 121, the modulated narrowband channel signals are connected to a multi-channel combiner based on inverse FFT through channel links 125-1,..., 125-N The corresponding input port of the unit 131, as described below, the combiner unit outputs a synthesized signal. This composite signal represents the content of the wideband signal composed of the corresponding narrowband communication channel signal input to the digital transmitter signal processing unit 121. The output of the multi-channel combiner unit 131 is connected to the I/Q converter unit 132. The I/Q converter receives the in-phase and quadrature signal components from the combiner 131 on the links 131I and 131Q, and provides the combined output signal to the digital-to-analog (DA) converter 133. The digital-to-analog (DA) converter 133, similar to the high-speed AD converter in the receiver part 100, preferably includes a currently commercialized component, such as the AD9712A DA converter manufactured by Analog Devices. The output of the DA converter 133 is connected to the broadband (multi-channel) transmitter unit 141, and transmits a broadband (multi-channel) communication channel signal including the synthesized signal output by the combiner unit 131 based on the inverse fast Fourier transform. The output of the transmitter unit 141 is connected to the antenna 39 for transmission.

The present invention reduces the amount of hardware required to provide broadband coverage for cellular transceiver sites with increased (full frequency band) capacity. One of its characteristics is to extract the structure of the broadband multi-channel signal (channel splitter 111) and the broadband multi-channel signal synthesis Each of the structures (combiner 131) uses a convolution-decimation spectrum analysis technique. Because all the channels in the operable communication frequency band that the service provider can use can be processed by digital processing elements that operate at a very high data rate that can accommodate the actual bandwidth of todays wireless communication systems, instead of having to provide for each channel. To establish a single narrowband signal processing unit, it is not necessary to limit the number of channels at each site below the full capacity of the network.

More specifically, the present invention makes it possible to significantly reduce the size and hardware complexity of wireless communication network transceiver sites by using overlapping and adding or multi-channel splitter and combiner structures. The basic signal processing of this structure is The function is described in detail in Chapter 7 of the textbook "Multirate Digital Signal Processing" written by RECrochiere et al. and published by Prentice-Hall Inc.. Since the algorithms for each of these two filter transformation functions are strictly proposed in Crochiere's textbook, we will not repeat them here. For a detailed description of overlap and addition and multiphase signal processing, as well as related content, please pay attention to Crochiere's textbook.

The following description will detail practical embodiments of overlap and addition and polyphase, the implementation of each channel splitter and combiner used in the invented transceiver device, in order to perform real-time broadband wireless IF signal processing, The device performs frequency conversion and channel division on multiple single narrow baseband signals.

In addition, the following description includes a detailed discussion of the sampling timing adjustment filter, which uses interpolation and decimation digital signal processing techniques to achieve the best sampling timing in each digital channel signal output by the channel splitter, while making The rate necessary to perform the fast discrete Fourier transform is minimized.

Overview of Channel Splitter and Combiner (Figures 4A and 4B) Figure 4A is a high-level block diagram of the channel splitter 111 according to the present invention, including a convolution filter 40, an FFT processor 42, and multiple sampling rate converters 43-1, 43-2,..., 43-N. Each of the N output channels provided by the channel splitter 111 is associated with a rate converter.

The convolution filter 40 receives the I and Q samples from the forward I/Q converter 107 (Figure 3) and performs the first part of a set of operations necessary to divide the wideband digital input into independent digital channel signals, Each such signal represents the content of a corresponding one of the communication channels received by the wideband multi-channel receiver 101 (FIG. 3). As will be described in detail below, the convolution filter 40 may be embodied in an overlap and addition structure or a polyphase structure. A more complete discussion of each of these implementations of the convolution filter 40 will be given below in conjunction with FIG. 5A and FIG. 14A, respectively.

To put it simply, the convolution filter 40 acts as a sliding analysis window to select and weight consecutive short-time parts of the I and Q samples 107I and 107Q output by the converter 107. Then the discrete discrete Fourier transform of the sequence provided by the FFT produces a short-time spectrum, for example, with a specific sampling frequency. The size of the analysis window, that is, the tap length of the filter 40, and the number of samples of the discrete Fourier transform respectively determine the time and frequency resolution of the generated short-time spectrum. The overlap and addition structure, as described in detail in conjunction with FIG. 5A, effectively implements these functions by using the benefits of the effective method of sharing filter calculations between channels.

The output of the convolution filter 40 is a complex-valued digital signal, which is passed to a discrete Fourier transform unit, which is typically, but not limited to, implemented by a fast Fourier transform (FFT) unit 42. The FFT unit 42 generates N output signals, which are called digital channel signals. Each of the N digital channel signals output by the FFT unit 42 represents the content of a corresponding one of the communication channels received by the multi-channel receiver 101.

The preferred embodiment of the FFT unit 42 is described in detail in conjunction with FIG. 5B for the overlap and addition embodiment; for the multiphase embodiment, it is described in FIG. 14B.

Then, the digital channel signal output by the FFT unit 42 is fed into a plurality of rate converters 43-1,...,43-N. A rate converter 43 is associated with each input channel signal. The rate converters 43-1,..., 43-N operate by determining the interpolated digital signal value corresponding to the best sample of each digital channel signal.

In particular, each rate converter 43 provides samples of its corresponding digital channel signal at or near the peak symbol amplitude. Mathematically speaking, this operation is equivalent to generating a zero-filling extension of the corresponding output bin of the FFT unit 42 and then filtering the zero-filled signal with a low-pass, linear phase, finite impulse response (FIR) filter. Then determine the sampling position closest to the peak amplitude of this low-pass filtered signal. The output of the filter is then decimated with appropriate timing so that only the samples closest to the peak amplitude position are retained.

Optionally, the rate converters 43-1,..., 43-N can also adjust the sampling rate difference to make the necessary difference between the sampling rate provided by the FFT 42 and the sampling rate expected by the demodulator 113.

The rate converters 43-1,...,43-N are discussed in more detail below in conjunction with Figs. 7 to 13. After the rate conversion, the N digital channel signals are fed into the demodulator function performed by the digital signal processors 113-1,..., 113-N in FIG. 3.

Overlapping and adding channel splitter (Figures 5A, 5B, and 6) Before discussing the specific embodiment of the overlapping and adding channel splitter shown in Figures 5A and 5B, reference should be made to Figure 6, which illustrates the implementation The sequence of operations necessary for the weighted overlap-add structure of the DFT filter array analyzer. The input data, x(n), is first moved into the N(h)-bit sampling shift register 422 in a group of M samples, where Nh is the number of taps in the analysis window H(n). It is assumed here that Nh is equal to four K; that is, the size of the window is four times the transform size. The data in the shift register is then weighted with the time domain inverse window H(-R) to produce a short-time sequence ym(r). Then the sequence is divided into blocks starting with r=0 and a group of K samples, and time confusion is performed to generate a sequence xm(r) of K samples confusion. Then calculate the K-point DFT of xm(r) to obtain the short-time Fourier transform xK(m), which is called the sliding time frame. Finally, this transformation is multiplied by the factor WK-KnM and converted into the required fixed time frame transformation XK(m). For more details on this particular filtering algorithm, please refer to the textbook of Crochiere et al. mentioned above.

The implementation of this overlap and add filter depicted in Figures 5A and 5B provides fully programmable control of system parameters through a standard VMEbustm interface, as well as channelized data on a custom time division multiplexing (TDM) data bus. distributed. In order to provide an unrestricted illustrative example, a four-hundred (400) channel, 30kHz system (which can be used in North American Digital Cellular (NADC), such as the Electronics Industry Council and Telecommunications Industry Council standards (TIA/EIAIS- 54) Cellular system definition) and fifty (50) channels, 200kHz system (can be used with Pan-European Groupe Speciale Mobile (GSM) cellular standard) in order to facilitate the understanding of system parameters (channel bandwidth, number of channels, The relationship between the sampling and processing rate, etc.) and the control parameters of the channel splitter itself. For a 400-channel, 30-kHz system, it is assumed that the FFT output sampling rate is 50kHz. For a 200kHz system, assume that the FFT output sampling rate is 300kHz. The channelized data is output by the channel splitter as a decomposed baseband signal, and the channel sampling rate will depend on the filter design of the channel splitter, as will be discussed.

As indicated above, the raw data operated by the channel splitter 111 is obtained from the wideband receiver 101 (FIG. 3). The sampling rate of the AD converter 103 associated with the receiver is controlled by the sampling rate clock signal provided by the link 401 from the buffer/drive interface 403 under the control of the control unit 405. The control unit 405 preferably includes a set of combinational logic and flip-flops driven by a related clock source 407 in order to realize the state machine sequence control function to be described. The input sampling clock rate is determined by the number of received channels and the bandwidth of the received channel.

The filter system, the FFT processor, and the clock signal outputting the TDM bus to be described are obtained from the high-speed (for example, 200 MHz) reference oscillator 412 and the related down counters 414 and 416.

Since the channel splitter 111 is based on FFT, the total number of channels must be a power of two. Due to the characteristics of the anti-aliasing filter contained in the wideband receiver, channels close to the edge of the frequency band are generally not usable. In order to process 400 channels of 30kHz, the size of the FFT channel splitter must be a 512-point processor. In order to process 50 200kHz channels, a 64-point FFT processor is required.

The total input bandwidth sampled is N times the channel bandwidth, where N is the size of the FFT processor. The channel splitter algorithm requires an input sampling rate equal to 2*N*channel bandwidth, which is a sampling rate equal to the minimum rate required by the Nyquist sampling law.

Therefore, for a 30kHz channel splitter, the minimum clock rate is 25.62MHz, and a 200kHz channel splitter filter has a minimum clock rate of 19.05MHz. In this example, in order to adapt to each sampling rate, the clock unit 407 may include dedicated oscillators 407-1 and 407-2, as shown in the figure. Which oscillator is used is determined by the system controller (for example, a CPU (not shown) connected to the system VMEbustm410) during the initialization process.

For the 30kHz channel, the 512-point FFT channel splitter covers the 15.36MHz bandwidth, and the 400 30kHz channels cover 12MHz. Therefore, the receiver must concentrate 400 30kHz channels in the center of the 15.36MHz band, so that 56 channels or 1.68MHz guard bands are provided at both ends of the band to allow confusion. Similarly, for the 200kHz channel, the 64-point FFT channel splitter covers the 12.8MHz bandwidth. Placing 50 channels in the center provides 7 channels or 1.4 MHz guard bands at both ends of the band to allow for confusion.

Through the control signal from the controller 405 on the bidirectional link 415, the digitized data output by the receiver's high-speed AD converter is sampled sequentially on the link 411 according to the clock cycle through the buffer/driver interface 403 and loaded into the rate buffer FIFO (first entry , First out) memory 413. When data is fed into the rate buffer FIFO, its two most significant bits are monitored by the logic circuit 416 used as an amplitude monitoring unit in order to provide gain control of the input signal and ensure full utilization of the dynamic range of the AD converter. The output of unit 416 is fed back to the broadband receiver, which controls an attenuator (not shown) located before the AD converter.

When the FIFO rate buffer 413 includes a block of M samples, it sends a signal to the control unit 405 to start processing the data block. Subsequently, these M samples are moved out of the FIFO 413 on the link 417 in a burst at a rate higher than the input sampling clock rate and enter the half-bandwidth filter 419, so as to adapt to the size of the FFT processor. The FFT processor needs N samples. As will be explained in detail below, N>M means that the overlap and add filter must operate at a clock rate higher than half the input sampling rate.

The half-bandwidth filter 419 performs a real-to-complex conversion on the input data and decimates the data by a factor of 2, thus dividing the clock rate by two. These complex data values enter the shift register 422 used in the overlap and add filter 420 on the link 421 in a clock tick. The filter 420 includes two real low-pass filters, and the cut-off frequency is half of the channel bandwidth. The entire length of the filter 420 is given as follows: filter length=N*number of filter taps. The shift register 422 is preferably implemented by a cascaded delay memory unit 431 and an interleaved "feedback" multiplexer 433, as shown in FIG. Shown. The corresponding tap stage 430 of the filter 420 is composed of memory elements 431A and 431B, a feedback multiplexer 433, a coefficient memory 435, and a multiplier 437. Each coefficient memory 435 stores a corresponding set of filter coefficients, and the number of coefficients corresponds to the size of the FFT processor. In the initialization process, the system controller downloads the coefficients to the coefficient memory through 20 VMEbustm410.

In the illustrated embodiment, there are four tap stages 430-1,..., 430-4. The outputs of the multipliers 437 of the corresponding tap stages are added together through the summation stages 432, 434, 436. Therefore, as shown in the functional description in FIG. 5, the shift register 422 can be considered to be composed of a set of J cascade-connected K-stage shift registers (in the preferred embodiment, J is equal to four), or by a length of J *K-level single shift register is formed, and digital data sampling output is provided to the shift register. The total length (J*K) of the shift register 422 is given by the (time domain) window length required by the convolution filter, so that the longer the register (the greater the number of stages), the sharper the characteristics of the filter. For the 30kHz channel splitter in this example, a 50kHz channel sampling rate must generate 512-point FFT every 20 microseconds, and for a 300kHz sampling rate of 200kHz channel splitter, a 64-point FFT must be generated every 3.333 microseconds. For a 200kHz channel splitter using a 64-point FFT processor, the total length of the filter 420 is 256 stages.

As shown in FIG. 5A, the basic structure of the overlap and add filter 420 is similar to a finite impulse response (FIR) filter. However, the filter of the present invention is different from the conventional FIR filter because the feedback multiplexer 433 and the long delay line element (memory 431) are used between the filter taps. The length of the memory 431 is configured by the system controller during the initialization process and determined according to the filter decimation rate M, see above. The decimation rate is defined as: M = rounding (input sampling rate/2*channel sampling rate) For the example of a 30kHz channel splitter, the decimation rate is: M=3.072*107/(2*5.0*104)=307 For an example of a 200kHz channel splitter, the decimation rate is: M=2.56*107/(2*3*105)=43. In the memory 431, the length of the memory 431B is the decimation rate M; the memory 431A represents the "overlap" of the filter The length of is equal to NM, where N is the size of the FFT processor. Therefore, for the example of a 30kHz channel splitter, the length or "overlap" of the corresponding memory 431A is 512-307=205 samples, and in the case of a 200kHz channel, the overlap length of the memory 431A is 64-43=21 samples .

As pointed out above, the input data is processed in "blocks" of M data samples, which are moved out of the FIFO 413 at clock beats in bursts higher than the input sampling clock rate. In order to accommodate the FFT processor that requires N samples size. That is, N>M means that the overlap and add filter must operate at a clock rate higher than half the input sampling rate. The minimum clock rate of the filter is defined as: filter sampling rate=input sampling rate*N/(2*M) Therefore, for a 30kHz channel splitter, the minimum sampling rate is 25.62MHz, and a 200kHz channel splitter The minimum sampling rate is 19.05MHz.

In order to process each block of M input samples, N clock signals are required to provide a sufficient number of data samples to the FFT 42 (FIG. 4A) for FFT processing. Among the first M of the N clock signals, M samples pass through the rate buffer 431 and the half-bandwidth filter 419 and enter the shift register 422 according to the clock tick. In this time frame, the filter control unit 440 implemented as a state machine adds the selection control signal to the selection input port 433S of the multiplexer 433 through the link 442 to select its upper port 433-, and the clock is transmitted through the link 444. The signal is applied to the delay memories 431 so that the data is shifted through each delay memory 431 from left to right. For the remaining NM of the N data samples, the gating unit 440 makes each multiplexer 433 select its lower port 433-2, so that the data is not moved out of the rate buffer memory 413 according to the clock tick and no data is shifted through the delay memory 431B . In other words, the data is no longer shifted from left to right through the shift register, only the memory 431A still runs on the clock. This timing of the memory 431A is a mechanism for generating the filter overlap schematically illustrated in the functional flow diagram of FIG. 6.

More specifically, within N clocks, the output of the delay memory 431A is multiplied by the filter coefficients stored in the coefficient memory 435 of the four tap stages 430-1,..., 430-4. The first set of N coefficients are stored in the coefficient memory 435 of the tap stage 430-1; the second set of N coefficients are stored in the coefficient memory 435 of the tap stage 430-2; the third set of N coefficients are stored in the tap stage 430- In the coefficient memory 435 of 3; the fourth set of N coefficients are stored in the coefficient memory 435 of the tap stage 430-4. It should be noted that the number of tap stages is not limited to four or any other number. More stages can be used to increase the length of the filter to reduce aliasing between channels, increase channel selectivity and allow a reduction in channel sampling rate. That is, the rate at which data is moved into the convolution filter operation corresponds to the decimation rate M of the filter, and therefore the sharpness of the filter roll-off is controlled. The setting M for the best system performance depends on the FFT processing capability and the available sampling rate of the digitizing component (AD converter 103).

Overlap and add FFT processor (Figure 5B)

When the four sets of coefficient-weighted data samples generated by the filter stages 430-1,..., 430-4 are added together through the summation stages 432, 434, and 436, a convolutional data sequence of N samples confusing is generated, which is stored in the The RAM parts 451A and 451B are used in the dual-port RAM 451 for the FFT 42. As shown in Figure 5B, the preferred implementation of FFT 42 therefore includes dual-port RAM 451, arithmetic logic unit (ALU) 453, numerically controlled oscillator/modulator (NCOM) 455, FFT machine 460, scaling logic 466, barrel shifter Bit 471, dual port output 473 and other components. The addressing of the other parts of the dual-port RAM 451 and the FFT 42 is controlled by a state machine, and is preferably implemented with a logic gate array 468.

The processing rate of FFT 42 is defined as: FFT rate = 1/(channel sampling rate). For the 30kHz channel splitter example considered, it takes 20 microseconds to generate a 512-point FFT with a 50kHz channel sampling rate, while for a 200kHz channel split Router, 300kHz channel sampling rate, 64-point FFT must be generated at a rate of 3.333 microseconds. Since the general FFT equipment currently available cannot work at such a rate, in order to ensure throughput, the FFT unit 42 (Figure 4A) contains multiple FFT machines as shown in Figure 5B (three -461, 462, 463 in the example) , And program them with the appropriate FFT size associated with the relevant signal processing parameters. Three FFT machines are used to implement FFT 42, which reduces the FFT re-access time of the 512-point FFT processor to 60 microseconds, and the 64-point FFT processor to 10 microseconds. The FFT processor can be maintained with the currently available integrated circuits Real-time data throughput.

According to a preferred embodiment, the FFT machine uses a radix-4 (block floating point) algorithm whose FFT size is a power of 4. For a 512-point FFT processor, all 512 frequency bins are generated by using two 256-point FFTs using a 2-base butterfly operation with frequency decimation applied. In order to use N/2-point FFT to generate even-numbered points (bin) of N-point FFT, X[2k]=FFT(x[n]+x[n+N/2]), where x[n] is FFT N-point input sequence, k is the number of FFT points (bin), and X[k] is the sampling of FFT points (bin).

In the case of 512-point FFT, the samples are read from the dual-port RAM 451 and provided to the arithmetic logic unit (ALU) 453. Under the control of the FFT control logic unit 468, the unit 453 samples the data x[n] and x[ n+N/2] to add. At this time, the downstream digitally controlled oscillator modulator 455-whose output can be driven by the output of the ALU 453-is disabled by the FFT control logic gate array 468. The sum value is provided to the FFT processor 460 which generates the even frequency point (bin) FFT, that is, the X[2k]=FFT(x[n]+x[n+N/2]) proposed above, in order to generate N points For odd points (bin) of FFT, use the following equation: X[2k+1]=FFT((x[n]-x[n+N/2])*WNn) where WN=ej*2*π/ N.

In order to generate a 512-point FFT for odd-numbered points (bin), when the odd-numbered point (bin) data samples are read from the dual-port RAM 451, the FFT control logic unit 468 controls the arithmetic logic unit (ALU) 451 to take data samples x[n] And x[n+N/2]. This difference is multiplied by the numerically controlled oscillator and modulator 455, and enters the FFT processor 460 according to the clock beat to generate an FFT of odd frequency points (bin), that is, X[2k+1]=FFT((x[n]-x[ n+N/2])*WNn). In the case of a 200kHz channel splitter using a 64-point, four-power FFT machine, neither the ALU 453 nor the oscillator 455 is needed, so they are disabled by the FFT control logic unit 468.

As mentioned earlier, the FFT engine 460 uses a block floating point algorithm to output a four-bit scale factor together with the complex FFT data. This scaling factor is fed back to the scaling logic circuit 466 to control the barrel shift circuit 470, and the output of the FFT machine is connected to the shift circuit. When the data is read from the FFT machine, the barrel shift circuit 470 adjusts it to ensure that the continuous FFT is calibrated to the same scale. The output of the barrel shift circuit 471 is connected to the dual-port RAM 473.

As mentioned in the textbook of Crochiere mentioned above, the output of the Fourier transform operator (here is the FFT machine of the processor 460) is multiplied by the complex exponent WN-kmM, where M is the decimation rate, and k is the number of FFT bins. , M is the number of FFTs (blocks) (ie, for the first FFT generated, m=0; for the next FFT, m=1; for the third FFT, m=2; etc.). The decimation rate M is programmed into the FFT control logic unit 468 during the initialization process. In order to perform equivalent operations, the FFT unit 42 of FIG. 5B uses the following identity: x[(nr)N]=FFT(WN-rk*X[k]), where x[n] is the input sequence of FFT, As mentioned above, x[(nr)N] is x[n] modulo N cyclically shifted r times. In the embodiment shown in Figure 5B, r is equal to mM.

Instead of performing complex multiplication downstream of the FFT, the control logic unit 468 controllably addresses the dual-port RAM 473 to access the processed data values in the order that the FFT input data sequence is cyclically shifted.

Once the FFT processed data (bin) of each channel is written into the output dual-port RAM 473, the FFT control logic unit 468 sends a signal to the following time division multiplexing (TDM) bus interface circuit 475 to ensure that the data is on the TDM bus 480 In this way, the data can be added to the processor 113 following the TDM bus. Such a processor corresponds to the aforementioned processor 113, and may include a digital signal processor, whose role is to demodulate and extract voice or data from channel data, and also execute interpolators 43-1,...,43- The function of N, as will be briefly described.

The data on the TDM bus 480 is divided into multiple time slots (e.g., 400 time slots per TDM frame). The TDM bus can be driven with a 20MHz clock, allowing a single time slot to be used to output single-channel data up to a 50kHz sampling rate. If a higher channel sampling rate is required, multiple time slots can be assigned to a single channel. For example, a 300kHz sampling rate can allocate six time slots. Time slots can be dynamically allocated by the system controller, and the controller configures the channel splitter with all active time slots. If the data is already in the dual-port RAM 473 and the time slot is active, the channel splitter outputs the data through the buffer circuit 481 and puts the data ready signal on the TDM bus 480 together. All digital signal processors that collect data from this time slot will read data from the TDM bus. The bus connected to the processor is synchronized to the TDM bus through a conventional frame signal, so that the processor 113 (FIG. 3) can know the correct time slot from which to read data.

Interpolation filters (Figures 7 to 13) As mentioned briefly above in relation to Figure 4A, in the preferred embodiment, the digital channel signals provided by the FFT 42 are not directly provided to the digital signal processors 113-1, ..., 113- The demodulation and/or error correction algorithm performed by N. This is because, for the best detection probability, the demodulation algorithm used by the DSP processor 113 hopes to sample each channel signal at or near the peak amplitude of each symbol. Generally, this peak amplitude occurs in or near the middle of each symbol.

In the prior art single-channel system, each channel is processed separately, so each digitized channel only represents information from one channel. In such a method, the output of the AD converter 103 (FIG. 3) contains information belonging to only one channel. Generally, a phase-locked loop technique is used to ensure that the samples output from the FFT 42 have the best phase.

However, for a wideband channel splitter 111 such as that shown in FIG. 4A, what appears at the output of the AD converter 103 are signals from multiple channels. In addition, these channel signals may not be guaranteed to be synchronized with each other. Therefore, there is no single optimal sampling time for the AD converter 103, because each single channel signal cannot be guaranteed to be in phase. Therefore, it is impossible to provide the best sampling for each channel by simply adjusting the sampling time of the AD converter 103.

In this case, a possible solution is to increase the number of digital samples output by the FFT 42 by an interpolation factor L, so that at least one sample can be guaranteed to appear at or near the peak of each symbol of each digital channel signal. Through this method of increasing the output sampling rate of the FFT 42, it is possible to ensure that each channel has a sample close enough to the optimal point.

However, increasing the size of the FFT requires a considerable increase in computational complexity. For example, as long as the FFT size is increased by a factor of 4 to ensure that a sampling point can be sampled within at least ninety degrees (90°) of the optimal point, about eight times the computing resources are required. This is because the complexity of FFT calculation is increased by (N/2)log2(N) in the following order. Therefore, as an example, in the embodiment of FIG. 5B discussed above, twenty-four FFT machines are used instead of three FFT machines 461 , 462, and 463, which quadruple the sampling rate.

Therefore, instead of increasing the total amount of FFT computing power by a large amount, rate converters 43-1,...,43-N are used. The rate converter 43 uses effective interpolation and decimation techniques to effectively interpolate the samples output by the FFT, and then only decimates these samples at the best sampling points.

The uppermost diagram in FIG. 8A illustrates an exemplary signal processing performed by the rate converter 43-i on the digital channel signal x(n), which is provided by an output of the FFT 42. As you can see from the solid curve, the channel signal x(n) is composed of a series of AC symbols, the first symbol has an amplitude of positive 1, the second symbol has an amplitude of negative 1, and the third symbol has an amplitude of positive 1. . The actual samples provided as the digital channel signal x(n) are represented by deeper vertical sampling lines marked with "x" along the horizontal, discrete time axis. These actual samples are drawn at the input sampling rate fi.

The sampling rate converter 43-I determines the position of the interpolated samples extracted at the rate fs, which is an integer multiple of the input sampling rate fi. Then a subset of these interpolated samples, that is, those interpolated samples closest to the middle of each symbol, are selected as the best samples. The best sample is at the time indicated by the double arrow. The lower graph in Fig. 8A shows the output z(n) of the rate converter 43-i, which includes only those samples at the best positions decimated at the output sampling rate f0.

In order to perform this optimal interpolation between input samples, the digital channel signal x(n) must first be effectively filled with additional zero-valued samples between actual samples. The positions of these additional zero-valued samples are indicated in the x(n) graph with samples marked with "0" on the x-axis. Generally, this zero-stuffing occurs at some integer multiples of the actual sampling rate fi of x(n). In the illustrated example, the interpolation factor L is set to 8.

In order to generate the value of each of the L-1 interpolated samples between each actual sample, the zero-filled signal can be filtered with a low-pass filter with a linear phase response, such as an FIR filter. The time-domain impulse response h(n) of an example of such a linear phase filter is shown in the top graph of Fig. 8B. The impulse response h(n) has a time period, also called the number of taps, equal to N', where N'is determined by the required filter parameters, such as response time, cut-off frequency, and spikes.

However, because only some of the interpolated output samples are useful at any given time, only certain parts of the entire impulse response h(n) need to be calculated. In other words, only a specific one of the L possible decimation filters needs to be applied to the digital channel signal x(n) at any given time. The L possible decimation filters represent the L possible phase shifts of the rate converter 43-i.

At any given time, a specific one of the L decimation filters implemented by the rate converter 43-i is determined by the filter index parameter "p".

Therefore, an exemplary rate converter 43-i can be implemented by a digital filter device with a selectable phase input parameter "p", as shown in FIG. 7. The digital channel signal x(n) output from the FFT 42 is fed into a low-pass filter structure 71 that implements one of L possible decimation filters. A single decimation filter in the filter structure 71 has "g" taps, where "g" is determined by the ratio of the total impulse response length N'of h(n) to the interpolation rate L. In the example shown, N'is equal to 32 and L is equal to 8, so g is equal to 4. (Please note that in this discussion of the rate converter, although the N'value is convenient to express the length of the filter h(n), this N'value is the same as the N value discussed in the description of the FFT processor above. It does not matter.) In order to understand how to determine the L sets of filter coefficients required to implement the L filters, now pay attention to Figure 8B, and consider the time domain response of the L possible decimation filters given by the following relationship: h0( n)=h(n), for n=0, 2L, 3L,..., h1(n)=h(n), for n=1, L+1, 2L+1, 3L+1,..., h2(n)=h(n), for n=2, L+2, 2L+2, 3L+2,..., hk(n)=h(n), for n=k, L+k, 2L +k, 3L+k,,..., hL-1(n)=h(n), for n=L-1, 2L-1, 3L-1,...,

The time domain response of each such filter is depicted in the lower part of Figure 8B.

The selector 72 determines the required filter index p based on the number of factors. Generally, the selector 72 performs an initialization timing synchronization process to find the best possible "p" as a starting point. Then, by accurately tracking the sampling timing deviation caused by any slight difference in the ratio between the input sampling rate fi and the output sampling rate f0, the parameter p can be adjusted as needed, and the rate converter 43-i will always have the appropriate phase .

For the purpose of synchronization timing, some intermediate samples decimated at the rate fs are used. The positions of these intermediate samples are indicated by the single arrow in Figure 8A. The intermediate sampling rate fs is equal to the required output rate f0 multiplied by a factor M'. It should be noted that this synchronization factor M'is not necessarily equal to or an integer multiple of the interpolation factor L. (Please note that the interpolation factor is marked as M'for convenience in the context of discussing rate converters, but this value of M'has nothing to do with the M discussed in the operation of contacting the FFT processor.) Figure 9 is the selector 72 In the detailed block diagram, the selector 72 determines the intermediate sample value by generating a set of M intermediate output signals z0(n) to zM'-1(n). Each intermediate output signal provides samples at the required output symbol rate fo, but for a different possible phase. The result is therefore an integer number of M'samples for each symbol in the output signal z(n).

Before discussing the operation of the selector 72 in detail, consider a typical channel signal x(n) shown in FIG. 10, which includes a preamble part, s(n) and a data part d(n). In the preamble s(n), the channel signal x(n) is composed of a predetermined and well-known data symbol sequence, such as a series of alternating sequences of negative and positive symbol values as shown. The basic concept of the operation of the selector 72 is to determine the actual response of each of the M'possible filter parts with respect to this leading part. Since the required response to the preamble is known, the quality factor of each of the M'filter responses can be determined by correlating or comparing the M'actual responses with the ideal response. Then the filter part with the best correlation to the ideal preamble response is selected and used as the filter part when the rate converter 43-i receives the data part d(n).

As shown in FIG. 9, the exemplary rate converter 43-i includes a plurality of -M' filter structure parts 92-0,...,92-M'-1, and a plurality of correlators 93-0,..., 93-M'-1, the same multiple demodulators 91-0, ..., 91-M'-1, phase selection and tracking circuit 94, and peak detector and comparison circuit 95. The illustrated embodiment performs both the function of the filter structure 71 in FIG. 7 and the function of the selector 72.

In order to perform the function of the selector 72, the digital channel signal x(n) is first fed in parallel to each of the M'filter sections 92-0,...,92-M'-1, and each of the sections 92 corresponds to In one of M'possible phases. The specific phase of a given filter 92 is input as the parameter u. Each of the M'filter sections 92 operates on the digital channel signal x(n) to provide M'filtered signals z0(n),...,zM'-1(n).

The M'filtered signals are then fed into the corresponding one of the demodulators 91-0,..., 91-M'-1, removing any symbol modulation such as phase encoding. For example, one such code that was removed is the known π/4DQPSK (Differential Quadrature Phase Shift Keying), according to the "EIA/TIA Interim Standard Cellular System Dual Mode Mobile Station Base Station Compatibility Standard IS-54-B" , Dated April 1992, promulgated by the Telecommunications Industry Commission.

The outputs of the M'demodulators are then fed into the correlators 93-0,...,93-M'-1, and the other input of the correlator is the ideal preamble sequence s(n). In the described example, the ideal preamble consists of a series of alternating positive and negative signs. The output of each correlator circuit 93-0,...,93-M' represents the correlation value between the corresponding intermediate filtered signal z0(n),...,zM'-1(n) and the ideal symbol sequence s(n) . This correlation can be done in any suitable way, for example by integrating the difference between the two signals in the direction of the preamble.

Peak detection and comparison 95 then processes the output of each correlator. In particular, when a peak is detected in the output of one of the correlators 93-0,...,93-M'-1, the magnitudes of the outputs of all the correlators are compared. When the rate converter operates on the data portion of the digital channel signal x(n), the specific filter portion 92 corresponding to the maximum output correlator 93 is selected to be used as the desired filter portion 92. This is represented by outputting a parameter x.

The rate converter 43-i then enters the tracking mode, and the selected intermediate signal zx(n) is maintained as the output signal z(n) required by the selection and tracking circuit 94. Therefore, in this mode, only the selected filter section 92 needs to be operable. This tracking mode is maintained until the preamble mode is entered again, usually when another preamble is detected.

As will be briefly discussed, the selection and tracking circuit 94 can also be done by combining the response of the selected filter section 92-x with a subset of all the responses of the filter sections 92-0,..., 92-M'-1 In comparison, the parameter x is actively adjusted, based on an error detection criterion to determine when the filter part of another phase can provide a better sample value.

An exemplary signal flow diagram of M'filter sections 92-u is shown in FIG. 12. In the described example, the number of taps g is equal to 4. Therefore, the filter section 92-u includes four delay units 125-0,...,125-3, four filter coefficient memories 126-0,...,126-3, and four multipliers 127-0,...,127 -3, and three adders 128-1,...,128-3. The filter 92-u is a standard digital filter structure, in which each input sample x(n) is first fed to the first delay unit 125-0, and then in the subsequent sample count represented by the clock signal 129, or clock cycle When it appears, it enters the delay units 125-1, 125-2, and 125-3 behind. The clock signal 129 provides one or more clock pulses for each sample of the input digital channel signal x(n).

The first stage of the filter 92-u also includes a multiplier 127-0, which receives the output of the delay unit 125-0 as one of its inputs. The other input of the multiplier 127-0 comes from the coefficient memory 126-0, which stores the coefficient hp(0) numbered 0 for each of the L possible filter sections. Therefore, the filter coefficient parameter p described above is also input to the coefficient memory 126-0 for the selection of the required hp(0). The output of the first filter stage is the multiplier 127-0 which is then provided to the adder 128-1.

Similarly, the second filter stage includes a delay unit 125-1, a coefficient memory 126-1 storing a coefficient hp(1) for each of the L possible filters, and a multiplier 127-1. The output of the second filter stage is fed to the adder 128-1 together with the output of the first filter stage. The following third and fourth filter stages are implemented similarly.

The output samples of zu(n) including the filter section 92-u are extracted from the output of the final stage, which in the illustrated example is the third stage adder 128-3.

In order to adjust the sampling timing in order to produce the greatest possible correct symbol detection, the correct filter coefficient parameter p must also be maintained. If the input sampling rate fo, that is, the sampling rate of the input digital channel signal x(n) is equal to the sampling rate of the output signal z(n), or at least an integer multiple of this rate, this may be a relatively simple matter. In this case, the initial phase difference does not change with the input digital channel signal passed. However, in most practical systems, this is not the case, and one sampling rate may be greater or less than the other, and the ratio is not necessarily an integer. Therefore, the present invention also provides a convenient method for adjusting this non-integer sampling rate difference.

In particular, by appropriately controlling the frequency of the clock signal 129 input to the filter section 92-u and the parameter p, any sampling rate difference can be accurately adjusted. In order to understand how to accomplish this process, consider a typical exemplary input channel signal sequence x(n) and output signal z(n), as shown in Figure 11A. The samples of x(n) from n=-2 to n=5 are shown along the upper part of the horizontal time line. The required output samples z(n) are shown along the lower part of the timeline. The stray flag indicated by the reference number 116 indicates the possible location of the interpolation sample. In the described example, since L=8, there are eight possible positions for each interpolation sample. The delay in the timing of the first sample of the output digital channel signal z(0) relative to the most recent output sample x(0) is also shown. This delay is an initial estimate of the parameter p.

For a given x(n) and a given z(n), the sampling rate adjustment factor, μ, can be determined, which is equal to the frequency ratio of each sequence. In the example shown in FIG. 11A, the sampling frequency of the digital channel signal x(n) is 45 thousand samples per second (ksps), and the required interpolation output signal sampling rate z(n) is 24.3 ksps. The rate adjustment factor μ is therefore equal to 1.851. Therefore, for each desired output sequence sample z(n), there are about 2, but not very precise, 2 input sequence samples x(n).

The actual required output sampling rate f0 is generally specified by the symbol rate of the specific signaling standard implemented by the receiver 100. For example, the aforementioned output sampling rate of 24.3 ksps is specified by an exemplary time division multiple access (TDMA) implementation of a cellular system, such as described in the aforementioned IS-54-B standard. (It should be understood that the use of this technology is not limited to IS-54-B.) However, recall that the rate converter 43-i actually includes M'filter sections 92-0,..., 92-M'-1. In order to determine how to optimally adjust the sampling rate difference μ between the input digital channel signal x(n) and the output digital channel signal z(n), consider the sampling output time required by the filter section 92-u by the following formula Given: tu(n)=(n+uM)T]]> where u is the coefficient of the filter part 92-u, M'is the total number of the filter part 92, and T is the symbol interval. Given the input sampling interval, Ti=1fi,]]> then the rate adjustment factor μ is given by the following formula: μ=TTi,]]> and the coefficient vu of a specific input sampling at discrete time n is given by the following formula :Vu(n)=integer(tu(n)Ti)=integer[(n+uM)TTi],]]>The parameter p is pu(n)=round L(tu(n)Ti-vu(n)).]]>For each sample of the output sequence z(n), the number of samples that shifts the input sequence x(n) is the difference between the input sampling coefficients: qu(n)=vu(n)-vu(n-1).

Figure 12 shows how to determine the clock 129 driving the filter section 92-u and the parameter p. The counter 140 counts the number of z-samples and synchronizes to the output rate f0 required for the output signal z(n). The content of the z-sampling counter 140 therefore provides a sampling coefficient number nz equal to the current output sampling coefficient.

The multiplier 141 then determines the ratio , And the adder 142 adds the value to the current sampling coefficient number nz. In order to determine the appropriate deviation due to the difference between the input and output sampling rates, this value is multiplied by the rate adjustment factor μ by the multiplier 143. The output of the multiplier 143 is then fed into an integer part selector 144 and a subtractor 145. Therefore, the output of the integer part selector 144 provides vu(n).

This vu(n) value is then fed into the subtractor 149 and the delay unit 148. The output of the subtractor 149 is the number qu(n), which represents the x(n) coefficient of the previous sample used to generate the previous output sample z(n) and the x(n) sample used for the current required z(n) output sample The difference between the coefficients. In the example discussed in FIG. 11A, where μ=1.851, qu(n) will have a value of 2 or a value of 1, depending on the current time nz.

In order to maintain proper output sampling timing, this qu(n) value is fed into a clock pulse generator 150, which outputs the indicated clock pulses to the delay units 125-0,...,125-g-1 of the filter section 92-u number.

In order to determine the filter coefficient parameter p, in the case where the input and output sampling rates are different, the result of the multiplication from the multiplier 143 is fed to the subtractor 145 together with the index vu(n). By multiplying this result by the interpolation factor L in the multiplier 146, and then rounding the result in block 147, the parameter p is determined.

Therefore, when the z-symbol counter 140 is running and the subsequent samples of the output sequence z(n) are obtained, the coefficient p and the clock signal 149 are adjusted to ensure that the L possible filters are properly selected.

In the discussion so far, it is assumed that the output selector 94 (FIG. 12) is simply a selector for M to select one of the intermediate signals zx(n) given by the parameter x from the peak comparator 95. Therefore, when in the tracking mode, only the filter part 92-x needs to be implemented. However, if it is required to dynamically adjust the coefficients of the filter section, the tracking function 94 can be enhanced by performing a delay locked loop determination.

As shown in Figure 13, this involves determining the output of the three filter sections 92-x-1, 92-x, 92-x+1. The output of each of these three filter sections is then forwarded to the peak excursion detection circuit 132 which determines the adjustment factor xadj.

As shown in Figure 13, if the amplitude of the samples from the currently selected or on-time filter section 92-x is greater than the samples from the backward filter section 92-x-1 and from the advanced filter section 92-x+1 For these two, there is no need to adjust. In this case, the xadj factor is set to 0, and x is not adjusted.

However, if the sampling amplitude from the leading filter part 92-x+1 is greater than the value of the on-time filter part 92-x and the value of the backward filter part 92-x-1, it means that the phase adjustment must be performed and the rate The output of the converter 43-i is near the middle of the symbol. Therefore, the output adjustment factor +1 is added to the x parameter from the peak detection and comparison 95 before being used to select the active filter section 92-x.

Similarly, when the sampling amplitude from the backward filter part 92-x-1 is greater than the value of the on-time filter part 92-x and the leading filter part 92-x+1, it means that it needs to be reversed. In the direction of adjustment.

The aforementioned operations of the rate converter 43-i are generally implemented in the corresponding DSP 113-u related to the specific channel i. However, it should be understood that the operation of the rate converter 43-i can also be performed by appropriately arranged hardware. In addition, there is a DSP unit 113 dedicated to perform the function of the rate converter 43-i for a plurality of channels.

Overlap and add combiner (FIGS. 14A and 14B) FIGS. 14A and 14B illustrate the structure of the multi-channel combiner 131 that is complementary to the broadband channel splitter 111 with the overlap and add filter structure of FIG. 5A described above. Signal processing structure. As in the case of the channel splitter, the signal processing function of the multi-channel combiner essentially corresponds and is functionally equivalent to the signal processing flowchart of Fig. 7.20 shown in Fig. 17 corresponding to the above-mentioned Crochiere text.

Like the overlapping and adding channel splitter shown in FIG. 5A described above, the actual implementation used by the combiner unit 131 can process multiple digital voice or data signals in real time, and perform frequency conversion and combine the signals into one. IF (intermediate frequency) output sampling rate. The implementation of FIG. 14A provides fully programmable control of system parameters through standard VMEbustm interfaces 601 and 603 and provides channelized data collection on a customized, time-division multiplexed (TDM) data bus 605.

As described above for the channel splitter of Figures 5A and 5B, the overlap and add combiner of Figures 14A and 14B will be described as a 400-channel/30kHz system that can be used in NADC (TDMA) cellular systems, and a system that can be used in Europe A non-limiting example of the 50-channel/200kHz system of the GSM cellular system. For a 30kHz channel, it is assumed that the sampling rate is 50kHz. For 200kHz, assume that the sampling rate is 300kHz. The sub-channel data is received by the combiner as a decomposed baseband signal. The channel sampling rate varies according to the filter design of the combiner.

Since in typical cases, the total data rate of all channels exceeds the bus bandwidth of VMEbustm605 and other standard bus protocols, the combiner structure of Figures 14A and 14B uses a customized TDM bus 610 to collect a large number of channels at a relatively high data rate. data. The clock of the TDM bus 610 is set to 20 MHz to allow 400 time slots per frame. Each time slot can transmit a single channel of data up to the 50kHz sampling rate mentioned above. For higher rates, multiple time slots per frame can be allocated to a signal source. As mentioned above with reference to the TDM bus of the combiner of Figure 4, since each time slot processes a sampling rate of 50 kHz (and 6 x 50 kHz is 300 kHz), a sampling rate of 300 kHz will require 6 time slots per frame.

It is determined that the data source of the sub-channel on the TDM bus is formatted (for example, to become a cellular standard) and modulates the incoming voice or data signal from the accompanying telephone network to provide a baseband decomposed signal DSP processor 113 (FIG. 3). Each data source is allocated one or more time slots during which it will transmit a single complex sample once requested by the combiner. No two sources will be assigned the same time slot. The time slot is allocated by the system controller (independent CPU on VMEbustm605) during system initialization. The system controller also programs the combiner to specify all time slots that include valid data.

The samples from each DSP processor are requested by control signals applied to the TDM bus 610 from the TDM bus controller 611 (state machine implemented by the logic array) and the associated buffer/driver 613. This sample is written into a dual-port RAM buffer 615 through the bus buffer unit 617. The TDM bus control logic unit 611 synchronizes the addressing of the RAM buffer 615 to the frame signal of the TDM bus to ensure that each channel is written to the correct address in the dual port RAM 615. After the combiner has collected data from all working channels, the TDM bus controller 611 couples the control signal to the FFT control logic unit 620 through the link 612, so that the FFT control logic unit 620 initializes FFT processing. Like the logic gate array 468 in the channel splitter, the FFT control logic unit 620 is a state machine that is preferably implemented as a logic gate array. Complementary to the forward FFT processor function of the channel splitter in Fig. 4, the combiner in Fig. 6 implements an inverse FFT. However, in terms of implementation, as will be described, the inverse FFT is generated using a forward FFT.

FFT Processor The FFT processor shown at 630 in FIG. 14A is configured to have a size equal to the next "power of 2" greater than the number of channels to be combined. As mentioned above, 400 30kHz channels require a 512-point FFT, while 50 200kHz channels require a 64-point FFT. The size of the FFT is programmed into the FFT machine during initialization. The channel rate also specifies the FFT processing rate according to the following identity: FFT rate = 1/(channel sampling rate) As previously explained, the 50kHz sampling rate for 30kHz channels requires a 512-point FFT every 20 milliseconds, while the 300kHz sampling rate It is required to generate a 64-point FFT every 3.333 milliseconds. Since typical FFT devices currently available do not work at these speeds, in order to obtain throughput, the FFT processor 630 includes multiple FFT machines that have been programmed with the correct FFT size related to the signal processing parameters (for example, in the illustrated example The middle is 3 -631, 632, 633). Implementing the FFT processor 630 with multiple machines reduces the FFT re-access time of the 512-point FFT processor by 60 milliseconds, and the 64-point FFT processor by 10 milliseconds.

A 512-point inverse FFT requires 512 samples; but there are only 400 time slots. These 400 time slots are in the middle of the 512 bin window of the FFT processor 630. The control logic unit 620 sequentially writes 0 into the first 56 bins of the FFT machine. The following 400 bins can be read from the dual-port RAM 615 for the active channel data. If the channel is an inactive channel, the control logic unit 620 will write 0 to those bins. The identification of those active channels is 5, which is programmed into the control logic unit 620 during system initialization. For the last 56 points (bin), write 0 to them. (For a 64-point FFT, 0 is written to 7 FFT points (bin) before and after it to allow 50 200kHz channels.) To provide built-in test capabilities, test data can be written to one or more bins through VMEbustm605. For this purpose, a first-in-first-out (FIFO) memory 635 dedicated to test capabilities is connected to the bus 605 through the transceiver unit 601, so that the CPU on the VMEbustm 605 can write test signals to the combiner. In addition, the system controller can program the FFT control logic unit 620 to start from the FIFO memory 635 instead of the dual-port RAM for special bins. 615 read data. Test data can be written into 7 FFT bins at the head and tail, leaving 50 200kHz channels for the active data channel.

Use the following identity to generate an inverse FFT using forward FFT: x[n]=K*FFT(X[((-k))K]), where x[n] is the inverse FFT of X[k], and n is The number of samples, k is the number of FFT bins, K is the size of the FFT, and X[((-k))K] represents the inverse sequence of the sequence X[k] modulo K. By generating a mirror image of the input data to the FFT about the 0th point (bin), the forward FFT becomes an inverse FFT scaled by the FFT size. When the control logic unit 620 writes data into the FFT machine, the dual-port RAM 615 is addressed in reverse order.

As with the channel splitter implementation of Figures 5A and 5B, in order to generate a 512-point FFT in the combiner structure of Figures 14A and 14B, the FFT machine uses a base 4 (block floating point) whose FFT size is a power of 4. )algorithm. Using N*2 point FFT to generate even point (bin) of N point FFT requires: X[k]=G[k]+H[k]*WNk, where X[k] is the N point of the input sequence x[n] FFT, k is the number of FFT points (bin), N is the FFT size (512), G[k] is the N/2-point FFT of the even sample of x[n], and H[k] is the odd sample of x[n] N/2-point FFT, and WN=ej*2*π/N.]]> Same as the channel splitter in Figures 5A and 5B, the 512-point FFT used in the combiner also uses two 256-point FFTs produced.

The N/2-point FFT is generated from the even and odd samples of the 512-point input sequence. In the structure of FIG. 6, the first (top in the figure) FFT data dual-port RAM 641 stores G[k]. The second (bottom in the figure) FFT data dual-port RAM 642 stores H[k]*WNK. The multiplication of H[k] and WNK is performed by Numerically Controlled Oscillator/Modulator (NCOM) 651, with k from 0 to 255. To process the first 256 bins of the 512-point FFT, the arithmetic logic unit (ALU) 655 adds the output of the RAM 641 and the output of the RAM 642. Since WNk=-WNk-N/2, k is from 256 to 511, for the remaining 256 bins of the 512-point FFT, the output N of the RAM 642 is subtracted from the output of the RAM 641.

In order to adjust the propagation delay through the NCOM 651 and ensure that the ALU 655 processes the correct sample pair, a set of delay registers 657 are connected on the output path from the dual port RAM 641 to the ALU. (For a 200kHz channel, a 64-point FFT is used. Since 64 is a power of 4, NCOM 651, dual-port RAM 642, and ALU 655 are not required and they are disabled by the control signal from the control unit 620.) As mentioned above As described in the Crochiere text, as shown in Figure 17, the combiner algorithm requires the input sequence of the inverse FFT to be multiplied by a complex exponent WKkmR, where k is equal to the number of input frequency points (bin), and K is equal to the size of the inverse FFT, m Is the inverse FFT number (ie, for the first inverse FFT generated, m=0; for the next FFT, m=1; etc.), R is the interpolation rate of the combiner, and WK=ej*2* π/K.]]>Using mathematical identities, this multiplication operation can be realized by the cyclic shift of the inverse FFT output samples, that is: x[((nr))k] = inverse FFT(WK-rk*X[k] ), where r is equal to -mR. By shifting the inverse FFT output samples by -mR, a complex exponential phase shift is produced. This shift is performed by the FFT output addressing logic in the FFT control logic gate array 620. The shift count is programmed during the initialization of the combiner.

As mentioned earlier, the FFT machine uses a block floating point algorithm to generate FFT. Block floating-point FFT provides a scale factor that depends on the characteristics of the input data. Because the two 256-point FFTs used to generate a 512-point FFT may not have the same scale factor or the continuous FFT may not have the same scale factor, the barrel shift circuits 658 and 659 are connected to the ALU 655. Signal flow on the input path. As described above in connection with the operation of the channel splitter in FIG. 4, the barrel shifter adjusts the FFT data to the same scale to correctly align the data for subsequent processing.

The overlap and addition filtering is the same as the channel splitter of FIGS. 5A and 5B. The deconvolution overlap and addition filter of the combiner of FIG. 6 shown at 660 in FIG. 14B includes four filter tap stages. 660-1, 660-2, 660-3, 660-4. The FFT size and the number of stages set the total length of the filter, as defined by the following formula: filter length=N*number of stages, where N is the FFT size.

The filter 620 is actually designed as a low-pass filter with a cut-off frequency equal to half of the channel bandwidth. It should be observed that the filter is not limited to a 4-stage filter, more stages can be used if necessary, which will increase channel selectivity, reduce aliasing in the channel, and reduce the channel sampling rate. Each stage 630-I of the filter 630 is composed of one or two of the memory components 631A and 631B, a feedback multiplexer 633, a coefficient memory 635, and a multiplier 637. Each coefficient memory stores a set of N filter (weighting) coefficients, the number of which corresponds to the size of the FFT processor. The coefficient is downloaded to the coefficient memory 635 through VMEbustm605 during initialization. The address input of the coefficient memory is provided from the filter control state machine 670 (implemented by gate array logic) through the link 629, and the data input is connected through the data link.

The first N coefficients are loaded into the coefficient memory 635 of the first or leftmost stage 630-1, the second N coefficients are stored in the coefficient memory 635 of the tap stage 630-2, and the third N coefficients are stored in the tap In the coefficient memory 635 of the stage 630-3, the fourth N coefficient is stored in the coefficient memory 635 of the tap stage 630-4. The output from the FFT processor of the ALU 655 is distributed through the link 656 to the multipliers 637 of all filter stages and is simultaneously multiplied by the coefficients of each stage. The output of the multiplier 637 is connected to the adder 639, and is added to the data accumulated and shifted by the delay memory.

Like the filter of the channel splitter of FIG. 4, each stage of the delay memory excluding the first stage 630-1 is divided into two memory sections 631A and 631B. The first filter tap stage 630-1 does not need to delay the memory portion 631B because what is moved into the first filter stage is the 0 provided through the link 632 to the multiplexer 633. The length of each delay memory is determined by the filter interpolation rate, which is defined according to the channel and output sampling rate. The output sampling rate of the combiner is given by the following formula: output sampling rate=N*channel bandwidth.

For a 30kHz channel, the output sampling rate is 3.0*104*512=15.36MHz. For the 200kHz channel, the output sampling rate is 2.0*105*64=12.8MHz. The filter interpolation rate R is the closest integer of the following quotient: R = rounding (output sampling rate/channel sampling rate) As mentioned above, for the example using a 30kHz channel with a 50kHz channel sampling rate, the interpolation rate is R =307; for a 200kHz channel with a 300kHz channel sampling rate, the interpolation rate is R=43. The length of each delay memory part 631A is R, and the length of the delay memory part 631B, also called filter overlap, is given by the following formula: overlap=(NR).

Therefore, for a 30kHz channel, the filter overlap is 205; for a 200kHz channel, the filter overlap is 21. The interpolation rate R also specifies the signal processing rate required by the overlap and add filter. The minimum clock rate, the filter must be able to process data to maintain the throughput given by the following formula: filter processing rate = output rate * N/R.

For a 30kHz channel system, the minimum rate is 25.62MHz. For a 200kHz channel system, the rate is 19.05MHz.

For every N samples output by the inverse FFT processor, the overlap and add filter 660 outputs R samples. For the first R samples of each inverse FFT, the filter control state machine 670 selects the first or upper input port 633-1 of the multiplexer 633 through the selection control link 671. During this period, all data is shifted from left to right through the clock control link 669 or clocked from left to right by the clock, as shown in Figure 6, and the sum generated by the adder 639 in the final stage 630-4 of the filter Output to the half-band filter 672.

For the remaining NR samples, the second or lower port 633-2 of each multiplexer 633 is selected, and the output of the adder 639 is fed back to the delay memory part 631A through the link 638. During this period, the memory portion 631B is not shifted and the data in the last stage 630-4 is not clocked to the half-band filter. In addition, as with the channel splitter filter, the feedback of the last NR samples provides filter overlap.

Half-band filter and rate buffer Since the RF transceiver excitation source typically requires a real signal rather than a complex signal, the output of the filter 630 is connected to the half-band filter 672. The half-band filter 630 is configured as an integrated circuit that provides complex-to-real data conversion, which doubles the output sampling rate. Although the overall combiner of Figure 6 can be implemented as a complete real system, this requires all sampling rates, processing rates and FFT sizes to be doubled, which increases complexity and cost. The rate buffer FIFO memory 674 is connected to the output of the half-band filter 672 to allow continuous data flow from the combiner. The data stored in the FIFO memory 674 is connected to the output data link 690 through the output driver unit 675 for use by the DA converter 133 (FIG. 3) at the transmitting end of the transceiver station.

As mentioned earlier, the overlap and add filter 630 provides a burst of R samples every N clock cycles, and the output of the FIFO 674 provides a continuous data stream at the actual output sample rate. In addition, the half full flag from the FIFO is provided to the control logic circuit through the control signal line 673, and through the control link distributed between the respective state machines, it indicates when the TDM bus interface unit 611 requests data. When the amount of data stored in the FIFO 674 falls below half of the capacity of the FIFO, the flag becomes invalid, which indicates that the TDM bus interface needs to request channel data from the active channel and process it to maintain the continuity of the output data stream.

As with the channel splitter structure of Figs. 5A and 5B, each required output sampling rate is provided by a respective oscillator. For the current example of a combiner that can handle both 30kHz and 200kHz channels, 30.72MHz and 25.6MHz (2*output sampling rate) clocks 676 and 677 are provided respectively. During the initialization of the combiner by the system controller, the correct oscillator is selected by the associated control logic unit 678.

Contains another set of logic circuits to generate additional clock signals used by the combiner. Like the channel splitter structure of Figures 5A and 5B, the clock output of the high-rate (approximately 200MHz) oscillator 681 is divided by counters 682 and 683 to generate the required filter processing clock, TDM bus clock, and FFT machine system clock. .

Channel splitter using polyphase filter (FIGS. 15A and 15B) The second embodiment of the wideband channel splitter of the present invention is configured as a polyphase filter structure, and its function is based on the above-mentioned Crochiere text The signal processing flow chart shown in Figure 7.15 is represented. In addition, since the algorithm of each filter transformation function (respectively used by the polyphase implementation of the filter structure contained in the channel splitter 111 and the combiner 131 of FIG. 3) is precisely described in the Crochiere text, I won't repeat it here.

Like the overlap and addition channel splitter of Figure 5A, the structure of the FFT-based polyphase filter bank analysis (channel splitter) system of Figure 15A also accepts real-time wideband IF (intermediate frequency) signals and performs frequency conversion as well as The channel is divided into multiple independent narrow baseband decomposition signals. The polyphase filter channel splitter provides fully programmable control of system parameters through the standard VMEbustm interface and provides split-channel data distribution on a self-customized, time-division multiplexed (TDM) data bus. (Like the previous example, the following description of the implementation of the polyphase filter will emphasize the specific 400-channel/30kHz system, and the 50-channel/200kHz system.) The characteristic of the multi-channel splitter structure is that the input sampling rate is the channel An integer multiple of the sampling rate. This means that the channel sampling rate must be a multiple of the channel bandwidth. In this description, the channel is oversampled by a factor of 2; therefore, it is assumed that the sampling rate of the 30kHz channel is 60kHz, and the sampling rate of the 200kHz channel is 400kHz. The channelized data is distributed as a decomposed baseband signal by the channel splitter.

The half-band filter and amplitude monitoring are now more specifically referring to FIG. 15A. The input of the channel splitter is interfaced with the upstream wideband digital receiver through the buffer/driver unit 701, in particular with the digital output from the AD converter 103 of FIG. 3 Data output link 703 interface. The clock line 705 provides a sampling clock for the encoding clock of the converter. The input sampling clock rate depends on the number of channels received and the bandwidth of those channels. The amplitude monitoring logic circuit 708 monitors the highest two valid bits of the input data from the AD converter of the digital receiver on the data link 703 to provide automatic gain control of the input signal. This ensures that the full dynamic range of the AD converter 103 in the receiver is utilized. The amplitude monitoring logic circuit outputs a control word to the receiver on the link 709 for controlling the digital attenuator upstream of the AD converter.

A respective oscillator 702, 704 is provided for the input rate that each channel splitter may use. The selection and divide-by-two logic circuit 706 is connected to the oscillators 702 and 704 under the control of the filter state machine 707. During initialization, the system controller (CPU on VMEbustm) configures the channel splitter to select the correct oscillator. The oscillator clock is also divided down to generate a clock on the output clock link 712 to drive the shift register delay memory of the channel splitter to be described. The input samples on the data link 703 are clocked to the half-band filter 711, which is configured as a finite impulse response (FIR) filter that performs a real-complex domain transformation of the input data. The half-band filter 711 is also divided by two, halving the clock rate of the data. The multi-sample is then fed into the shift register 713 of the polyphase filter 715. In particular, the output of the half-band filter 711 is clocked to the delay memory 721 of the shift register 713 of the first filter stage 715-1 of the filter 715. The length of each delay memory 721 is equal to the FFT size in the channel splitter. The output of each delay memory 721 is used by the coefficient multiplier 723. The coefficient multiplier 723 and other hardware components all work at a rate that is one times the clock rate of the shift register 713, where I is the oversampling factor. As mentioned above, the oversampling factor is equal to 2. This means that each sample at the output of the delay memory is multiplied by 2 (I=2) filter coefficients before being clocked into a delay memory.

In the filter structure of FIG. 15A, the polyphase filter 715 includes four filter stages 715-1, 715-2, 715-3, and 715-4. The FFT size, oversampling factor, and number of stages determine the total length of the filter. The length of the filter is: filter length=I*N*S where S is the number of filter taps. As mentioned earlier, more filter stages improve channel selectivity and reduce aliasing in the channel. When the filter coefficients are provided from the VMEbustm interface 710 through the bus transceiver 731, the coefficients are downloaded to the coefficient RAM 725 by the control gate array 707. The RAM 725 of each stage 715-i stores N coefficients. When the coefficient RAM 725 is loaded according to the following decimation identity, the filter coefficient is decimated by the number of taps (here 4): Ca[n]=c[S*n+a], n is from 0 to N*I-1 where c (n) is the sequence of filter coefficients, a is the number of taps (a from 0 to S-1), and ca is the coefficient loaded into the taps. For example, the coefficient RAM 725 of the first filter tap stage 715-1 is loaded with the following coefficients: c0[n]={c[0], c[4], c[8], c[12]...c[I* NS]} Then the output of the coefficient multiplier 723 is summed by the adders 732, 734, and 736 and written into the dual port RAM 740 including the memory portions 741 and 742.

The FFT processor for the polyphase filter (FIG. 15B) As described above, the FFT processor of the polyphase combiner shown in FIG. 15B and the FFT processor of the overlap and add channel splitter of FIG. 5B are actually Have the same configuration and generally work in the same way. After the N samples are written into the dual-port RAM 740, the filter control unit 707 couples the control signal to the (state machine implemented by gate array logic) FFT control unit 735 via the link 719 to start FFT processing. In the FFT processor 7'50, a set of three FFT machines 751, 752, 753 have been pre-programmed with the correct FFT size during initialization.

As in the overlap and addition implementation of FIG. 5B, the FFT machine used by the polyphase combiner uses a radix-4 algorithm and generates a power-of-four FFT size. In the structure of FIG. 15B, all 512 bins of the FFT are generated by applying the radix 2 frequency decimation FFT butterfly algorithm to the 256-point FFT.

In the process of generating even-numbered FFT bins, data samples are read from the dual-port RAM 740 and fed into the arithmetic logic unit (ALU) 743. ALU 743 sums x[n] and x[n+N/2] and sends this sum directly to the FFT processor as a numerically controlled oscillator. The modulator (NCOM) 745 is used during even point (bin) processing. Prohibited. For singularity (bin) processing, the FFT control logic circuit 735 configures the ALU 743 through the control link 744 to obtain the difference between x[n] and x[n+N/2]. This difference is multiplied by WNn by NCOM 745 and timed to the FFT machine that generates a 512-point FFT bin. (For the 200kHz channel splitter, a power of 4 64-point FFT is required, and the ALU 743 and NCOM 745 are not required and they are disabled by the FFT control unit 735.) As described above, the FFT machines 751, 752, and 753 use block floats. Point algorithm and output a 4-bit scale factor together with the complex FFT data. The scale factor is used to control the downstream barrel shifter 761 under the control of the proportional logic circuit 762. In addition, the barrel 10 shifter is used to adjust the data read from the FFT machine to ensure that the data from the continuous FFT is adjusted to the same scale. The data from the barrel shifter 761 is written into the dual port RAM memory 765.

As mentioned above, the channel splitter algorithm requires the output of the FFT processor to be multiplied by a complex exponent WN-kmM, where M = decimation rate, K = number of FFT points (bin), and m = number of FFT (blocks) ( That is, for the first FFT generated, m=0; for the next FFT generated, m=1; 20, etc.). In other words, use the following identity: x[((nr))N]=FFT(WN-rk*X[k]) where x[n] is the FFT input sequence, and x[((nr))N] is x[n] is cyclically shifted by r modulo N, and the channel splitter performs equivalent operations. Here, mM=r. Different from the complex exponent downstream of the multiplying FFT processor, the FFT control logic unit 735 of the channel splitter can control the addressing of the dual-port RAM 765 to perform sequential access processing of the cyclic shift of the data sequence of the FFT. Data value.

Once the FFT processed data for each channel (frequency point (bin)) has been written into the dual-port RAM 765, the FFT control logic unit 735 signals the auxiliary time division multiplexing (TDM) bus interface circuit 767 to determine the data On the TDM bus 770, it can be used by the auxiliary digital signal processor on the bus for demodulating and extracting voice and data from the channel data.

The multi-channel splitter can also be configured to write one or more data channels into the test FIFO memory 771. The FIFO memory 771 allows the CPU on the VMEbustm to collect and analyze channel data without interfacing with the customized TDM bus 710.

Once the data from each channel has been written into the dual-port RAM 765 from the FFT machine, the FFT control logic unit 735 uses a signal to notify the TDM bus interface logic circuit 767 to distribute the data to the bus for demodulating and extracting the data from the channel. Digital signal processor for voice and data digital signal processor. The bus buffer unit 775 is connected between the dual port RAM 765 and the TDM bus 770. The data on the TDM bus can be divided into 400 time slots per frame provided by the counter circuit 781 as if driven by the high-speed reference oscillator 782, thereby allowing a single time slot to be used to output a sampling rate up to 60kHz Single channel data. If a higher channel sampling rate is required, multiple time slots can be allocated to a single channel. For example, as described above, a 400kHz sampling rate will allocate 7 time slots.

Time slots can also be dynamically allocated by the system controller. The channel splitter is configured by the controller with all active time slots. If the data exists in the dual-port RAM and the time slot is active, the channel splitter outputs the data and a data available signal on the TDM bus. All processors that collect data from this time slot will read data from the TDM bus. The processor is synchronized with the TDM bus 770 by the frame signal, so the processor will know the correct time slot from which data will be read.

Polyphase combiner (FIGS. 16A and 16B) FIGS. 16A and 16B illustrate the signal processing structure of the multiphase implementation of the combiner 131, which is similar to the above-described multiphase filter of FIGS. 15A and 15B The broadband 20-channel splitter is complementary. A feature of the polyphase combiner is that the output sampling rate is an integer multiple of the channel sampling rate. This means that the channel sampling rate must be a multiple of the channel 25 bandwidth. In this description, the channel is oversampled by a factor of 2, therefore, it is assumed that the sampling rate of the 30kHz channel is 60kHz, and the sampling rate of the 200kHz channel is 400kHz. The channelized data is received by the polyphase combiner as a decomposed baseband signal.

Like the overlap and add combiner shown in Figures 14A and 14B described above, the actual implementation used by the multiphase combiner can process multiple digital voice or data signals in real time, and perform frequency conversion and combine the signals into one IF (intermediate frequency) output sampling rate. The implementation of FIGS. 16A and 16B provides fully programmable control of system parameters through standard VMEbustm interfaces 801, 803 and provides channelized data collection on a customized, time-division multiplexed (TDM) data bus 805.

In addition, as with the description of the multi-channel splitter above, the multi-phase combiner will be described as a 400-channel/30kHz system that can be used in the NADC (TDMA) cellular system, and a 50-channel system that can be used in the European GSM cellular system. A non-limiting example of the /200kHz system. For a 30kHz channel, it is assumed that the sampling rate is 50kHz. For 200kHz, assume that the sampling rate is 400kHz. The channelized data is received by the combiner as a decomposed baseband signal. The channel sampling rate varies according to the filter design of the combiner.

Since in typical cases, the total data rate of all channels exceeds the bus bandwidth of VMEbustm805 and other standard bus protocols, the combiner structure of Figures 16A and 16B uses a customized TDM bus 810 to collect a large number of channels at a relatively high data rate. data.

In order to implement a transceiver system using a polyphase combiner (and channel splitter), it is appropriate to set the TDM bus clock to 24MHz, which allows 400 time slots per frame, and each time slot can be up to the above mentioned A single channel of data is transmitted at a sampling rate of 60kHz. This clock rate is different from the TDM bus clock rate in the overlap and add combiner/channel splitter embodiment of a transceiver system with a channel sampling rate of 50 kHz given as an example. The clock rate is not limited to this value, but was chosen to provide a simple example of the implementation of a transceiver system.

For higher rates, multiple time slots per frame can be allocated to a single signal source. As mentioned above with reference to the TDM bus of the channel splitter of Figures 16A and 16B, a sampling rate of 400 kHz would require 7 time slots per frame.

It is determined that the channelized data source on the TDM bus is a DSP processor that is formatted (for example, to become a cellular standard) and modulates the incoming voice or data signal from the auxiliary telephone network to provide a baseband decomposed signal. Each data source is allocated one or more time slots during which it will transmit a single complex sample once requested by the combiner. No two sources will be assigned the same time slot. The time slot is allocated by the system controller (independent CPU on VMEbustm805) during system initialization. The system controller also programs the combiner to specify all time slots that include valid data. The samples from each DSP processor are requested by control signals applied to the TDM bus 810 from the TDM bus controller 811 (state machine implemented by the logic array) and the associated buffer/driver 813. This sample is written into a dual-port RAM buffer 815 through the bus buffer unit 817. The TDM bus control logic unit 811 synchronizes the addressing of the RAM buffer 815 to the frame signal of the TDM bus to ensure that each channel is written to the correct address in the dual port RAM 815.

After the combiner has collected data from all working channels, the TDM bus controller 811 couples the control signal to the FFT control logic unit 820 via the link 812, so that the FFT control logic unit 820 initializes FFT processing. The FFT control logic unit 820 is a state machine preferably implemented as a logic gate array. Complementary to the forward FFT processor function of the channel splitter in Fig. 7, the polyphase combiner in Fig. 8 implements an inverse FFT. However, like the overlap and add combiner of Figure 6, in terms of actual implementation, as will be described, the generation of the inverse FFT is done using a forward FFT.

After the combiner has collected data from all working channels, the TDM bus controller 811 couples the control signal to the FFT control logic unit 820 via the link 812, so that the FFT control logic unit 820 initializes FFT processing. The FFT control logic unit 820 is a state machine that is preferably implemented as a logic gate array.

The FFT processor (FIG. 16A) is complementary to the forward FFT processor of the channel splitter in FIG. 15B, and the polyphase combiner in FIG. 16A implements inverse FFT. However, like the overlap and add combiner of Figure 6, in terms of actual implementation, as will be described, the generation of the inverse FFT is done using a forward FFT.

The two polyphases shown at 830 in Figure 14A? ? ? The FFT processor is configured to have a size equal to the next "power of two" greater than the number of channels to be combined. As mentioned above, 400 30kHz channels require a 512-point FFT, while 50 200kHz channels require a 64-point FFT. The size of the FFT is programmed into the FFT machine during initialization. The channel rate also specifies the FFT processing rate according to the following identity: FFT rate = 1/(channel sampling rate) As previously explained, the 60kHz sampling rate for a 30kHz channel requires a 512-point FFT every 16.667 milliseconds, while the 400kHz sampling rate It is required to generate a 64-point FFT every 2.5 milliseconds. Since typical FFT devices currently available do not work at these speeds, in order to obtain throughput, the FFT processor 830 includes multiple FFT machines that have been programmed with the correct FFT size related to the signal processing parameters (for example, in the illustrated example The middle is 3 -831, 832, 833). Implementing the FFT processor 830 with 3 machines reduces the FFT revisit time to 50 milliseconds for the 512-point FFT processor and 7.5 milliseconds for the 64-point FFT processor.

As previously described, a 512-point inverse FFT requires 512 samples; but only 400 time slots. These 400 time slots are in the middle of the 512 bin window of the FFT processor 830. The control logic unit 820 writes 0 sequentially into the first 56 bins of the FFT machine. The following 400 bins can be read from the dual-port RAM 815 for the active channel data. If the channel is an inactive channel, the FFT control logic unit 820 will write 0 to those bins. The identification of those active channels is programmed into the control logic unit 820 during system initialization. For the last 56 points (bin), write 0 to them. (For 64-point FFT, 0 is written to 7 FFT points (bin) before and after it to allow 50 200kHz channels.) In order to provide built-in test capability, test data can be written to one or more bins through VMEbustm805. For this purpose, a first-in-first-out (FIFO) memory 835 dedicated to test capabilities is connected to the bus 805 through the transceiver unit 801, so that the CPU on the VMEbustm can write test signals to the combiner. In addition, the system controller can program the FFT control logic unit 820 to start from the FIFO memory 835 instead of the dual-port RAM for special bins. 815 read data. Test data can be written into 7 FFT bins at the head and tail, leaving 50 200kHz channels for the active data channel.

In order to use forward FFT to generate an inverse FFT, the FFT control logic unit 820 addresses the input dual-port RAM 815 in reverse order when writing data to the FFT machine.

Similar to the implementation of the overlap and add combiner in Fig. 14A, in order to generate 512-point FFT in the polyphase combiner structure in Fig. 16A, the FFT machine uses base 4 (block floating point) whose FFT size is a power of 4. algorithm. Also in the combiner of Figure 14A, the 512-point FFT of the combiner is generated from two 256-point FFTs. The N/2-point FFT is generated from the even and odd samples of the 512-point input sequence.

In the structure of FIG. 14A, the first (upper side in the figure) FFT data dual-port RAM 841 stores G[k]. The second (bottom in the figure) FFT data dual-port RAM842 stores H[k]. The multiplication of H[k] and WNK is performed by Numerically Controlled Oscillator/Modulator (NCOM) 851, with k from 0 to 255. To process the first 256 bins of the 512-point FFT, the arithmetic logic unit (ALU) 855 adds the output of the RAM 841 and the output of the RAM 842. Since WNk=-WNk-N/2, k is from 256 to 511. For the remaining 256 bins of the 512-point FFT, the output of RAM 842 is subtracted from the output of RAM 841 by NCOM.

In order to adjust the propagation delay through the NCOM 851 and ensure that the ALU 855 processes the correct sample pairs, a set of delay registers 857 20 are connected on the output path from the dual port RAM 841 to the ALU. (For a 200kHz channel, a 64-point FFT is used. Since 64 is a power of 4, NCOM 851, dual-port RAM 842, and ALU 855 are not required and they are disabled by the control signal from the control unit 820.) Compared with the Crochiere referenced above As the text points out, the combiner algorithm requires the input sequence of the inverse FFT to be multiplied by a complex exponent WKkmR, where k is equal to the number of input frequency points (bin), K is equal to the size of the inverse FFT, m is the number of inverse FFTs, and R is the combiner Interpolation rate, and WK=ej*2*π/K.]]> Using mathematical identities, this multiplication operation can be realized by the cyclic shift of the inverse FFT output sample, that is: x[((nr))k]=inverse FFT(WK-rk*X[k]), where r is equal to -mR. By shifting the inverse FFT output samples by -mR, a complex exponential phase shift is produced. This shift is performed by the FFT output addressing logic in the FFT control logic gate array 820. The shift count is programmed during the initialization of the combiner.

In addition, the FFT machine uses block floating point arithmetic to generate FFT, and block floating point FFT provides a scale factor that depends on the characteristics of the input data. Because the two 256-point FFTs used to generate a 512-point FFT may not have the same scale factor or the continuous FFT may not have the same scale factor, the barrel shift circuits 858 and 859 are connected to the ALU 855 Signal flow on the input path. As previously described in connection with the operation of the overlap and add combiner in FIG. 14A, the barrel shifter adjusts the FFT data to the same scale to correctly align the data for subsequent processing.

The output of the FFF provided by the polyphase filter (FIG. 16B) ALU 855 is timed into the delay memory 861 of the shift register 863 of the first filter stage 865-1 of the filter 865. The length of each delay memory 861 is equal to the FFT size. The output of each delay memory 861 is used by each coefficient multiplier 869. The coefficient multiplier 869 and other hardware components all operate at a rate that is one times the clock rate of the shift register 863, where I is an oversampling factor of 10. As mentioned above, the oversampling factor is equal to 2. This means that each sample at the output of the delay memory is multiplied by 2 (I=2) filter coefficients before being timed to the next delay memory.

In the filter structure of FIG. 16B, the polyphase filter 865 includes four filter stages 865-1, 865-2, 865-3, and 865-4. The FFT size, oversampling factor, and number of stages determine the total length of the filter. The length of the filter is: filter length=N*S where S is the number of filter taps. As mentioned earlier, more filter stages improve channel selectivity and reduce aliasing in the channel. Like the filter coefficients provided from the VMEbustm interface 803 through the bus transceiver 801, the filter coefficients are downloaded from the control gate array 871 to the coefficient RAM 867. The RAM 867 of each level 865-i stores N coefficients. When the coefficient RAM 867 is loaded according to the following decimation identity, the filter coefficient is decimated by the number of taps (here 4): Ca[n]=c[S*n+a], n is from 0 to N-1 where c(n ) Is the sequence of filter coefficients, a is the number of taps (a from 0 to S-1), and ca is the coefficient loaded into the taps. For example, the coefficient RAM 725 of the first filter tap stage 865-1 is loaded with the following coefficients: c0[n]={c[0], c[4], c[8], c[12]...c[NS] }The output of the coefficient multiplier 869 is then summed by the adders 872, 874, and 876 and provided to the half-band filter 872.

The half-band filter and rate buffer (Figure 16B) are the same as the overlap and add combiner of Figure 14A. Since the RF transmitter excitation source typically requires a real signal instead of a complex signal, half-band filtering is usedDevice672. The half-band filter 872 is configured as an integrated circuit that provides complex-to-real data conversion, which doubles the output sampling rate. Although the overall combiner of Fig. 8 can be implemented as a complete real system, this will require all sampling rates, processing rates and FFT sizes to be doubled, increasing complexity and cost.

The output of the half-band filter 872 is connected to the output data link 866 through the output driving unit 874 for use by the DA converter (FIG. 3) at the transmitting end of the transceiver site. Like the combiner structure of Figure 6, a separate oscillator is provided for each output sampling rate required. For the current example that can handle both 30kHz and 200kHz channels, 30.72MHz and 25.6MHz (2*output sampling rate) clocks 876 and 877 are provided respectively. During the initialization of the combiner by the system controller, the correct oscillator is selected by the associated control logic unit 878.

Contains another set of logic circuits to generate additional clock signals used by the combiner. As with the combiner structure of FIG. 6, the clock output of the high-rate (approximately 200 MHz) oscillator is divided by counters 882 and 883 to generate the required filter processing clock, TDM bus clock, and FFT machine system clock.

As admired in the foregoing description, the multi-channel transceiver device of the present invention successfully avoids the limited channel capacity and substantial hardware requirements related to the signal processing structure currently used by multi-channel wireless communication (e.g., cellular) service providers. The use of convolution-decimation spectrum analysis technology for each wideband multi-channel signal extraction structure and wideband multi-signal combination structure reduces the amount of hardware required to provide wide coverage for expanded (full spectrum) cellular transceiver sites. Since all channels of the operable communication band available to the service provider can be processed by digital processing elements that work at a very high data rate that adapts to the substantial bandwidth of todays wireless communication systems, it is no longer necessary to construct one for each channel. The independent narrowband signal processing unit may limit the number of channels per site to be less than the total capacity of the network. The concise design of the present invention makes it easily physically accommodated in different installation sites, such as the suspended ceiling in office buildings or on electric tool poles, and has the ability to provide multi-channel communication services that span the entire channel capacity provided by the service provider. And not just a subset of the available channels.

When we show and describe several embodiments 20 according to the present invention, as known by those skilled in the art, it should be understood that there are also not limited but many changes and modifications are allowed, and we therefore do not wish to be limited to The details shown and described here are intended to cover all such changes and modifications that are obvious to a person skilled in the art.