Delay line system, high frequency sampler, analog-to-digital converter and oscilloscope

Delay line systems, high-frequency samplers, analog-to-digital converters, and oscilloscopes

Technical field

[0001] The present invention relates to a delay line system for high frequency signal transmission. The invention also relates to a high frequency sampler comprising a delay line system. The invention also relates to an analog-to-digital converter comprising a high frequency sampler. Finally, the present invention relates to an oscilloscope comprising an analog-to-digital converter for measuring a high frequency signal.

Background technique

The sampling frequency fs of an analog signal having a frequency component from 0 hertz to B hertz must be higher than the Nyquist rate fN to avoid aliasing effects. This can be represented by the following equation:

[0003] fs ^ fN = 2 & lt; B & gt ;.

[0004] Therefore, the higher the bandwidth B of the analog input signal, the higher the required sampling rate dj. This is why applications requiring very high analog input bandwidth, B, such as a real-time oscilloscope (RT0), are required for very high sample rates.

[0005] Referring to W0 94/06121 A1, a high-speed instantaneous sampling unit is described. Wherein the tap transmission line is used to transfer an input signal from an input node of the transmission line to an output node. The tap is provided with a high-speed sampling gate and a distributed gate is applied at the high-speed sampling gate. Each sampling gate obtains the same distributed gating signal without phase shift. Therefore, the same strobe signal is applied at each tap of the transmission line, thereby increasing the sampling rate.

[0006] Another method for increasing the sampling rate is shown in FIG. Herein, an input node for applying an analog input signal IN, which needs to be sampled using a so-called interleaved sampling architecture, is shown. Such an interleaved sampling architecture is described, for example, in the prior art document US 2013/0027234 A1. Interleaved sampling architecture is very attractive for increasing the sampling rate. Where the individual analog-to-digital converter (ADC) Γ, ADC 1 "and ADC 1" 'are interleaved, thus increasing the overall sampling rate of the system. Thus, each ADC 1 obtains a different sampling unit 2 and a different digitizing unit 3. On the sampling unit 2 and the digitizing unit 3, a sampling clock 5 is provided. Thus, time interleaving to improve the overall sampling rate of the system is achieved by operating two or more ADCs 1 in parallel. Based on experience, parallel operation of N ADCs 1 increases the sampling rate by approximately N times.

Each ADC 1 obtains a phase shifting unit 4 that applies a phase shifting unit 4 to delay a particular sampling clock 5 for each particular ADC1. Each sampling unit 2 in front of the respective ADC 1 thus receives a clock signal CLK having a determined phase shift, fW,%, and decay so that the sampling times of the sampling unit 2 are equally spaced in time. Thereby realizing an interleaving operation for generating an effective clock signal. By using the clock signal CLK at the frequency f, the effective clock can be expressed by the following equation:

Feff = f ci [omicron] k * N

[0009] Thus, a higher sampling rate is achieved with this architecture.

[0010] A clocking diagram of a quadruple interleaved sampler is shown in FIG. The sample clock 5 is applied to the ADC 1 and provides the sample S0. The clock 5 & apos; provides a sample clock that is phase shifted by phase shifter 4 & apos; and provides a sample Sl of the input signal IN. Clock 5 & quot; provides a sample clock that is phase-shifted by% by phase shifter 4 & quot; and provides sample S2 of input signal IN. The clock 5 '' provides a sample S3 which is phase shifted by phase by the phase shifter 4 '' 'and provides a sample S3 of the input signal IN. The sampling clock 5, the sampling clock 5 ', the sampling clock 5', and the sampling clock 5 '' are time shifted by the specific phase shifter 4 to obtain a higher sampling rate for the input signal IN.

[0011] The time-interleaved sampling architecture greatly reduces the power consumption of the subsequent digitizing unit 3, the digitizing unit 3 & apos ;, the digitizing unit 3 & quot ;, the digitizing unit 3 & apos; & quot ;, and the comparator metastability caused by the given technique error.

[0012] However, the advantages of a staggered architecture are not without drawbacks. There are a variety of limitations and considerations that must be considered before making a staggered solution successful.

[0013] One drawback is bandwidth limitation. Each sampling unit 2 shown in Figure 1 typically has a high analog bandwidth B when operating alone. However, connecting the sampling unit 2 in a tree form will severely reduce the overall signal bandwidth B at its input. The bandwidth reduction is caused by the parasitic effects of the input line metal interconnects connecting the analog signal to each of the sampling units 2, since the metal wiring parasitic effect includes a special inductance, impedance and / or capacitance. Those parasitic effects give rise to various effects. In addition, although only one sampling unit 2 operates at a time, the lumped parasitic effect of the sampling units 2 at their inputs is reduced by a bandwidth B due to the additional load that is always at the input line. Thus, as the number N of interleaved sampling units 2 increases, the bandwidth B will decrease. Therefore, the number N of interleaved sampling units 2, which are typically directly connected to the analog input IN, is limited to four.

[0014] Another drawback is clock-deterministic and random phase errors. If the sampling time of the time-interleaved sampler is not equidistant in time, the sampled input signal will contain an error at a determined frequency in its spectrum. In addition, the higher the analog input bandwidth B, the greater the error caused by the error sampling time.

[0015] The input clock signal elk must be physically routed to all sampling units 2. [0015] In addition, each sampling unit 2 receives a phase-adjusted input clock which is phase-shifted by a specific phase shifting unit 4, a phase shifting unit 4 ', a phase shifting unit 4' ', and a phase shifting unit 4' ''. It is very clear that, as the number N of interleaved sampling units 2 becomes higher, longer metal wirings have to be used for the clock signal elk. This longer metal wiring will reduce the bandwidth B of the clock signal elk until the clock signal elk reaches a particular sampling cell 2. The longer the metal wiring, Therefore, the clock signal elk also needs intermediate buffering to maintain its signal level. All necessary clock re-buffering will introduce not only a random error source into the clock signal, but also its phase stability. This makes it more difficult to generate and maintain equally spaced sampling times.

[0016] It is generally achieved by applying the local phase shifting unit 4 near the sampling unit 2 to ensure that each sampler receives the correct clock phase. The higher the number N of interleaved sampling units 2, the greater the phase correction range. As a result, the complexity of the local phase shifting unit 4 increases. The phase shift unit 4 will also increase the random noise source to the clock signal elk and will suffer from phase instability due to temperature, process, and the like.

[0017] Another disadvantage is offset and gain errors. The gain mismatch and offset mismatch between the ADC 1 outputs is an important parameter in a time interleaving system. If a channel comprising a particular sampling unit 2 and a corresponding digitizing unit 3 shows offset and gain errors, the digitized signal represents not only the initial input signal IN, but also the undesirable errors in the digital domain. Offset differences and gain mismatches signal clutter in the spectrum of the digitized signal. Therefore, for interlaced designs, the digitizing unit 3 with integrated gain and offset correction should be selected or include external circuitry that allows correction of these mismatches.

Summary of the Invention

[0018] Accordingly, it is an object of the present invention to provide an interleaved sampling structure for an analog-to-digital converter that increases sampling speed without bandwidth limitations and clocked deterministic and random phase errors.

[0019] The above identified objects and disadvantages are solved by the subject matter of the independent claims of the invention described herein. Advantageous embodiments are described in the respective dependent claims.

According to a first aspect of the present invention, there is provided a delay line system for high-frequency signal transmission. The delay line system includes a first delay line including a first terminal and a second terminal, wherein an analog input signal is applied to a first terminal of the first delay line. The system includes a second delay line including a first terminal and a second terminal, wherein a clock signal is applied to a first terminal of the second delay line. Wherein the first delay line and the second delay line are tap delay lines. An analog input signal transmitted over said first delay line is transmitted in a direction opposite to a clock signal transmitted on said second delay line.

[0021] Thus, in the delay line system of the present invention, the analog input signal and the clock signal are transmitted toward each other in their respective delay lines. This is mainly achieved by applying a clock signal at a terminal opposite to the analog input signal.

According to the inventive concept, the tap concept and the interleaving method are combined in an advantageous manner to achieve a synergistic effect of an increased sampling rate. To mitigate the bandwidth limitations associated with analog input signals and clock re-buffering, a tap concept is now used. The term & quot; tap & quot; is synonymous with the expression & quot; distributed & quot; or & quot; segmented & quot; and in particular relates to a delay line comprising taps between its delay elements.

[0023] By applying an analog input signal at a first terminal of the first delay line and applying a clock signal at a first terminal of the second delay line (disposed at the opposite end in the delay line system), in the delay line system In the analog input signal to the clock signal transmission. At each tap of the delay line system, the respective delayed analog signals may be sampled using respective delayed clock signals.

[0024] Thus, the interleaving operation is implemented in a concise manner by using the delay performance of the delay line and by causing the analog signal and the clock signal to be transmitted toward each other in their respective tap delay lines.

[0025] In a preferred embodiment, the first delay line is arranged parallel to the second delay line, wherein a first terminal of the first delay line is arranged between a first terminal of the first delay line and a first terminal of the first delay line, Terminal opposite the end. This results in a reverse transfer of the analog input signal relative to the clock signal and yields the inventive concept.

[0026] In a preferred embodiment, the first and second delay lines each comprise equal-sized delay elements, wherein the number of delay elements in the first delay line is equal to the number of the second The number of delay elements in the delay line.

[0027] In this way, the delay element allows the application of an analog input signal and a clock signal with a higher bandwidth, as compared to the tree-type signal routing circuit according to the prior art solution. Preferably, the delay elements comprise the same length, the same parameters and / or the same material. The use of an equal number of delay elements for the first delay line and the second delay line directly allows the interleaving effect and provides an interleaved tap concept.

[0028] In a preferred embodiment, the delay element is a section of a transmission line and / or is a discrete element arranged at a delay line. This allows easy manufacture of the delay line system and avoids the highly complicated metal wiring structure for obtaining the interleaving. Therefore, the above described bandwidth reduction and phase error are avoided.

[0029] In a preferred embodiment, the discrete element is configured to include a circuit arrangement of series inductances and capacitances, wherein the capacitance is connected to a reference potential.

[0030] Preferably, the delay element between the respective terminal of the delay line and the respective first tap causes a first transfer delay that is different from the delay caused by the delay element between two consecutive taps, Two transfer delays. However, the characteristic impedances of all the delay elements in the delay line system are the same. Advantageously, the first transfer delays of the delay elements of the respective terminals directly connected to the respective delay lines are equal to each other, wherein the first transfer delay may be different from the second transfer delay of the delay elements between two consecutive taps . The different transmission delays are caused by different routing schemes.

[0031] Preferably, the first delay line and the second delay line are taps, wherein taps are arranged between two adjacent distribution sections of a respective delay line. The tap is used to apply the sampling unit to the delay line, wherein the tap of the first delay line is arranged in close proximity to the tap of the second delay line. This avoids long metal wirings and provides interleaved samples that operate at a higher sampling rate without bandwidth limitations and clock and phase errors.

[0032] Preferably, the taps are arranged such that each tap of the first delay line corresponds to a tap of the second delay line. Preferably, the same delay line segment is used between consecutive taps of the clock signal line and the analog input signal line, resulting in sampling times of equal time intervals.

[0033] In a preferred embodiment, the delay element is arranged between two adjacent taps, wherein, preferably, the delay element in the first delay line is identical to the delay element in the second delay line. Therefore, the same delay elements are used in the delay line system. This causes the input signal and the clock signal to produce an equal time delay in the respective delay line.

[0034] In a preferred embodiment, the taps are equally spaced in the two delay lines.

A simple way to increase the signal bandwidth in a given technique is to use a tap (distribution) concept by using a tapped delay line that includes a dedicated distribution point / tap between its delay elements. In a given discrete circuit, the parasitic capacitance at its input will degrade the bandwidth at its terminating node. The use of a tap delay line circumvents this problem by absorbing the circuit input capacitance into the characteristic parameters of the tap delay element. Thus, a distributed delay line can operate at much higher frequencies than a tree-type signal routing circuit according to the prior art.

Preferably, the tap delay line is constructed as a mixture of transmission line segments and discrete components and / or is constructed entirely in discrete form and is terminated to their characteristic impedance Z. [0036] . Line characteristic impedance Z. Can be calculated as follows:

<img id="idf0001" file="CN106324311AD00071.tif" img-content="drawing" img-format="tif" />

Where inductance L is the total inductance of the line segment between two adjacent tap points, C is the line segment capacitance between two adjacent taps plus the input to the circuit connected to the taps &amp; lt; RTI ID = 0.0 &amp; gt; The sum of the capacitances.

[0039] The tap delay line allows the transmission of an input signal with a very high bandwidth B. Line cut-off frequency ω. Can be calculated as follows:

<img id="idf0002" file="CN106324311AD00072.tif" img-content="drawing" img-format="tif" />

The voltage step applied to the first terminal is transferred down the tap delay line so that the step signal appears successively at each lumped circuit input. If the structure is periodic such that all of the delay elements between consecutive taps are similar, the step signal will appear at equal tap delays at successive tap points. The transfer rate is typically at least 50% of the speed of light in free space, depending on the equivalent dielectric constant value of the delay element.

[0042] Another way to quantify the delay τ at successive tap points is by calculating the following equation:

<img id="idf0003" file="CN106324311AD00073.tif" img-content="drawing" img-format="tif" />

Where inductance L is the total inductance of the line segment between two adjacent tap points, C is the line segment capacitance between two adjacent taps plus the input to the circuit connected to the taps &amp; lt; RTI ID = 0.0 &amp; gt; The sum of the capacitances.

According to a second aspect of the present invention, there is provided a high-frequency sampler including a delay line system according to the above-described manner. Since both delay lines are taps, the sampler is an interleaved sampler.

[0046] The delay line is arranged such that each tap of the second delay line is physically close to the tap of the first delay line. Thus, each sampling unit of the high frequency sampler receives the input signal and the clock signal without additional metal wiring and, more importantly, includes in the tap circuit characteristic either the sampling unit or the input line or the line terminal Clock signal path, or any residual parasitic capacitance of the analog input signal path. The buffers can be used locally on each sampling cell for the analog input signal and the clock signal on each tap.

The interleaving operation of the high frequency sampler is accomplished in a concise manner by using the delay performance of a particular delay line and by inverting the analog input signal and the clock signal in their respective tap lines.

In a preferred embodiment, the taps are arranged between two adjacent distribution sections of a respective delay line, wherein the taps are arranged such that each tap of the first delay line corresponds to And wherein the respective taps of the first delay line and the corresponding taps of the second delay line are connected to a separate sampling unit. In the case where the clock signal enables the sampling unit to be active, the sampling unit provides the sampled output signal. Enabling and failing the sampling unit is accomplished by means of a clock signal, preferably by detecting a rising or falling edge of the clock signal.

[0049] In a preferred embodiment, the clock period of the clock signal is at least equal to the transfer time between two consecutive taps on the second delay line and two on the first delay line The sum of the transfer times between consecutive taps, where the sum is multiplied by the interleaving factor. This is the minimum clock period to avoid double sampling caused by the next clock edge traveling along the delay line.

The same type of delay elements are used for the first delay line and the second delay line to obtain similar transmission times for the respective signals. The selection of similar delay elements facilitates physically aligning the analog taps with the clock taps to eliminate additional clock signaling or analog signaling for each sampling unit.

According to a third aspect of the present invention, there is provided an analog-to-digital converter including a high-frequency sampler according to the above-described manner.

Preferably, the ADC comprises a staggering factor of at least 4, preferably 6, more preferably 8, even more preferably 10, most preferably 16. Since the use of a tap concept in conjunction with the interleaving method greatly reduces the delay line bandwidth limitations and phase errors, a higher number of sampling units can be provided in the interleaving method, which advantageously results in a higher sampling rate. Because the parasitic capacitance makes the bandwidth of the terminal node worse, the tap concept circumvents this problem by absorbing the circuit input capacitance into the characteristic parameters of the tap delay line.

Preferably, the respective taps of the first delay line and the corresponding taps of the second delay line in the high frequency sampler of the ADC are connected to a separate sampling unit, wherein the output of the sampling unit passes through the digitizing unit Is digitized. The digitizing unit has a quantizing unit and / or a binarizing unit to provide a separate signal corresponding to the analog sample of the sampling unit.

According to yet another aspect of the present invention, there is provided an oscilloscope for measuring a high frequency signal, wherein the oscilloscope includes an input node and an ADC according to the aforementioned manner downstream of the input node for applying a high frequency analog Input signal, which is used to convert an analog input signal into a digital input signal. Oscilloscopes with ADCs of the present invention can be used in ultra-high-speed sampling architectures, particularly within the next generation of RTOs with sampling cells that operate at sampling rates up to 160 gigahertz.

BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. Those exemplary embodiments do not limit the scope of the invention. Unless indicated otherwise, like reference numerals refer to like elements or elements of at least the same function in different figures. In the figure:

[0056] Figure 1 shows an ADC using an interleaved sampling concept according to the prior art;

[0057] Figure 2 shows an exemplary time signaling diagram of the ADC according to Figure 1;

[0058] Figure 3a shows a first exemplary embodiment of a tap concept for use in an interleaved ADC according to the present invention;

[0059] Figure 3b shows a second exemplary embodiment of a tap concept for use in an interleaved ADC according to the present invention;

[0060] FIG. 4 illustrates a first exemplary embodiment of a delay line system according to the present invention;

[0061] Figure 5 shows a second exemplary embodiment of a delay line system according to the present invention;

[0062] FIG. 6 illustrates a third exemplary embodiment of a delay line system according to the present invention;

[0063] FIG. 7 shows an inventive concept of an opposite direction of transmission of an input signal and a clock signal in a delay line system; and

[0064] FIG. 8 illustrates an exemplary timing diagram of an implementation of the present invention with four sampling units.

detailed description

1 and 2 have been described with respect to the background of the present invention.

[0066] Referring to Figures 3a and 3b, a tap concept in accordance with the present invention is shown in more detail. In a given lumped circuit, the parasitic capacitance at its input node will degrade the bandwidth at its terminating node. The tap concept circumvents this problem by absorbing the circuit input capacitance into the characteristic parameters of the tap delay line. Thus, the tap delay line 7 can operate at a much higher signal bandwidth than the tree-type signal routing circuit shown in FIG.

[0067] In Figure 3a, a first exemplary embodiment of a tap concept for use in an interleaved ADC according to the present invention is shown. The first delay line 7 includes a first terminal 71 and a second terminal 72. The first terminal 71, At the first terminal 71, an analog input signal IN is applied. At the second terminal 72, a terminating resistor Z is connected. To terminate the first delay line 7. The bias voltage V blas is applied at the second terminal 72 of the first delay line 7 so as to bias the first delay line 7 and the bias voltage Vblas may also be a ground signal. The first delay line 7 according to Fig. 3a comprises five delay elements 9a connected to the respective terminals 71 and 72 of the delay line 7, and a delay element 9a. According to each delay element 9 of Figure 3a, the delay element 9a is constructed as a section of the transmission line. Each transmission line segment delays the transmission of the analog input signal IN to a limited amount.

[0068] A second exemplary embodiment of a tap concept for use in an interleaved ADC according to the present invention is shown in Fig. 3b, wherein each delay element 9 and delay element 9a are constructed using discrete elements. Each delay element 9, the delay element 9a is configured as a circuit arrangement connected in series with the inductance L and the capacitance C of the reference potential GND. Each circuit arrangement delays the transmission of the analog input signal IN to a limited amount.

The taps 10 are arranged between the two delay elements 9 in Figs. 3a and 3b. The phrase "tap" is also referred to as the phrase "distribution point" where four taps 10 are used in the first delay line 7 of Fig. 3b. At each tap 10, a sampling unit 2 (not shown) may be applied.

The delay element 9a between the respective terminal 71, the terminal 72 and the respective first tap 10 of the delay line 7 does not have to be equivalent to the delay element 9 arranged between the two taps 10. It is necessary that the delay element 9a includes the same characteristic impedance Z. , The transmission delay? Between the delay element 9a and the delay element 9 may be different. For example, the length of the transmission line 9a as the delay element 9a is half the length of the transmission line 9 of the delay element 9 between the two successive taps 10. As shown in Fig.

According to Figures 3a and 3b, the delay element 9, the delay element 9a may be constructed as a section of a transmission line or as a discrete delay element. Since the delay elements 9 are terminated to their characteristic impedances Z. , A higher bandwidth B can be achieved for the first delay line 7. Fig. Line characteristic impedance Z. Can be calculated as follows:

<img id="idf0004" file="CN106324311AD00101.tif" img-content="drawing" img-format="tif" />

The tapped delay line allows the transmission of an input signal having a very high bandwidth B. Line cut-off frequency ω. Can be calculated as follows:

<img id="idf0005" file="CN106324311AD00102.tif" img-content="drawing" img-format="tif" />

[0075] Another way to quantify the delay τ at successive tap points is by calculating the following equation:

<img id="idf0006" file="CN106324311AD00103.tif" img-content="drawing" img-format="tif" />

[0077] The inductance L is the total inductance of the delay element 9 between two adjacent taps 10. Capacitor C is the sum of the capacitance of all the delay elements 9 between two adjacent taps 10 and the input capacitance of the lumped circuit connected at the taps 10.

The analog input signal IN applied to the first terminal 71 is transmitted downwardly to the second terminal 72 so that the input signal appears successively at each of the lump circuits. Its configuration is periodic such that all delay elements 9 between two consecutive taps 10 are similar; the clock signal CLK will appear with an equal delay τ along with successive tap points 10. In this case, The transfer rate is usually between 50% and 60% of the speed of light in free space, depending on the equivalent relative permittivity value? P of the delay element 9

The delay element 9 and the delay element 9a may be of equal size or may be different from each other. According to a preferred embodiment (not shown), the delay element 9a is constructed as a plurality of segments of a transmission line, wherein the delay element 9 between two successive taps 10 is constructed as a discrete element 9, and vice versa. Advantageously, each delay element 9 between two successive taps 10 is similarly constructed so as to adjust the same propagation delay τ between the two taps 10.

4, a first exemplary embodiment of a delay line system according to the present invention is illustrated. The first delay line 7 includes a first terminal 71 and a second terminal 72. The first terminal 71, At the first terminal 71, an input signal IN of an analog characteristic is applied. The first delay line 7 includes a plurality of delay elements 9 so as to become a tap delay line. The tap 10 is arranged between the two delay elements 9.

The delay line system further includes a second delay line 8. The second delay line 8 includes a first terminal 81 and a second terminal 82. The first terminal 81 of the second delay line 8 is provided with a clock signal CLK. The second terminal 82 of the second delay line 8 is terminated at the delay line impedance Z. , And also bias the second terminal 82 of the second delay line 8 with the bias voltage V blas, which may also be a ground signal.

4, the clock signal CLK is applied to the first terminal 81 of the second delay line 8, which is opposite to the first terminal 81 of the second delay line 8, as compared to the first delay line 7 .

[0083] To mitigate the bandwidth limitations associated with analog input signals and clock re-buffering, the tap concept is used in an interleaving method. Also, the analog input signal IN and the clock signal CLK are routed to all sampling units 2, which are arranged at corresponding taps 10 between the first delay line 7 and the second delay line 8. The delay element 9 is physically arranged such that each tap 10 of the second delay line 8 is physically close to the tap 10 on the first delay line 7. [ In this manner, each sampling unit 2 receives the analog input signal IN and the clock signal CLK without requiring additional wiring. In addition, the tap-line characteristics include the lumped parasitic capacitance of the clock signal CLK of the sampling unit 2 and the analog input signal IN. The input buffer 6 can be used locally on each sampling unit 2 for the analog input signal IN and the clock signal CLK for each tap 10. The input buffer 6,

The interleaving operation of the high frequency sampler is performed by using the delay line 7 by delaying the delay performance of the line 8 and by making the analog input signal IN and the clock signal CLK in their respective tap delay lines 7, tap-delay lines 8 toward each other Transmission and in a simple way to achieve.

By using the same delay element 9 between successive taps 10 of the first delay line 7 and the second delay line 8, a sampling instant of equal time intervals is obtained. In addition, the delay line taps 10 are arranged in the following manner:

If the taps 10 of the second delay line 8 and the first delay line 7 are numbered from zero to the number N, N + 1 is the total number of taps 10 on the delay line 8 for each delay line 7, where zero is The tap 10 of the first terminal 81 closest to the second delay line 8 and zero is also the tap 10 of the first terminal 71 closest to the first delay line 7, the first delay line 7 and the second delay line 8 are connected in the following manner Mode: the tap number K on the second delay line 8 corresponds to the tap number NK on the first delay line 7. As shown in Fig.

In addition, the delay elements 9 for the second delay line 8 and the first delay line 7 are marked in the following manner:

The sum of the transfer times τ between two consecutive taps 10 on the second delay line 8 and the transfer times between the two successive taps 10 on the first delay line 7 is multiplied by the interleave factor &amp; lt; RTI ID = 0.0 &amp; gt; According to Figure 4, the interleave factor is N + 1) is equal to the clock period Tw #, which can be expressed as:

T_ = (N + 1) (τ + + τ)

If the same type of delay element 9 is used for the first delay line 7 and the second delay line 8, the transmission time is equal to the transmission time. The selection of a similar delay element 9 facilitates physically aligning the analog tap 10 with the clock tap 10 to eliminate additional clock signal wiring or analog signal wiring for the high frequency sampler.

At the output of each sampling unit 2 between the first delay line 7 and the second delay line 8, a sampling unit output signal S_0 is obtained which provides a sampling of the input signal IN over a particular sampling time S Hold value. In the present inventive concept, for a high frequency sampler using four sampling units 2, a four times higher sampling rate fs is achieved, resulting in four different sample values ​​3_0.

In Fig. 5, a second exemplary embodiment of the present invention is shown. Here, in the delay line 7 and the delay line 8 arranged in parallel, the analog input signal IN and the clock signal CLK also travel toward each other. The analog input signal IN and the clock signal CLK include tap delay elements 10 similar to each other. For both the first delay line 7 and the second delay line 8, the taps 10 are equally spaced and equidistant. The transfer time and the transfer time are equal to the adjacent sampling distance divided by the rate at which the signal is transmitted. The delay line 7, the delay line 8, may be any type of waveguide, such as a microstrip waveguide, a stripline waveguide, a coplanar waveguide, or the like.

The delay element 9 for a single-ended signal is shown for simplicity, but the present concept is also valid in the case where the analog input signal IN or the clock signal CLK, or both, uses a differential signal scheme. In this case, for example, a differential delay element 9 is used for the differential microstrip line. The differential signal actually corresponds to the majority of the implementation.

The tap delay line 7 and the tap delay line 8 may be implemented by using an integrated circuit chip technique, for example, by using a single-ended signal or a differential signal on the chip microstrip delay line 7 and the chip microstrip line 8 .

In Fig. 6, a third exemplary embodiment of the present invention is shown. 5, the number of sampling units 2 relates to four, resulting in that four sampling units are arranged between the first delay line 7 and the second delay line 8. As shown in Fig. As shown in Figures 7 and 8, this results in four taps 10 in which an analog input signal IN with a particular delay can be obtained at four taps 10. [ The above also applies to the clock signal CLK and the four taps 10 on the second delay line 8.

[0096] FIG. 7 shows an inventive concept of an opposite transmission direction of an input signal IN and a clock signal CLK in a delay line system. As shown in Fig. 7, the analog input signal IN and the clock signal CLK travel toward each other. Shows four different waveforms for the analog input signal IN and the clock signal CLK. They represent the signals at the sampling instants at the sampling unit 2, the sampling unit 2 ', the sampling unit 2' and the sampling unit 2 '.

In this particular example, when the rising clock edge of the clock signal CLK reaches the corresponding sampling tap position 10, all the sampling units 2 perform the sampling function. The sampler 2 is activated / enabled in chronological order for each rising clock edge coming in from the first terminal 81 of the second delay line 8 and traveling downwardly along the second delay line 8 towards the second terminal 82, , The sampler 2 &amp; quot; and the sampler 2 &amp; apos; &amp; quot ;, where the interval difference [tau] between two successive samples of the transfer time is equal to the adjacent sampling distance (ASD) divided by the transfer rate, The following formula:

[0098] [0098]

<img id="idf0007" file="CN106324311AD00121.tif" img-content="drawing" img-format="tif" />

[0099] It should be noted that during the first half of the clock cycle Tw # all sampling units 2 should preferably perform the sampling function. In addition, it should be noted that the samples obtained on the analog input signal IN correspond to the sampling distance 2τ. This is due to the fact that the analog input signal IN and the clock signal CLK are traveling towards each other.

During the second half of the clock cycle Tw #, no sampling occurs. During this period, the analog input signal IN is further transmitted over its tap delay line 7 and travels down along the first delay line 7 so that when the next rising clock edge reaches the tap number 0, the analog input signal IN obtained at sample number 0 The samples correspond to the analog values ​​on the analog input signal IN, which is 2 τ away from the last sample (ie, sample number 3) obtained.

In Fig. 8, the sampling output S_01, the sampling output S_02, the sampling output S_03, and the sampling output S_04 are shown to indicate the timing at which each of them is sampled. Note also that the sample number 0 (at the sample point SO) corresponds to 2 · τ after the sample number 3 (at the sample point S3) on the analog input signal IN, and therefore, for successive clock edges, all Of the samplers operate in a staggered mode.

In the present invention, the clock deterministic and random phase errors are significantly reduced, since no significant phase adjustment clock is required. The clock phase adjustment on each sampler is a proven source of clock stability error and can be avoided with the inventive concept.

[0103] All of the features described and / or claimed herein may be combined with one another.

[0104] While the various embodiments of the present invention have been described above, it should be understood that these embodiments have been presented by way of example only and not by way of limitation. Numerous variations of the disclosed embodiments may be made in light of the present disclosure without departing from the spirit or scope of the invention. Thus, the breadth of the scope of the invention should not be limited by any of the embodiments described above. But rather that the scope of the invention should be defined in accordance with the appended claims and their equivalents.

While the invention has been shown and described with respect to one or more implementations, equivalent modifications and alterations will occur to those skilled in the art upon reading and understanding the present specification and the accompanying drawings. [0051] While the present invention has been described and illustrated with respect to one or more implementations, . In addition, while specific features of the invention may be disclosed in relation to only one of some implementations, the feature may be combined with one or more other features of other implementations as desired and will facilitate any given Application or application-specific.