Solid state image pickup device and its driving method using two field/frame period

Solid-state imaging device and its driving method using two field/frame periods

The present invention relates to a solid-state imaging device and a driving method thereof for expanding the processing range of incident light quantity on the high-brightness side. In particular, it relates to setting at least two signal charging cycles in a specific period represented by a video signal field or frame, and reproducing the signal charge in the signal charging cycle time without any external field memory or any frame memory. A solid-state imaging device and its driving method to expand the processing range of the amount of incident light on the high-brightness side.

According to the conventional technology, when expanding the processing range of the incident light quantity, at least two different charging periods are set for each frame or field signal period. For example, in the one field period TF, the first charging period T1 is set corresponding to the normal vertical scanning period, and corresponding to the vertical blanking period, a second charging period T2 shorter than the first charging period is set. . Thus, the signal charge Q1 obtained in the first charging cycle time is reproduced with a gain of 1, and the signal charge Q2 obtained in the second charging cycle time is reproduced with a gain (T1/T2). In this case, when the signal charge Q1 reaches the saturation charge amount, the final result is to use the signal information of the signal charge Q2 to obtain a processing range that has a gain (T1/T2) times larger than the normal situation.

Regarding the aforementioned element driving method for expanding the processing range of the incident light amount, there is a proposal that can omit any external frame memory (Japanese Patent Publication No. SHO63-250980). The proposal describes a method of successively transferring the signal charges obtained in two charging cycles. The condition is that the current CCD structure has 4 pixels and a total of 8 transfer electrodes, and 3 signals are generated during one field period TF of the vertical CCD A packet, in which the signal charge of two pixels is used as two packets in the first charging period, and the signal charge of 4 pixels is used as one packet in the second charging period.

However, in order to add and mix the mixed signal charges of 4 pixels, it is necessary to read twice in the ΔT time interval, and there are two different types of signal charges T2 and (T2+ΔT) in the same packet. When the mixed signal charge of 4 pixels in the two charging cycles of the mutual difference time ΔT is subjected to the calculation processing with an indistinguishable gain of (T1/T2), the second charging cycle time T2 will be adjusted according to the incident light amount of the target object. Defects such as color misalignment and brightness misalignment appear.

In view of the problem that the signal charge is read at least twice in a field period from the photoelectric conversion element to the vertical CCD, the object of the present invention is to provide a method to avoid the difference ΔT between the two charging periods in the second charging period time T2 to enlarge The driving method of the solid-state imaging device with dynamic range and the solid-state imaging device enable the expansion of the processing range of the incident light amount to be realized without causing color misalignment or brightness misalignment.

The solid-state imaging device of the present invention is characterized by comprising: a plurality of unit pixel devices arranged in a two-dimensional matrix with horizontal and vertical axes, the unit pixel device having at least an input conversion portion and a CCD charge transfer device, wherein One unit pixel device is provided with 4 transfer electrodes, and the 8 transfer electrodes provided to two unit pixel devices adjacent to each other in the vertical direction are driven by a certain number of phase transfer clock pulses generated by the pulse generator.

The driving method of the solid-state imaging device of the present invention is characterized in that two signal charging periods, one of which is shorter than the other, are set in one frame or one field of the video signal, and wherein two unit pixel devices adjacent to each other in the vertical direction The two short signal charging cycles have different starting timings but the same duration.

The driving method of the solid-state imaging device of the present invention is characterized by including: setting one of two signal charging periods shorter than the other in one frame or one field of the video signal, and determining that the input signal conversion part is in the long signal charging period Whether the signal obtained during the period is saturated; when the signal is saturated, the signal obtained by the signal conversion part during the long signal charging period is not input, but the signal obtained during the short period is used to determine the input The amount of light, and when the signal is not saturated, the signal during the short signal charging period is not used but the signal during the long signal charging period is used to measure the input light amount.

For a subject with a wide range of brightness distribution, the first charging cycle time T1 is used to process the light quantity less than the standard light quantity and the light quantity about twice the standard light quantity, and use the second charging cycle time T2 in the vertical blanking period. To process the target area that reaches the saturation charge amount in the first charging period T1, it is possible to expand the processing range of the incident light amount on the high-brightness side without using any external field memory or any frame memory.

FIG. 1 is a diagram of a solid-state imaging device of the present invention; FIG. 2 is a schematic diagram illustrating the first driving method of the present invention; FIG. 3 is an A field diagram of the first driving embodiment of the present invention; FIG. 4 is the first driving method of the present invention B-field diagram of the embodiment; FIG. 5 is a first implementation diagram of the solid-state imaging device of the present invention; FIG. 6 is a graph illustrating the effect of the first embodiment of the present invention; FIG. 7 is a schematic diagram illustrating the second driving method of the present invention 8 is the A field diagram of the second driving embodiment of the present invention; FIG. 9 is the B field diagram of the second driving embodiment of the present invention; FIG. 10 is a schematic diagram illustrating the third driving method of the present invention.

The embodiments of the present invention will be described below with reference to the above-mentioned drawings.

FIG. 1 shows the implementation of the solid-state imaging device related to claim 1 of the present invention.

The four transfer electrodes of a VCCD110 correspond to one unit pixel 100, and the eight transfer electrodes are: φV1 transfer electrode 101, φV2 transfer electrode 102, φV3 transfer electrode 103, φV4 transfer electrode 104, φV5 transfer electrode 105, φV6 transfer electrode 106 The φV7 transfer electrode 107, and the φV8 transfer electrode 108 are used as a total of 8 transfer electrodes corresponding to 2 consecutive unit pixels when an 8-phase transfer clock is applied. The φV2 transfer electrode 102 and the φV6 transfer electrode 106 are each provided with a read gate 109. Although the first layer of polysilicon is used to make the two read gates correspond to one read electrode, the read electrode can use either the first layer or the second layer of polysilicon. In the case of using a conventional CCD, two pixels in the VCCD direction can be combined into one pixel. For the component driving examples in FIG. 2 and the following figures, the description is based on the structure of FIG. 1.

FIGS. 2, 3, and 4 show embodiments related to claims 2, 3, and 4 to which the solid-state imaging device shown in FIG. 1 is applied.

Fig. 2 shows the A field 201 and the B field 203 of a normal TV frame. Figure 2 also shows the timing relationship between charge reading and signal transfer in each odd-numbered row of pixels and each even-numbered row of pixels. By a known electronic shutter closing operation (VOD, that is, vertical overflow drain shutter closing operation scanning), the odd-numbered row pixels 232 and the even-numbered rows of pixels 233 have in advance simultaneous charging cycle start timings.

The pixels 233 in the even rows obtain the first signal charges 205 in the even rows according to the signal input in the period T11224. The operation of reading the VCCD is executed by the timing TAF1210. At the same time, the odd-line pixels 232 obtain an odd-line first signal charge 206 according to the signal input in the period T12225, and use the timing TAF21211 to perform the operation of reading to the VCCD. In addition, in the V-blanking period 202, the pixels 233 in the even rows obtain the second signal charges 207 in the even rows according to the signal input in the period T2227. Use the timing TAs1212 to perform the operation of reading to the VCCD. At the same time, the odd-numbered rows of pixels 232 obtain an odd-numbered row of second signal charges 208 according to the signal input set in the cycle time T2228 with the same photoelectric cycle as the cycle time T2227, and use the timing TAs21213 to perform the reading operation to the VCCD. In this case, by adjusting the VOD scanning period 229 set in the entire field period 226, the charging time in the control period T2227 and T2228 is performed to complete the V-blanking period 202 for the target area with high brightness. Ingest.

Although the same operation is performed in the B field 203, a charging period of the first signal charge 215 of an even-numbered row is allowed to replace the charging period of the first signal charge 214 of an odd-numbered row.

Figures 3 and 4 show the timing of read and transfer operations. The signal charge 240 read out at the timing TAF1210 is transferred to the VCCD by one pixel. The signal charge 241 is read out with the timing TAF21211. In FIG. 3, a total of 20 clock pulses are used from timing TAF1210 to timing TAF21211. Therefore, by using a total of 20 clock pulses from the timing TAS1212 to the timing TAS21213, the charging cycles of T2227 and T2228 are allowed to have the same duration. Also, the signal charges 242 corresponding to the second signal charges 207 of the even-numbered rows and the signal charges 243 corresponding to the second signal charges 208 of the odd-numbered rows are mixed with each other with the timing TAS21213 in the manner shown in FIG. 3. There is an interval of 20 clock pulses from TAS1212 to TAS21213 in the period of reading the two signal charges. Then transfer the signal charge into the VCCD according to the 8-phase clock. Although the charging cycles T2227 and T2228 in this example have a charging cycle of 20 clock pulses, the number of clock pulses is certainly not allowed to be limited. At the same time, as mentioned above, the charging cycle of T2227 and T2228 is controlled by increasing or decreasing the time interval from TAF21211 to TAS1212 according to the increase or decrease of the corresponding VOD scan period 229.

Figure 5 shows an embodiment related to claims 5, 6 and 8. Fig. 6 shows the effect of expanding the processing range of the incident light amount.

The photoelectric conversion of incident light is performed in the photoelectric converter part 300 of a unit pixel. At the same time, the two-pixel mixed signal charge 301, field signal charge 1302, and field signal charge 2303 are transferred by HCCD1304, HCCD2305, and HCCD3306 during the closing time of the electronic shutter. After passing through a CDS and clamp circuit 307, the signal determination circuit 309 determines the signal saturation of each of the above-mentioned signal charges based on the saturation or unsaturation of all or part of the output signals from the HCCDs 1, 2 and 3. After their output is selected by the signal selector circuit 308, they perform calculation processing to be described below in the signal processing circuit 310 to perform the reproduction of the image signal.

Next, an embodiment of the image reproduction method is shown. In the following conditional expressions, VT represents a voltage corresponding to the saturated charge amount of the element.

First, when the conditional equation 1 concerning the signal voltages V(T11) and V(T12) in the charging periods T11 and T12 is established, the signal selector circuit 308 selects the signals V(T11) and V(T12). When the conditional equation 1 is not established, the signal selector circuit 308 selects the electronic shutter closing time two-pixel mixed signal charge 301, and converts the signal voltage in the charging period T2 into the Vsig( T2). Although Equation 3 defines a at this time, it is also allowed to use another appropriate value as shown in Equation 4, for example. It should be noted that other unselected values will be discarded.

Equation 1: max(V(T11), V(T12)<VT Equation 2: Vsig(T2)=a×V(T2) Equation 3: a=T11/T2 Equation 4: a=T12/T2 In this embodiment Refer to the description shown in FIG. 6 for the processing range of expanding the amount of incident light.

The two pixels are mixed in the traditional CCD. The output signal charge amount obtained by the read and transfer operations can be represented by the conventional two-pixel mixed type saturated charge amount 302. Fig. 2(a) shows that the saturation charge of the signal charge in the charging periods T11224 and T12225 has a value corresponding to the transfer electrode value in a unit pixel 100 in the unit pixel 100 shown in Fig. 1, so the value is a traditional two-pixel hybrid type A quarter of the saturation charge. When the brightness signal is formed, the signal charge 240 and the signal charge 241 are added in an external circuit. Therefore, this value is half of the traditional two-pixel hybrid type saturation charge. This value is expressed as the saturation charge amount 321 of the reading time independent of all pixels.

According to the element and driving method of this embodiment, the signal charges obtained by mixing the even-numbered row second signal charges 207 in the charging period T2227 with the odd-numbered row second signal charges 208 in the charging period T2228 can be read separately at the same time. Therefore, the saturated charge amount 312 can be obtained during the mixing time of the two pixels when the electronic shutter is closed. In this case, the cycle times T2227 and T2228 can be changed, for example, from 1/500 second to 1/2000 second to allow the effect represented by variable 325 in FIG. 6 to be obtained. Therefore, it is possible to obtain an enlarged range 323 of the processing incident light quantity larger than the upper limit 324 of the conventional processing incident light quantity.

Figures 7, 8 and 9 show an embodiment in the case where VOD scanning is not used. FIG. 7 shows the timing of odd-numbered rows of pixels 432 and even-numbered rows of pixels 433 as well as signal charge, reading, and transfer in the A field and the B field of a normal TV frame.

In this case, the start timing of the charging cycle of the odd-numbered row pixels 432 and the even-numbered row pixels 433 are different, and the even-numbered row pixels 433 obtain an even-numbered row of first signal charges 405 according to the signal input in the period T11424. Use the timing TAF1410 to perform the operation of reading to the VCCD. At the same time, the odd rows of pixels 432 obtain an odd row of first signal charges 406 according to the signal input in the period T12425, and use the timing TAF21411 to perform the operation of reading to the VCCD. In addition, in the V blanking period 402, the pixels 433 of the even rows obtain the second signal charges 407 of an even row according to the signal input in the period T2427. Use the timing TAS1412 to perform the operation of reading to the VCCD. At the same time, the odd rows of pixels 432 obtain an odd row of second signal charges 408 according to the signal input in the period T2428. The period T2428 is set to have the same charging period as the period T2427, and the timing TAS21413 is used to perform the operation of reading to the VCCD. In this case, the periods T11424 and T12425 are different from each other, and also differ depending on whether they are in the A field 401 or the B field 403. Therefore, when the periods T2427 and T2428 with the same charging time are controlled, it is possible to cause color misalignment and brightness misalignment in 4 field periods. However, the readout of pixel data in the present invention is carried out independently, allowing calculation of the ratio of the charging cycle (Equation 5). Therefore, by using a value Vsig'(T11) calculated from the charging period T12, neither color misalignment nor brightness misalignment occurs.

Equation 5: b=T12/T11 Equation 6: Vsig'(T11)=b×V(T11) Figures 8 and 9 show the timing of read and transfer operations. The signal charge 440 read out by the timing TAF 1410 is transferred by one pixel in the VCCD. The signal charge 441 is read out with the timing TAF21411. In FIG. 3, a total of 20 clock pulses are used from timing TAF1410 to timing TAF21411. As a result, by arranging the timings from TAS1412 to TAS21413 within 20 clock pulses, it is allowed to make the charging periods in periods T2427 and T2428 have the same duration. In addition, after the signal charge 442 corresponding to the second signal charge 407 of the even-numbered row is transferred by one pixel within 20 clock pulse periods, the signal charge 443 corresponding to the second signal charge 408 of the odd-numbered row passes the superimposition timing in the manner shown in FIG. The TAS21412 is read out to be mixed with the signal charge, and then transferred to the VCCD according to the 8-phase clock. Although the charging periods T2427 and T2428 correspond to 20 clock pulses in this example, this is of course not a limitation on the number of clock pulses.

FIG. 10 shows a case where the charging period of the first signal charge 414 in the odd-numbered rows and the charging period of the first signal charge 415 in the even-numbered rows can be replaced with each other as shown in FIG. 7. In this case, the first signal charge 505 of the even-numbered row is a signal charge obtained by the signal input in the period T11524. Use the timing TAF1510 to perform the operation of reading to the VCCD. The first signal charge 506 of the odd-numbered row is a signal charge obtained by the signal input in the period T12525, and the operation of reading to the VCCD is performed with the timing TAF2511. The second signal charge 507 of the even-numbered row is a signal obtained by a signal input in the T2527 period. Use the timing TAS1512 to perform the operation of reading to the VCCD. The second signal charge 508 of the odd-numbered row is a signal obtained by the signal input in the T2528 period, and the operation of reading to the VCCD is performed with the timing TAS2513.

In the present invention, the periods T11524 and T12525 can be set with the same duration, and the transformation of Equation 6 is not necessary.

As described above, in the present invention, the processing range of the amount of incident light can be expanded to the high brightness side without using any field memory or any frame memory.