Solar Battery Manufacturing Technique And Solar Battery Processing Technique

Solar cell manufacturing process and solar cell processing technology technical field

[0001] The present invention relates to a solar cell manufacturing process and a solar cell processing process.

Background technique

[0002] The current solar cell, due to its structure, will have the problem of battery performance degradation after a period of use, that is to say, the battery performance suddenly drops sharply during use, more specifically, the battery Suddenly, his work efficiency dropped. Generally speaking, the performance degradation of solar cells occurs during operation. Changes in battery operating parameters, such as the light intensity and operating temperature of solar cells powered by solar cells, are useful for judging whether solar cells have occurred. The performance degradation plays an important role. The degradation of solar cell performance is also triggered during the operation of the solar cell.

[0003] Recently, it has been discovered that the recombination defect may be the cause of the degradation of the performance of the solar cell, and the recombination defect is caused by sunlight irradiating the inside of the silicon element. This phenomenon of solar cell performance degradation caused by light irradiation is also called LIDTight induced degradation. The reason for this phenomenon is the formation of boron-oxygen complexes in the crystal lattice of the silicon element. The above-mentioned effects can be prevented by using silicon wafers with a very low content of boron and oxygen in the production of solar cells according to known methods.

[0004] However, even if the amount of boron and oxygen added is reduced in the process of manufacturing silicon wafers, solar cells manufactured using such silicon wafers as raw materials still suffer from battery performance degradation. More precisely, in solar cells The attenuation effect has appeared and continues to appear in battery design, and its degree cannot be explained based on the above-mentioned boron-oxygen effect. In addition to the boron-oxygen decay effect (boron-oxygen decay or LID) that has been gradually understood in the industry, there is another decay effect, such as the 27th European Photovoltaic Solar Conference and Exhibition (EUPVSEC) in 2012. ) During K. The article "Light Induced Degradation of Rear Passicated mc-Si Solar Cells" published by Ramspeck et al. can draw this conclusion. The article explained that polycrystalline silicon solar cells (mc-Si solar cells) designed with surface passivation PERC (PERC-passivation emitter and back cell) will produce a kind of light-induced attenuation that cannot be explained by the previous boron-oxygen model . By reducing the oxygen content, the boron-oxygen decay effect in polycrystalline silicon solar cells is relatively small. However, there is an attenuation effect that may significantly exceed the known boron-oxygen attenuation. The above article pointed out: When the light intensity is 400 watts per square meter (W/tf) and the battery temperature is 75°C, the efficiency attenuation value is 5-6% (relatively).

Summary of the invention

[0005] The object of the present invention is to provide a solar cell manufacturing process, by which a solar cell with low late attenuation or no late attenuation can be produced in a reliable manner. In addition, the present invention also provides a solar cell processing method. After the solar cell undergoes the above-mentioned treatment, the sensitivity of the cell to attenuation during subsequent operation can be reduced or eliminated in a process step in the solar cell manufacturing process. Increased susceptibility of solar cells to cell degradation phenomena.

[0006] According to the present invention, the above-mentioned object is achieved by satisfying the solar cell manufacturing process described in the claims and the solar cell processing process satisfying the claims. Other improvements of the invention will be described in the dependent claims.

[0007] In this article, in order to distinguish the performance degradation mechanism related to the present invention from the performance degradation mechanism related to LID light-induced degradation, in the following parts of the article, eLID is used to represent the performance degradation described in this article. The name means enhanced light induced degradation (eLID-enhanced light induced degradation). Standard solar cells also exhibit enhanced light-induced attenuation, but solar cells made of polycrystalline semiconductors have a particularly high probability of enhanced light-induced attenuation. Solar cells made of polycrystalline semiconductors have relatively low oxygen content, so The sensitivity of LID light-induced attenuation is also relatively low. Newer solar cells developed in the recent period show higher eLID sensitivity, such as solar cells with a PERC structure or other solar cells with passivation treatment on the surface, especially those using solar cell sintering laser equipment (LFC a Solar cells with ohmic contacts realized by laser fired contacts are very prone to eLID.

[0008] The present invention is based on the following knowledge, that is, the sensitivity of the solar cell described in this article to the above-mentioned attenuation, that is, the eLID sensitivity of the solar cell largely depends on the production in the solar cell manufacturing process parameter. The inventors have discovered that this type of battery performance degradation phenomenon is related to another battery performance degradation mechanism that is different from the currently known degradation mechanism in the boron-oxygen degradation effect. In addition, the inventor successfully designed a method to significantly reduce or even completely avoid eLID sensitivity.

[0009] The sensitivity of the eLID and the sensitivity of the LID have similar properties, that is, when the solar cell is irradiated by light or after the current flows through the solar cell, it is very likely that the battery performance will deteriorate. Although there is the term "photoinduced" in both LID and eLID, in fact, when current flows through the solar cell, a voltage is applied to both ends of the solar cell, which results in high levels of energy generated between different positions of the solar cell. The current flowing from the voltage to the low voltage may also cause degradation of the performance of the solar cell. The light intensity or current density required to produce the attenuation depends on the operating temperature, light or power-on time, and other operating and production parameters of the solar cell.

[0010] When eLID-type battery performance degradation occurs, the solar cell efficiency will drop by several percentage points, for example, by at least 3%, 5%, 7%, 9% or more. This kind of efficiency decay is usually accompanied by a decrease in carrier lifetime, with a decrease of at least half or even an order of magnitude. For example, the carrier lifetime may be shortened from hundreds of microseconds to tens of microseconds. The carrier lifetime measurement on the substrate is performed before the substrate is contacted or metalized.

[0011] An important aspect of the present invention is based on the discovery that there is a manufacturing step in the manufacturing process of solar cells that can induce eLID sensitivity in the finished solar cell, that is, the eLID sensitivity of the solar cell Sex will improve. Generally speaking, in the solar cell manufacturing process, the sintering process or sintering step is a particularly critical step, that is, the above-mentioned decisive step that affects its eLID sensitivity. In order to realize the metallization of the metallization slurry, a layer of metallization slurry is coated on the surface of the substrate, so that after the substrate undergoes a sintering step, the metallization slurry generates a metallization layer. The above sintering step is very easy to cause eLID sensitivity of the solar cell in the future use process. Up to now, it has not been studied which effect causes eLID. It is now known that when LID-type performance degradation occurs, the mechanism of battery performance degradation is the formation of boron-oxygen complexes in solar cells. When eLID occurs, there may be multiple different battery performance degradation mechanisms at the same time.

[0012] It can be understood from the above description that an annealing treatment step can be provided to reduce the increasing tendency of eLID sensitivity caused in a manufacturing step. In other words, after the substrate has undergone a manufacturing step that leads to an increase in eLID sensitivity, the semi-finished product is subjected to an annealing treatment step to eliminate the eLID sensitivity to a certain extent. For this reason, in the annealing step, the substrate undergoes an annealing temperature profile. The annealing temperature curve needs to be set so that the substrate is placed in an environment that reaches a certain temperature range within an annealing treatment time of at least 3 seconds. The lower limit of the temperature range is about 400°C and the upper limit is about 700°C. Similarly, it can also be used in the processing of a finished solar cell

Use the above annealing temperature profile. In this article, all the annealing temperature curves mentioned in the solar cell manufacturing process are applicable to the solar cell processing process, and vice versa.

[0013] When the substrate or the finished solar cell is placed at a certain temperature within an annealing treatment period, and the above-mentioned temperature is within the annealing temperature range, eLID sensitivity can also be eliminated. In a preferred treatment scheme, the annealing treatment time is at least 3, 4, 5, 7 or 9 seconds. Preferably, the lower limit of the annealing temperature is 400°C, 420°C, 450°C or 480°C. Preferably, the upper limit of the annealing temperature is 550°C, 600°C, 650°C or 700°C.

[0014] In a preferred embodiment of the present invention, the annealing step includes a heating stage and/or a cooling stage, The substrate undergoes an annealing temperature curve during the annealing process, and the maximum slope is 100 Kelvin per second (K/s), 70K/S, 50K/S, 40K/s in the heating stage and/or a cooling stage of the annealing treatment step Or 30K/s. In the preferred annealing treatment plan, the maximum slope in the heating stage of the annealing treatment step is 100 Kelvin per second (K/s), 70K/s, 50K/s, 40K/s or 30K/s, and the temperature reduction of the annealing treatment step The maximum slope in the stage is 100 Kelvin per second (K/s), 70K/s, 50K/s, 40K/s or 30K/s. This refers to the absolute value of the maximum slope, especially during the cooling process. The value is negative. [0015] By changing the temperature of the substrate or the finished solar cell within a certain temperature range within a certain time, the eLID sensitivity of the solar cell can be greatly reduced or completely eliminated. It is also possible to change the processed parts. The temperature of the processed part changes to replace the annealing method that changes the temperature of the substrate or the finished solar cell within a certain period of time. For example, the substrate or the finished solar cell is moved from a certain position in the space to another temperature. In the same position, the annealing treatment of the part is realized. In particular, it should be noted that the substrate/finished solar cell can be passed through a continuous heating furnace to realize the entire annealing treatment process of the part.

[0016] During the annealing process, the substrate or finished solar cell can be heated to the maximum allowable heating temperature, which is greater than 400°C, 430°C, 450°C, 470°C, 500°C, or 550°C.

[0017] In a preferred embodiment of the present invention, during the manufacturing process of the solar cell, the substrate undergoes a sintering step, a heating stage of a sintering step or a cooling stage of a sintering step, through the above treatment, so that the substrate is coated on The metallization paste on the surface of the substrate generates a metallization layer. The sintering process may become the process that causes eLID sensitivity in solar cells, depending on the process parameters in the process. That is to say, because of the above-mentioned sintering process, or only because of the heating stage during the sintering process or only the cooling stage during the sintering process, the manufactured solar cell has a higher eLID sensitivity. In this case, if the relevant components are subjected to an annealing step after the sintering step is completed, so that the eLID sensitivity of the solar cell is eliminated, it is beneficial to improve the performance of the solar cell.

[0018] If a solar energy manufacturing process includes a sintering step, and includes a heating stage therein, it is preferable to integrate the annealing treatment step into a cooling stage in a sintering step. For example, when setting the treatment temperature of the sintering step, a plateau period (Plateau) can be set on the temperature change curve of the sintering step to realize the annealing treatment step, that is, when the temperature of the sintering treatment reaches the maximum temperature, keep the temperature for a period time.

[0019] According to a preferred embodiment of the present invention, during the annealing process, the substrate or the solar cell is irradiated with light and/or the substrate or the solar cell is energized. Illuminating or energizing the substrate or the solar cell can promote the solar cell to eliminate its eLID sensitivity, or it can be used to observe the substrate and the solar cell during the annealing process.

[0020] According to a preferred embodiment of the present invention, the substrate is made of monocrystalline (monocrystalline), polycrystalline (polycrystalline) or polycrystalline (multicrystalline) semiconductor. The substrate is preferably made of silicon.

[0021] The present invention relates to a solar cell manufacturing solution that is conducive to the realization of solar cell design requirements, and a substrate

One or both sides are covered with a passivation layer with surface passivation function. The passivation layer may preferably be provided on the surface of the metal paste coated with the metal paste in order to produce the paste metalized substrate. In this case, a laser sintering contact processing step (LFC) can be additionally provided before or after the sintering step. In the industry, the passivation layer is preferably an aluminum oxide layer, an aluminum oxynitride layer, a silicon dioxide layer and/or a silicon nitride layer. In practical applications, there are also multiple passivation layers that can be set to overlap each other. For example, one layer is a chemical passivation layer, and the other layer is a passivation layer with field-effect passivation characteristics.

[0022] The above-mentioned passivation layer is suitable for use as a back passivation layer and/or as a front passivation layer, where an aluminum oxide layer, an aluminum oxynitride layer and/or an aluminum oxide, aluminum oxynitride, and oxynitride layer are often used. The back passivation layer is composed of a multilayer structure composed of several substances in silicon and/or silicon nitride, and a layer composed of silicon oxynitride or silicon nitride is suitable as a front passivation layer and/or an anti-reflection layer.

Description of the drawings

[0023] Hereinafter, the present invention will be explained through embodiments with reference to the accompanying drawings, in which:

[0024] FIGS. 1a) to e) are schematic diagrams of the steps involved in the present invention in the manufacturing process of solar cells;

[0025] FIG. 2 is a graph of annealing temperature; and

[0026] FIG. 3 is a graph of temperature changes in a sintering step integrated with an annealing treatment step.

Detailed ways

[0027] Figures la) to e) show the different steps in the solar cell manufacturing process. In particular, it can be seen from this schematic diagram that after the component has obtained the functional layer, it has undergone an annealing step. As shown in Figure 1a), a base 1 is provided first. As shown in Figure 1b), a functional layer 2 is formed on the substrate. In the example given in the present invention, the functional layer may be, for example, a metallization layer, a passivation layer, a doped layer or a similar functional layer, and it is also possible to provide multiple layers of the above functional layer on a component. In the subsequent steps, the substrate 1 coated with the functional layer 2 passes through the continuous heating furnace 3, and the annealing treatment step is completed in the above process.

[0028] In the continuous heating furnace 3 shown in the figure, the temperature is different, and the description can be simplified to divide the temperature in the furnace into three temperature zones, namely 31, 32, and 33. The substrate 1 first enters the entrance area 30, and then enters the continuous heating furnace 3. When the substrate 1 passes through the exit area 34, it leaves the continuous heating furnace 3. In the above process, the substrate 1 passes through all three temperature zones 31, 32, 33. In the first temperature zone 31, the substrate 1 is heated and raised. In other words, the base body 1 has also undergone the heating stage of the annealing high temperature treatment during this period. In the second temperature range 32, the temperature of the substrate 1 reaches the maximum temperature or the maximum limit temperature. Then, while the substrate 1 passes through the third temperature zone of the continuous heating furnace 3, the substrate 1 undergoes a cooling stage of annealing treatment.

[0029] As can be seen in FIG. 1c), the substrate 1 enters the continuous heating furnace 3 and passes through the first temperature zone 31. After that, as shown in Figure Id), the substrate 1 enters the second temperature zone 32. Here, the temperature of the substrate has reached the highest temperature in the entire process. After that, as shown in Fig. 1e), the substrate 1 enters the third temperature zone and its temperature starts to drop. Then, the substrate 1 passes through the exit zone 34 and leaves the continuous heating furnace 3.

[0030] As shown in FIG. 2, because the substrate 1 has to pass through the continuous heating furnace 3, the substrate 1 will undergo a temperature change process. In the temperature diagram, time changes are shown along the X axis, and temperature changes are shown along the Y axis. It can be seen from the figure that the annealing temperature curve 51 is composed of a heating stage 51a and a cooling stage 51b. Due to the process of conforming to the annealing temperature curve 51, the eLID sensitivity that may have occurred in the solar cell is reduced or completely eliminated. For this reason, the maximum slope during the heating phase 51a and/or the cooling phase 51b cannot exceed approximately

100K/so

[0031] FIG. 3 is another schematic diagram, in which a temperature change process curve 4 during the sintering process is involved. The temperature change process curve 4 includes a temperature rise stage 4a of the sintering process and a temperature drop stage 4b of the sintering process. Here, the temperature change curve in the temperature increase stage 4a of the sintering process and the temperature decrease stage 4b of the sintering process may be the temperature change curve commonly used. In this case, if the temperature change in the sintering process step changes according to the temperature change curve 4, it is likely to cause the eLID sensitivity of the manufactured solar cell to increase. In order to avoid the above situation, it is necessary to introduce an annealing treatment step, which is integrated in the cooling stage 4b of the sintering step. In other words, the temperature of the substrate 1 is kept within a certain temperature range during the annealing treatment time, that is, higher than the lower limit temperature and lower than the upper limit temperature. In this way, in the cooling stage 4b of the sintering treatment step, the substrate 1 is annealed deal with. In the example shown in FIG. 3, the annealing temperature curve 52 of another annealing treatment step with another cooling stage 52b constitutes a plateau in the cooling stage 4b of the sintering treatment stage.

<td>[0032]</td><td colspan="2">List of reference signs:</td>

<td>[0033]</td><td>1</td><td>Matrix</td>

<td>[0034]</td><td>2</td><td>Functional layer</td>

<td>[0035]</td><td>3</td><td>Continuous heating furnace</td>

<td>[0036]</td><td>30</td><td>Entrance area</td>

<td>[0037]</td><td>31</td><td>First temperature zone</td>

<td>[0038]</td><td>32</td><td>Second temperature zone</td>

<td>[0039]</td><td>33</td><td>The third temperature zone</td>

<td>[0040]</td><td>34</td><td>Export area</td>

<td>[0041]</td><td>4</td><td>The temperature change process of the sintering step</td>

<td>[0042]</td><td>4a</td><td>The heating phase of the sintering step</td>

<td>[0043]</td><td>4b</td><td>The cooling stage of the sintering step</td>

<td>[0044]</td><td>51</td><td>Annealing temperature curve</td>

<td>[0045]</td><td>51a</td><td>Warming up phase</td>

<td>[0046]</td><td>51b</td><td>Cooling stage</td>

<td>[0047]</td><td>52</td><td>Another annealing temperature profile</td>

<td>[0048]</td><td>52b</td><td>Another cooling stage</td>