Composition of memory cell with resistance-switching layers

Synthesis of memory cell and resistance switching layer

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the rights of priority of U.S. Application No. 13/40 & 394 filed on February 29, 2012. The U.S. Application No. 13/408, 394 requires the United States filed on November 7, 2011 The rights and interests of provisional patent application no. 61/556, 486 are incorporated herein by reference.

Technical field

[0003] The present technology relates to data storage.

Background technique

[0004] Various materials show reversible resistance change or resistance switching behavior, where the resistance of a material is a function of the history of the current flowing through the material and/or the voltage across the material. These materials include chalcogenides, carbon polymers, perovskites, and certain metal oxides (MeOx) and metal nitrides (MeN). Specifically, there are metal oxides and nitrides that include only one metal and exhibit reliable resistance switching behavior. This group includes, for example, nickel oxide (NiO), ingot oxide (Nb205), titanium dioxide (Ti02), zirconium dioxide (HfO2), aluminum oxide (A1203), magnesium oxide (MgOx), Luo dioxide (Cr02), oxidizer ( V0), Boron Nitride (BN) and Aluminum Nitride (A1N), such as Pagnia and Sotnick in Bistable Switching in Electroformed MetalTnsulator-metal Device, Phys. Stat. Sol. (A) As described in 108, 11-65 (1988). The resistance switching layer (RSL) of one of these materials can be formed in an initial state, for example a relatively low resistance state. After a sufficient voltage is applied, the material switches to a stable high-resistance state, which is maintained even after the voltage is removed. This resistance switching is reversible, so that subsequent application of an appropriate current or voltage can be used to return the RSL to a stable low resistance state, which is maintained even after the voltage or current is removed. This conversion can be repeated many times. For some materials, the initial state is high resistance rather than low resistance. Set processing may refer to switching the material from high resistance to low resistance, and reset processing may refer to switching the material from low resistance to high resistance. The resistance switching memory element (RSME) may include an RSL between the first and second electrodes.

[0005] Of interest is the use of these reversible resistance change materials in non-volatile memory arrays. For example, one resistance state may correspond to data "0", while another resistance state corresponds to data "1". Some of these materials can have more than two stable resistance states. Furthermore, in the memory cell, the RSME may be connected in series with an operating element such as a diode, which operating element selectively limits the voltage across the RSME and/or the current flowing through the RSME. For example, a diode may allow current to flow in only one direction of RSME, while substantially preventing current from flowing in the opposite direction. Such a manipulation element itself is usually not a resistance changing material. Rather, the manipulation element allows writing to and/or reading from the memory cell without affecting the state of other memory cells in the array.

[0006] Non-volatile memories having memory elements or cells formed of resistance change materials are known. For example, U.S. Patent Application Publication No. 2006/0250836, which is incorporated herein by reference, entitled Rewriteable Memory Cell Comprising A Diode And A Resistance-Switching Material describes a rewritable non-volatile memory cell, which includes a non-volatile memory cell such as MeOx Or the resistance of MeN changes the material of the diode coupled in series.

[0007] However, there is a constant demand for technologies that allow memory cell size reduction.

Description of the drawings

[0008] FIG. 1 is a simplified perspective view of one embodiment of a memory cell including an RSME in series with a manipulation element.

[0009] FIG. 2A is a simplified perspective view of a portion of a first memory level formed by a plurality of memory cells of FIG. 1.

[0010] FIG. 2B is a simplified perspective view of a portion of a three-dimensional memory array formed by a plurality of memory cells of FIG. 1.

[0011] FIG. 2C is a simplified perspective view of a portion of a three-dimensional memory array formed by a plurality of memory cells of FIG. 1.

[0012] FIG. 3 is a block diagram of one embodiment of a memory system.

[0013] FIG. 4A is a graph depicting the I-V characteristics of an example unipolar RSL.

[0014] FIG. 4B is a diagram depicting the different-V characteristics of the unipolar RSL of two examples.

[0015] FIG. 4C is a diagram depicting the I-V characteristics of another example of a unipolar RSL.

[0016] FIG. 4D is a diagram depicting the I-V characteristics of an exemplary bipolar RSL.

[0017] FIG. 4E is a diagram depicting the I-V characteristics of another example of a bipolar RSL.

[0018] FIG. 5 depicts an embodiment of a circuit for reading the state of a memory cell.

[0019] FIG. 6A depicts an example memory cell with an RSME and a manipulation element (SE) below the RSME.

[0020] FIG. 6B depicts an alternative configuration of a memory cell with RSME, where the steering element (SE) is above the RSME.

[0021] FIG. 6C depicts the implementation of the RSME of FIG. 6A as an example of a mirror resistance switch (MRS) in a vertical stack.

[0022] FIG. 6D depicts an example implementation of the RSME of FIG. 6A using multiple intermediate layers (IL) between RSLs.

[0023] FIG. 6E depicts an example implementation of the RSME of FIG. 6A using repeated RSL/IL patterns.

[0024] FIG. 6F depicts an example implementation of the RSME of FIG. 6A, in which each layer of the RSME extends horizontally and one or more layers are arranged end-to-end.

[0025] FIG. 6G depicts another example implementation of the RSME of FIG. 6A, in which each layer of the RSME extends horizontally and one or more layers are arranged end to end.

[0026] FIG. 6H depicts another example implementation of the RSME of FIG. 6A, where each layer of the RSME extends vertically.

[0027] FIG. 61 depicts another example implementation of the RSME of FIG. 6A, which includes RSL1, IL, RSL2, and E2

L-shaped part.

[0028] FIG. 6J depicts another example implementation of the RSME of FIG. 6A, which includes RSL1, IL, RSL2, and E2

U-shaped part.

[0029] FIG. 6K1 depicts another example implementation of the RSME of FIG. 6A, which uses an RSL and a breakdown layer below the RSL.

[0030] FIG. 6K2 is a diagram showing the transition of the breakdown layer from the initial state to the breakdown state.

[0031] FIG. 6K3 is a graph showing the I-V characteristics of the breakdown layer in the initial state (solid line) and the breakdown state (dashed line).

[0032] FIG. 6L depicts an example implementation of the RSME of FIG. 6A, which uses an RSL and a breakdown layer above the RSL.

[0033] FIG. 6M depicts an example implementation of the RSME of FIG. 6A, where RSL is of different types.

[0034] FIG. 7A depicts an example implementation of a manipulation element (SE) of the memory cell of FIG. 6A as a Si diode.

[0035] FIG. 7B depicts an example implementation of the manipulation element of the memory cell of FIG. 6A as a punch-through diode.

[0036] FIG. 8 depicts an example implementation of the memory cell of FIG. 6A connected between a bit line and a word line.

[0037] FIG. 9A depicts an embodiment of the RSME of FIG. 6C, where E1 is composed of Co, CoSi, n+Si, p+Si, or p+Sic

And E2 is made of n+Si.

[0038] FIG. 9B depicts an embodiment of the RSME of FIG. 6C, where E1 and IL are made of p+Sic, and E2 is made of n+Si, n+SiC, or p+Sic.

[0039] FIG. 9C is a graph plotting the Fermi (Feimi) energy levels of p+SiC relative to other materials.

[0040] FIG. 10A depicts one embodiment of the RSME of FIG. 6C depicting an alternative IL material.

[0041] FIG. 10B depicts an embodiment of the RSME of FIG. 6C in an inverted mirror stack configuration.

[0042] FIG. 10C depicts an embodiment of the RSME of FIG. 6A in an asymmetrical upright stack configuration.

[0043] FIG. 10D depicts an embodiment of the RSME of FIG. 6A in an asymmetric reverse stack configuration.

[0044] FIG. 11A depicts an embodiment of the RSME of FIG. 6C, showing the growth of SiOx when E2 is n+Si.

[0045] FIG. 11B depicts an embodiment of the RSME of FIG. 6C, showing the growth of a low band gap material such as TiOx when E2 is TiN.

[0046] FIG. 11C depicts an embodiment of the RSME of FIG. 6C, where the RSL is made of doped metal oxide to reduce the operating voltage.

[0047] FIG. 11D depicts an embodiment of the RSME of FIG. 11C, where E2 is TiN instead of n+Si.

[0048] FIG. 11E depicts an embodiment of the RSME of FIG. 6C configured with an asymmetric mirror unit, where the RSL is made of different materials.

[0049] FIG. 11F depicts an embodiment of the RSME of FIG. 6C configured as an asymmetric mirror unit without SiOx. [0050] FIG. 12 depicts the energy diagram of the RSME of FIG. 6C.

[0051] FIG. 13 depicts the application of a high electric field in the RSL setting process.

[0052] FIGS. 14A-14D depict different stages in the formation of a conductive filament in the RSL setting process.

[0053] FIGS. 14E, 14F, and 14G are energy diagrams describing the setting processing stages of FIGS. 14A, 14B, and 14D, respectively.

[0054] FIGS. 15A-15C depict different stages of removal of the conductive filament in the reset process of the RSL.

[0055] FIGS. 15D, 15E, and 15F are energy diagrams describing the reset processing stages of FIGS. 15A, 15B and 15C, respectively.

[0056] FIG. 16A depicts the setting process of the RSME of FIG. 6A.

[0057] FIG. 16B depicts the reset process of the RSME of FIG. 6A.

[0058] FIG. 17 is a perspective view of a non-volatile memory cell of an embodiment.

[0059] FIGS. 18A, 18B, 18C, 18D, and 18E are side cross-sectional views schematically illustrating a nonvolatile memory cell of an embodiment of the present invention.

[0060] FIG. 19A is a schematic illustration of a test structure for testing one embodiment of a memory cell.

[0061] FIGS. 19B, 19C, and 19D are standardized diagrams illustrating test results of the structure of FIG. 19A.

[0062] FIG. 20A is a schematic illustration of a test structure of a memory cell used for test comparison.

[0063] FIGS. 20B, 20C and 20D are standardized diagrams illustrating test results of the structure of FIG. 20A.

Detailed ways

[0064] A memory system is provided that includes a reversible resistivity-switching memory element (RSME) having two or more resistance-switching layers (RSL). In an example implementation, the RSME includes a first electrode (E1) connected in series , The first resistance switching layer (RSL1), the intermediate layer (IL) which is considered as the scattering layer or coupling electrode, the second RSL (RSL2) and the second electrode (E2). In one approach, RSME has a mirror configuration, where on either side of IL, the RSME configuration is

Weighed. However, such a mirror configuration is not required.

[0065] Generally, as the size of RSME-based memory devices shrinks, the disadvantage is that the ballistic current during the setting or resetting process of RSME may damage the associated operating elements connected in series with RSME, or even prevent memory cells to reduce A lot of size and operation. Moreover, generally, too many RSL-based memory devices require forming steps, during which the initial insulation properties of the RSL are destroyed. This formation step is usually associated with a very short and very high discharge current peak, which can set the on-resistance level of RSL for subsequent switching events. If the on-resistance level is very low (eg 100-30kQ), the associated switching current is also very high, and thus, the memory cell will be inoperable at very small technology nodes. The set or reset process is the type of resistance switching operation for RSL and RSME. To solve this problem, an RSME is provided that includes a separate RSL on either side of the conductive IL.

[0066] Specifically, the memory cell including the RSME as provided herein can limit the inrush current overshoot by actively reducing the operating current _oA thin IL such as TiN can prevent current overshoot and can restrict current flow, thereby making it easier to create a large electric field across the respective RSL. Due to the reduced current, the possibility of damaging the operating elements of the unit is reduced, and thinner operating elements can be used, which helps to shrink the memory device and may reduce power consumption. The switching capability of the unit is maintained because the ion current is still allowed.

[0067] RSME is based on a qualitative model for the respective RSL, which describes a number of findings, including: switching current based on electron/hole and ion conduction, exponential E-field dependence of ion current, and measurement The current is the rush current and is not used for the switching mechanism. Specifically, the qualitative model describes: (i) avalanche-type setting current increases, (ii) why it is difficult to limit the setting state to a high on-resistance state, (iii) the sensitivity of the loop field to the setting process , (Iv) Why the reset voltage can be higher than the set voltage, (ν) why a deeper reset requires a higher reset voltage, and (vi) why the reset current is higher for a deeper reset. The inrush current model can also be applied to any other "thin" storage materials/ion memory, such as TiSi, CBRAM (conductive bridge RAM). For RSL or MeOx, these findings also indicate that the electron/hole current does not contribute to the switching effect, but travels impulsively in MeOx, only transferring heat to the contact, and this is different from thicker carbon or phase change Materials, among these materials, if the memory cell is long enough, this current generates heat in the memory cell.

[0068] FIG. 1 is a simplified perspective view of an embodiment of a resistance switching memory cell (RSMC) 100 that includes an RSME 102o coupled in series with a manipulation element 104 between a first conductor 106 and a second conductor 108

[0069] The RSME 102 includes RSL 130 and 135 on either side of the conductive intermediate layer (IL) 133. As mentioned, RSL has a resistivity that can be reversibly switched between two or more states. For example, the RSL can be in an initial high-resistivity (high-resistivity) state during manufacture, and it can be switched to a low-resistivity state after applying the first voltage and/or current. Application of the second voltage and/or current can return the RSL to a high resistivity state. Alternatively, the RSL can be in an initial low-resistance state during manufacture, and it can be reversibly switched to a high-resistance state after applying an appropriate voltage and/or current. When used in a memory cell, one resistance state for each RSL (and the corresponding resistance state of RSME) can represent the binary "0" of RSME, and the other resistance state for each RSL (and the corresponding resistance state of RSME) ) Can represent the binary "1" of RSME. However, more than two data/resistance states can be used. For example, in the aforementioned US Patent Application Publication No. 2006/0250836, a plurality of reversible resistance changing materials and the operation of a memory cell using the reversible resistance changing materials are described.

[0070] In one embodiment, the process of switching the RSME from a high resistivity state (representing, for example, binary data "0") to a low resistivity state (representing, for example, binary data "1") is called setting or forming, and The process of switching the RSME from the low-resistivity state to the high-resistivity state is called reset. In other embodiments, set and reset and/or data encoding

It can be the opposite. The memory cell can be set or reset to program it to a desired state representing binary data.

[0071] In some embodiments, RSL130 and 135 may be formed of metal oxide (MeOx), an example of which is

Hf02o

[0072] Can be published on January 1, 2009 entitled ^uMemory Cell That Employs a Selectively Deposited Reversible Resistance Switching Element and Methods of Forming The Same, US2009/0001343, finds more information on the use of reversible resistance changing materials to fabricate memory cells, which is incorporated herein by reference.

[0073] The RSME 102 includes electrodes 132 and 134. The electrode 132 is located between the RSL 130 and a conductor 108 such as a bit line or a word line (control line). In one embodiment, the electrode 132 is made of titanium (Ti) or titanium nitride (TiN). The electrode 134 is located between the RSL 133 and the manipulation element 104. In one embodiment, the electrode 134 is made of titanium nitride (TiN) and serves as an adhesion and barrier layer.

[0074] The manipulation element 104 may be a diode or other suitable manipulation element that exhibits non-ohmic conductivity by selectively limiting the voltage across the RSME 102 and/or the current flowing through the RSME 102. In one approach, the steering element allows current to flow through the RSME in only one direction, for example from bit line to word line. In another method, manipulating elements such as punch-through diodes are allowed to flow through RSMEo in either direction

[0075] The operating element acts as a one-way valve and conducts current more easily in one direction than in the other direction. Below the critical "on" voltage in the forward direction, the diode conducts little or no current. By using an appropriate biasing scheme, when a separate RSME is selected for programming, the diodes of adjacent RSMEs can be used to electrically isolate the adjacent RSMEs, thus preventing unintentional resistance switching, as long as the adjacent RSMEs are crossed When applied in the forward direction of the adjacent RSME, the voltage does not exceed the turn-on voltage of the diode or does not exceed the reverse breakdown voltage when applied in the reverse direction.

[0076] Specifically, in a large cross-point array of RSME, when a relatively large voltage or current is required, there is an RSME that shares a top or bottom conductor (such as a word line or a bit line) with the RSME to be addressed. The danger of being exposed to voltage or current sufficient to cause undesired resistance switching. Depending on the biasing scheme used, excessive leakage current across unselected cells may also be a problem. The use of diodes or other control elements can overcome this danger.

[0077] In this way, the memory cell 100 can be used as part of a two-dimensional or three-dimensional memory array, and data can be written to and/or read from the memory cell 100 without affecting the performance of other memory cells in the array. status. The steering element 104 may include any suitable diode such as a vertical polysilicon pn or pin diode, regardless of whether the n-region of the diode is directed upward above the p-region or the p-region of the diode is directed downward above the n-region. Or even punch-through diodes or Zener diodes can be used, which can operate in both directions. The operating element and RSME together can be in the shape of a vertical column. In other methods, the parts of the RSME are arranged laterally to each other, as discussed further below.

[0078] In some embodiments, the manipulation element 104 may be formed of a polycrystalline semiconductor material such as polysilicon, polysilicon-aluminium alloy, polygermanium, or any other suitable material. For example, the manipulation element 104 may include a heavily doped n+ polysilicon region 142, a lightly doped or intrinsic (unintentionally doped) polysilicon region 144 above the n+ polysilicon region 142, and above the intrinsic region 144 The heavily doped p+ polysilicon region 146. In some embodiments, a thin (for example, a few hundred angstroms or less) aluminum and/or silicon-aluminium alloy layer (not shown) may be formed on the n+ polysilicon region 142-when a silicon-aluminum alloy layer is used About 10% or more errors-to prevent and/or reduce the migration of dopants from the n+ polysilicon region 142 to the intrinsic region 144, for example, as described in the title "Deposited

Semiconductor Structure To Minimize N-Type Dopant Diffusion And Method Of Making is described in US Patent Application Publication No. 2006/0087005, which is incorporated herein by reference. It will be understood that the positions of the n+ and P+ regions can be reversed.

[0079] When the manipulation element 104 is manufactured from deposited silicon (for example, amorphous or polycrystalline), a silicide layer may be formed on the diode to place the deposited silicon in a low resistivity state during manufacture. Such a low-resistivity state allows for easier programming of the memory cell because a large voltage is not required to switch the deposited silicon to a low-resistivity state.

[0080] As in U.S. Patent No. 7, 176, 064 incorporated herein by reference ^uAs described in Memory Cell Comprising a Semiconductor Junction Diode Crystallized Adjacent to a Silicide, a silicide-forming material such as titanium and/or diamond reacts with deposited silicon to form a silicide layer during annealing. The lattice spacing of titanium silicide and drill silicide is close to that of silicon, and it seems that such a silicide layer can be used as a "crystallization template" or "template" for adjacently deposited silicon when the deposited silicon crystallizes. Seed" (for example, the silicide layer enhances the crystal structure of the silicon diode during annealing). As a result, silicon with lower resistivity can be provided. Similar results can be achieved for silicon-aluminium alloys and/or zirconium diodes.

[0081] The conductors 106 and 108 include any suitable conductive materials such as ducks, suitable metals, heavily doped semiconductor materials, conductive silicides, conductive silicide-complexes, conductive complexes, and the like. In the embodiment of FIG. 1, the conductors 106 and 108 are rail-shaped and extend in different directions (eg, substantially perpendicular to each other). Other conductor shapes and/or configurations can be used. In some embodiments, barrier layers, adhesion layers, anti-reflective coatings, etc. (not shown) may be used with conductors 106 and 108 to improve device performance and/or aid device manufacturing. The conductor 106 can be a word line, and the conductor 108 can be a bit line, or vice versa.

[0082] Although RSME 102 is shown in FIG. Various other configurations are also possible. RSL can exhibit unipolar or bipolar resistance switching characteristics. Utilizing the unipolar resistance switching feature, the voltages used for setting and resetting have the same polarity, that is, both are positive or both are negative. In contrast, using the bipolar resistance switching feature, voltages of opposite polarity are used for set and reset processing. Specifically, the voltage used for the setting processing may be positive and the voltage used for the reset processing may be negative, or the voltage used for the setting processing may be negative and the voltage used for the reset processing may be positive.

[0083] FIG. 2A is a simplified perspective view of a portion of the first memory level 114 formed from the plurality of memory cells 100 of FIG. 1. Briefly, the RSME 102, the manipulation element 104, and the barrier layer 113 are not separately shown. The memory array 114 is a "cross-point" array that includes a plurality of bit lines (second conductor 108) and word lines (first conductor 106) to which a plurality of memory cells are coupled. Other memory array configurations can be used, such as multi-level memory.

[0084] FIG. 2B is a simplified perspective view of a portion of a monolithic three-dimensional array 116 that includes a first memory level 118 located below a second memory level 120. In the embodiment of FIG. 3, each memory level 118 and 120 includes a plurality of memory cells 100 in a cross-point array. It will be understood that there may be additional layers between the first and second memory levels 118 and 120 (eg Intermediate dielectric), but not shown in Figure 2B for simplicity. Other memory array configurations can be used, such as additional memory levels. In the embodiment of FIG. 2B, all diodes can be "pointed" in the same direction, such as up or down depending on whether a pin diode with a p-doped region on the bottom or top of the diode is used.

[0085] In some embodiments, the memory level may be formed as described in US Patent No. 6,952,030, High-Density Three-Dimensional Memory Cell, which is incorporated herein by reference. For example, the upper conductor of the first memory level can be used as the lower conductor of the second memory level located above the first memory level, as shown in Figure 2C

Shown. In such an embodiment, the diodes on adjacent memory levels preferably point in opposite directions, as in US Patent 7,586, entitled Large Array Of Upward Pointing PIN Diodes Having Large And Uniform Current, which is incorporated herein by reference. 773. For example, the diode of the first memory level 118 may be an upward-pointing diode as indicated by arrow A1 (for example, the ρ area is at the bottom of the diode), and the diode of the second memory level 120 may be such as The downward-pointing diode indicated by arrow A2 (for example, the n area is at the bottom of the diode), or vice versa.

[0086] A monolithic three-dimensional memory array is an array in which multiple memory levels are formed on a single substrate such as a wafer without an intermediate substrate. Direct deposition or growth directly on the existing one or more level layers to form a memory level layer. In contrast, stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels on top of each other, as in Leedy's US Patent No. 5, 915, 167, Three Dimensional, which is incorporated herein by reference Like in Structure Memory. The substrate can be thinned or removed from the memory stage before bonding, but because the memory stage is initially formed on a separate substrate, such a memory is not a true monolithic three-dimensional memory array.

[0087] The above examples show memory cells in the shape of cylinders or columns and conductors in the shape of rails according to the disclosed arrangement. However, the technology described here is not limited to any specific structure of the memory cell. Other structures can also be used to form memory cells including RSMEs. For example, each of U.S. Patent Nos. 6,952, 043, 6, 951, 780, 6, 034, 882, 6, 420, 215, 6, 525, 953, and 7, 081, 377, which are incorporated herein by reference, provides An example of the structure of a memory cell adapted to use RSME. In addition, other types of memory modules can also be used with the techniques described here.

JL· ο

[0088] FIG. 3 is a block diagram depicting an example of a memory system 300 that can implement the techniques described herein. The memory system 300 includes a memory array 302, which may be a two-dimensional or three-dimensional array of memory cells as described above. In one embodiment, the memory array 302 includes various layers of word lines organized as rows and various layers of bit lines organized as columns. However, other orientations can also be achieved.

[0089] The memory system 300 includes a row control circuit 320 whose output 308 is connected to a corresponding word line of the memory array 302. The row control circuit 320 receives a set of M row address signals and one or more various control signals from the system control logic circuit 330, and may generally include, for example, a row decoder 322, an array terminal driver 324, and a device for reading and programming ( For example, setting and resetting) operate both the block selection circuit 326 such a circuit. The memory system 300 also includes a column control circuit 310, the input/output 306 of which is connected to the corresponding bit line of the memory array 302. The column control circuit 306 receives a set of N column address signals and one or more various control signals from the system control logic 330, and may generally include, for example, a column decoder 312, an array terminal receiver or driver 314, a block selection circuit 316, and The read/write circuit of the sense amplifier 318 and circuits such as the I/O multiplexer are included. The system control logic 330 receives data and commands from the host and provides output data to the host. In other embodiments, the system control logic 330 receives data and commands from a separate controller circuit and provides output data to the controller circuit, which communicates with the host. The system control logic 330 may include one or more state machines, registers, and other control logic for controlling the operation of the storage system 300. E.g, The write circuit 460, the read circuit 461, and the clamp control circuit 464 discussed further below may be provided.

[0090] In one embodiment, all the components depicted in FIG. 3 are arranged on a single integrated circuit. For example, the system control logic 330, the column control circuit 310, and the row control circuit 320 may be formed on the surface of the substrate and the memory array 302 in the monolithic three-dimensional memory array may be formed on the substrate (therefore, in the system control logic 330, column control Above the circuit 310 and the row control circuit 320). In some cases, the control can be formed on the same layer as some memory arrays.

Control the logic of the circuit.

[0091] Integrated circuits incorporating a memory array usually subdivide the array into multiple sub-arrays or blocks. Blocks can be further grouped together into bays, which contain, for example, 16, 32, or different numbers of blocks. As often used, a sub-array is a continuous group of memory cells with continuous word lines and bit lines that are usually not interrupted by decoders, drivers, sense amplifiers, and input/output circuits. Do this for any variety of reasons. For example, in a large array, the signal delay (ie, RC delay) down the word line and bit line caused by the resistance and capacitance of the word line and bit line may be very significant. These RC delays can be reduced by subdividing the larger array into a set of smaller arrays so that the length of each word line and/or each bit line is reduced. As another example, the power associated with accessing a group of memory cells can dictate the upper limit to the number of memory cells that can be accessed simultaneously during a given memory cycle. Thus, large memory arrays are usually subdivided into smaller sub-arrays to reduce the number of memory cells that are accessed at the same time. However, for ease of description, an array can be used synonymously with a sub-array to refer to a continuous set of memory with continuous word lines and bit lines that are usually not interrupted by decoders, drivers, sense amplifiers, and input/output circuits. unit. The integrated circuit may include one or more than one memory array.

[0092] As described above, the RSME 102 can reversibly switch between two or more states by reversibly switching each of its RSLs. For example, the RSM can be in an initial high-resistivity state during manufacture, and it can be switched to a low-resistivity state when the first voltage and/or current is applied. Application of the second voltage and/or current can return RSME to a high resistivity state. The memory system 300 can be used with any of the RSMEs described herein.

[0093] FIG. 4A is a graph of voltage versus current for an example embodiment of a unipolar RSL. The x-axis plots the absolute value of the voltage, the y-axis plots the current, and the line is adjusted to reach the origin of the graph. In the setting process, the line 404 represents the I-V characteristic of the RSL in the high resistivity, reset state, and the line 406 represents the transition to the low resistivity, set state at Vset. In the reset process, the line 400 represents the I-V characteristic of the RSL when it is in the low resistivity, set state, and the line 402 represents the transition to the high resistivity, reset state at Vreset. This example shows a unipolar mode of operation, where the polarity of the voltage is the same for both set and reset switching.

[0094] In order to determine the state of the RSL, a voltage can be applied across the RSL, and the resulting current can be measured. A higher or lower measured current indicates that the RSL is in a low resistivity or high resistivity state, respectively. In some cases, the high-resistivity state is substantially higher than the low-resistivity state, for example, the magnitude is two or three orders of magnitude higher (100-1,000 times). Note that other variants of RSL with different I-V characteristics can also be used with the technology here.

[0095] When in the reset state, in response to an applied voltage between 0 and Vset, RSME exhibits the resistance characteristic shown by line 404. However, when in the set state, in response to an applied voltage between 0 and Vreset, RSME exhibits the resistance characteristic shown by line 400, where Vreset<Vseto. Therefore, depending on the resistance state of RSME, RSME therefore responds to The same voltage in the same voltage range (for example, between 0 and Vreset) exhibits different resistance characteristics. In the read operation, a fixed voltage VreacKVreset can be applied. In response to this voltage, the sensed current is Ia in the set state or Ibo in the reset state. Therefore, at least one of the I-V characteristics of RSL or RSME can be recognized. Click to sense its status.

[0096] In one method, the RSME may include multiple RSLs, and each RSL exhibits substantially similar unipolar switching characteristics.

[0097] FIG. 4B is a diagram depicting the different I-V characteristics of two example unipolar RSLs. For two or more unipolar RSLs, IV (current-voltage) characteristics may be substantially the same, so that I increases with V at a common ratio, and for example, the set and/or reset levels may be substantially the same. Alternatively, the Ι-V characteristics of RSL can be different, such that for example, for RSL

One, I increases more rapidly with V, or the set and/or reset levels can be different. In this example, "A" represents the first type of RSL, and "B" represents the second type of RSL, where the RSL has different unipolar resistance switching characteristics. The x-axis plots the voltage (V) and the y-axis plots the current (1). For type "A" RSL, the lines 400, 402, 404, and 406 are the same as in FIG. 4A. And for type "A" RSL, VsetA is the setting voltage, VresetA is the reset voltage, IresetA is the reset current, and Iset_limitA is the current setting limit. For type "B" RSL, lines 420, 422, 424, and 426 correspond to lines 400, 402, 404, and 406, respectively. And for type "B" RSL, VsetB is the setting voltage, VresetB is the reset voltage, IresetB is the reset current, and Iset_limitB is the current setting limit. In the method shown here, VsetA>VsetB, VresetA>VresetB, IresetA>VresetB, and Iset_limitA>Iset_limitB, but this is only an example, and other alternative relationships can be applied.

[0098] When two or more RSLs are in the same RSME, the switching characteristics of the RSME will be a function of the switching characteristics of each RSL. During the setup process, for example, as V increases, the type "B" RSL can be switched before the type "A" RSL, if it is divided evenly across each RSL. Similarly, during the setting process, for example, as V increases, the type "B" RSL may be switched before the type "A" RSL, assuming that the same voltage is applied in each RSL.

[0099] Alternatively, it is possible that the type "A" and type "B" RSL have different -V characteristics with opposite polarities. For example, it is possible to make VsetA>0V and Vreset>0V, while VsetB<0V and VresetB<0V. As an example, the characteristics of the type "A" RSL may be as described in FIG. 4A, and the characteristics of the type "B" RSL may be as described in FIG. 4C below. In theory, it is also possible that one RSL in RSME has unipolar characteristics and the other RSL in RSME has bipolar characteristics. However, the use of only one switching characteristic (unipolar or bipolar) among all RSLs in RSME may allow for a simplified control scheme.

[0100] In some cases, the reading of the RSME switches the data state of one of the RSLs. For example, when the first RSL is in a low resistance state and the second RSL is in a high resistance state, the read operation will basically not detect current, assuming that the magnitude of the high resistance state is several orders of magnitude higher than the low resistance state. That is, the resistance of RSME, which is equal to the sum of the resistances of each RSL, will be very high, so the current will be very low or essentially zero. The read operation can switch the second RSL to a low resistance state, so that the resistance of RSME is low, and the current flowing through it is relatively high and detectable. Next, a write back operation can be performed to switch the second RSL back to the high resistance state.

[0101] When a voltage is applied across the electrodes of the RSME, the voltage will cross each RSL divided voltage in proportion to the resistance of each RSL. When the first RSL is in a low resistance state and the second RSL is in a high resistance state, the first RSL will transfer the potential at the electrode to the IL so that substantially all voltage is applied across the second RSL. This voltage will switch the second RSL, if the voltage has the appropriate magnitude and polarity.

[0102] In addition, RSL can use materials that can operate as unipolar or bipolar devices, such as in Coexistence of the bipolar and unipolar resistive switching behaviours in Au/SrTi03/Pt cells, J. Sun et al., which is incorporated herein by reference. . Phys. D: Appl. Phys. 44, 125404, described in March 10, 2011.

[0103] FIG. 4C is a diagram depicting the I-V characteristics of another example of a unipolar RSL. Compared with the characteristic of FIG. 4A, a negative voltage is used instead of a positive voltage during the set and reset process. In the setting process, the line 434 represents the characteristics of the RSL when it is in the high resistivity, reset state, and the line 436 represents the transition to the low resistivity, set state at Vset. In the reset process, the line 430 represents the I-V characteristic of the RSL when in the low resistivity, set state, and the line 432 represents the transition to the high resistivity, reset state at Vreset. Vread, Vreset, Vset, and Vf are all negative voltages. In the read operation, a fixed voltage Vread>Vreset can be applied, and the current sensed in response to this is la in the set state or Ibo in the reset state.

[0104] FIG. 4D is a graph depicting the I-V characteristics of an exemplary bipolar RSL. Here, voltages of opposite polarity are used for the setup and reset processing. In addition, a positive voltage is used for the setting process, and a negative voltage is used for the reset process. In this bipolar RSL, the setting process occurs when a positive voltage is applied, and the reset process occurs when a negative voltage is applied at that time. In the setting process, the line 444 represents the IV characteristic of the RSL when it is in the high resistivity, reset state, and the line 446 represents the transition to the low resistivity, set state at Vset. In the reset process, the line 440 represents the IV characteristic of the RSL when it is in the low-resistivity, set state, and the line 442 represents the transition to the high-resistivity, reset state at Vreset. Vset and Vf are positive voltages, and Vreset is a negative voltage.

[0105] FIG. 4E is a diagram depicting the I-V characteristics of another example of a bipolar RSL. In this bipolar RSL, reset processing occurs when a positive voltage is applied, and setting processing occurs when a negative voltage is applied. In the setting process, the line 454 represents the IV characteristic of the RSL when it is in the high resistivity, reset state, and the line 456 represents the transition to the low resistivity, set state at Vset. In the reset process, the line 450 represents the IV characteristic of the RSL when it is in the low-resistivity, set state, and the line 452 represents the transition to the high-resistivity, reset state at Vreset. Vset and Vf are positive voltages, and Vreset is a negative voltage.

[0106] Although the Ireset level in FIGS. 4D and 4C is higher than the Iset level, it should be emphasized that this can be reversed. This means that for opposite polarities, the Iset level in Figures 4D and 4C can be higher than the Ireset level.

[0107] FIG. 5 depicts an embodiment of a circuit for reading the state of a memory cell. Part of the memory array includes memory cells 550,552,554, and 556. Two of many bit lines and two of many word lines are drawn. The bit line 559 is coupled to the cells 550 and 554, and the bit line 557 is coupled to the cells 552 and 566. The bit line 559 is the selected bit line, and may be at 2V, for example. The bit line 557 is an unselected bit line, and may be grounded, for example. The word line 547 is the selected word line, and may be at 0V, for example. The word line 549 is an unselected word line, and may be at 2V, for example.

[0108] The read circuit for one of the bit lines 559 is depicted as being connected to the bit line via a transistor 558, which is controlled by the gate voltage provided by the column decoder 312 in order to select or not select the corresponding bit line. The transistor 558 connects the bit line to the data bus 563. The write circuit 560 (part of the system control logic 330) is connected to this data bus. The transistor 562 is connected to the data bus and operates as a clamping device that is controlled by a clamping control circuit 564 (as part of the system control logic 330). The transistor 562 is also connected to a sense amplifier 566, which includes a data latch 568. The output of the sense amplifier 566 is connected to the data output terminal (connected to the system control logic 330, the controller and/or the host). The write circuit 560 is also connected to the sense amplifier 566 and the data latch 568.

[0109] When trying to read the state of RSME, all word lines are first biased at Vread (for example, approximately 2V), and all bit lines are grounded. Then the selected word line is pulled to ground. For example, this discussion will assume that memory cell 550 is selected for reading. One or more selected bit lines 559 are pulled to Vread via the data bus (by turning on transistor 558) and the clamping device (transistor 562, which receives ~2V+Vth, Vth is the threshold voltage of transistor 562). The gate of the clamping device is above Vread, but is controlled to keep the bit line near Vread. In one method, the selected memory cell 550 pulls current from the sense node in the sense amplifier via the transistor 562. The sensing node can receive a reference current between the high-resistivity state current and the low-resistivity state current. The sensing node moves corresponding to the current difference between the cell current and the reference current. The sense amplifier 566 generates a data output signal by comparing the sensed voltage with a reference read voltage. If the memory cell current is greater than the reference current, the memory cell is in a low resistivity state, and the voltage at the sensing node will be lower than the reference voltage. If the memory cell current is less than the reference current, the memory cell will be in a high resistivity state, and the voltage at the sensing node will be higher than the reference voltage. The output data signal from the sense amplifier 566 is latched in the data latch 568.

[0110] Referring again to FIG. 4A, for example, in a high resistivity state, if a voltage vset and a sufficient current are applied,

Then RSL will be set to low resistivity state. Line 404 shows the behavior when Vset is applied. The voltage will remain somewhat constant, and the current will increase towards Iset_limit. At some point, the RSL will be set and the device behavior will be based on line 406. Note that when RSL is set for the first time, Vf (formation voltage) needs to be set for the device. After that, Vset is enough to set the device used. The formation voltage Vf can be greater than Vset in absolute value_o

[0111] In the low resistivity state (line 400), if Vreset and sufficient current (Ireset) are applied, the RSL will be reset to the high resistivity state. Line 400 shows the behavior when Vreset is applied. At some point, the RSL will be reset and the device behavior will be based on line 402.

[0112] In one embodiment, Vset is approximately 7V, Vreset is approximately 9V, Iset_limit is approximately 10 μA, and Ireset may be as low as 100 nA. These voltages or currents are applied to the current of Figure 5, which has RSME and diodes connected in series.

[0113] FIGS. 6A-6M may be cross-sectional views in a vertical or horizontal plane of, for example, RSME.

[0114] FIG. 6A depicts an example memory cell with an RSME and a manipulation element (SE) below the RSME. The memory unit can have various configurations. One configuration is a stacked configuration in which each type of material is provided in one layer, and each layer is located below the layer above it, and generally has a similar cross-sectional area. In another possible configuration, one or more layers can be arranged end-to-end with one or more other layers (see Figures 6F-6J).

[0115] Note that in the drawings, any two layers or materials that are depicted as being adjacent to each other may be in contact with each other. However, unless otherwise indicated, this is not required, and any two layers or materials depicted as being adjacent to each other may be separated by one or more layers of other materials not depicted. In addition, in some cases, the material may be formed as a by-product of manufacturing. For example, by-products such as SiOxo formed on the Si layer are not necessarily drawn in the drawings. In addition, variants of the described implementation are possible. For example, the order of the layers in each implementation can be reversed, for example so that the word line is at the top and the bit line is at the bottom. An intermediate layer can be provided between each layer drawn. Moreover, the position of the manipulation element can be changed so that it is located above or below other layers including the RSL. The orientation of the layers can be modified from vertical to horizontal or any other orientation. It is considered that multiple layers or parts that can form a common conductive path are connected in series.

[0116] The memory cell includes a bit line contact (BLC) material such as W or NiSi, which is connected to the bit line of the memory device. The bit line is a type of control line, so that the BLC is also in contact with the first control line. After the BLC in the serial path is a first adhesion layer (AL1) such as TiN, which helps the BLC to adhere to the RSME and acts as a barrier. The TiN layer can be deposited by any conventional method, such as sputtering. After the RSME in the serial path is a steering element (SE) such as a diode. The manipulation element allows signals such as voltage or current to be selectively applied to one or more memory cells via word lines and bit lines to individually control the cells to change the resistance switching behavior of their respective data states RSME through the switch RSME Independent of SE. SE can have its own resistance switching behavior, but this behavior will be independent of the resistance switching behavior of RSME.

[0117] After the SE in the serial path is a second adhesion layer (AL2) such as TiN. After AL2 in the serial path is a word line contact (WLC) material such as W or NiSi, which is connected to the word line of the memory device. The word line is a type of control line, so that the WLC is also in contact with the second control line. The depicted parts of the memory cells are therefore arranged in series.

[0118] FIG. 6B depicts an alternative configuration of a memory cell with RSME, where the steering element (SE) is above RSME.

The order of the other layers from top to bottom can also be reversed from top to bottom.

[0119] FIG. 6C depicts an example implementation of the RSME of FIG. 6A as a mirrored resistance switch (MRS) in a vertical stack. RSME includes: a first electrode (E1), which in some configurations is the top electrode; a first resistance switching layer (RSL1); and a conductive

Electric Intermediate Layer (IL), which acts as a divergent layer, a coupling electrode or a coupling layer. The RSME also includes a second RSL (RSL2) and a second electrode (EL2), which in some configurations is the bottom electrode. For example, RSL can be a reversible RSL. A reversible RSL can switch from one state to another and switch back to that one state. IL is electrically between E1 and E2 and in series with E1 and E2. RSL is electrically between E1 and IL and in series with E1 and IL. RSL2 is electrically between E2 and IL and in series with E2 and IL. "Electrically between" or similar can mean in a conductive path. For example, IL may be electrically between E1 and E2, physically or not physically between E1 and E2.

[0120] For example, the RSME can be formed by anti-serially connecting two bipolar memory resistors (memristor) (memory-resistor) elements into one mirrored resistance switch (MRS). A storage resistor is a passive two-terminal circuit component, where the resistance is a function of the resistance flowing through the device and the history of the voltage across the device. Such an MRS may be made of a first storage resistance element including: El such as n-type silicon; RSL1, which may be a transition such as zirconium dioxide (HfO2) or zirconium oxide silicon (HfSiON) Metal oxide; and IL, which may be an oxidizable electrode (such as TiN) that can undergo a chemical reaction with oxygen.

[0121] The RSME includes a second storage resistance element, which is made of the same (or different) material, but in the reverse order, sharing the oxidizable electrode of the IL. Furthermore, in one method, both the first and second storage resistance elements have bipolar or unipolar-V (current-voltage) characteristics. In another method, one of the storage resistance elements has unipolar characteristics, and the other storage resistance element has bipolar characteristics. By merging these two storage resistance elements into one RSME, the RSME has a -V characteristic that is a superposition of the -V characteristics of the composed storage resistance element, but has another benefit: it is much lower than that of a single storage resistance element. Current while operating.

[0122] More generally, the RSME will have an I-V characteristic that is a superposition of the I-V characteristic of the constituent RSL, but enables operation with low current.

[0123] IL acts as a divergent layer by diverging electrons entering from the RSL, thereby slowing down the flow of electrons that do not contribute to the switching mechanism, so as to avoid damage to the operating element. In addition, IL acts as a coupling electrode or coupling layer by setting the potentials of E1 and E2, and its capacitance is coupled to the voltage applied to RSME.

[0124] Through such divergence, the IL provides a resistance that reduces the peak current during the set or reset process while achieving low current operation. The current limiting operation is believed to originate from two aspects of the IL layer. First, through electron-electron interaction, hot electrons radiate very well in the IL layer. Second, as soon as one of the RSL begins to break down and transfer the excess charge Q to IL, it effectively reduces the voltage applied to the RSL through V = Q/C, where C is the capacitance of the IL layer towards the electrodes E1 and E2 . At the same time, the higher voltage is now at the second RSL, which induces the breakdown of the second RSL. Because the amount of charge Q available is limited, the current that can flow here is also very limited. In this way, this RSME enables the memory cell to be operated with low current. The resistance is believed to be based on the IL's ability to dissipate electrons and give very effective negative feedback to the applied bias voltage, resulting in the formation of small conductive filaments that allow switching to occur at low currents. Without IL, when a voltage is applied, a filament with a very low resistance will be formed, resulting in a high current peak in the memory cell (due to the relationship I=V/R), and the required switching current will also be very high.

[0125] RSME has a mirrored configuration with respect to IL because the sequence of RSL and electrodes extends on either side of IL. The mirror configuration can also use the same material for the RSL and the electrode. The combination of El, RSL1, and IL forms a first storage resistance (memory-resistor) element, and the combination of E2.RSL2 and IL forms a second storage resistance element. The two storage resistance elements can be bipolar storage resistance elements, which are connected in anti-serial or serial connection as a mirrored resistance switch (MRS). [0126] In use, when a voltage is applied across E1 and E2, an electric field (E) is generated, which is a voltage divided by the distance between E1 and E2. IL can float, which means it is not directly driven by voltage/current signals, but can be capacitive

Coupled to one or more other electrodes (such as El and/or E2) directly driven by voltage/current signals. Due to capacitive coupling, part of the voltage between E1 and E2 will be applied from E1 to the coupling layer and across RSL1, and another part of the voltage between E1 and E2 will be applied from the coupling layer to E2 and across RSL. The voltage across each RSL is divided in proportion to the resistance of each RSL.

[0127] In addition, the first storage resistor may have a first 1-V characteristic, and the second storage resistor may have a second 1-V characteristic, so that the overall 1-V characteristic of the memory cell is the first and second The superposition of the i-v characteristics of the storage resistor, but has an additional benefit: it operates at a much lower current than the storage resistance element alone. In one approach, the I-v characteristics of the first and second storage resistors are different, but have the same polarity. In another method, the I-V characteristics of the first and second storage resistors have opposite polarities. The previously discussed Figures 4A-4E provide example I-V characteristics of RSL.

[0128] The elements of RSME can be provided in many possible configurations, which are described in further detail below. Example materials for E1 include n+Si (polysilicon), p+Si (polysilicon), TiN, TiSix, TiAlN, TiAl, W, WN, WSix, Co, CoSi, p+Si, Ni, and NiSio. For RSL1 and RSL2 Example materials include metal materials such as MeOx and MeN. However, non-metallic materials can also be used, as discussed in some embodiments herein. RSL1 and RSL2 can be the same type or different types. The RSL can also be a phase change unit, a carbon-based, carbon nanotube-based, nano-ion memory, a conductive bridge, or a unit that changes its phase, rotation, magnetic component, etc. The RSL may have an on-resistance (conduction state resistance) in the MQ range, for example, 1-10 MΩ or more. This is in contrast to a programmable metallization cell (PMC) such as conductive bridge RAM or CBRAM, which forms quantum point contacts and has a much lower resistance of about 25KQ or lower. Higher resistance provides low current operation and better scalability.

[0129] Example materials for E2 include n+Si, n+SiC, p+SiC, and p+Si (polysilicon), TiN, TiAlN, TiAl, W, WN, Co, CoSi, p+Si, Ni, and NiSi. A specific combination of materials in the different layers can be advantageous. The various configurations are discussed in further detail below.

[0130] Example materials for IL include TiN, TiN, Al, Zr, La, Y, Ti, TiAlN, TixNy, TiAl alloy, and p+SiCo. Therefore, IL can be made of oxidizable materials such as TiN, Al, Zr, La , Y, Ti) or non-oxidizable materials (such as TiAlN, TixNy, TiAl alloys and carbon, including, for example, graphene, amorphous carbon, carbon nanotubes, carbon with different crystal structures, and p+SiC). Generally, the same material of El and E2 can be used for the IL layer. In some cases, one or more oxide layers are formed intentionally or unintentionally as a by-product of the deposition and formation steps. For example, Si can be oxidized by depositing MeOx on top of Si. Even TiN or other suggested metals may be oxidized by providing MeOx deposition on one side, and may be oxidized at the interface by the interface reaction of MeOx and TiN.

[0131] As mentioned, E1, E2, and IL are made of conductive materials. Conductive materials can be determined by their conductivity. =Ι/p or its reciprocal to characterize, the reciprocal is the resistivity P =E/J_OThe conductivity is measured in Siemens per meter (S/m), and the resistivity is measured in ohm-meter (Qm) or Q-cm. E is the magnitude of the electric field in V/m, and J is the magnitude of the current density in A/m2. For insulators, P >108 Ω-cm or σ <10-8S/cm_oFor semiconductors, 10-3 Ω-cm< P <108 Ω-cm or 103S/cm>o >10-8S/cm_oFor conductor, 10-3 Ω -cm> P or 103S/cm< σ _οSemiconductors can be distinguished from conductors in that semiconductors are usually formed by doping insulators into p-type or n-type semiconductors, and conductors do not depend on doping. Semiconductors can also be distinguished from conductors in that semiconductors allow current to flow based on the polarity of the applied voltage, so that current can flow strongly in one direction but not in the opposite direction. The direction in which a semiconductor allows forward current to flow depends on whether it is a p-type or n-type semiconductor. On the contrary, conductors allow current to flow well and equally in either direction. Conductive materials are intended to include semiconductors (semiconductor materials) and conductors. Conductors can also be referred to as conductive materials. Conductors have higher conductivity than semiconductors.

[0132] Note that RSME does not rely on high band gap triple stacking (relatively high band gap material between layers of relatively low band gap material), because IL is a conductive material that can receive a coupling voltage.

[0133] FIG. 6D depicts an example implementation of the RSME of FIG. 6A using multiple ILs of different types between RSLs. Use multiple adjacent intermediate layers, including a first IL of type "1" (IL1) and a second IL of type "2" (IL2). The advantage of this embodiment is that the IL can be of different types, with different divergence properties and work functions, to provide additional capabilities to tailor the performance of the RSME. In addition, using multiple ILs of the same or different types can increase the divergence/resistance in the path, thereby reducing the current, because I = V/R. Multiple adjacent ILs can increase divergence, as a thicker single IL can. However, the scaling challenge brought by the thicker IL is that if the stack height increases, the aspect ratio of the pillar etch increases. As a result, manufacturing processes such as etching, cleaning, and gap filling become very challenging. It may be preferable to have two (or more) adjacent (or non-adjacent) thinner ILs (or similar or dissimilar properties/materials) rather than one thicker IL. For example, two 5nm thick ILs can provide divergence comparable to a single thicker IL, such as 20nm.

[0134] IL1 and IL2 may be, for example, different materials having different resistivities and crystal structures. They can also be the same material, but can have different crystal structures or orientations or different particle sizes, which will dissipate charge carriers differently. As another example, one IL may be composed of fine grained materials or nanoparticles (which may be the same or different from another IL).

[0135] If RSL1 and RSL2 are different materials, and IL1 and IL2 are different materials and/or material types, the optimal arrangement of IL relative to RSL will be material dependent.

[0136] One possible implementation uses a pn junction, IL1 is n+Si, and IL2 is p+Si. Each of IL1 and IL2 may have a thickness of, for example, at least 20 nm. Another possible combination uses a metal such as TiN for one of the ILs and n+ or p+Si for the other IL. For example, see Figure 10C.

[0137] FIG. 6E depicts an example implementation of the RSME of FIG. 6A using repeated RSL/IL patterns. The pattern or combination of RSL and IL is repeated at least twice. For example, provide RSL1 and the first IL (IL1), in addition to providing RSL2 and the second IL (IL2)_OThe third RSL (RSL3) is adjacent to E2. RSL can be the same or different types, and IL can be the same or different types. The advantage of this embodiment is that multiple divergent layers can increase the amount of divergence/resistance in the path of the RSME. In addition, the ability to use different types of IL and RSL provides additional capabilities to tailor the performance of the RSME.

[0138] It is possible that three RSLs have multiple characteristics (all the same, two the same and one different, all different, etc.). Using more than one IL with a dissimilar RSL will change the characteristics of the RSME and provide additional functions to adjust its performance.

[0139] When a voltage is applied across the RSME, the voltage is divided across each RSL according to the resistance of each RSL. In a possible implementation, two RSLs have the same I-V characteristic, and the other RSL has a different I-V characteristic, so that, for example, when the other RSL is in a high resistance state, both RSLs are at a low level. Resistance state, or when another RSL is in a low resistance state, both of the two RSLs are in a high resistance state. Other variations are possible.

[0140] FIG. 6F depicts an example implementation of the RSME of FIG. 6A, where each layer of the RSME extends horizontally, and one or more layers are arranged end to end. Instead of a fully stacked (vertical) configuration, parts of the RSME are arranged laterally (on its sides) or end to end with the other parts of the RSME. For example, El, RSL1, and IL are in one stack, while RSL2 and E2 are in another stack, and RSL2 and IL are arranged side by side. Referring to Figure 6A, BLC and AL1 can be provided above E1, and SE, AL2 and WLC can be provided below IL. In one possible method, a non-conductive (NC) layer can be provided below IL and arranged side by side with E2. The parts/layers of RSME are still arranged in series. In another possible implementation, E2 is on one side of RSL2 instead of below it, so that the three parts (IL, RSL2, and E2) are connected end to end

GroundLayout. Other variations are possible. Having parts of the RSME extend end to end or otherwise extend laterally provides an additional ability to trim the layout of the RSME. For example, the height of RSME can be reduced. In one method, BLC and AL1 can be provided above E1, and SE, AL2, and WLC can be provided below E2.

[0141] FIG. 6G depicts another example implementation of the RSME of FIG. 6A, in which each layer of the RSME extends horizontally and one or more layers are arranged end to end. RSL2.IL and RSL2 are in one stack, while E2, non-conductive layer (NC) and E2 are in another adjacent stack. E1 is arranged end to end on the side of RSL1, and E2 is arranged end to end on the side of RSL2. It can still be considered that these parts are arranged serially in a serial path of E1, RSL1, IL, RSL2, E2, for example. In another option, for example, E1 and RSL extend laterally and above the RSL, and E2 and RSL extend laterally and below the RSL. In one method, BLC and AL1 can be provided above E1, and SE, SL2, and WLC can be provided below E2.

[0142] Generally, it can be considered that at least one of E1, E2, IL, RSL1, and RSL2 may be at least partially associated with E1, E2, IL,

At least one of RSL1 and RSL2 is arranged laterally.

[0143] In FIGS. 6F and 6G, the horizontal arrangement is connected end to end. For example, RSL1 and E1 are arranged end to end laterally, and/or RSL2 and E2 are arranged end to end laterally. Moreover, the IL and at least one of RSL1 and RSL2 are laterally arranged end to end.

[0144] FIG. 6H depicts another example implementation of the RSME of FIG. 6A, where each layer of the RSME extends vertically. Parts of RSME and other parts of RSME are arranged laterally or face to face. For example, BLC can be above, below, or at E1 and WLC above, below, or at E2. BLC and WLC are in a path in series with RSME. Manufacturing may involve n repeated cycles of layer deposition and layer spacer etching, with a final CMP step. For example, the E1 layer can be deposited as a horizontally extending layer and then etched to form the vertically extending portion as shown. The RSL1 layer can then be deposited as a horizontally extending layer and then etched to form the vertically extending part as shown. This is repeated for each part of IL.RSL2 and E2. In one method, AL1 and BLC (FIG. 6A) extend vertically upward from E1, and SE, AL2, and WLC extend vertically downward from E2.

[0145] Two or more of the layers may be arranged laterally face-to-face with each other. For example, RSL1, IL, and RSL2 may each be arranged laterally facing each other. Also, El, RSL1, IL, RSL2, and E2 may each be arranged laterally facing each other.

[0146] Compared with the L-shaped cross-section of FIG. 61 and the U-shaped cross-section of FIG. 6J, for example, the RSME portion of FIGS. 6D-6H has a rectangular cross-section.

[0147] FIG. 61 depicts another example implementation of the RSME of FIG. 6A, which includes L-shaped portions for RSL1, IL, RSL2, and E2. For example, suppose that the cross-sectional view is in a plane perpendicular or horizontal to the vertical axes X and y. In the X direction, E1 has a thickness tlx, RSL1 has a thickness t2x, IL has a thickness t3x, RSL2 has a thickness t4x, and E2 has a thickness t5x. In the y direction, E1 has a thickness tly, RSL1 has a thickness t2y, IL has a thickness t3y, RSL2 has a thickness t4y, and E2 has a thickness t5y. For each part, the x-direction thickness can be the same or different from the corresponding y-direction thickness. The order of the layers can be reversed so that they extend in the order E2, RSL2, IL, RSL1, and E1 instead of El, RSL1, IL, RSL2, and E2. For example, the BLC can be above, below, or on the E1 side, and the WLC can be above, below, or on the E2 side. BLC and WLC are in a serial path with RSME. By providing the L-shaped portion, it is possible to form a conductive filament in the setting process of the RSME, in which the filament extends in the X direction and the y direction. Because there is a relatively large area on which the filament extends, its creation is potentially facilitated. The depicted implementation can also be rotated 90 degrees or 180 degrees.

[0148] In this method, the parts of the layers are arranged laterally to each other, similar to the concept of FIGS. 6F-6H, but the layers are nested

The L shape has two parts extending at right angles to each other. For example, the L-shaped RSL2 is nested in the L-shaped E2, the L-shaped IL is nested in the L-shaped RSL2, and the L-shaped RSL1 is nested in the L-shaped IL. E1 is nested inside L-shaped RSL1 but in this example it is not L-shaped itself. In one or more dimensions, each part can be the same or different.

[0149] Here, it can be considered that at least one of E1, E2, IL, RSL1, and RSL2 is at least partially arranged laterally with at least one of E1, E2, IL, RSL1, and RSL2.

[0150] FIG. 6J depicts another example implementation of the RSME of FIG. 6A, which includes U-shaped portions of RSL1, IL, RSL2, and E2. For example, suppose the cross-sectional view is in a plane perpendicular or horizontal to the vertical axes X and y. In the X direction, E1 has thickness tlx, RSL1 has thicknesses t2xa and t2xb, IL has thicknesses t3xa and t3xb, RSL2 has thicknesses t4xa and t4xb, and E2 has thicknesses t5xa and t5xb. In the y direction, E1 has a thickness tly, RSL1 has a thickness t2y, IL has a thickness t3y, RSL2 has a thickness t4y, and E2 has a thickness t5y. The thickness of xa may be the same as or different from the corresponding thickness of xb. Moreover, the xy thickness may be the same as or different from the corresponding xa and/or xb thickness. The order of the layers can be reversed so that they extend in the order E2, RSL2, IL, RSL1, and E1 instead of El, RSL1, IL, RSL2, and E2. For example, the BLC can be above, below, or on the E1 side, and the WLC can be above, below, or on the E2 side. BLC and WLC are in a serial path with RSME. By providing the U-shaped portion, a conductive filament can be formed in the setting process of the RSME, where the filament extends in the X direction and in the y direction on either side of E1. The depicted implementation can also be rotated 90 degrees or 180 degrees.

[0151] In this method, portions of the layer are arranged laterally to each other, similar to the concept of FIG. 6F-6H, the layer is a nested U-shaped, having a right angle to the parallel portions of the base portion and extending therefrom. For example, U-shaped RSL2 is nested in U-shaped E2, U-shaped IL is nested in U-shaped RSL2, and U-shaped RSL1 is nested in U-shaped IL. E1 is nested within U-shaped RSL1 but in this example it is not U-shaped itself. In one or more dimensions, each part can be the same or different.

[0152] In general, any vertical stacking embodiment may be suitable for an L-shaped or U-shaped embodiment.

[0153] Here, it can be considered that at least one of E1, E2, IL, RSL1, and RSL2 is at least partially arranged laterally with at least one of E1, E2, IL, RSL1, and RSL2.

[0154] FIG. 6K1 depicts an example implementation of the RSME of FIG. 6A, which uses an RSL and a breakdown layer below the RSL. Use RSL1 as previously discussed, but use a breakdown layer between IL and E2 instead of RSL2. The breakdown layer is a material that does not have resistance switching behavior, and a baffle layer can be provided between IL and E2. Only materials with resistance switching behavior can switch repeatedly between the start and end resistance states. In contrast, a breakdown material is a material that has been broken down from an initial state with an associated -V characteristic to a breakdown state with another associated -V characteristic by applying a relatively high voltage and/or current, and Usually, the transition from the initial state to the breakdown state can only be done once. Resistance-switching materials can be considered as multi-time programmable materials, and breakdown materials can be considered as one-time programmable materials. Here, programmable may include the ability to change the resistance state. Although the resistance-switching material can be paired with a fuse or an anti-fuse to form a one-time programmable, the resistance-switching material itself is still multi-time programmable. One-time programmable materials are useful in, for example, setting a unique identifier of a chip or setting operating parameters such as clock or voltage parameters.

[0155] Example materials used for the breakdown layer (and the associated range of resistivity P in the initial state before breakdown for some examples) include: SiN (for S13N4 at 25C, P = 1014 Ω-cm ), Si02 (at 25C, Ρ = 1014-1016 Ω -cm), SiC (Ρ = 102-106 Ω -cm), SiCN, SiON or can be broken down, such as from a relatively non-conductive state of higher resistance Any layer that changes to a conductive state of lower resistance, but is not generally referred to as the reversible resistance-switching material itself. The breakdown layer may be a material that maintains a resistance of at least about 1-10 ΜΩ while conducting electricity in the breakdown state.

material. The resistance in the initial state is usually one or several orders of magnitude higher than the value in the breakdown state. If the resistance of the layer is too low, it is less effective as a protective layer. The resistance of the breakdown layer material is R=ρ ι/A, where 1 is the length of the material and A is the cross-sectional area. The length is the thickness of the breakdown layer. Knowing P and R, you can use A and 1 to select the size of the material.

[0156] The breakdown layer may be a one-time programmable breakdown layer. Such a breakdown layer can be considered as a non-switchable breakdown layer or a one-time switchable breakdown layer, because the breakdown process is irreversible. That is, once the breakdown layer is broken down from the initial non-conductive state, the breakdown layer remains in the breakdown state and cannot return to the starting state. In contrast, in some cases, a unipolar or bipolar unit can operate in a one-time programmable mode, but usually does not physically break down, while maintaining a resistance of at least about 1-10 MΩ when conducting.

[0157] One or more RSLs may be configured in a breakdown state, such as by applying a relatively high voltage or current to the RSL. For example, the applied voltage can be significantly higher than the threshold voltage of the material. The breakdown process may be partly due to thermal effects. Further details are shown in Figure 6K2 and 6K3o

[0158] FIG. 6K2 is a diagram showing the transition of the breakdown layer from the initial state to the breakdown state. This transition can be achieved by applying a current or voltage across the breakdown layer for an extendable period of time, such as a few minutes. At time tb, when a breakdown event occurs, the current through the breakdown layer increases in the step size (because the resistance decreases in the step size). In some cases, multiple breakdown events can occur. For the applied voltage, the voltage applied across RSME will be divided across the breakdown layer and RSL1 in proportion to their respective resistances. RSL1 can be configured in a low resistance state so that substantially all voltage is applied across the breakdown layer.

[0159] FIG. 6K3 is a graph showing the I-V characteristics of the breakdown layer in the initial state (solid line) and the breakdown state (dashed line). For a given voltage, the current is higher (and the resistance is lower) in the breakdown state. The RSME in which the breakdown layer is in the initial state can be distinguished from the RSME in which the breakdown layer is in the breakdown state, so that data bits can be stored according to the state of the breakdown layer. RSL can be further adjusted between the two states to store data bits. By applying an appropriate read voltage, the state of the breakdown layer and RSL can be determined.

[0160] FIG. 6L depicts an example implementation of the RSME of FIG. 6A, which uses a reversible RSL (RSL1) and a breakdown RSL above the RSL1. This is an alternative to the configuration of Figure 6K1.

[0161] FIG. 6M depicts an example implementation of the RSME of FIG. 6A, where the resistance switching layer (RSL) is of a different type. RSL1 and RSL2 can be made of different types of materials with different switching characteristics, for example to allow more than one data bit to be stored through RSME. Example materials for RSL1 and RSL2 include: Ti02, NiOx, HfSiON, HfOx, Zr02, and ZrSiONo

[0162] FIG. 7A depicts an example implementation of a manipulation element (SE) of the memory cell of FIG. 6A as a Si diode. Se is a Si diode with an n-type region, an intrinsic (i) region, and a p-type region. As mentioned, Se selectively limits the voltage across RSME and/or the current flowing through RSME. SE allows writing to and/or reading from a memory cell without affecting the state of other memory cells in the array.

[0163] FIG. 7B depicts an example implementation of the steering element (SE) of the memory cell of FIG. 6A as a punch-through diode. The punch-through diode includes an n+ area, a p-area, and an n+ area. The punch-through diode can be operated in both directions. Specifically, the punch-through diode allows bipolar operation of the cross-point memory array and can have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at a high bias voltage for selected cells, and a low leakage current at a low bias voltage for unselected cells. Therefore, it can be compatible with bipolar switching in a cross-point memory array with resistance switching elements. Punch-through diodes can be n+/p-/n+ devices or p+/n-/p+ devices.

[0164] Although example implementations involving memory cells with diodes are provided, the techniques provided herein are generally applicable to other devices and manipulation elements, including transistors, punch-through transistors, punch-through diodes, PN diodes, NP diodes, and PIN diodes. , Zener diode, NPN diode, PNP diode, Schottky diode, carbon silicon diode, transistor layout, etc.

[0165] In another method, the steering element may be a transistor such as a bipolar or CMOS transistor.

[0166] In addition, in some configurations, it is not necessary to use a manipulation element.

[0167] FIG. 8 depicts an example implementation of the memory cell of FIG. 6A connected between a bit line and a word line. The bit line contact (BLC) is W or NiSi, the first adhesion layer (AL1) is TiN, the first electrode (E1) is n+Si, RSL is MeOx, such as HfO2, IL is TiN, RSL2 is MeOx, such as HfO2 , Provide an additional adhesion layer (AL) for the Si diode as the operating element (SE), the second adhesion layer (A) is TiN, the word line contact (WLC) is W or NiSi. In addition, the following can be used The material selected in the group provides one or more cover layers: Ti0x, A1203, Zr0x, La0x, and YOx. Generally, the cover layer can be a metal oxide. In this example, the cover layer is adjacent to IL and RSL, specifically , One capping layer (Capl) is between RSL1 and IL and adjacent to each of RSL1 and IL, and the other capping layer (Cap2) is between IL and RSL2 and adjacent to each of IL and RSL2. From From the perspective of MeOx, the cover layer can be used as a source or getter of oxygen, which facilitates switching in RSL. When acting as a taker of oxygen, for example, the cover layer can help provide the IL/electrode from the MeOx RSL Oxygen. When acting as a source of oxygen, for example, the cover layer can help provide the MeOx RSL from the IL/electrode oxygen. Gettering is a process in which a material such as oxygen moves to the position of the getter. The taker position is an alternate position where oxygen will preferably be present because it is in a lower energy state.

[0168] RSME is composed of layers extending from E1 to E2. In an example implementation, E1 and E2 each have a thickness or height of, for example, about 1-3 nm or about 1-10 nm, and IL may have a thickness or height of, for example, about 1-5 nm or about 1-10 nm. Therefore, the overall thickness of RSME can be very small.

[0169] FIG. 9A depicts an embodiment of the RSME of FIG. 6C, where E1 is made of Co, CoSi, n+Si, p+Si, or p+SiC, and E2 is made of n+Si. The order of the layers from top to bottom is: El, RSL1, Cap1, IL, Cap2, RSL2, E2. The RSME also includes RSL1 such as MeOx, IL such as TiN, RSL2 such as MeOx, and a second electrode (E2) such as n+Si. In addition, a cover layer such as TiOx is provided between RSL1 and IL (Cap1) and between IL and RSL2 (Cap2). When E1 and E2 are made of different materials, this embodiment can provide an asymmetric structure. For example, E1 made of cobalt (Co) is desirable because it has a relatively high work function of about -5 eV, which is close to the work function of Ni, and can be better switched. This is due to the higher barrier height, which can be used as a benefit of having a high work function. In another method, E1 made of drilled silicon is also desirable because it also has a relatively high work function. In another method, E1 is made of n+Si (polysilicon), which provides the benefits of high work function (approximately 4.1 to 4.15 eV) and oxidation resistance. Other suitable materials include p+Si (polysilicon) with a high work function of about 5.1 to 5.2 eV and about 6.6 to 6.6 due to the high energy gap. Very high work function p+ silicon carbide (SiC) of 9eV. These energy gaps are significantly higher than the energy gap of Si, for example, the energy gap of Si is about 1. leVo

[0170] In one embodiment, for example, P+SiC can be deposited by ion implantation, by dopants such as B, Al, Be, or Ga, and then doped to a concentration of about 10E19 to 1J 10E20 atoms per cubic centimeter . This is an example of in-situ doping. SiC is chemically inert and therefore resistant to oxidation. Due to the sublimation temperature of 2700C, it does not actually melt, and has a high thermal conductivity of 3.6 to 4.9W/(cm*K) (compared to Sis 1.49W/(cm*K)), due to high current Density, which is beneficial for memory cell operation.

[0171] FIG. 9B depicts an embodiment of the RSME of FIG. 6C, where E1 and IL are made of p+SiC, and E2 is made of n+Si,

Made of n+SiC or p+SiC. The order of the layers from top to bottom is: El (e.g. p+SiC), RSL1, IL (e.g. p+SiC), RSL2, E2o. The high work function of El and IL can contribute to the cell current reduction, where IL is used as Divergent layer. In addition, by adjusting the doping of IL, the layer resistance can be adjusted to increase the divergence and reduce the current. With the increased doping, the IL resistance is smaller, making the depletion layer have a smaller depletion width and a smaller voltage drop.

[0172] In addition, E2 may be made of n+Si, n+SiC, or p+SiC. When E2 is made of n+SiC, there is a thinner SiO 2 layer formed between E2 and RSL2 during manufacturing. In contrast, in the case of an n+Si bottom electrode, a thicker SiO 2 layer can be formed between E2 and RSL2. As an alternative to n+SiC, E2 can be made of p+SiC. For example, RSL1 and RSL2 can be MeOxo

[0173] In one method, the IL may be made of nanoparticles, such as by providing the IL as a nanocrystalline SiC film.

For example, see W. Yu et al. discussed below.

[0174] FIG. 9C is a graph plotting the Fermi levels of p+SiC relative to other materials. As mentioned above, p+SiC has a very high work function of about 6.6 to 6.9 eV due to the high energy gap. To illustrate this real-time, an energy diagram for 4H-SiC is provided, which plots the energy level in vacuum, the energy level of the conductance band (Ec), the intrinsic energy level (Ei), and the valence band (valence). band) Energy level (Εν). This figure is from T. Ayalew, Dissertation's SiC Semiconductor Devices Technology, Modeling And Simulation, Institute for Microelectronics, Vienna, Austria, January 2004, incorporated here by reference. Other examples of materials and their Fermi levels are also drawn: Al (4.28eV), Ti, Zn (4.33eV), W (4.55eV), Mo (4.60eV), Cu (4.65eV) ), Ni (5.1OeV), Au (5.15eV) and Pt (5.65eV). As mentioned, p+SiC has a relatively high work function. Specifically, the Fermi level will be close to the valence band level.

[0175] In practice, undoped SiC has a work function of about 4.5-4. 8 eV, or about 4.9 eV if covered with oxygen. However, for p+SiC, the Fermi level will be closer to the valence band, making the work function higher. Depends on the level of P+ doping and the type of SiC polymerization (for 4H-S1C energy band gap Eg = 3.23-3.26eV, or for 6H-S1C, Eg = 3.05eV), as shown, the work function q Μ It can be about 6. 6-6. 9 eV.

[0176] Various techniques for relatively low temperature deposition are available for SiCo to be applied by deposition when the appropriate temperature is not too high. For example, in I. Golecki et al., which is incorporated herein by reference^uSingle-crystalline, epitaxial cubic SiC films grown on (100) Si at 750°C by chemical vapor deposition, Applied Physics Letter, vol. 60, No. 14, pages 1703-1705, described in April 1992 at 750°C Of deposition. In this method, methylsilane (SiCH3H3), a single precursor with a Si:C ratio of 1:1, and H2 are used to grow a SiC film by low-pressure chemical vapor deposition.

[0177] In another example method, molecular beam epitaxy has been used to deposit SiC at low temperature, such as in Low-temperature growth of SiC thin films on Si and 6H~Sic by A. Fissel et al., which is incorporated herein by reference. Solid-source molecular beam epitaxy, Applied Physics Letter, vol. 66, No. 23, pages 3182-3184, described in June 1995. This method involves the use of a solid-state source molecular beam epitaxy controlled by a quadrupole mass spectrometer-based magnetic flux meter at about 800-1000 Ό in Si (111) and 2° -5° off-oriented 6H-S1C( 0001) Stoichiometric epitaxial growth of SiC on a substrate. Obtain a film on a stable surface of Si, showing (3x3) and (2x2) superstructures in the case of SiC (OOOl)_oThe Reflected High Energy Diffraction (RHEED) pattern and damped RHRRF-oscillation during T>900Ό growth on 6H-SiC (0001) indicate that stepped two-dimensional nucleation is the dominant growth process.

[0178] Another example of a low temperature method for depositing SiC is described in W. Yu et al. "Low

Temperature deposition of hydrogenated nanocrystalline SiC films by helicon wave plasma enhanced chemical vapor deposition, J. Vac. Sci. Technol. A28 (5), American Vacuum Society, pages 1234-1239, described in September 3, 2010. Here, a hydrogenated nanocrystalline silicon carbon (nc-SiC:Η) film was deposited by using spiral wave plasma enhanced chemical vapor deposition at a low substrate temperature. The effects of radio frequency (rf) power and substrate temperature on the properties of the deposited nc-SiC:H film were studied. It was found that the hydrogenated amorphous SiC film was manufactured with low rf power, while the nc-SiC:H film with the microstructure of SiC nanocrystals embedded in the amorphous counterpart can be deposited when the rf power is 400W or more. The plasma transition from capacitor-dominated discharge to spiral wave discharge with high plasma density affects the microstructure and surface morphology of the film. Analysis of films deposited at various substrate temperatures revealed that the onset of SiC crystallization occurred at substrate temperatures as low as 150°C.

[0179] FIG. 10A depicts an embodiment of the RSME of FIG. 6C, depicting an alternative IL material. The order of the layers from top to bottom is: E1 (e.g. TiN), El (e.g. n+Si), RSL1 (e.g. MeOx), capl (e.g. TiOx), IL (e.g. TiN), cap2 (e.g. TiOx), RSL2 ( For example, MeOx), E2 (for example, n+Si). In one implementation, El includes a combination of TiN layers on top of the n+Si layer. In addition, a cover layer such as TiOx is provided between RSL1 and IL and between IL and RSL2. Further Ti contacts (not shown) can be above E1. Alternatively, IL can be selected from the group consisting of Al, Zr, La, Y, Ti, TiAlN, TixNy, and TiAl alloys. These are popular coupling layers that can enable lower V and I unit operations. This embodiment provides a mirror image structure with respect to IL because the cover layer, RSL, and electrode extend from both sides of the IL in the same order and optionally have the same material (for example, the same cover layer material above and below the IL). , Such as TiOx, followed by the same RSL material above and below IL, such as MeOx, followed by the same electrode material above and below IL, such as n+Si).

[0180] FIG. 10B depicts an embodiment of the RSME of FIG. 6C in an inverted mirror stack configuration. The order of the layers from top to bottom is: E1 (such as TiN), capl (such as TiOx), RSL1 (such as MeOx), IL (such as n+Si), RSL2 (such as MeOx), cap2 (such as TiOx), E2 ( For example TiN). In one method, El is made of TiN, IL is made of n+Si, and E2 is made of TiN. The IL layer may be, for example, n+Si having a thickness of 10-100 nm. This embodiment is an inverted mirror configuration, which provides an inverted stack relative to the embodiment of FIG. 10A, because the n+Si layer is now IL instead of the E1 or E2 layer, and the cover layer is between the RSL and the electrode layer. (Capl is between RSL1 and E1; cap2 is between RSL2 and E2) rather than between RSL and IL. Specifically, the RSL, the cover layer, and the electrode extend from both sides of the IL in the same order and optionally have the same material (for example, the same RSL material above and below IL, such as MeOx, followed by above and below IL The same cover layer material, such as TiOx, followed by the same electrode material above and below IL, such as TiN).

[0181] FIG. 10C depicts an embodiment of the RSME of FIG. 6C in an asymmetric vertical stack configuration. The order of the layers from top to bottom is: E1 (e.g. TiN). capl (e.g. TiOx), RSL1 (e.g. MeOx), IL (e.g. n+Si), IL (e.g. TiN), cap2 (e.g. TiOx), RSL2( For example, MeOx), E2 (for example, n+Si). In one approach, IL is a combination of n+Si layers (eg, 10-100 nm thickness) above the TiN layer. A cover layer such as TiOx is provided above and adjacent to the MeOx layer. For example, capl is above and adjacent to RSL1, and cap2 is above and adjacent to RSL2. The configuration is asymmetrical and is a vertical stack, with all layers arranged vertically. Do not use mirror configuration. This configuration is asymmetric because the layer extending above IL (n+Si) includes RSL1 followed by capl, and the layer extending below IL (TiN) includes cap2 followed by RSL2. This configuration is vertical because capl is above RSL1 , And cap2 is above RSL2.

[0182] FIG. 10D depicts an embodiment of the RSME of FIG. 6A in an asymmetric inverted stack configuration. From top to bottom

The order of the layers is: E1 (such as TiN), E1 (such as n+Si), RSL1 (such as MeOx), capl (such as TiOx), IL (such as TiN), IL (such as n+Si), RSL2 (such as MeOx) , Cap2 (such as TiOx), E2 (such as TiN). Do not use mirror configuration. This configuration is asymmetric, because above IL, cap is followed by RSL, but below IL, RSL is followed by cap. This configuration is reversed with respect to the embodiment of FIG. 10C because the n+Si layer is now The E1 layer is not the E2 layer, and the TiN layer is now the E2 layer instead of the lower E1 layer. The IL layer may be, for example, a combination of n+Si having a thickness of 10-100 nm and TiN in a manner opposite to that of FIG. 10C.

[0183] Other embodiments of IL use one or more metals such as metals selected from the group consisting of TiAlN, WN, W, NiSi, CoSi, and C.

[0184] FIG. 11A depicts the embodiment of the RSME of FIG. 6C, showing the growth of SiOx when E2 is n+Si. The order of the layers from top to bottom is: E1 (such as n+Si), RSL1 (such as MeOx), capl (such as TiOx), IL (such as TiN), cap2 (such as TiOx), RSL2 (such as MeOx) SiOx, E2 (For example, n+Si). When E2 is made of Si and RSL2 includes a metal oxide, there may be a large change in the formation voltage in RSL due to the change in the thickness of the SiOx layer formed between RSL2 and E2. For example, when RSL2 is a metal oxide and is directly deposited on E2 including n+Si, the top part of the n+Si layer is oxidized to obtain an SiOx layer. In an example implementation, a 1-2nm layer of SiOx may be formed between RSL2 and E2, where RSL is each made of 2-4nm MeOx such as HfO2, and E2 is made of n+Si. Alternatively, E1 and/or E2 may be made of p+Si, nitrided duck (eg WN, WN2, N2W3), TiN or SiGe.

[0185] FIG. 11B depicts an embodiment of the RSME of FIG. 6C, showing the growth of a low band gap material such as TiOx when E2 is TiN. The order of the layers from top to bottom is: E1 (e.g. n+Si), RSL1 (e.g. MeOx), capl (e.g. TiOx), IL (e.g. TiN), cap2 (e.g. TiOx), RSL2 (e.g. MeOx), Ti/ TiOx, E2 (such as TiN). In order to prevent the formation of SiOx, a material such as Ti deposited on the TiN electrode can be used instead of the n+Si layer. The Ti layer can be considered as part of the electrode. Specifically, during the deposition of a MeOx layer (RSL2) such as HfOx above the Ti layer, the top portion of the Ti layer (~1-5 nm) is oxidized and converted into a layer of TiOx. The thickness of the TiOx layer depends on the temperature of MeOx deposition. In this case, the second electrode (E2) includes MeOx, and a layer of TiOx is formed on the Ti layer and is in contact with the second resistance switching layer.

[0186] The band gap of Ti/TiOx is much lower than that of SiOx, so a large change in the formation voltage can be avoided. E1 may be n+Si or a high work function material such as Ni or NiSi. In an example implementation, the RSLs are each made of 2-4 nm MeOx such as HfO2.

[0187] In addition, a high work function material can be used for E1 to reduce the operating current. For example, Ni having a work function of 5. leV can be used. NiSi is another alternative. In comparison, the work function of TiN is about 4. 2-4. 7eV, and the work function of n+Si is about 4. 1-4. 3eVo

[0188] FIG. 11C depicts an embodiment of the RSME of FIG. 6C, where the RSL is made of doped metal oxide to reduce the operating voltage. The order of the layers from top to bottom is: E1 (e.g. n+Si), RSL1 (e.g. doped MeOx), capl (e.g. TiOx), IL (e.g. TiN), cap2 (e.g. TiOx), RSL2 (e.g. doped MeOx), SiOx, E2 (such as n+Si). For example, a heavily doped MeOx layer such as HfOx or HfSiON can be used. The doping of MeOx can be achieved by implanting or diffusing dopants such as Ti, Al or Zr into the MeOx layer at a concentration of about 0.01-5%. Test results indicate that these dopants provide good properties. For example, ion implantation or in-situ atomic layer deposition (ALD) can be used. In an example implementation, the RSLs are each made of 2-4nm MeOx such as HfO2, and a 1-2nm SiOx layer is formed on E2 as n+Si.

[0189] FIG. 11D depicts an embodiment of the RSME of FIG. 6C, where E2 is TiN instead of n+Si. The order of the layers from top to bottom is: E1 (e.g. n+Si), RSL1 (e.g. doped MeOx), capl (e.g. TiOx), IL (e.g. TiN), cap2 (e.g. TiOx), RSL2 (e.g. doped MeOx), Ti/TiOx, E2 (such as TiN). In an example implementation, the RSLs are each made of 2-4 nm MeOx such as HfO2, and a Ti/TiOx layer is formed on E2.

[0190] FIG. 11E depicts an embodiment of the RSME of FIG. 6C configured with an asymmetric mirror unit, where the RSL is made of different materials. The order of the layers from top to bottom is: E1 (e.g. n+Si), RSL1 (e.g. type A MeOx). capl (e.g. TiOx), IL (e.g. TiN), cap2 (e.g. TiOx), RSL2 (e.g. type B MeOx) ), SiOx, E2 (such as n+Si). It may be problematic to make the RSME switch in both the forward direction and the reverse direction, so it may be preferable to switch in a certain polarity. One possible solution is to use different materials for RSL1 and RSL2. For example, RSL1 can be of type "A", while RSL2 is of type "B". For example, two different types of MeOx can be used to control the switching polarity, so that RSL1 is MeOx type "A" and RSL2 is MeOx type "B". Examples of MeOx include AlOx, TiOx, NiOx, ZrOx, CuOx, WOx, so that RSL1 can use one of these materials, and RSL2 can use another of these materials. The RSL material can be selected to obtain the desired switching performance, where switching occurs under desired conditions such as the specified -V condition. For example, E1 and E2 can be made of n+Si or TiN.

[0191] FIG. 11F depicts an embodiment of the RSME of FIG. 6C configured with an asymmetric mirror unit without SiOx. The order of the layers from top to bottom is: E1 (e.g. n+Si), RSL1 (e.g. type A MeOx), capl (e.g. TiOx), IL (e.g. TiN), cap2 (e.g. TiOx), RSL2 (e.g. type B MeOx) ), Ti/TiOx, E2 (such as TiN). In this case, the second electrode (E2) is a material such as TiN instead of n+Si, so that the SiO 2 layer is not formed during manufacturing. As described in connection with FIG. 11B, Ti is deposited on the TiN electrode, and during the deposition of a MeOx layer such as HfOx on Ti, the top portion of the Ti layer is oxidized to obtain a TiOx layer.

[0192] FIG. 12 depicts the energy diagram of the RSME of FIG. 6C. The horizontal axis plots the distance from E1 to E2 along RSME, while the vertical axis represents the energy level. Ec is the conduction band, which ranges from the high level of Ec2 at the junction between E1 and RSL1 to the low value of Ecl at the junction between E2 and RSL2. EE1 is the energy level of E1, EIL is the energy level of IL, and EE2 is the energy level of E2. Εν is the valence band. The groove in the conduction band represents the lower energy level achieved at IL, as described below.

[0193] MRS relies on ionic conductivity as a switching mechanism. In ion conductors, current is transmitted by the movement of ions around and by the movement of electrons and holes. For example, current transport via ions, or ions, and electrons and holes is found in conductive liquids called electrolytes and ion conductive solids also called solid electrolytes. In addition, ionic conductivity is important for many products, such as type I and type II batteries (ie conventional and rechargeable), fuel cells, electrochromic windows and displays, solid-state sensors, especially for reactive gases, conductive bridges Switching and bipolar MeOx switching as described herein.

[0194] In contrast to pure electronic current transmission, there are chemical reactions (such as changes in the system over time) associated with currents that occur whenever ionic currents are converted into electronic currents, that is, contacts or electrodes. This is a significant difference compared to the current flow using electrons (or holes) in which the current flows across the contact and does not require a chemical reaction. Bipolar MeOx switching attempts to move oxygen vacancies in MeOx to create metal filaments, thereby storing oxygen at the interface. Electrical conduction is provided through mechanisms including: Fowler-Nordheim, Schottky, Space Charge Limited Current (SCLC), SCLC, and Poole-Frenkel (Poole-Frenkel, PF) Together, PF and Hills Law (Ex. 11, s Law)_oIonic conductivity includes conductivity, diffusion, and field type.

[0195] Typical ionic conductivity values are relatively low and depend on the supply of oxygen from the air at the electrode, temperature, and electric field (exponentially).

[0196] FIG. 13 depicts the application of a high electric field in the RSL setting process. This scanning electron microscopy image depicts the left electrode (EL) of n+Si including the growth layer of SiO2, the RSL of Hf02, and the right electrode (ER) of TiN. A high electric field can be applied to move oxygen into the RSL of MeOx such as Hf02. Here, in an example implementation, a high electric field exists in a region of 3-5 nm wide HfO2. Using a value of 5nm, the electric field is therefore 5V/5nm = lMV/cm.

[0197] FIGS. 14A-14D depict different stages in the formation of conductive filaments in the RSL setting process. The normally occurring breakdown of a single MeOx film is depicted. The left electrode (EL) is set at 0V as a ground electrode, the middle area represents RSL such as HfO2, and the right area represents, for example, the driven right electrode (ER) at 5V. 5V is an approximation for the situation without a current limiter (resistor). These figures show the expected behavior of RSMEs with two or more such RSLs. Recall that the right electrode in RSME will receive the coupling voltage and will not be driven directly.

[0198] In the setting or forming process, the RSL is initially non-conductive. Empty or white circles represent oxygen ions, and closed or black circles represent metal. The high electric field couples to the negatively charged oxygen ions, extracts the oxygen ions from HfO2 and attracts them to the ER. After the situation of FIG. 14A, there is the situation of FIG. 14B in which some oxygen ions have been extracted and stored at the ER (as represented by the empty circle at the ER), and the region of HfO2 from which oxygen ions are extracted becomes Metallic (as represented by a closed circle). This process continues so that after the situation of FIG. 14B, the situation of FIG. 14C is reached, in which additional oxygen ions have been extracted and stored at the intermediate electrode, and additional regions of HfO2 from which oxygen is extracted become metallic. Finally, after the situation of Figure 14C, the situation of Figure 14D is reached, in which additional oxygen ions have been extracted and stored at the ER, and a sufficient part of the HfO2 from which oxygen has been extracted becomes metallic, forming a RSL The conductive filament or path acts as a short circuit between the electrodes.

[0199] Therefore, there is a transition from an off state to an on state, in which the RSL is in a relatively high resistance state, similar to an open (non-conducting) circuit, in which the RSL is in a relatively low The resistance state is similar to a short (conducting) circuit or a closed circuit.

[0200] FIGS. 14E, 14F, and 14G are energy diagrams, which respectively describe the setup processing stages of FIGS. 14A, 14B, and 14D. The Y-axis plots energy, and the X-axis plots the distance in RSME. The peaks indicate barriers to electron transport, which are imposed by oxygen in HfO2. The peak follows the conduction band Ec, which ranges from Ecl to Ec2. The conduction band maintains this fixed range in Figures 14E-14G. EEL is the energy of EL, and EER is the energy of ER. Moreover, the ideal case of linear belt bending is drawn.

[0201] At the beginning of the treatment, the electric field (E) is at the starting level of 10 Mv/cm (5V/5nm), assuming that 5V is applied across the EL and ER, and they are separated by 5 nm. Relatively small point flow flows, as shown by the thin dotted arrow (Figure 14E). As the process continues, oxygen is extracted from the RSL and it is replaced by the metal region that is part of the growth filament. The metal region essentially becomes an extension of the Si electrode, so that the effective distance between EL and ER is reduced, for example, from 5nm to 4nm, and the E field is correspondingly increased to 12MV/cm (5V/4nm). Due to the higher field, a larger amount of current flows, as shown by the thicker dotted arrow (Figure 14F). Subsequently, additional oxygen is extracted from HfO2, so that the filament grows, and the effective distance between EL and ER decreases, for example, from 4nm to 1nm, and due to the exponential relationship between the field and distance, the E field increases to 50Mv/cm (5V/lnm)_oDue to the even higher field, an even larger amount of current flows as an inrush current, as shown by the even thicker dotted arrow (Figure 14G).

[0202] Note that in FIGS. 14E-14G, the heights of the first and last energy peaks are approximately the same, but the presence of fewer peaks indicates a lower barrier to electron transport. The current limiting effect of the proposed RSME through the IL layer can therefore advantageously avoid the inrush current in the forming and setting process.

[0203] FIGS. 15A-15C depict different stages of the removal of the conductive filament in the reset process of the RSL.

[0204] FIGS. 15D, 15E, and 15F are energy diagrams describing the reset processing stages of FIGS. 15A, 15B and 15C, respectively. Left side

The area represents the grounded electrode (EL), the middle area represents the RSL such as Hf02, and the right area represents the driven electrode (ER). The voltage and electrons plotted are an approximation for the case where there is no current limiting effect of IL. These figures indicate the expected behavior of RSL. Recall that RSME is composed of at least two RSLs connected in series, and in RSME, the right electrode will receive the coupling voltage and will not be driven directly, thus effectively reducing the current flow.

[0205] The reset processing is basically the reverse of the reset processing of FIGS. 14A-14D. At the beginning of the reset process (FIGS. 15A and 15D), at 50 MV/cm in the E field, a relatively small amount of oxygen ions are returned to the part of Hf02 near the ER, breaking the short circuit formed by the filament. A voltage of, for example, -5V is applied across ER and EL using the opposite polarity compared to the setting process. Therefore, during the reset period, it can start at -5V, for example. For example, the effective distance of applying the E field is 1 nm, and an E field of 50 Mv/cm is obtained. Subsequently, a voltage of -7V was applied at a distance of 1.3 nm to obtain an E field of 53 MV/cm (FIGS. 15B and 15E). Subsequently, a voltage of -9V was applied at a distance of 1.6 nm to obtain an E field of 56 MV/cm (FIGS. 15C and 15F). This process is completely different in RSME, and the RSME can therefore advantageously avoid the inrush current in the reset process.

[0206] Using bipolar MeOx switching, ion mobility is provided, where ions are removed from the RSL, making the RSL more metallic. This is a self-amplification effect, because as soon as one ion is removed, the removal of other ions is accelerated because the field increases, and the dependence of movement on the field is exponential. Therefore, if one ion is removed, the field has increased, and the mobility of ion movement increases exponentially. Therefore, the device has a more rapid avalanche effect. This illustrates the setup and formation of dependencies.

[0207] In addition to ion movement, at the same time, by symbolically skipping the energy peak, electrons can move in the RSL. Initially, only a small amount of electrons flow. But as the electric field increases, more electrons can flow through the energy peak and they flow much easier. Eventually, a large number of electrons flow violently towards IL. However, this electron flow is undesirable because the electrons do not contribute to the switching mechanism, which relies on the movement of individual ions. In order to move ions, a sufficient electric field needs to be established. The associated electron flow is undesirable because if a steering element such as a diode is placed in series with the RSL, the diode needs to be able to withstand current from not only a small ion current but also a larger electronic current.

[0208] Also, during the reset period, oxygen moves back to the resistance switching element, and therefore, the effective distance between IL and E1 or E2 increases again. An electric field is created that allows a large amount of electrons to flow.

[0209] The RSME structure allows the establishment of an electric field sufficient to move ions slightly without causing electrons to flow too much. RSME essentially provides a poor conductor that does not conduct very many electrons. Moreover, IL provides a barrier to stop and reflect electrons. Together with the capacitive coupling effect, ions can therefore be moved without causing too much electron current to flow.

[0210] RSME can generally be symmetrical, with IL between RSL1 and RSL2, so the switching mechanism between RSLs can be concentrated at IL. IL allows an electric field to be established in the center of the device so that ions will move in the RSL but will not cross the ILo in the middle region. IL is a conductor and can store oxygen ions. IL can be metallic, although it is also possible that it is not metallic. IL can be very thin, and should be able to reflect and/or hold electrons so that they stay at IL. The capacitance of IL can be adjusted by changing the thickness of IL. This may be especially important for the reduced period.

[0211] The goal is to provide RSMEs that have an energy diagram such as that depicted in FIG. 12 and include a potential step where electrons are reflected but there is still an established electric field. A symmetrical configuration can be used, where RSL1 and RSL2 have the same thickness, or RSL1 and RSL2 can also have different thicknesses. One RSL can be slightly thicker than the other so that the field can be established and does not cause a handover. This will result in an inexpensive band gap diagram as shown in Figure 12 based on the thickness of RSL1 and RSL2. If the thickness of the RSL is the same, their fields will behave the same, and they will switch with the same electric field. On the other hand, by introducing asymmetry, only one RSL can be adjusted, in which case the other RSL becomes a barrier layer without switching.

[0212] Regarding the inrush current, this occurs because the distance between IL and E1 or E2 is too short to have a chance to interact with space. In an electrical conductor, electrons are accelerated in an electric field and travel in an average mean-free path (average mean-free path)

It travels until it is diverged through electron-to-electron, electron-to-phonon, electron-to-impurity, or electron-to-interface mechanisms. For typical conductors such as silicon or copper, the typical mean free path of divergence is about 40nm. In a scaled memory device, the current is impulsive because the typical size is much smaller, so that the electrons are overshot and diverged deep inside the electrode, and no energy is transferred to the switching area.

[0213] FIG. 16A depicts the setting process of the RSME of FIG. 6A. In step 1600, the setting process of the memory unit is started. In practice, multiple memory cells in the memory device can be set or reset at the same time by applying appropriate voltages to appropriate bit lines and word lines. In step 1602, a set voltage is applied across the first and second electrodes. A voltage is applied across the first and second electrodes of the resistance-switching memory cell via a manipulation element connected in series with the resistance-switching memory cell.

[0214] The set voltage may have, for example, a desired waveform such as one or more pulses of a fixed amplitude, a ramp wave, or a step. Therefore, the voltage may be a time-varying voltage signal, for example, the magnitude increases with time. For fixed amplitude pulses, for example, the amplitude can be at or above a level such as Vset (Figure 4A). For ramps or ladders, the set voltage can start at a level lower than Vset and increase to Vset or higher. In one method, the set voltage is applied blindly for a specified period of time without determining whether the set state has actually been reached. In this case, based on the previous statistical analysis of the memory device, the setting voltage has a duration and/or magnitude sufficient for nearly 100% of all memory cells to reach the setting state.

[0215] In another method, when the set voltage is applied, the state of the memory cell is monitored, and the set voltage is removed when the monitoring indicates that the set state has been reached. Removing the voltage may mean allowing the first and second voltages to float. This method is, for example, in US2010/0085794, entitled Set And Reset Detection Circuits For Reversible Resistance Switching Memory Material, published on April 8, 2010, and US7, 391, 638, entitled^uMemory device for protecting memory cells during programming, published on June 24, 2008, is further described, and both are incorporated herein by reference.

[0216] In step 1604, the voltage is coupled to the intermediate layer (IL), and the IL radiates electrons entering the IL from the RSL. In step 1606, one or more filaments are formed in the RSL. Also see Figures 14A-14. Do filament formation can proceed at different rates and complete at different times in different RSLs. For example, referring to FIG. 4B, when the set voltage reaches VsetB, the RSL for type "B" will first reach the set state, and then when the set voltage reaches VsetA, the RSL for type "A" will reach the set state. The setting voltage is sufficient to form a filament in each RSL to provide a conductive path in the RSL, thereby providing a conductive path through the RSME and the memory cell. Therefore, a low resistance state is reached in each RSL and RSME. The low resistance state of RSME can be assigned to the first binary data state, such as 0 or 1. In step 1608, the set voltage is removed, and the memory cell including the RSME is discharged. Note that steps 1602-1606 occur at least partially simultaneously.

[0217] Optionally, only one of the RSLs may complete the setting process, or less than all of the RSLs in the RSME may complete the setting process.

[0218] FIG. 16B depicts the reset process of the RSME of FIG. 6A. In step 1620, the reset process of the memory cell is started. In step 1622, a reset voltage (Vreset, see Figure 4A) is applied across the first and second electrodes. The voltage is applied across the first and second electrodes of the resistance-switching memory cell via a manipulation element connected in series with the resistance-switching memory cell. The set voltage may have a desired waveform such as a fixed-amplitude pulse or a ramp wave. Therefore, the voltage may be a time-varying voltage signal, for example, the magnitude increases with time. As mentioned before, in one method, the set voltage is applied blindly without determining whether the set state is actually reached. In this case, the reset voltage has a duration and/or magnitude sufficient to achieve close to 100% of the reset state for all memory cells.

[0219] In another method, when the reset voltage is applied, the state of the memory cell is monitored, and when the monitoring indicates that the

When the reset state is reached, the reset voltage is removed. This method is further described in the aforementioned US2010/0085794 and US7,391,638.

[0220] In step 1624, the voltage is coupled to the intermediate layer, and the IL radiates electrons from the RSL into the IL. At step 1626, one or more filaments are removed or destroyed in the RSL. See also Figure 15A-15C_OThe removal of filaments can be done at different rates and can be done at different times in different RSLs. For example, referring to FIG. 4B, when the reset voltage reaches VresetB, the RSL for type "B" will first reach the reset state, and then when the reset voltage reaches VresetA, the RSL for type "A" will reach the reset state. This reset voltage is sufficient to remove the filament in each RSL to remove the conductive path in the RSL, thereby removing the conductive path through the RSME and the memory cell. Therefore, a high resistance state is reached in each RSL and RSME. The high resistance state of RSME can be assigned to a second binary data state, such as 1 or 0. In step 1628, the reset voltage is removed, and the memory cell including the RSME is discharged. Note that steps 1622-1626 occur at least partially simultaneously.

[0221] Optionally, it is possible that only one of the RSLs completes the reset process, or less than all of the RSLs in the RSME complete the reset process.

[0222] The above method may include: applying a voltage across the first and second electrodes of the memory cell to switch the resistance to set the first data state in the memory cell, wherein the voltage is capacitively coupled to the electrical ground at the first and second electrodes. A conductive intermediate layer between and in series with the first and second electrodes, and the voltage causes the resistance state to be switched in at least one of the following: (a) the first resistance switching layer, which is electrically connected to the first electrode and the conductive intermediate layer Between and in series with the first electrode and the conductive intermediate layer, and (b) a second resistance switching layer, which is electrically between the second electrode and the conductive intermediate layer and is connected to the second electrode and the conductive intermediate layer In series; and removing the voltage to allow the resistance-switching memory cell to discharge. The resistance switching layer may be reversible or irreversible.

[0223] The above method may further include changing the resistance state in the resistance-switching memory cell by the following steps: (a) increasing the magnitude of the time-varying voltage applied across the resistance-switching memory cell until the first time in the resistance-switching memory cell And one of the first resistance-switching layers to switch the resistance state, and (b) subsequently, further increase the magnitude of the time-varying voltage applied across the resistance-switching memory cell until the first and second resistances of the memory cell are switched at that resistance The resistance state is switched in the other of the switching layers. The switching of the resistance state can be reversible or irreversible.

[0224] The above method may further include: applying a voltage across the first and second control lines, wherein the first control line is connected to one end of the resistance-switching memory cell, and the second control line is connected to a manipulation that is connected in series with the resistance-switching memory cell. Element, and apply the voltage across the first and second resistance-switching layers of the resistance-switching memory cell and across the conductive intermediate layer between the first and second resistance-switching layers; and remove the voltage to allow the The resistance switching memory cell discharges. The resistance switching layer may be reversible or irreversible.

[0225] Thus, it can be seen that, in one embodiment, the resistance-switching memory cell includes first and second electrodes; the conductive intermediate layer is electrically between and connected to the first and second electrodes. In series; and the second resistance switching layer is electrically between the second electrode and the conductive intermediate layer and in series with the second electrode and the conductive intermediate layer, the first and second resistance switching layers both have bipolar switching Characteristics or both have unipolar switching characteristics.

[0226] In another embodiment, the resistance-switching memory cell includes: a diode operating element; and a resistance-switching memory element connected in series with the diode operating element, the resistance-switching memory element includes: first and second electrodes; A conductive or semiconductive intermediate layer between the first and second electrodes and in series with the first and second electrodes; electrically between the first electrode and the conductive or semiconductive intermediate layer and with the first electrode A first resistance-switching layer connected in series with an electrode and the conductive or semi-conductive intermediate layer; and electrically connected to the second electrode and the conductive or semi-conductive intermediate layer

A second resistance switching layer in between and in series with the second electrode and the conductive or semiconductive intermediate layer.

[0227] In another embodiment, the memory device includes: a memory array including a plurality of resistance-switching memory cells, each resistance-switching memory cell includes a manipulation element connected in series with the resistance-switching memory element, and each resistance-switching memory element The element includes an intermediate layer electrically between the first and second resistance-switching layers; a plurality of word lines and bit lines; each resistance-switching memory cell has one end communicating with a corresponding one of the plurality of bit lines, and The other end of the corresponding word line communication among the word lines; and a control circuit, which communicates with the plurality of word lines and bit lines, the control circuit switching to the resistance via the corresponding word line and bit line of at least one of the resistance switching memory cells The at least one of the memory cells applies a voltage to cause the resistance-switching memory element of the at least one of the resistance-switching memory cells to switch from one resistance state to another resistance state.

[0228] In another embodiment, the resistance-switching memory cell includes: first and second electrodes; a conductive or semi-conductive intermediate layer, which is electrically between the first and second electrodes and connected to the first and second electrodes. Two electrodes are connected in series; a first resistance switching layer is electrically between the first electrode and the conductive or semiconductive intermediate layer and in series with the first electrode and the conductive or semiconductive intermediate layer; and a second resistance switching layer Layer, electrically between the second electrode and the conductive or semiconductive intermediate layer and in series with the second electrode and the conductive or semiconductive intermediate layer, the first electrode, the second electrode, the conductive or At least one of the semiconductive intermediate layer, the first resistance switching layer, and the second resistance switching layer is at least partially switched with the first electrode, the second electrode, the conductive or semiconductive intermediate layer, and the first resistance The layer and at least the other one of the second resistance switching layer are arranged laterally.

[0229] In another embodiment, the resistance-switching memory cell includes: first and second electrodes; a conductive or semi-conductive intermediate layer, which is electrically between the first and second electrodes and connected to the first and second electrodes. Two electrodes are connected in series; a first resistance switching layer is electrically between the first electrode and the conductive or semiconductive intermediate layer and in series with the first electrode and the conductive or semiconductive intermediate layer; and a second resistance switching layer Layer, electrically between the second electrode and the conductive or semiconductive intermediate layer and in series with the second electrode and the conductive or semiconductive intermediate layer, the conductive or semiconductive intermediate layer and the first and The first resistance switching layer is at least one of an L shape and a U shape.

[0230] In another embodiment, the memory device includes: a memory array including a plurality of resistance-switching memory cells, each resistance-switching memory cell includes: a manipulation element connected in series with the resistance-switching memory element, and first and second Two electrodes, each resistance-switching memory element includes an intermediate layer electrically between the first and second resistance-switching layers; for each resistance-switching memory cell: the first electrode, the second electrode, the conductive or semi-conductive At least one of the intermediate layer, the first resistance switching layer, and the second resistance switching layer is at least partially connected to the first electrode, the second electrode, the conductive or semiconductive intermediate layer, the first resistance switching layer, and At least the other one of the second resistance-switching layer is arranged laterally; a plurality of word lines and bit lines; each resistance-switching memory cell has one end communicating with the corresponding bit line of the plurality of bit lines, and the The other end of the corresponding word line communication; and a control circuit, which communicates with the plurality of word lines and bit lines, the control circuit to the at least one of the resistance-switching memory cells via the corresponding word line and bit line of at least one of the resistance-switching memory cells One applies a voltage to cause the at least one resistance-switching memory element of the resistance-switching memory cell to switch from one resistance state to another resistance state.

[0231] In another embodiment, a method for changing a resistance state in a resistance switching memory cell includes: applying a voltage across the first and second electrodes of the electronic switching memory cell to set the first electrode in the memory cell. Data state, the voltage capacitively coupled to a conductive or semi-conductive intermediate layer electrically between the first and second electrodes and in series with the first and second electrodes, the voltage causing switching in at least one of the following Resistance state: (a) The first resistance switching layer, which is electrically between the first electrode and the conductive or semi-conductive intermediate layer and is connected to the first electrode and the conductive or

The semi-conductive intermediate layer is connected in series, and (b) a second resistance switching layer, which is electrically between the second electrode and the conductive or semi-conductive intermediate layer and is connected to the second electrode and the conductive or semi-conductive intermediate layer In series; and removing the voltage to allow the resistance-switching memory cell to discharge.

[0232] In another embodiment, a method for changing the resistance state in a resistance-switching memory cell includes: increasing the magnitude of the time-varying voltage applied across the electronically-switching memory cell until the resistance switching memory cell The resistance state is switched in one of the first and second resistance-switching layers; and, subsequently, the magnitude of the time-varying voltage applied across the resistance-switching memory cell is further increased until the first and second resistance-switching memory cells are switched. The other of the resistance switching layers switches the resistance state.

[0233] In another embodiment, a method for changing a resistance state in a resistance-switching memory cell includes: applying a voltage across first and second control lines, the first control line is connected to one end of the resistance-switching memory cell, The second control line is connected to the manipulation element in series with the resistance-switching memory cell, across the first and second resistance-switching layers of the resistance-switching memory cell, and across electrically between the first and second resistance-switching layers The conductive or semi-conductive intermediate layer applies the voltage; and removes the voltage to allow the resistance-switching memory cell to discharge.

[0234] In another embodiment, the resistance-switching memory cell includes: a manipulation element; and a resistance-switching memory element in series with the manipulation element, and the resistance-switching memory element includes: first and second electrodes; A conductive or semiconductive intermediate layer between the second electrode and in series with the first and second electrodes; between the first electrode and the conductive or semiconductive intermediate layer and with the first electrode and the conductive or A first resistance switching layer connected in series with a semiconducting intermediate layer; and a second resistance between the second electrode and the conductive or semiconducting intermediate layer and connected in series with the second electrode and the conductive or semiconducting intermediate layer Switch layers.

[0235] In another embodiment, the resistance-switching memory element includes: first and second electrodes; and a conductive or semi-conductive intermediate layer between the first and second electrodes and with the first and second electrodes. The electrodes are connected in series; the first resistance switching layer is between the first electrode and the conductive or semiconductive intermediate layer and in series with the first electrode and the conductive or semiconductive intermediate layer; the first resistance switching layer is in the Between the first electrode and the conductive or semiconductive intermediate layer and in series with the first electrode and the conductive or semiconductive intermediate layer, the second resistance switching layer includes MeOx; and a cover layer, where the conductive or semiconductive intermediate layer Between the intermediate layer and the first electrode, the covering layer is selected from the group consisting of TiOx, A12O3, ZrOx, LaOx, YOx. From the perspective of the first resistance switching layer, the covering layer acts as oxygen Source or taker.

[0236] In another embodiment, the memory device includes a memory array including a plurality of memory cells, each memory cell includes a manipulation element connected in series with a resistance-switching memory element, and each resistance-switching memory element includes a An intermediate layer between the first and second resistance switching layers; a plurality of word lines and bit lines; each memory cell has one end communicating with a corresponding bit line of the plurality of bit lines and a corresponding word line of the plurality of word lines The other end of the communication; and a control circuit that communicates with the plurality of word lines and bit lines, and the control circuit applies a voltage to the at least one of the memory cells via corresponding bit lines and word lines of at least one of the memory cells to cause the The at least one resistance-switching memory element of the memory cell switches from one resistance state to another resistance state.

[0237] In another embodiment, a resistance-switching memory cell includes: first and second electrodes; a conductive intermediate layer, electrically between the first and second electrodes and in series with the first and second electrodes; A resistance switching layer, electrically between the first electrode and the conductive intermediate layer and in series with the first electrode and the conductive intermediate layer; and a breakdown layer, electrically between the second electrode and the conductive intermediate layer And in series with the second electrode and the conductive intermediate layer, the breakdown layer maintains a resistance of at least about 1-10 MΩ when in a conductive state.

[0238] In another embodiment, the resistance-switching memory cell includes: a manipulation element; and a resistance-switching memory cell

Piece, connected in series with the manipulation element, the resistance-switching memory element includes: first and second electrodes; a conductive or semi-conductive intermediate layer between the first and second electrodes and in series with the first and second electrodes A resistance switching layer, electrically between the first electrode and the conductive or semiconductive intermediate layer and in series with the first electrode and the conductive or semiconductive intermediate layer; and a breakdown layer, electrically on the first electrode Between the two electrodes and the conductive or semiconductive intermediate layer and in series with the second electrode and the conductive or semiconductive intermediate layer, the breakdown layer maintains a resistance of at least about 1-10 MΩ when in a conductive state.

[0239] In another embodiment, the memory device includes a memory array including a plurality of memory cells, and each memory cell includes a manipulation element connected in series with a resistance-switching memory element. Each resistance-switching memory element includes: first and second electrodes; a conductive or semi-conductive intermediate layer between the first and second electrodes and in series with the first and second electrodes; a resistance-switching layer, which is electrically grounded Between the first electrode and the conductive or semi-conductive intermediate layer and in series with the first electrode and the conductive or semi-conductive intermediate layer; and a breakdown layer, which is electrically connected between the second electrode and the conductive or semi-conductive intermediate layer; Between the conductive intermediate layer and in series with the second electrode and the conductive or semiconductive intermediate layer, the breakdown layer maintains a resistance of at least about 1-10 MΩ when in a conductive state. The memory device also includes: a plurality of word lines and bit lines; each memory cell has one end communicating with a corresponding one of the plurality of bit lines and another end communicating with a corresponding one of the plurality of word lines; and control The circuit communicates with the plurality of word lines and bit lines, and the control circuit applies a voltage to the at least one of the memory cells via the corresponding bit lines and word lines of at least one of the memory cells to cause the at least one of the memory cells to The resistance switching memory element switches from one resistance state to another resistance state.

[0240] FIG. 17 illustrates a perspective view of a memory unit 100 according to another embodiment. In this embodiment and the embodiment shown in FIGS. 18A-18E, the resistance switching layer of the resistance switching memory element is preferably made of hafnium silicon oxynitride, hafnium silicon oxide, or a combination thereof. to make. The unit 100 includes a first electrode 106 and a second electrode 108 formed of a conductive material. The first electrode 106 and the second electrode 108 may independently include any one or more suitable conductive materials known in the art, such as duck, Copper, aluminum, bare, titanium, diamond, titanium nitride or their alloys. For example, in some embodiments, bustard is preferred to allow processing at relatively high temperatures. In some other embodiments, copper or aluminum is the preferred material. The first electrode 106 (for example, a word line) extends in a first direction, and the second electrode 108 (for example, a bit line) extends in a second direction different from the first direction. A barrier or adhesion layer such as a TiN layer may be included on the first (e.g., bottom) electrode 106 and/or the second (e.g., top) electrode 108.

[0241] The manipulation element 104 may be a transistor or a diode. If the manipulation element 104 is a diode, the storage element 102 may be arranged vertically and/or horizontally and/or patterned to form a pillar or block containing a diode and a storage element connected in series and having a substantially cylindrical shape. In one embodiment, as shown in FIGS. 17 and 18A-18E, the manipulation element 104 is a vertically arranged semiconductor diode, which has a heavily doped n-type region 142 at the bottom and an unintentionally doped The selected intrinsic region 144 and the heavily doped p-type region 146 at the top, although the orientation of the diode can be reversed. Such a diode will be called a pin diode or simply a diode regardless of its orientation. The diode may include any single crystal, polycrystalline or amorphous semiconductor material, such as silicon, aluminum, silicon aluminum, or other compound semiconductor materials, such as III-V, II-VI, and the like. For example, a pin polysilicon diode 104 can be used.

[0242] The storage element 102 (eg, resistivity switching memory element, RSME) is disposed above the top region 146 of the manipulation element 104 or below the bottom region 142 of the manipulation element 104 in series with the manipulation element 104. The storage element 102 may include a metal oxide switchable layer (RSL), such as zirconium oxynitride, zirconium oxide, or a combination thereof. Preferably, the resistance switching layer is deposited by ALD, chemical vapor deposition (CVD), or physical vapor deposition (PVD) at a temperature sufficiently low that the RSL is amorphous. That is, it is preferable to deposit the resistance switching layer at a temperature below the crystallization temperature, such as 250-400°C,

Therefore, crystal grains (for example, 0-5% volume microcrystal grains) are basically not formed in the amorphous RSL. The inventors found that amorphous silicon oxynitride RSL exhibits high thermal stability, which is believed to enhance conductive filament formation during programming of the memory cell. The high thermal stability allows RSL to remain amorphous during and after high thermal cycles used to manufacture three-dimensional memory devices containing multiple memory device levels (eg, after annealing up to about 1100°C, such as 600 to 1100°C).

[0243] The zirconium oxynitride resistance switching layer can be deposited as a blanket film on the underlying layer by ALD, CVD or PVD. Alternatively, the zirconium oxide layer can be deposited first, and then the next step Nitride it to form a silicon oxynitride. For example, nitriding can be performed at a temperature of 400°C from room temperature (25°C) Dawkins in nitrogen containing plasma. Alternatively, thermal nitriding (ie, annealing of ortho-silicon oxide in nitrogen containing the external environment) or implanting nitrogen ions into the silicon oxide followed by annealing can be used to form the zirconium oxynitride layer. One advantage of the nitridation process is that after the memory cell pillars are formed, the sidewalls of the pillars are effectively treated with atomic nitrogen in the three-dimensional structure to further enhance the data retention.

[0244] The nitrogen content in the RSL can be in the range of 0 (for example, zirconium oxide) to 20 in %, for example, in the range of greater than 0 to 20 in %, for example, in the range of 5-20 in %. Within range. The content of error in RSL may be in the range of 5-35 in %, for example, in the range of 15-30 in %, and the silicon content in RSL may be in the range of 5-35 in %, for example, in% Within the range of 10-20. The balance of components in RSL is oxygen and unavoidable impurities. Oxygen can be in the range of 25-70%. Preferably, the thickness of the RSL is 10Ajnm, such as 1-4nm.

[0245] In an embodiment of the present invention, an optional dielectric resistor 200 is located in series with the manipulation element 104 and the metal oxide storage element 102 between the top electrode 108 and the bottom electrode 106. The dielectric resistor 200 preferably includes a layer of electrically insulating material. For example, the electrically insulating material layer may include a silicon nitride or silicon oxynitride layer with a thickness of about 1 to about 10 nm, such as 1-2 nm. The silicon nitride layer may include stoichiometric silicon nitride (ie, Si₃N₄) Or non-stoichiometric silicon nitride (such as Si₃N_4±x, Wherein X is preferably in the range between 0.001 and 1).

[0246] Without wishing to be bound by a particular theory, it is believed that the resistor in the memory cell 200 reduces or eliminates high transient currents, which are believed to result from metal oxidation during the initial formation (eg, cell programming) process. Large-size conductive filaments appearing in storage materials. These filaments may cause subsequent high current operation of the unit. It is believed that the in-cell resistor 200 provides in-cell resistance management or tuning during the formation process and provides subsequent lower current (eg, less than 1 microampere) operation (eg, low read current operation) to the ReRAM cell being programmed. It is believed that tuning of the cell resistance allows for the formation of smaller size filaments in the metal oxide layer to achieve low current cell operation without sacrificing good data retention. In addition, although the dielectric layer 200 is described as a resistor, it can operate as a capacitor or a combination of a resistor and a capacitor to reduce the size of the filament and allow low current cell operation.

[0247] Without wishing to be bound by a particular theory, at least one conductive filament (and usually a plurality of conductive filaments) is formed through the metal oxide memory element or layer 102 during the formation and programming of the memory cell to remove the metal oxide memory element from Its initial higher resistivity state previously formed is switched to a lower resistivity state. However, it is considered that the conductive filament passing through the dielectric resistor 200 is not formed during the formation and programming of the memory cell, so that the resistivity of the dielectric resistor 200 does not substantially change after the formation and programming of the memory cell. Therefore, during the formation and programming of the memory cell, substantially no transient current flows through the memory cell. In other words, no typical current measurement tool (such as a tool with a sensitivity of 100 microamperes or higher) can detect a detectable transient current flowing through the memory cell.

[0248] FIGS. 18A-18E are side cross-sectional views schematically illustrating a nonvolatile memory cell of an embodiment of the present invention. Preferably, the memory cell includes at least one heavily doped semiconductor layer 202.204 and a metal oxide storage element (for example, RSL) 214 in series with the manipulation element 104_OFor a diode with an n-type region 146 facing the storage element

The manipulation element 104, preferably the at least one heavily doped semiconductor layer 202, 204 includes n-type silicon, for example, having 5×10¹⁸To 2xl0²¹cm^³The n+ dopant concentration (such as P or As concentration) of n+ doped polysilicon. The diode operating element 104 may also include a heavily doped p+ polysilicon region 142, such as a 5xl0¹⁸To 2xl0²¹cm^³The p+ doped polysilicon with a p+ dopant concentration (for example, a B concentration) of 3, and a lightly doped or intrinsic (unintentionally doped) polysilicon region 144 included between the p+ region 142 and the n+ region 146.

[0249] For example, as shown in FIG. 18A, the memory cell 100 may include a first n+ polysilicon layer 202 located between the n+ region 146 of the diode 104 and the storage element 214. The memory cell may also include a second n+ polysilicon layer 204 between the storage element 214 and the top electrode 108. Alternatively, as shown in FIGS. 18B-18E, the second n+ polysilicon layer is omitted.

[0250] The memory cell may also include one or more optional conductive barrier layers 206, 208 and 210, such as titanium nitride or other similar layers. These barrier layers 206, 208, and 210 may be located between the bottom electrode 106 and the diode 104, respectively. Between, and/or between the diode 104 and the storage element 214, and/or between the "ReRAM" element (eg, RSME) 212 and the top electrode 108. The ReRSM 212 may include doped semiconductor layers 202, 204 and a storage element 214.

[0251] In a non-limiting embodiment shown in FIG. 18B, the metal oxide memory element 102 includes a stack of a TiO' layer 216 and a zirconium oxynitride or zirconium oxide layer 214. Preferably, TiO_xThe layer 216 is located closer to the upper electrode 108 than the zirconium oxynitride or zirconium oxide layer 214, and the zirconium oxynitride or zirconium oxide layer 214 is located more than the TiO_xThe layer 216 is closer to the diode 104. In other words, for the cell shown in FIG. 18B with the ReRAM element 212 above the diode manipulation element 104, the TiOx layer 216 is located on the zirconium oxynitride or zirconium oxide layer 214.

[0252] FIG. 18C is similar to FIG. 18B, but it omits the optional metal layer. In FIG. 18C, the TiOx layer 216 is omitted, so that the TiN layer 210 directly contacts the HfSiON layer 214. FIG. 18D is similar to FIG. 18C, but it omits the optional n+ polysilicon layer 202, so that the TiN layer 208 directly contacts the HfSiON layer 214.

[0253] Therefore, as shown in FIGS. 18A-18D, the manipulation element 104 is located above the lower electrode 106, and the ReRAM element 212 including the metal oxide storage element 214 and heavily doped semiconductor layers 202, 204 is located in the pillar above the manipulation element 110 , And the upper electrode 108 is located above the column. In addition, as shown in FIG. 18A, the titanium nitride barrier layer 208 is located above the manipulation element 104, and the upper electrode 108 is located above the pillar, the first heavily doped semiconductor layer 202 is located above the titanium nitride barrier layer 208, and the metal oxide The storage element 214 is located above the first heavily doped semiconductor layer 202, and the second lightly doped semiconductor layer 204 is located above the metal oxide storage element 214.

[0254] In the embodiment shown in FIG. 18E, the ReRAM element 212 includes two metal oxide storage elements 214A, 214B (for example, HfSiON RSL) separated by a conductive barrier layer 215. The conductive layer 215 may include any suitable material, such as TiN or W. As shown, the ReRAM element 212 is in a mirror configuration, where the thickness and composition of the layers 214A. 214B are the same. However, as described above, the ReRAM element 212 can also use multiple RSL layers 214A, 214B with different thicknesses and/or compositions. Come to decorate.

[0255] The test structure 300 with a memory layer of silicon oxynitride was fabricated to test the performance and stability of the silicon oxynitride ReRAM. A schematic diagram of this structure is illustrated in FIG. 19A. The test structure has a multi-layer RSL configuration with an n+ bottom polysilicon layer 202, a 2nm first zirconium oxynitride storage layer 214A, a 5nm conductive TiN barrier layer 215, and a 4nm second silicon oxynitride The material storage layer 214B and the TiN upper electrode 210. The test structure 300 does not include manipulation elements.

[0256] The test is performed by cycling the voltage of the test structure 300 ten times in a low current system. Cycle this voltage between the test voltage of the opposite polarity and the reset voltage. After each set/reset operation, record at room temperature within one minute

Twelve consecutive read operations.

[0257] A new full or half programming cycle is performed when needed to place the bit in the on (ie set) state. In order to test the temperature stability of the test structure in the on state (that is, the data retention after exposure to heat), the test structure is then baked at 85°C for two hours and retested (for example, read at room temperature). Perform a new full or half cycle when needed to place the bit in the off (ie reset) state. To test the temperature stability of the test structure in the on state, bake the test structure at 85°C for two hours and retest (for example, read at room temperature).

[0258] The results of the test are illustrated in Figures 19B-19D. FIG. 19B is a probability diagram of sigma (σ in the figure) relative to the reading current of the test structure 300 when the reading voltage is 1.5V. In Figure 19B, the line with the circle symbol corresponds to the "verification" reading current, which is read after 5-10 cycles. The line with the rhombus symbol corresponds to the 60-second relaxation (or relaxation) read current, which shows the read current measured 60 seconds after the set/reset operation. The line with the triangle symbol corresponds to the read current before the 85C baking, and the line with the round symbol symbol corresponds to the read current after the 85C baking. The test structure showed good relaxation stability (ie, high stability of the resistivity of RSL as a function of time after programming) and data retention after baking. Crossover occurred at T. 7 Above, such as the sigma of -1.8 to -2.1 and the median read current of about 200nA in the on state and about 20nA in the off state (that is, the difference of at least 10 between the states factor).

[0259] FIG. 19C illustrates a similar graph of the data retention (ie, the read current measured within 60 seconds after programming) of the test structure 300 from a different batch. This test structure exhibits a sigma of about -2 and good relaxation stability. The median read current is about 200 nA in the on state and about 40 nA in the off state. FIG. 19D illustrates the test structure 300 from the same batch. Data retention. The line with the closed circle symbol corresponds to the read current before the 85C baking, and the line with the empty circle symbol corresponds to the read current after the 85C baking. The test structure exhibits good data retention, and the crossover occurs at a sigma greater than T·5.

[0260] The comparison test structure 302 with the oxide RSL was manufactured as a comparison with the polysilicon oxynitride ReRSM test structure 300. A schematic diagram of this structure 302 is illustrated in FIG. 20A. The comparative test structure 302 has a multi-layer RSL configuration with an n+ bottom polysilicon layer 202, a 2nm first zirconium oxide storage layer 214A, and a 5nm conductive TiN barrier layer 215. , 4nm second zirconium oxide storage layer 214B and TiN upper electrode 210. Like the test structure 300, the comparison test structure 302 does not include manipulation elements.

[0261] The test of the comparative test structure 302 is performed under the same test conditions as the structure 300. The results of the comparison test are illustrated in Figures 20B-20D, which are similar to the test structures 302 in Figures 19B-19Do and Figures 19B-19C from the same batch and have approximately 200nA in the on state and in the off state. It is a median read current of about 20nA. The test structure 302 is from a different batch and has a median read current of approximately 200 nA in the on state and approximately 40 nA in the off state. Compared with the test structure 300, the comparative test structure 302 exhibits generally poor data relaxation and retention (crossover occurs at a sigma less than -1 in FIGS. 19C and 19D).

[0262] The above detailed description of the present invention has been given for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Considering the above teaching many modifications and variations are possible. The described embodiments are selected in order to best illustrate the principles of the present invention and its practical applications, thereby enabling those skilled in the art to best use various modifications suitable for the specific uses of the drawings in various embodiments. Use the present invention. It is intended that the scope of the present invention is defined by the appended claims.

<img file="CN104040746A_D0001.tif" />

figure 1

<img file="CN104040746A_D0002.tif" />