Techniques for providing a semiconductor memory device

Semiconductor memory device and method for biasing semiconductor memory device

[0001] Cross reference of related applications

[0002] This patent application claims priority to the U.S. Provisional Patent Application No. 61/313,986 filed on March 15, 2010, and the entire content of the provisional application is hereby incorporated by reference.

Technical field

[0003] The present invention relates generally to semiconductor memory devices, and more particularly, to techniques for providing junctionless semiconductor memory devices.

Background technique

[0004] The semiconductor industry has experienced technological advancements that have allowed the density and/or complexity of semiconductor memory devices to increase. And, the technological advancement has allowed the reduction of power consumption and package size of various types of semiconductor memory devices. There is a continuing trend to utilize and/or manufacture advanced semiconductor memory devices using technologies, materials, and devices that improve performance, reduce leakage current, and enhance overall scaling. Silicon on Insulator (SOI) and bulk substrates are examples of materials that can be used to manufacture such semiconductor memory devices. For example, such semiconductor memory devices may include partially depleted (PD) devices, fully depleted (FD) devices, multi-gate devices (for example, double gate, tri-gate, or surround gate), and fin FET (Fin-FET) device.

[0005] A semiconductor memory device may include a memory cell having a memory transistor with an electrically floating body region in which charge can be stored. When excess majority charge carriers are stored in the electrically floating body region, the memory cell can store a logic high (for example, a binary "1" data state). When the electrically floating body region is depleted of majority charge carriers, the memory cell can store a logic low (for example, a binary "0" data state). Also, semiconductor memory devices can be fabricated on silicon-on-insulator (SOI) substrates or bulk substrates (for example, with bulk isolation enabled). For example, semiconductor memory devices can be manufactured as three-dimensional (3D) devices (eg, multi-gate devices, finFET devices, and vertical pillar devices).

[0006] In a conventional technique, the memory cell of the semiconductor memory device can be manufactured through an implantation process. During the conventional implantation process, defect structures may be generated in the silicon lattice of various regions of the memory cell of the semiconductor memory device. The defect structure formed during the implantation process can reduce the retention time of majority charge carriers stored in the memory cell of the semiconductor memory device. Also, during the conventional implantation process, various regions of the memory cell may be doped with undesired doping concentrations. The undesired doping concentration can thus produce undesirable electrical properties for the memory cell of the semiconductor memory device. In addition, the conventional implantation process may face lateral and vertical scaling challenges.

[0007] In view of the above, it can be understood that there may be significant problems and disadvantages associated with conventional techniques for providing semiconductor memory devices.

Summary of the invention

[0008] A semiconductor memory device is disclosed, which includes a plurality of memory cells arranged in an array of rows and columns, each memory cell includes: a first region; a second region; a body region capacitively coupled to at least one The word line is arranged between the first area and the second area; and a third area, wherein the third area and the first area, the

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The second region and the body region are doped differently.

[0009] In addition, a method for biasing a semiconductor memory device is disclosed. The step includes: applying a plurality of voltage potentials to a plurality of memory cells arranged in an array of rows and columns, wherein applying the plurality of voltage potentials to the plurality of memory cells includes: applying a first voltage potential To the first area of each of the plurality of memory cells; applying a second voltage potential to the second area of each of the plurality of memory cells; capacitively coupled to At least one corresponding word line of the body region applies a third voltage potential to the body region of each of the plurality of memory cells; and applies a fourth voltage potential to the third region.

Description of the drawings

[0010] In order to promote a more complete understanding of the present invention, reference is now made to the accompanying drawings, in which the same elements are referenced with the same reference numerals. These drawings should not be construed as limiting the present invention, but are intended to be exemplary only.

[0011] FIG. 1 shows a block diagram of a semiconductor memory device including a memory cell array, a data writing and sensing circuit, and a memory cell selection and control circuit according to an embodiment of the present invention.

[0012] FIG. 2 shows a cross-sectional view of the memory cell shown in FIG. 1 according to an embodiment of the present invention.

[0013] FIG. 3 shows a cross-sectional view of the memory cell shown in FIG. 1 according to an alternative embodiment of the present invention.

[0014] FIG. 4 shows a cross-sectional view of the memory cell shown in FIG. 1 according to an embodiment of the present invention.

[0015] FIG. 5 shows a cross-sectional view of the memory cell shown in FIG. 1 according to an alternative embodiment of the present invention.

[0016] FIG. 6 shows a cross-sectional view of at least a portion of the memory cell array shown in FIG. 1 according to an embodiment of the invention.

[0017] FIG. 7 shows a cross-sectional view of at least a portion of the memory cell array shown in FIG. 1 according to an alternative embodiment of the present invention.

[0018] FIG. 8 shows a cross-sectional view of at least a portion of the memory cell array shown in FIG. 1 according to an alternative embodiment of the invention.

[0019] FIG. 9 shows a cross-sectional view of at least a portion of the memory cell array shown in FIG. 1 according to an alternative embodiment of the present invention.

[0020] FIG. 10 shows a control signal voltage waveform used to perform a write operation on the memory cell shown in FIG. 2 according to an embodiment of the present invention.

[0021] FIG. 11 shows a control signal voltage waveform used to perform a read operation on the memory cell shown in FIG. 2 according to an embodiment of the present invention.

Detailed ways

1, there is shown a block diagram of a semiconductor memory device 10 including a memory cell array 20, a data writing and sensing circuit 36, and a memory cell selection and control circuit 38 according to an embodiment of the present invention. The memory cell array 20 may include a plurality of memory cells 12, each of which is coupled to a memory cell selection and control circuit 38 via a word line (WL) 28 and a carrier injection line (EP) 34, and via a bit line (CN) 30 and The source line (EN) 32 is coupled to the data writing and sensing circuit 36. It can be understood that the bit line (CN) 30 and the source line (EN) 32 are names used to distinguish the two signal lines, and they can be used interchangeably.

[0023] The data writing and sensing circuit 36 can read data from the selected memory cell 12 and can write data to the selected memory cell 12. In an exemplary embodiment, the data writing and sensing circuit 36 Can include multiple data sensing

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Amplifier circuit. Each data sense amplifier circuit can receive at least one bit line (CN) 30 and a current or voltage reference signal. For example, each data sense amplifier circuit may be a cross-coupling type sense amplifier to sense the state of the data stored in the memory cell 12. The data writing and sensing circuit 36 may include at least one multiplexer that may couple the data sense amplifier circuit to at least one bit line (CN) 30. In an exemplary embodiment, the multiplexer may couple a plurality of bit lines (CN) 30 to the data sense amplifier circuit.

[0024] Each data sense amplifier circuit can utilize voltage and/or current sensing circuits and/or technologies. In an exemplary embodiment, each data sense amplifier circuit may utilize current sensing circuits and/or technologies. For example, the current sense amplifier may compare the current from the selected memory cell 12 with a reference current (eg, the current of one or more reference cells). According to the comparison, it can be determined whether the selected memory cell 12 stores a logic high (for example, a binary "1" data state) or a logic low (for example, a binary "0" data state). Those skilled in the art can understand that various types or forms of data writing and sensing circuits 36 (including one or more sensing circuits that use voltage or current sensing technology to sense the state of data stored in the memory cell 12 The amplifier) can be used to read the data stored in the memory cell 12.

[0025] The memory cell selection and control circuit 38 can select and/or enable one or more predetermined by applying control signals to one or more word lines (WL) 28 and/or carrier injection lines (EP) 34 The memory cell 12 is used to facilitate reading data from the memory cell 12. The memory cell selection and control circuit 38 can generate such control signals from address signals (for example, row address signals). In addition, the memory cell selection and control circuit 38 may include a word line decoder and/or driver. For example, the memory cell selection and control circuit 38 may include one or more different control/selection techniques (and circuits) to select and/or enable one or more predetermined memory cells 12. Obviously, all such control/selection techniques and their circuits (whether known now or later developed) are intended to fall within the scope of the present invention.

[0026] In an exemplary embodiment, the semiconductor memory device 10 may implement a two-step write operation, whereby a row can be written by first performing a "clear" or logic low (for example, binary "0" data state) write operation All the memory cells 12 in the memory cells 12 are written into a predetermined data state, whereby all the memory cells 12 in the row memory cells 12 are written into a logic low (for example, a binary "0" data state). Thereafter, the selected memory cell 12 among the row memory cells 12 can be selectively written to a predetermined data state (for example, logic high (binary "1" data state)). The semiconductor memory device 10 can also perform a one-step write operation, whereby a selected memory cell 12 in a row of memory cells 12 can be selectively written to a logic high (for example, a binary "1" data state) or a logic low (For example, binary "0" data state) without first implementing the "clear" operation. The semiconductor memory device 10 may utilize any of the exemplary write, prepare, hold, refresh, and/or read techniques described herein.

[0027] The memory cell 12 may include N-type, P-type and/or both types of transistors. Circuits at the periphery of the memory cell array 20 (for example, sense amplifiers or comparators, row and column address decoders, and line drivers (not described herein)) may also include P-type and/or N-type transistors. Regardless of whether a P-type transistor or an N-type transistor is used in the memory cell 12 of the memory cell array 20, a suitable voltage potential for reading from the memory cell 12 (for example, a positive or negative voltage potential) will be further described herein. ).

[0028] Referring to FIG. 2, there is shown a cross-sectional view of the memory cell 12 shown in FIG. 1 according to an embodiment of the present invention. The memory cell 12 may include a first N-region 120, a second N-region 122, a third N-region 124, and/or a P-region 126. The first N-region 120, the second N-region 122, the third N-region 124, and/or the P-region 126 may be arranged in a continuous adjacent relationship in a planar configuration, which may extend horizontally or be combined with an oxide Area 128 and/or P-substrate

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The plane defined by 130 extends in parallel. In an exemplary embodiment, the second N-region 122 may be an electrically floating body region of the memory cell 12 configured to accumulate/store charge, which may be spaced apart from the word line (WL) 28 and capacitive Sexually coupled to the word line (WL) 28.

[0029] The first N-region 120 of the memory cell 12 may be coupled to a source line (EN) 32 via a first N+ poly plug 232. The first N+ polysilicon plug 232 may be directly coupled to the first N-region 120 of the memory cell 12. The second N-region 122 of the memory cell 12 may be coupled to the word line (WL) 28 via the gate region 228. The gate region 228 may be capacitively coupled to the second N-region 122 of the memory cell 12. The third N-region 124 of the memory cell 12 may be coupled to the bit line (CN) 30 via the second N+ polysilicon plug 230. The second N+ polysilicon plug 230 may be directly coupled to the third N-region 124 of the memory cell 12. The P- region 126 of the memory cell 12 may be coupled to the carrier injection line (EP) 34 via the P+ region 234. The P+ region 234 may be directly coupled to the P- region 126 of the memory cell 12.

[0030] The first N-region 120, the second N-region 122, and the third N-region 124 may be formed of the same material or different materials. Also, the first N-region 120, the second N-region 122, and the third N-region 124 may be formed of the same material with various doping concentrations. In an exemplary embodiment, the first N-region 120, the second N-region 122, and the third N-region 124 may be formed of a semiconductor material (for example, silicon) containing donor impurities (for example, nitrogen, stele, and/or phosphorous) form. In an exemplary embodiment, the first N-region 120, the second N-region 122, and/or the third N-region 124 may have 10¹⁵Atom/cm³To 10 flash atoms/cm ³The concentration of donor impurities is formed of silicon material.

[0031] The P-region 126 may be formed of a semiconductor material (for example, intrinsic silicon) containing acceptor impurities. For example, the P-region 126 may be formed of a silicon material doped with boron impurities. In an exemplary embodiment, the P-region 126 may be formed of a silicon material with acceptor impurities having a concentration of 1015 atoms/cut 3 to 10 aluminum atoms/cm% scoop. In another exemplary embodiment, the P-region 126 may be formed of an undoped semiconductor material (for example, intrinsic silicon).

[0032] The first N+ polysilicon plug 232 and the second N+ polysilicon plug 230 may be formed of the same material or different materials. The first N+ polysilicon plug 232 and the second N+ polysilicon plug 230 may be formed of a metal material, a polysilicon material, a silicon dioxide material, and/or a combination thereof. The first N+ polysilicon plug 232 and the second N+ polysilicon plug 230 can couple the voltage potentials from the source line (EN) 32 and the bit line (CN) 30 to the first N-region 120 and the first N-region 120 of the memory cell 12, respectively. Three N-area 124. In another exemplary embodiment, the first N+ polysilicon plug 232 and the second N+ polysilicon plug 230 may be formed of hook, titanium, titanium nitride, polysilicon, or a combination thereof. The first N+ polysilicon plug 232 and the second N+ polysilicon plug 230 may have a height extending from the first N- region 120 and the third N- region 124 to the source line (EN) 32 and the bit line (CN) 30, respectively .

[0033] The gate region 228 may be formed of a polycide material, a silicon material, a metal material, and/or a combination thereof. In another exemplary embodiment, the gate region 228 may be formed of a doped silicon layer. The gate region 228 may be formed of a semiconductor material (for example, silicon) containing acceptor impurities. For example, the gate region 228 may be formed of a silicon material doped with boron impurities.

[0034] The P+ region 234 may be formed of a semiconductor material (for example, silicon) containing acceptor impurities. For example, the P+ region 234 may be formed of a silicon material doped with boron impurities. In an exemplary embodiment, the P+ region 234 may be doped with 10²° Atom/cn? or higher concentration of acceptor impurities.

[0035] The oxide layer 128 may be formed on the P-substrate 130. For example, the oxide layer 128 may be formed of an insulating material. The oxide layer 128 may include a continuous planar area disposed on the P-substrate 130. In an exemplary embodiment, the oxide layer 128 may be formed of an insulating oxide material. The oxide layer 128 may form a channel region, and the channel region may have

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It is useful for adapting to the cross-sectional shape of one or more memory cells 12. For example, the channel region may have a square, rectangular, cylindrical, and/or other cross-sectional shape that can accommodate one or more memory cells 12.

[0036] In an exemplary embodiment, the P-substrate 130 may be made of a semiconductor material (for example, silicon) including acceptor impurities, and may form the base of the memory cell array 20. In an alternative exemplary embodiment, a plurality of P-substrates 130 may form the base of the memory cell array 20, or a single P-substrate 130 may form the base of the memory cell array 20. Also, the P-substrate 130 may be manufactured in the form of a P-well substrate.

[0037] The insulating layer 132 may be formed on top of the oxide layer 128. For example, the insulating layer 132 may be formed of an insulating material, an oxide material, and/or a dielectric material. In an exemplary embodiment, the insulating layer 132 may be formed of a silicon nitride material. The insulating layer 132 may be formed on the oxide layer 128 to electrically insulate the first N+ polysilicon plug 232, the gate region 228, the second N+ polysilicon plug 230, and/or the P+ region 234.

[0038] Referring to FIG. 3, there is shown a cross-sectional view of the memory cell 12 shown in FIG. 1 according to an alternative embodiment of the present invention. The memory cell 12 illustrated in FIG. 3 may be similar to the memory cell 12 illustrated in FIG. 2 except that the memory cell 12 may include multiple undoped regions. The plurality of undoped regions may include a first undoped region 320 coupled to the corresponding first N+ polysilicon plug 232, a second undoped region 322 capacitively coupled to the corresponding gate region 228, and/ Or coupled to the third undoped region 324 corresponding to the second N+ polysilicon plug 230.

[0039] The plurality of undoped regions may be formed of the same material or different materials. For example, the plurality of undoped regions (for example, the first undoped region 320, the second undoped region 322, and/or the third undoped region 324) may be made of undoped semiconductor materials (for example, Intrinsic silicon) is formed.

[0040] Referring to FIG. 4, there is shown a cross-sectional view of the memory cell 12 shown in FIG. 1 according to an embodiment of the present invention. The memory cell 12 illustrated in FIG. 4 may be similar to the memory cell 12 illustrated in FIG. 2, except that the memory cell 12 may include a first P-region 420, a second P-region 422, a third P-region 424, and/ Or the evening of N-area 426. The first P-region 420, the second P-region 422, the third P-region 424, and/or the N-region 426 may be arranged in a continuous adjacent relationship in a planar configuration, which may extend horizontally or be combined with an oxide The plane defined by the region 128 and/or the P-substrate 130 extends in parallel. In an exemplary embodiment, the second P-region 422 may be an electrically floating body region of the memory cell 12 configured to accumulate/store charge, which may be spaced apart from the word line (WL) 28 and capacitively Sexually coupled to word line (WL) 28_O

[0041] The first P-region 420 of the memory cell 12 may be coupled to the source line (EN) 32 via the first P+ polysilicon plug 432. The first P+ polysilicon plug 432 may be directly coupled to the first P-region 420 of the memory cell 12. The second P-region 422 of the memory cell 12 may be coupled to the word line (WL) 28 via the gate region 428. The gate region 428 may be capacitively coupled to the second P-region 422 of the memory cell 12. The third P-region 424 of the memory cell 12 may be coupled to the bit line (CN) 30 via the second N+ polysilicon plug 430. The second N+ polysilicon plug 430 may be directly coupled to the third P-region 424 of the memory cell 12. The N- region 426 of the memory cell 12 may be coupled to the carrier injection line (EP) 34 via the N+ region 434. The N+ region 434 may be directly coupled to the N- region 426 of the memory cell 12.

[0042] The first P-region 420, the second P-region 422, and the third P-region 424 may be formed of the same material or different materials. Also, the first P-region 420, the second P-region 422, and the third P-region 424 may be formed of the same material with various doping concentrations. In an exemplary embodiment, the first P-region 420, the second P-region 422, and the third P-region 424 may be formed of a semiconductor material (for example, silicon) including acceptor impurities. For example, the first P-region 420, the second P-region 422, and/or the third P-region 424 may be formed of a silicon material doped with boron impurities. In an exemplary embodiment,

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The first P-region 420, the second P-region 422, and/or the third P-region 424 may be formed of a silicon material with acceptor impurities having a concentration of 10 atoms/cm to 10 flash atoms/cm%.

[0043] The N-region 426 may be formed of a semiconductor material containing donor impurities (for example, intrinsic silicon). For example, the N-region 426 may be formed of a silicon material doped with nitrogen, stele, and/or phosphorus impurities. In an exemplary embodiment, the N-region 426 may be formed of a silicon material with donor impurities having a concentration of 10 m atoms/cm 3 to 10 m*atoms/cm 3. In another exemplary embodiment, the N-region 426 may be formed of an undoped semiconductor material (eg, intrinsic silicon).

[0044] The first P+ polysilicon plug 432 and/or the second P+ polysilicon plug 430 may be formed of the same material or different materials. The first P+ polysilicon plug 432 and the second P+ polysilicon plug 430 may be formed of a metal material, a polysilicon material, a silicon dioxide material, and/or a combination thereof. The first P+ polysilicon plug 432 and/or the second P+ polysilicon plug 430 can couple the voltage potential from the source line (EN) 32 and the bit line (CN) 30 to the first P-region 420 of the memory cell 12, respectively And the third P-region 424. In another exemplary embodiment, the first P+ polysilicon plug 432 and/or the second P+ polysilicon plug 430 may be formed of hook, titanium, titanium nitride, polysilicon, or a combination thereof. The first P+ polysilicon plug 432 and/or the second P+ polysilicon plug 430 may have respective extensions from the first P- region 420 and the third P- region 424 to the carrier injection line (EP) 34 and the bit line (CN). ) 30 height.

[0045] The gate region 428 may be formed of polysilicon material, silicon material, metal material, and/or a combination thereof. In another exemplary embodiment, the gate region 428 may be formed of a doped silicon layer. The gate region 428 may be formed of a semiconductor material (for example, silicon) containing acceptor impurities. For example, the gate region 428 may be formed of a silicon material doped with boron impurities.

[0046] The N+ region 434 may be formed of a semiconductor material (for example, silicon) containing donor impurities. For example, the N+ region 434 may be formed of a silicon material doped with nitrogen, stele, and/or phosphorus impurities. In an exemplary embodiment, the N+ region 434 may be formed of a silicon material with donor impurities having a concentration of 10 atoms/cm 3 or higher.

[0047] Referring to FIG. 5, there is shown a cross-sectional view of the memory cell 12 shown in FIG. 1 according to an alternative embodiment of the present invention. The memory cell 12 illustrated in FIG. 5 may be similar to the memory cell 12 illustrated in FIG. 4, except that the memory cell 12 may include multiple undoped regions. The plurality of undoped regions may include a first undoped region 520 coupled to the corresponding first P+ polysilicon plug 432, a second undoped region 522 capacitively coupled to the corresponding gate region 428, and/or It is coupled to the third undoped region 524 corresponding to the second N+ polysilicon plug 430.

[0048] The plurality of undoped regions may be formed of the same material or different materials. For example, the plurality of undoped regions (for example, the first undoped region 420, the second undoped region 422, and/or the third undoped region 424) may be made of undoped semiconductor materials (for example, Intrinsic silicon) is formed.

[0049] Referring to FIG. 6, there is shown a cross-sectional view of at least a portion of the memory cell array 20 shown in FIG. 1 according to an embodiment of the present invention. 6 illustrates a cross-sectional view of at least a portion of the memory cell array 20 along the bit line (CN) 30, and a cross-sectional view of at least a portion of the memory cell array 20 along the word line (WL) 28. The memory cells 12 of the memory cell array 20 may be implemented in a vertical configuration having various regions. For example, the memory cell 12 may include a first N-region 620, a second N-region 622, a third N-region 624, and/or a P+ region 626. The first N-region 620, the second N-region 622, the third N-region 624, and/or the P+ region 626 may be arranged in a continuous adjacent relationship, and may extend vertically from a plane defined by the P-substrate 130. In an exemplary embodiment, the second N-region 622 may be an electrically floating body region of the memory cell 12 configured to accumulate/store charge, and may be spaced apart from and capacitively coupled to a plurality of word lines (WL) 28 To multiple word lines (WL) 28_O

[0050] The first N-region 620 of the memory cell 12 may be coupled to the source line (EN) 32. The second N-region 622 of the memory cell 12 may be capacitively coupled to the word line (WL) 28. The third N-region 624 of the memory cell 12 can be coupled to

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In-position line (CN) 30. The P+ region 626 of the memory cell 12 may be coupled to a carrier injection line (EP) 34.

[0051] The first N-region 620, the second N-region 622, and the third N-region 624 may be formed of the same material or different materials. Also, the first N-region 620, the second N-region 622, and the third N-region 624 may be formed of the same material with various doping concentrations. In an exemplary embodiment, the first N-region 620, the second N-region 622, and the third N-region 624 may be made of a semiconductor material (for example, silicon) containing donor impurities (for example, nitrogen, stele, and/or phosphorous) form. In an exemplary embodiment, the first N-region 620, the second N-region 622, and/or the third N-region 624 may have 10" atoms/cm³To 10 flash atoms/cm ³The concentration of donor impurities is formed of silicon material.

[0052] The P+ region 626 may be formed of at least one layer. In an exemplary embodiment, the P+ region 626 may include multiple layers. For example, the first layer of P+ region 626 may be formed of polysilicon material or silicon dioxide material and/or a combination thereof. In another exemplary embodiment, the first layer of the P+ region 626 may be formed of a semiconductor material including acceptor impurities (for example, intrinsic silicon). For example, the first layer of the P+ region 626 may be formed of a silicon material doped with boron impurities. In an exemplary embodiment, the first layer of the P+ region 626 may be formed of a silicon material with acceptor impurities having a concentration of 10 min atoms/cm 3 or more. The second layer of the P+ region 626 may be formed of a metal material, a polysilicon material, a silicon dioxide material, and/or a combination thereof. In an exemplary embodiment, the second layer of the P+ region 626 may be formed of hooks, titanium, titanium nitride, polysilicon, or a combination thereof.

[0053] The source line (EN) 32 may be formed of a metal material. In another exemplary embodiment, the source line (EN) 32 may be formed of a polysilicon material (for example, a combination of a metal material and a silicon material). In other exemplary embodiments, the source line (EN) 32 may be formed of an N+ doped silicon layer. The source line (EN) 32 may provide a voltage potential to the first N-region 620 of the memory cell 12. For example, the source line (EN) 32 may be coupled to a plurality of memory cells 12 (eg, a column or row of memory cells 12 of the memory cell array 20). The source line (EN) 32 may be configured on the side portion of the first N-region 620.

[0054] The word line (WL) 28 may be capacitively coupled to the second N-region 622. The word line (WL) 28 may be oriented in the row direction of the memory cell array 20 and be coupled to a plurality of memory cells 12. The word line (WL) 28 may be arranged on a side portion of the memory cell 12 (for example, the memory cell 12 located in the row direction of the memory cell array 20). For example, the word line (WL) 28 may be arranged at both side portions of the second N-region 622 of the memory cell 12.

[0055] For example, the word line (WL) 28 may be formed of a polysilicon material (for example, a combination of a metal material and a silicon material), a metal material, and/or a combination of a polysilicon material and a metal material. In another exemplary embodiment, the word line (WL) 28 may be formed of N+ doped silicon material. In an exemplary embodiment, the word line (WL) 28 may capacitively couple the voltage/current source of the memory cell selection and control circuit 38 to the second N-region 622 of the memory cell 12. In an exemplary embodiment, the first word line (WL) 28 may implement a write logic low (eg, binary "0" data state) operation to the memory cell 12, and the second word line (WL) 28 may implement a write Logic high (for example, binary "1" data state) operation.

[0056] The bit line (CN) 30 may be coupled to the third N-region 624 of the memory cell 12. The bit line (CN) 30 may be formed of a metal material. In another exemplary embodiment, the bit line (CN) 30 may be formed of a polysilicon material (for example, a combination of a metal material and a silicon material). In other exemplary embodiments, the bit line (CN) 30 may be formed of an N+ doped silicon layer. For example, the bit line (CN) 30 may be coupled to multiple memory cells 12. The bit line (CN) 30 may be arranged on the side portion of the third N-region 624. In an exemplary embodiment, the bit line (CN) 30 may be configured on a side portion opposite to the source line (EN) 30.

[0057] The oxide layer 128 may be formed on the P-substrate 130. For example, the oxide layer 128 may be formed of an insulating material. In an exemplary embodiment, the oxide layer 128 may be formed of an insulating oxide material. The oxide layer 128 may include a plurality of barrier walls formed of an insulating oxide material. The plurality of barrier walls may be oriented in the column direction and the row direction of the memory cell array 20. For example, the first barrier wall of the plurality of barrier walls may be oriented in the column direction. Multiple barriers

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The second barrier wall can be oriented in the row direction. In an exemplary embodiment, the first barrier walls oriented in the column direction and the second barrier walls oriented in the row direction may cross to form a channel region. The oxide layer 128 may form a channel region, which may have a cross-sectional shape for adapting to one or more of the memory cells 12. For example, the channel region may have a square, rectangular, cylindrical, and/or other cross-sectional shape that can accommodate one or more memory cells 12.

[0058] In an exemplary embodiment, the P-substrate 130 may be manufactured in the form of a P-well substrate. In another exemplary embodiment, the P-substrate 130 may be made of a semiconductor material (for example, silicon) containing acceptor impurities, and may form the base of the memory cell array 20. In an alternative exemplary embodiment, a plurality of P-substrates 130 may form the base of the memory cell array 20, or a single P-substrate 130 may form the base of the memory cell array 20.

[0059] The insulating layer 132 may be formed on the top of the P+ region 626. For example, the insulating layer 132 may be formed of an insulating material, an oxide material, and/or a dielectric material. In an exemplary embodiment, the insulating layer 132 may be formed of a silicon nitride material. The insulating layer 132 may be formed over the P+ region 626 to electrically insulate the P+ region 626.

[0060] Referring to FIG. 7, there is shown a cross-sectional view of at least a portion of the memory cell array 20 shown in FIG. 1 according to an alternative embodiment of the present invention. 7 illustrates a cross-sectional view of at least a portion of the memory cell array 20 along the bit line (CN) 30, and a cross-sectional view of at least a portion of the memory cell array 20 along the word line (WL) 28. The memory cells 12 of the memory cell array 20 can be implemented in a vertical configuration having various regions. For example, the memory cell 12 may include a first N-region 720, a second N-region 722, a third N-region 724, and/or a P+ region 726. The first N-region 720, the second N-region 722, the third N-region 724, and/or the P+ region 726 may be arranged in a continuous adjacent relationship, and may extend vertically from a plane defined by the N+ substrate 130. In an exemplary embodiment, the second N-region 722 may be an electrically floating body region of the memory cell 12 configured to accumulate/store charge, and may be spaced apart from and capacitively coupled to a plurality of word lines (WL) 28 To multiple word lines (WL) 28_O

[0061] The first N-region 720 of the memory cell 12 may be coupled to the source line (EN) 32. The second N-region 722 of the memory cell 12 may be capacitively coupled to the word line (WL) 28. The third N-region 724 of the memory cell 12 may be coupled to the bit line (CN) 30. The P+ region 726 of the memory cell 12 may be coupled to a carrier injection line (EP) 34.

[0062] The first N-region 720, the second N-region 722, and the third N-region 724 may be formed of the same material or different materials. Also, the first N-region 720, the second N-region 722, and the third N-region 724 may be formed of the same material with various doping concentrations. In an exemplary embodiment, the first N-region 720, the second N-region 722, and the third N-region 724 may be formed of a semiconductor material (for example, silicon) containing donor impurities (for example, nitrogen, stele, and/or phosphorous) form. In an exemplary embodiment, the first N-region 720, the second N-region 722, and/or the third N-region 724 may have 10¹⁵Atom/cm³To 10 flash atoms/cm ³The concentration of donor impurities is formed of silicon material.

[0063] The P+ region 726 may be manufactured in the form of a P-well region. In another exemplary embodiment, the P+ region 726 may be made of a semiconductor material (for example, silicon) including acceptor impurities, and may form the base of one or more memory cells 12. For example, the P+ region 726 may form the base of a row or column of memory cells 12 of the memory cell array 20. The P+ region 726 may include a continuous planar region disposed on the N+ substrate 130. The P+ region 726 may also include a plurality of barrier walls formed on the continuous planar region. The multiple barrier walls of the P+ region 726 may be oriented in the column direction and/or the row direction of the memory cell array 20.

[0064] The source line (EN) 32 may be formed of at least one layer. In an exemplary embodiment, the source line (EN) 32 may include multiple layers. For example, the first layer of the source line (EN) 32 may be formed of polysilicon material or silicon dioxide material and/or a combination thereof. In another exemplary embodiment, the first layer of the source line (EN) 32 may be made of a semiconductor material containing donor impurities (e.g.

CN 102812552 Β

For example, intrinsic silicon) is formed. For example, the first layer of the source line (EN) 32 may be formed of a silicon material doped with nitrogen, a stele, and/or phosphorus impurities. In an exemplary embodiment, the first layer of the source line (EN) 32 may be formed of a silicon material with acceptor impurities having a concentration of 10 min atoms/cm 3 or more. The second layer of the source line (EN) 32 may be formed of a metal material, a polysilicon material, a silicon dioxide material, and/or a combination thereof. In an exemplary embodiment, the second layer of the source line (EN) 32 may be formed of hook, titanium, titanium nitride, polysilicon, or a combination thereof. For example, the source line (EN) 32 may be coupled to a plurality of memory cells 12 (eg, a column or row of memory cells 12 of the memory cell array 20). The source line (EN) 32 may be arranged above the first N-region 720.

[0065] The word line (WL) 28 may be capacitively coupled to the second N-region 722. The word line (WL) 28 may be oriented in the row direction of the memory cell array 20 and be coupled to a plurality of memory cells 12. The word line (WL) 28 may be arranged on a side portion of the memory cell 12 (for example, the memory cell 12 located in the row direction of the memory cell array 20). For example, the word line (WL) 28 may be arranged at both side portions of the second N-region 722 of the memory cell 12.

[0066] For example, the word line (WL) 28 may be formed of a polysilicon material (for example, a combination of a metal material and a silicon material), a metal material, and/or a combination of a polysilicon material and a metal material. In another exemplary embodiment, the word line (WL) 28 may be formed of N+ doped silicon material. In an exemplary embodiment, the word line (WL) 28 may capacitively couple the voltage potential/current source of the memory cell selection and control circuit 38 to the second N-region 722 of the memory cell 12. In an exemplary embodiment, the first word line (WL) 28 may implement a write logic low (eg, binary "0" data state) operation to the memory cell 12, and the second word line (WL) 28 may implement a write Logic high (for example, binary "1" data state) operation. [0067] The bit line (CN) 30 may be coupled to the third N-region 724 of the memory cell 12. The bit line (CN) 30 may be formed of a metal material. In another exemplary embodiment, the bit line (CN) 30 may be formed of a polysilicon material (for example, a combination of a metal material and a silicon material). In other exemplary embodiments, the bit line (CN) 30 may be formed of an N+ doped silicon layer. For example, the bit line (CN) 30 may be coupled to multiple memory cells 12. The bit line (CN) 30 may be arranged on the side portion of the third N-region 724.

[0068] The oxide layer 128 may be formed on the P+ region 726 and/or the N+ substrate 130. For example, the oxide layer 128 may be formed of an insulating material. In an exemplary embodiment, the oxide layer 128 may be formed of an insulating oxide material. The oxide layer 128 may include a plurality of barrier walls formed of an insulating oxide material. The plurality of barrier walls may be oriented in the column direction and the row direction of the memory cell array 20. For example, the first barrier wall of the plurality of barrier walls may be oriented in the column direction. The second barrier wall of the plurality of barrier walls may be oriented in the row direction. The first barrier wall oriented in the column direction may have a different height from the second barrier wall oriented in the row direction. In an exemplary embodiment, the first barrier walls oriented in the column direction and the second barrier walls oriented in the row direction may cross to form a channel region. The oxide layer 128 may form a channel region, which may have a cross-sectional shape for adapting to one or more of the memory cells 12. For example, the channel region may have a square, rectangular, cylindrical, and/or other cross-sectional shape that can accommodate one or more memory cells 12.

[0069] In an exemplary embodiment, the N+ substrate 130 may be manufactured in the form of an N-well substrate. In another exemplary embodiment, the N+ substrate 130 may be made of a semiconductor material (for example, silicon) including donor impurities, and may form the base of the memory cell array 20. In an alternative exemplary embodiment, a plurality of N+ substrates 130 may form the base of the memory cell array 20, or a single N+ substrate 130 may form the base of the memory cell array 20.

[0070] The insulating layer 132 may be formed on the top of the first N-region 720. For example, the insulating layer 132 may be formed of an insulating material, an oxide material, and/or a dielectric material. In an exemplary embodiment, the insulating layer 132 may be formed of a silicon nitride material. The insulating layer 132 may be formed over the first N-region 720 to electrically insulate the source line (EN) 32.

CN 102812552 Β

[0071] Referring to FIG. 8, there is shown a cross-sectional view of at least a portion of the memory cell array 20 shown in FIG. 1 according to an embodiment of the present invention. FIG. 8 illustrates a cross-sectional view of at least a portion of the memory cell array 20 along the bit line (CN) 30 and a cross-sectional view of at least a portion of the memory cell array 20 along the word line (WL) 28. The memory cells 12 of the memory cell array 20 can be implemented in a vertical configuration having various regions. For example, the memory cell 12 may include a first P-region 820, a second P-region 822, a third P-region 824, and/or an N+ region 826. The first P-region 820, the second P-region 822, the third P-region 824, and/or the N+ region 826 may be arranged in a continuous adjacent relationship, and may extend vertically from a plane defined by the N+ substrate 130. In an exemplary embodiment, the second P-region 822 may be an electrically floating body region of the memory cell 12 configured to accumulate/store charge, and may be spaced apart from and capacitively coupled to a plurality of word lines (WL) 28 To multiple word lines (WL) 28_O

[0072] The first P-region 820 of the memory cell 12 may be coupled to the source line (EN) 32. The second P-region 822 of the memory cell 12 may be capacitively coupled to the word line (WL) 28. The third P-region 824 of the memory cell 12 may be coupled to the bit line (CN) 30. The N+ region 826 of the memory cell 12 may be coupled to a carrier injection line (EP) 34.

[0073] The first P-region 820, the second P-region 822, and the third P-region 824 may be formed of the same material or different materials. Also, the first P-region 820, the second P-region 822, and the third P-region 824 may be formed of the same material with various doping concentrations. In an exemplary embodiment, the first P-region 820, the second P-region 822, and the third P-region 824 may be formed of a semiconductor material (for example, silicon) including acceptor impurities. The first P-region 820, the second P-region 822, and/or the third P-region 824 may be formed of a silicon material doped with boron impurities. In an exemplary embodiment, the first P-region 820, the second P-region 822, and/or the third P-region 824 may have a concentration of 10 atoms/cm to 10 flash atoms/cm%. The main impurity silicon material is formed.

[0074] The N+ region 826 may be formed of at least one layer. In an exemplary embodiment, the N+ region 826 may include multiple layers. For example, the first layer of the N+ region 826 may be formed of polysilicon material or silicon dioxide material and/or a combination thereof. In another exemplary embodiment, the first layer of the N+ region 826 may be formed of a semiconductor material including donor impurities (for example, intrinsic silicon). For example, the first layer of the N+ region 826 may be formed of a silicon material doped with boron impurities. In an exemplary embodiment, the first layer of the N+ region 826 may be formed of a silicon material with donor impurities having a concentration of 10 min atoms/cm or more. The second layer of the N+ region 826 may be formed of a metal material, a polysilicon material, a silicon dioxide material, and/or a combination thereof. In an exemplary embodiment, the second layer of the N+ region 826 may be formed of hooks, titanium, titanium nitride, polysilicon, or a combination thereof.

[0075] The source line (EN) 32 may be formed of a metal material. In another exemplary embodiment, the source line (EN) 32 may be formed of a polysilicon material (for example, a combination of a metal material and a silicon material). In other exemplary embodiments, the source line (EN) 32 may be formed of a P+ doped silicon layer. The source line (EN) 32 may provide a voltage potential to the first P-region 820 of the memory cell 12. For example, the source line (EN) 32 may be coupled to a plurality of memory cells 12 (eg, a column or row of memory cells 12 of the memory cell array 20). The source line (EN) 32 may be arranged on the side portion of the first P-region 820.

[0076] The word line (WL) 28 may be capacitively coupled to the second P-region 822. The word line (WL) 28 may be oriented in the row direction of the memory cell array 20 and be coupled to a plurality of memory cells 12. The word line (WL) 28 may be arranged on a side portion of the memory cell 12 (for example, the memory cell 12 located in the row direction of the memory cell array 20). For example, the word line (WL) 28 may be arranged at both side portions of the second P-region 822 of the memory cell 12.

[0077] For example, the word line (WL) 28 may be formed of a polysilicon material (for example, a combination of a metal material and a silicon material), a metal material, and/or a combination of a polysilicon material and a metal material. In another exemplary embodiment, the word line (WL) 28 may be formed of P+ doped silicon material. In an exemplary embodiment, the word line (WL) 28 can select memory cells and

CN 102812552 Β

The voltage/current source of the control circuit 38 is capacitively coupled to the second P-region 822 of the memory cell 12. In an exemplary embodiment, the first word line (WL) 28 arranged on the side portion of the second P-region 822 may implement a write logic low (for example, binary "0" data state) operation to the memory cell 12, The second word line (WL) 28 arranged on the opposite side portion of the second P-region 822 can implement a write logic high (for example, a binary "1" data state) operation.

[0078] The bit line (CN) 30 may be coupled to the third P-region 824 of the memory cell 12. The bit line (CN) 30 may be formed of a metal material. In another exemplary embodiment, the bit line (CN) 30 may be formed of a polysilicon material (for example, a combination of a metal material and a silicon material). In other exemplary embodiments, the bit line (CN) 30 may be formed of a P+ doped silicon layer. For example, the bit line (CN) 30 may be coupled to multiple memory cells 12. The bit line (CN) 30 may be arranged on the side portion of the third P-region 824. In an exemplary embodiment, the bit line (CN) 30 may be configured on a side portion opposite to the source line (EN) 30.

[0079] The oxide layer 128 may be formed on the N+ substrate 130. For example, the oxide layer 128 may be formed of an insulating material. In an exemplary embodiment, the oxide layer 128 may be formed of an insulating oxide material. The oxide layer 128 may include a plurality of barrier walls formed of an insulating oxide material. The plurality of barrier walls may be oriented in the column direction and the row direction of the memory cell array 20. For example, the first barrier wall of the plurality of barrier walls may be oriented in the column direction. The second barrier wall of the plurality of barrier walls may be oriented in the row direction. In an exemplary embodiment, the first barrier walls oriented in the column direction and the second barrier walls oriented in the row direction may cross to form a channel region. The oxide layer 128 may form a channel region, which may have a cross-sectional shape for adapting to one or more of the memory cells 12. For example, the channel region may have a square, rectangular, cylindrical, and/or other cross-sectional shape that can accommodate one or more memory cells 12.

[0080] In an exemplary embodiment, the N+ substrate 130 may be manufactured in the form of an N-well substrate. In another exemplary embodiment, the N+ substrate 130 may be made of a semiconductor material (for example, silicon) including donor impurities, and may form the base of the memory cell array 20. In an alternative exemplary embodiment, a plurality of N+ substrates 130 may form the base of the memory cell array 20, or a single N+ substrate 130 may form the base of the memory cell array 20.

[0081] The insulating layer 132 may be formed on the top of the N+ region 826. For example, the insulating layer 132 may be formed of an insulating material, an oxide material, and/or a dielectric material. In an exemplary embodiment, the insulating layer 132 may be formed of a silicon nitride material. The insulating layer 132 may be formed over the N+ region 826 to electrically insulate the N+ region 826.

[0082] Referring to FIG. 9, there is shown a cross-sectional view of at least a portion of the memory cell array 20 shown in FIG. 1 according to an alternative embodiment of the present invention. 9 illustrates a cross-sectional view of at least a portion of the memory cell array 20 along the bit line (CN) 30, and a cross-sectional view of at least a portion of the memory cell array 20 along the word line (WL) 28. The memory cells 12 of the memory cell array 20 may be implemented in a vertical configuration having various regions. For example, the memory cell 12 may include a first P-region 920, a second P-region 922, a third P-region 924, and/or an N+ region 926. The first P-region 920, the second P-region 922, the third P-region 924, and/or the N+ region 926 may be arranged in a continuous adjacent relationship, and may extend vertically from a plane defined by the P+ substrate 130. In an exemplary embodiment, the second P-region 922 may be an electrically floating body region of the memory cell 12 configured to accumulate/store charge, and may be spaced apart from and capacitively coupled to a plurality of word lines (WL) 28 To multiple word lines (WL) 28_O

[0083] The first P-region 920 of the memory cell 12 may be coupled to the bit line (CN) 30 _oThe second P-region 922 of the memory cell 12 may be capacitively coupled to the word line (WL) 28. The third P-region 924 of the memory cell 12 may be coupled to the source line (EN) 32. The N+ region 926 of the memory cell 12 may be coupled to a carrier injection line (EP) 34.

[0084] The first P-region 920, the second P-region 922, and the third P-region 924 may be formed of the same material or different materials. In addition, the first P-region 920, the second P-region 922, and the third P-region 924 can have various doping concentrations.

CN 102812552 Β

Of the same material. In an exemplary embodiment, the first P-region 920, the second P-region 922, and the third P-region 924 may be formed of a semiconductor material (eg, silicon) including acceptor impurities. For example, the first P-region 920, the second P-region 922, and/or the third P-region 924 may be formed of a silicon material doped with boron impurities. In an exemplary embodiment, the first P-region 920, the second P-region 922, and/or the third P-region 924 may be provided with a receiver having a concentration of 10 "atoms/cm"*atoms/cm 3 The main impurity silicon material is formed.

[0085] The N+ region 926 may be manufactured in the form of an N-well region. In another exemplary embodiment, the N+ region 926 may be made of a semiconductor material (for example, silicon) including donor impurities, and may form the base of one or more memory cells 12. For example, the N+ region 926 may form the base of a row or column of memory cells 12 of the memory cell array 20. The N+ region 926 may include a continuous planar region disposed above the P+ substrate 130. The N+ region 926 may also include a plurality of barrier walls formed on the continuous planar region. The plurality of barrier walls of the N+ region 926 may be oriented in the column direction and/or the row direction of the memory cell array 20.

[0086] The bit line (CN) 30 may be formed of at least one layer. In an exemplary embodiment, the bit line (CN) 30 may include multiple layers. For example, the first layer of the bit line (CN) 32 may be formed of polysilicon material or silicon dioxide material and/or a combination thereof. In another exemplary embodiment, the first layer of the bit line (CN) 30 may be formed of a semiconductor material including donor impurities (for example, intrinsic silicon). For example, the first layer of the bit line (CN) 30 may be formed of a silicon material doped with nitrogen, a stele, and/or phosphorus impurities. In an exemplary embodiment, the first layer of the bit line (CN) 30 may be formed of a silicon material with donor impurities having a concentration of 10 min atoms/cm 3 or more. The second layer of the bit line (CN) 30 may be formed of a metal material, a polysilicon material, a silicon dioxide material, and/or a combination thereof. In an exemplary embodiment, the second layer of the bit line (CN) 30 may be formed of hooks, titanium, titanium nitride, polysilicon, or a combination thereof. For example, the bit line (CN) 30 may be coupled to a plurality of memory cells 12 (eg, a column or row of memory cells 12 of the memory cell array 20). The bit line (CN) 30 may be arranged above the first P-region 920.

[0087] The word line (WL) 28 may be capacitively coupled to the second P-region 922. The word line (WL) 28 may be oriented in the row direction of the memory cell array 20 and be coupled to a plurality of memory cells 12. The word line (WL) 28 may be arranged on a side portion of the memory cell 12 (for example, the memory cell 12 located in the row direction of the memory cell array 20). For example, the word line (WL) 28 may be arranged at both side portions of the second P-region 922 of the memory cell 12.

[0088] For example, the word line (WL) 28 may be formed of a polysilicon material (for example, a combination of a metal material and a silicon material), a metal material, and/or a combination of a polysilicon material and a metal material. In another exemplary embodiment, the word line (WL) 28 may be formed of N+ doped silicon material. In an exemplary embodiment, the word line (WL) 28 may capacitively couple the voltage potential/current source of the memory cell selection and control circuit 38 to the second P-region 922 of the memory cell 12. In an exemplary embodiment, the first word line (WL) 28 may implement a write logic low (for example, binary "0" data state) operation to the memory cell 12, and the second word line (WL) 28 may implement write Logic high (for example, binary "1" data state) operation. [0089] The source line (EN) 32 may be coupled to the third P-region 924 of the memory cell 12. The source line (EN) 32 may be formed of a metal material. In another exemplary embodiment, the source line (EN) 32 may be formed of a polysilicon material (for example, a combination of a metal material and a silicon material). In other exemplary embodiments, the source line (EN) 32 may be formed of a P+ doped silicon layer. For example, the source line (EN) 32 may be coupled to a plurality of memory cells 12. The source line (EN) 32 may be arranged on the side portion of the third P-region 924.

[0090] The oxide layer 128 may be formed on the N+ region 926 and/or the P+ substrate 130. For example, the oxide layer 128 may be formed of an insulating material. In an exemplary embodiment, the oxide layer 128 may be formed of an insulating oxide material. The oxide layer 128 may include a plurality of barrier walls formed of an insulating oxide material. The plurality of barrier walls may be oriented in the column direction and the row direction of the memory cell array 20. For example, the first barrier wall of the plurality of barrier walls can be defined in the column direction.

CN 102812552 Β

Towards. The second barrier wall of the plurality of barrier walls may be oriented in the row direction. The first barrier wall oriented in the column direction may have a different height from the second barrier wall oriented in the row direction. In an exemplary embodiment, the first barrier walls oriented in the column direction and the second barrier walls oriented in the row direction may cross to form a channel region. The oxide layer 128 may form a channel region, which may have a cross-sectional shape for adapting to one or more of the memory cells 12. For example, the channel region may have a square, rectangular, cylindrical, and/or other cross-sectional shape that can accommodate one or more memory cells 12.

[0091] In an exemplary embodiment, the P+ substrate 130 may be manufactured in the form of a P-well substrate. In another exemplary embodiment, the P+ substrate 130 may be made of a semiconductor material (for example, silicon) including acceptor impurities, and may form the base of the memory cell array 20. In an alternative exemplary embodiment, a plurality of P+ substrates 130 may form the base of the memory cell array 20, or a single P+ substrate 130 may form the base of the memory cell array 20.

[0092] The insulating layer 132 may be formed on the top of the first P-region 920. For example, the insulating layer 132 may be formed of an insulating material, an oxide material, and/or a dielectric material. In an exemplary embodiment, the insulating layer 132 may be formed of a silicon nitride material. The insulating layer 132 may be formed over the first P-region 920 to electrically insulate the bit line (CN) 30.

[0093] Referring to FIG. 10, there is shown a control signal voltage waveform used to perform a write operation on the memory cell 12 shown in FIG. 2 according to an embodiment of the present invention. For example, various control signals may be configured to perform write logic low (eg, binary "0" data state) operations and/or write logic high (eg, binary "1" data state) operations. In an exemplary embodiment, various control signals may be applied to the memory cells 12 to perform one or more write logic lows (eg, binary "0" data state) to one or more selected memory cells 12 operate. For example, a write logic low (for example, binary "0" data state) operation may be performed to one or more selected memory cells 12, so as to consume as much as possible has been accumulated/stored in the one or more selected memory cells 12 Of charge carriers in the floating body region of the memory cell 12. Various voltage potentials can be applied to various regions of the memory cell 12. In an exemplary embodiment, the voltage potential applied to the first N-region 120, the third N-region 124, and/or the P-region 126 may be maintained at 0 V. The voltage potential applied to the second N-region 122 may be capacitively coupled. The voltage potential of the word line (WL) 28 can rise from the voltage potential applied during the sustain operation. In an exemplary embodiment, the voltage potential applied to the word line (WL) 28 that may be capacitively coupled to the second N-region 122 may rise to -0.5V.

[0094] Under this bias, the junction between the first N-region 120 and the second N-region 122 and the junction between the second N-region 122 and the third N-region 124 can be forward biased . The junction between the third N-region 124 and the P-region 126 may be reverse-biased or weakly forward-biased (for example, above the reverse-bias voltage and below the forward-bias threshold voltage potential). Down). The hole charge carriers that may have accumulated/stored in the second N-region 122 may flow to the first N-region 120 and/or the third N-region 124. Therefore, the hole charge carriers that may have accumulated/stored in the second N-region 122 may be depleted through the first N-region 120 and/or the third N-region 124. By removing hole charge carriers that may have accumulated/stored in the second N-region 122, a logic low (for example, a binary "0" data state) can be written to the memory cell 12.

[0095] After performing a write logic low (e.g., binary "0" data state) operation, the control signal may be configured to perform a hold operation in order to maintain the data state stored in the memory cell 12 (e.g., logic high (binary "1" data status)). In particular, the control signal may be configured to perform a hold operation in order to maximize the hold time of the data state (eg, logic low (binary "0" data state)) stored in the memory cell 12. Also, the control signal for maintaining operation can be configured to eliminate or reduce activity or fields within the memory cell 12 (eg, electric fields between junctions that can cause charge leakage). In an exemplary embodiment, during the holding operation, a negative voltage potential may be applied to the

CN 102812552 Β

Capacitively coupled to the word line (WL) 28 of the second N-region 122 of the memory cell 12, while a constant voltage potential can be applied to the first N-region 120 via the source line (EN) 32, via the bit line ( CN) 30 is applied to the third N-region 124 and/or applied to the P-region 126 via the carrier injection line (EP) 34, and can be maintained at OVo

[0096] For example, the negative voltage potential applied to the word line (WL) 28 (eg, capacitively coupled to the P-region 122 of the memory cell 12) can be -2. OVo can be reversed during the hold operation The junction between the first N-region 120 and the second N-region 122 and the junction between the third N-region 124 and the second N-region 122 are biased to maintain the state of the data stored in the memory cell 12 ( For example, logic high (binary "1" data state) or logic low (binary "0" data state)).

[0097] In another exemplary embodiment, the control signal may be configured to write a logic high (eg, a binary "1" data state) to one or more selected rows of the memory cell array 20. More than one selected memory cell 12. For example, a write logic high (for example, binary "1" data state) operation may be performed on one or more selected rows of the memory cell array 20 or the entire memory cell array 20. In another exemplary embodiment, the write logic high (eg, binary "1" data state) operation may have a control signal configured to cause hole charge carriers to be accumulated/stored in the second N-region 122 .

[0098] In an exemplary embodiment, the voltage potential applied to the first N-region 120 of the memory cell 12 via the source line (EN) 32 and the voltage potential applied to the third N-region 124 via the bit line (CN) 30 The voltage potential can be maintained at the same voltage potential as the voltage potential during the sustain operation. For example, the voltage potential applied to the first N-region 120 via the source line (EN) 32 and the third N-region 124 via the bit line (CN) 30 may be maintained at 0V. The voltage potential applied to the word line (WL) 28 that can be capacitively coupled to the second N-region 122 can also be maintained at the same voltage potential as the voltage potential during the hold operation. For example, the voltage potential applied to the word line (WL) 28 that can be capacitively coupled to the second N-region 122 can be maintained at -2. OVo

[0099] The voltage potential applied to the P-region 126 via the carrier injection line (EP) 34 may rise from the voltage potential applied during the holding operation. In an exemplary embodiment, the voltage potential applied to the P-region 126 via the carrier injection line (EP) 34 may rise from 0V to about 0.7V to 0.9V_O

[0100] Under this bias, the junction between the third N-region 124 and the P-region 126 can become forward biased. For example, most charge carriers (for example, holes) can flow from the P-region 126 to the second N-region 122 via the third N-region 124. Therefore, a predetermined amount of hole charge carriers can be accumulated/stored in the N-region 122 through the P+ region 126 and the third N-region 124. A predetermined amount of charge carriers accumulated/stored in the second N-region 122 (for example, capacitively coupled to the word line (WL) 28) may indicate a logic high (for example, a binary "1" data state) may be Write in the memory unit 12.

[0101] Referring to FIG. 11, there is shown a control signal voltage waveform used to perform a read operation on the memory cell 12 shown in FIG. 2 according to an embodiment of the present invention. In an exemplary embodiment, the control signal may be configured to perform a data state (e.g., logic low) stored in one or more selected memory cells 12 of one or more selected rows of the memory cell array 20 (Binary "0" data state) and/or logic high (binary "1" data state)) read operations.

[0102] The control signal may be configured to a predetermined voltage potential to implement a read operation via the bit line (CN) 30. In an exemplary embodiment, the voltage potential applied to the first N-region 120 via the source line (EN) 32 and the voltage potential applied to the P-region 126 via the carrier injection line (EP) 34 may be maintained at 0V. The voltage potential applied to the word line (WL) 28 that can be capacitively coupled to the second N-region 122 and the voltage potential applied to the third N-region 124 can be changed from the holding operation period

CN 102812552 Β

The applied voltage potential rises. In an exemplary embodiment, the voltage potential applied to the word line (WL) 28 that can be capacitively coupled to the second N-region 122 can be raised from -2.0V to -1.0V via the bit line (CN) 30 The voltage potential applied to the third N-region 124 can rise from 0V to 1.0V_o

[0103] Under this bias, when a logic low (for example, a binary "0" data state) is stored in the memory cell 12, a predetermined amount of accumulated/stored in the second N-region 122 during the hold operation Hole charge carriers can flow to the third N-region 124. A predetermined amount of hole charge carriers flowing to the third N-region 124 may cause injection of electron charge carriers from the third N-region 124. The injection of electronic charge carriers from the third N-region 124 can cause current spikes and can change the voltage potential on the bit line (CN) 30. The data sensing amplifier in the data writing and sensing circuit 36 can detect a small amount of voltage potential or current (for example, compared with the reference voltage potential or current via the bit line (CN) 30 coupled to the third N-region 124). Compared) or no voltage potential or current can be detected.

[0104] When a logic high (for example, a binary "1" data state) is stored in the memory cell 12, a predetermined amount of hole charge carriers (for example, which is accumulated/stored in the second N-region 122) It may indicate that a logic high (for example, a binary "1" data state) may flow to the third N-region 124. The predetermined amount of hole charge carriers injected into the third N-region 124 may also cause electron charge carriers to be injected into the third N-region 124. The injection of electron charge carriers into the third N-region 124 can cause a current spike and can change the voltage potential on the bit line (CN) 30. The data sensing amplifier in the data writing and sensing circuit 36 can detect the generated voltage potential or current (for example, compared with a reference voltage potential or current) via the bit line (CN) 30.

[0105] Here, it should be noted that the technology provided for providing the semiconductor memory device according to the present invention as described above generally involves the processing of input data and the generation of output data to some extent. This input data processing and output data generation can be implemented in hardware or software. For example, certain electronic components may be used in a semiconductor memory device or similar or related circuits for implementing functions associated with providing a semiconductor memory device according to the present invention as described above. Alternatively, one or more processors operating in accordance with instructions may implement functions associated with providing semiconductor memory devices according to the present invention as described above. If this is the case, it is within the scope of the present invention that such instructions may be stored on one or more processor-readable media (for example, disks or other storage media), or may be embodied in one or more One or more signals in the carrier wave are transmitted to one or more processors.

[0106] The scope of the present invention should not be limited by the specific embodiments described herein. Rather, in addition to those described herein, those skilled in the art will easily understand other various embodiments of the present invention and modifications to the present invention from the foregoing description and drawings. Therefore, these other embodiments and modifications are intended to fall within the scope of the present invention. In addition, although the present invention has been described herein for a specific purpose in a specific environment in the context of a specific embodiment, those skilled in the art will recognize that the usefulness of the present invention is not limited thereto, and the present invention can be It is advantageously implemented in any number of environments for any number of purposes. Therefore, the appended claims should be understood in the context of the entire breadth and spirit of the invention as described herein.

CN 102812552 Β