Transistor with controllable compensation regions

Technical field of transistors with controllable compensation area

[0001] Embodiments of the present invention relate to transistors, and more particularly, to a MOS transistor with a compensation region.

Background technique

[0002] MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), especially power MOSFETs, are widely used as electronic switches for switching electric loads or as electronic switches in various switching converters. The power MOSFET includes a drain region each having a first conductivity type, a drift region adjacent to the drain region, a source region, and a body region of the second conductivity type arranged between the drift region and the source region. The gate electrode is used to control the conductive channel in the body region between the source region and the drift region. The source electrode is electrically connected to the source electrode also connected to the body region, and the drain region is electrically connected to the drain electrode. The MOSFET can be turned on or off by applying an appropriate driving potential to the gate terminal.

[0003] In a specific type of MOSFET (which is also called a compensation type or a super junction MOSFET), the compensation region is configured in the drift region. The compensation region has the same doping type as the body region and is electrically connected to the body region. The compensation region includes doping charges, which supplement the doping charges in the drift region, and when the MOSFET is in an off state, the doping charges "compensate" the doping charges in the drift region. Thanks to the compensation region, the drift region can be more highly doped than conventional MOSFETs, which makes the on-resistance lower for a given voltage blocking capability (blocking capability).

[0004] A MOSFET includes a voltage-dependent output capacitance (commonly referred to as Coss), which usually includes a drain-source capacitance Cds between its drain terminal and a source terminal, and a gate-drain capacitance between its gate terminal and drain terminal. Cgd. When the MOSFET transitions from the on state to the off state, the output capacitor is charged, that is, energy is stored in the output capacitor; when the MOSFET transitions from the off state to the on state, the output capacitor is discharged. The output energy Eoss (which is the energy stored in the output capacitor) mainly depends on the voltage on the drain-source path when the MOSFET is in its off state and on the capacitance value of the output capacitor. The compensation type MOSFET has a high drain-to-source capacitance because it is connected to the compensation area of the body area and the source electrode, and therefore, has a high output capacitance.

[0005] Losses occur when the MOSFET is operating. These losses mainly include (a) capacitance loss and (b) ohmic loss.

[0006] (a) Capacitance losses are defined by the energy stored in the output capacitance of the MSOFET, where these losses increase as the output capacitance increases. In many applications, under normal load conditions, capacitive losses dominate the switching losses.

[0007] (b) When the MOSFET is in its on state, ohmic loss occurs. The ohmic loss is due to the on-resistance of the MOSFET. In addition, when the MOSFET is switched from the on-state to the off-state, switching losses occur, and vice versa. These switching losses are caused by the fact that the MOSFET will not be turned on or off suddenly, but gradually in the on state (the ohmic resistance of the MOSFET is at a minimum in this state) and the off state (the MOSFET is blocked and connected Prevent current) from changing. The minimum value of the ohmic resistance is the on-resistance.

[0008] The ohmic loss is proportional to the square of the load current, and the capacitive loss has a smaller load current dependency. Therefore, depending on the specific load conditions, ohmic loss or capacitive loss may be dominant. For example, when the load connected to the MOSFET draws a low load current so that the low current flows through the on-state MOSFET, the capacitance loss can mainly determine the total loss. However, when the load draws a high load current, the ohmic loss and switching loss during the transition phase can mainly determine the total loss. The switching loss and capacitance loss during the conversion phase are directly proportional to the switching frequency of the device.

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[0009] In addition, the output charge Qoss, which is the charge stored in the output capacitor, is important for some applications. For example, the turn-off delay time of a MOSFET at low load current is dominated by the output charge. This is the charge that has to be stored in the output capacitor before the transistor is completely turned off. The output charge is provided by the load current. Therefore, the turn-off delay time increases inversely proportional to the reduced load current.

[0010] Therefore, there is a need to provide a MOSFET with a compensation region in which loss and turn-off delay time can be minimized depending on load conditions.

Summary of the invention

[0011] The first aspect relates to a semiconductor device including at least one transistor unit, in particular, a MOSFET. The transistor unit includes a source region, a drain region, a body region, and a drift region in a semiconductor body, wherein the body region is configured between the source region and the drain region, and the drift region is configured Between the body region and the drain region. The transistor unit further includes: a compensation region, which is configured in the drift region; a source electrode, which is in electrical contact with the source region and the body region; and a gate electrode, which is configured to be adjacent to the body region and passes through a gate dielectric Dielectrically insulated from the body region; the coupling configuration includes a control terminal, and is configured to electrically couple the compensation region to the body region, the source region, and the compensation region according to the control signal received at the control terminal At least one of the source electrode and the gate electrode.

[0012] The second aspect relates to a semiconductor device including at least one transistor cell of the first type and at least one transistor cell of the second type, in particular, a MOSFET.

[0013] The at least one transistor cell of the first type includes: a first source region, a first drain region, a first body region, and a first drift region, wherein the first body region is configured in the first Between the source region and the first drift region, and the first drift region is arranged between the first body region and the first drain region. The at least one transistor unit of the first type further includes: a first gate electrode configured to be adjacent to the first body region and dielectrically insulated from the first body region by the first gate dielectric; and a first source electrode , Electrically contacting the first source region and the first body region; a first compensation region, configured in the first drift region, and electrically connected to the first body region and the first source region And at least one of the first gate electrodes.

[0014] The at least one second type transistor cell includes: a second drain region, a second body region, and a second drift region, wherein the second drift region is configured in the second body region and the Between the second drain regions; the second compensation region is configured in the second drift region and has a distance from the second body region, and the second source electrode is in electrical contact with the second body region. The at least one second type of transistor unit further includes a coupling configuration, including a control terminal, and is configured to electrically couple the second compensation area to the second compensation area according to a control signal received at the control terminal At least one of the body region and the second source electrode.

[0015] The third aspect relates to a semiconductor device that includes a gate terminal, at least one control terminal, and first and second load terminals, and includes at least one device unit. The at least one device unit includes: a MOSFET device having a load path and a control terminal, the control terminal is coupled to the gate terminal; a JFET device having a load path and a control terminal, the load path is connected in series with the load path of the MOSFET device Connected between the load terminals; a first coupling transistor having a load path and a control terminal, the load path is coupled between one of the source terminal and the gate terminal and the control terminal of the JFET device, and The control terminal is coupled to the at least one control terminal of the transistor device.

Description of the drawings

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[0016] The embodiments will be explained with reference to the drawings. The drawings are used to illustrate the basic principles, so only the aspects necessary for understanding the basic principles are shown. The drawings are not shown to scale. In the drawings, the same reference numerals indicate similar features.

[0017] FIG. 1 schematically shows that a MOSFET is used as an electronic switch for switching a load;

[0018] FIG. 2 schematically shows the voltage dependence of the output capacitance of the MOSFET;

[0019] FIG. 3 schematically shows a vertical cross-sectional view of a MOSFET including a coupling configuration coupled between a compensation region and a source electrode;

[0020] FIG. 4 schematically shows a vertical cross-sectional view of a MOSFET including a plurality of transistor cells;

[0021] FIG. 5 schematically shows a horizontal cross-sectional view of a MOSFET implemented with elongated transistor cells;

[0022] FIG. 6 schematically shows a horizontal cross-sectional view of a MOSFET implemented with rectangular transistor cells;

[0023] FIG. 7 schematically shows a horizontal cross-sectional view of a MOSFET implemented with hexagonal or polygonal transistor cells;

[0024] FIG. 8 schematically shows a vertical cross-sectional view of a MOSFET including a coupling configuration with a control electrode;

[0025] FIG. 9 shows a horizontal cross-sectional view of the MOSFET according to FIG. 8 when implemented with elongated transistor cells;

[0026] FIG. 10 shows a horizontal cross-sectional view of the MOSFET according to FIG. 8 when implemented with rectangular transistor cells;

[0027] FIG. 11 shows a horizontal cross-sectional view of the MOSFET according to FIG. 8 when implemented with hexagonal transistor cells;

[0028] FIG. 12 shows a horizontal cross-sectional view of the MOSFET according to FIG. 8 when implemented with rectangular transistor cells and strip-shaped control electrodes;

[0029] FIG. 13 shows a horizontal cross-sectional view of the MOSFET according to FIG. 8 when implemented with elongated transistor cells and rectangular control electrodes;

[0030] FIG. 14 schematically shows a perspective cross-sectional view of a transistor unit including a MOSFET having a coupling configuration of a control electrode, a connection electrode, and a contact electrode;

[0031] FIG. 15 schematically shows a vertical cross-sectional view of the transistor cell of section CC of FIG. 14;

[0032] FIG. 16 schematically shows a perspective cross-sectional view of a transistor unit of a MOSFET according to another embodiment;

[0033] FIG. 17 schematically shows a perspective cross-sectional view of a conventional transistor unit;

[0034] FIG. 18 schematically shows a first embodiment in which a transistor unit having a coupling configuration and a conventional transistor unit are configured in a semiconductor body;

[0035] FIG. 19 schematically shows a second embodiment in which a transistor unit having a coupling configuration and a conventional transistor unit are configured in a semiconductor body;

[0036] FIG. 20 schematically shows a vertical cross-sectional view of a transistor cell including a compensation region and a coupling configuration and not including a channel region;

[0037] FIG. 21 shows a circuit diagram of a MOSFET including a transistor cell having a coupling configuration and a conventional transistor cell according to the first embodiment;

[0038] FIG. 22 shows a circuit diagram of a MOSFET including a transistor cell having a coupling configuration and a conventional transistor cell according to the second embodiment;

[0039] FIG. 23 schematically shows a vertical cross-sectional view of a MOSFET including a coupling configuration connected between a compensation region and a source electrode according to another embodiment;

[0040] FIG. 24 shows a vertical cross-sectional view of a MOSFET including a coupling configuration with a JFET located between a compensation region and a source electrode according to the first embodiment;

[0041] FIG. 25 shows an equivalent circuit diagram of the MOSFET of FIG. 24;

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[0042] FIG. 26 shows a horizontal cross-sectional view of the MOSFET of FIG. 24 according to the first embodiment;

[0043] FIG. 27 shows a horizontal cross-sectional view of FIG. 24 according to the second embodiment;

[0044] FIG. 28 shows a modification of the MOSFET of FIG. 24;

[0045] FIG. 29 shows a vertical cross-sectional view of a MOSFET including a coupling configuration with a JFET located between a compensation region and a source electrode according to the second embodiment;

[0046] FIG. 30 shows a vertical cross-sectional view of a MOSFET including a coupling configuration with a JFET located between a compensation region and a source electrode according to a third embodiment;

[0047] FIG. 31 shows a vertical cross-sectional view of a MOSFET including a coupling configuration with a JFET located between a compensation region and a source electrode according to a fourth embodiment;

32 shows a vertical cross-sectional view of a MOSFET including a coupling configuration with two JFETs connected in series between the compensation region and the source electrode according to the first embodiment;

[0049] FIG. 33 shows an equivalent circuit diagram of the MOSFET of FIG. 32;

[0050] FIG. 34 shows a modification of the MOSFET of FIG. 24;

[0051] FIG. 35 shows a vertical cross-sectional view of a MOSFET including a coupling configuration with two JFETs connected in series between the compensation region and the source electrode according to the second embodiment;

[0052] FIG. 36 shows an equivalent circuit diagram of the MOSFET of FIG. 35;

[0053] FIG. 37 shows a vertical cross-sectional view of a MOSFET including a coupling configuration with two JFETs located between a compensation region and a source electrode according to the first embodiment;

[0054] FIG. 38 shows a vertical cross-sectional view of a MOSFET including a coupling configuration with two JFETs located between a compensation region and a source electrode according to the second embodiment.

Detailed ways

[0055] In order to facilitate a better understanding of the embodiments of the present invention which will be further explained below, the use of the transistor component as an electronic switch will be explained with reference to FIG. 1. FIG. 1 shows a circuit diagram of a transistor component 1 used as an electronic switch for switching a current through a load Z. The transistor component 1 implemented as a MOSFET in the example of FIG. 1 includes a gate terminal G configured to receive a driving signal S1 from the driving circuit 2 and a load path. This load path (also referred to as an internal load path) extends between the drain D and the source S in the transistor 1. The load path DS is connected in series with the load Z, and the series circuit of the transistor 1 and the load Z is connected between the first supply potential V+ and the second supply potential GND. The load Z may be a resistive load such as a light bulb, an inductive load such as a coil, an inverter, or an induction motor, or a capacitive load.

[0056] The transistor 1 can be turned on and off by a drive circuit 2 that generates a suitable drive signal S1 at the gate terminal G of the transistor 1. The driving signal is, for example, a pulse width modulation (PWM) signal. This is well known, so no further explanation is needed at this point.

[0057] When the MOSFET is turned on, that is, when the MOSFET is in the on state, the load current Id flows through the load path of the load Z and the transistor 1, wherein the magnitude of the load current Id is mainly determined by the first supply potential V+ and The characteristics of the supply voltage existing between the second supply potential GND and the load Z are limited. When the transistor 1 is in the on state, ohmic loss occurs in the transistor. These losses result from the on-resistance of the transistor 1 and the load current Id flowing through the transistor 1. When the MOSFET changes its working state from the on state to the off state, that is, when the MOSFET is turned off, or when the working state is changed from the off state to the on state, the loss increases in a short period of time. This is a high current and a high voltage simultaneously existing between the load terminals D and S of the transistor in the transition phase between the on state and the off state.

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[0058] The transistor component (especially a MOSFET) includes an output capacitance acting between the drain terminal and the source terminal and between the drain terminal and the gate terminal, and usually includes a drain-source capacitance between the drain terminal D and the source terminal S Cds and the gate-drain capacitance Cgd between the gate terminal and the drain terminal. In Fig. 1, the drain-source capacitance Cds is schematically shown. It should be noted that at this point, the drain-source capacitance and the drain-gate capacitance can be considered to be connected in parallel in a small-signal equivalent circuit diagram, where the parallel circuit forms the output capacitance of the MOSFET. The capacitance value Coss of the output capacitor depends on the voltage between the drain terminal D and the source terminal S of the transistor. The dependence of the capacitance to the voltage between Coss and the drain terminal D and the source terminal S is schematically shown in FIG. 2.

[0059] When the transistor 1 is turned off and the voltage Vds on the load path of the transistor 1 increases, the output capacitance is charged, that is, energy is stored in the output capacitance. Equivalently, when the MOSFET is turned on, the output capacitor discharges. The charging of the output capacitance when the MOSFET is turned off and the discharge of the output capacitance when the MOSFET is turned on cause loss, which will be referred to as capacitance loss in the following.

[0060] The loss generated when the transistor component 1 is operated in the cut-off mode (ie, the transistor component 1 is periodically turned on and off) includes ohmic loss, switching loss in the transition phase, and capacitance loss. Which of these losses dominates depends on the load conditions of the transistor component 1. The load condition of the transistor component 1 is mainly defined by the load current Id flowing through the transistor 1 in the on state, but is also defined by the switching frequency when the transistor is turned on and off.

[0061] The capacitance loss depends on the energy stored in the output capacitor when the transistor 1 is turned off. This energy depends on the maximum voltage between the load paths of the transistor 1 when the transistor is in the off state and the capacitance value Coss of the output capacitor.

[0062] There are transistor components in which the capacitance value Coss of the output capacitor depends on the voltage on the load path of the transistor. Figure 2 schematically shows this voltage dependence of the output capacitance and the voltage across the transistor. In FIG. 2, Coss represents the output capacitance value, and Vds represents the voltage between the drain terminal D and the source terminal S of the transistor. As can be seen from FIG. 2, there is a voltage Vdso at which the output capacitance value Coss decreases significantly when the voltage Vds increases.

[0063] In FIG. 2, in addition to the curve where the output capacitance value Coss rapidly decreases at Vdso, it also shows that the capacitance value rapidly decreases at a voltage higher than Vdso and decreases rapidly at a voltage lower than Vdso. Two curves. The Vdso voltage may depend on the maximum capacitance value, which appears at the low drain-source voltage Vds. According to an embodiment, the Vdso voltage decreases as the maximum capacitance value Coss decreases.

[0064] The energy Eoss stored in the output capacitor is given by the following formula:

[0065] E°S£=J ^OSS DS ^DS^DS \

[0066] where Vds" is the voltage across the load path when the transistor 1 is in the on state, and VDS°ff is the voltage across the load path when the transistor is in the off state. Coss (Vds) is the voltage that depends on the voltage Vds. Output capacitance value. Since the voltage VDSon between the transistors in the on state is usually very low and is significantly lower than the voltage VDSoff in the off state, the equation (la) can be simplified as:

[0067] E_oss = J ^oss^yds Clb)

[0068] As can be seen from FIG. 2 and from equations (la) or (lb), respectively, the energy stored in the output capacitor Eoss, and thus the capacitor loss, can be reduced by reducing the output capacitor Coss and by reducing the Vds. The steady value (that is, the maximum capacitance value) to decrease.

[0069] Now, the transistor part 10 having a voltage-dependent output capacitance and in which the voltage dependency of the output capacitance can be adjusted will be explained with reference to FIG. 3.

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[0070] The transistor component 10 shown in FIG. 3 is implemented as a MOSFET, specifically, as a compensation type or a super junction type MOSFET. The characteristic curve of the output capacitor Coss shown in Figure 2 (where there is a strong correlation between the output capacitor Coss and the drain-source voltage Vds) is usually used for super junction MOSFETs. Refer to Figure 3, The MOSFET includes a source region 12 connected to a source electrode 51 forming a source terminal S and a drain region 14 connected to a drain terminal D. The drain terminal D may be formed by a drain electrode disposed on the drain region 14. The oMOSFET further includes a drift region 11 and a body region 13, wherein the body region 13 is disposed between the source region 12 and the drift region 11, and the drift region 11 is configured Between the body region 13 and the drain region 14. The source region 12, the body region 13, the drift region 11 and the drain region 14 are integrally formed in the semiconductor body 100. The MOSFET according to FIG. 3 is implemented as a vertical MOSFET, which is a MOSFET in which the source region 12 and the drain region 14 have a distance in the vertical direction of the semiconductor body 100; in this case, when the MOSFET is in the on state, the current is substantially at The semiconductor body 100 flows in the vertical direction. However, implementing the MOSFET as a vertical MOSFET is only an example. The basic principle explained below is also applicable to a lateral MOSFET in which the source region and the drain region have a distance in the lateral direction of the semiconductor body. The basic principle is also applicable to a MOSFET (not shown) in which the drain region is implemented as a buried layer, wherein, The buried layer is configured to have a distance from the source region in the vertical direction of the semiconductor. The buried layer may be connected to a drain terminal which is arranged on or above the same surface of the semiconductor body as the source terminal.

[0071] Both the source region 12 and the body region 13 are connected to the source electrode 51 forming the source terminal S. This is a common practice in MOSFETs. [0072] The MOSFET further includes a gate electrode 21 connected to the gate terminal G or forming the gate terminal G. The gate electrode 21 is arranged adjacent to the body region 13, wherein the gate dielectric 22 is arranged between the gate electrode 21 and the body region 13. In a well-known manner, the gate electrode 21 is used to control the first conductive channel in the body region 13 between the source region 12 and the drift region 11. In the embodiment shown in FIG. 3, the gate electrode 21 is a planar electrode, that is, the gate electrode 21 is arranged above one of the surfaces of the semiconductor body 100. However, this is only an example, and the gate electrode 21 may also be implemented as a trench electrode (not shown) in a trench of a semiconductor.

[0073] When the potential applied to the gate terminal G is suitable to generate the first conductive channel along the gate dielectric 22 in the body region 13, the MOSFET is in a conductive state, and when there is no presence at the gate terminal G, the body region 13 When the appropriate driving potential of the conduction channel, the MOSFET is in the off state.

[0074] The MOSFET may be implemented as an enhancement type MOSFET _oIn this case, the body region 13 is doped complementary to the source region 12, so that the first conductive channel generated in the body region 13 and controlled by the gate electrode 15 is an inversion channel. However, the MOSFET can also be implemented as a depletion MOSFET. In the n-type MOSFET, the source region 12 and the drain region 14 are of n-doped type, and in the p-type MOSFET, the source region 12 and the drain region 14 are of p-doped type.

[0075] The MOSFET of FIG. 3 is implemented as a compensation type or a super junction type MOSFET, and includes a compensation region 31 in the drift region 11. The compensation region 31 has a doping type complementary to that of the drift region, so that a pn junction is formed between the compensation region 31 and the drift region 11.

[0076] The MOSFET further includes a coupling configuration 40 configured to electrically couple the compensation region 31 to at least one of the body region 13, the source region 12, and the source electrode 51 according to the control signal received at the control terminal G2. The coupling configuration is only schematically shown as a switch. The switch may be implemented as an electronic switch, such as a transistor, connected between the compensation area 31 and the source electrode 51. The compensation area 31 may include a contact electrode (not shown) at which the switch is connected to the compensation area. In the embodiment shown in FIG. 3, the compensation region 31 is implemented as a buried region, which is below the body region 13 and has a distance from the surface of the semiconductor in the vertical direction. However, the compensation area may include a portion extending to the surface (in a vertical plane different from the plane shown in FIG. 3) where the compensation area may be contacted. Hereinafter, other embodiments for realizing the coupling configuration will be explained.

[0077] According to another embodiment (not shown), the coupling configuration may be connected between the compensation region 31 and the gate electrode 21, rather than between the body region 13, the source region 12, or the source electrode 51.

[0078] In the embodiment shown in FIG. 3, the compensation region 31 (the doping type of which is the same as that of the body region 3) is divided into 12 points from the body region.

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from. Specifically, the compensation region is disposed below the body region 13 and has a distance from the body region 13 in the vertical direction of the semiconductor body 100 so that the part 11 of the drift region 11 is disposed between the body region 13 and the compensation region 31. This allows the potential presented by the compensation zone 31 to be different from the potential of the body zone 13. The coupling configuration 40 is configured to electrically couple the compensation region 31 to the body region 13 or to electrically isolate the compensation region 31 from the body region 13.

[0079] The coupling configuration 40 can present two different working states. In the first working state, the coupling configuration 40 couples the compensation region 31 to at least one of the body region 13, the source region 12 and the source electrode 51; and, In the second working state, the coupling configuration 40 decouples (separates) the compensation region 31 and the body region 13/source electrode 51, so that the compensation region 31 floats. The coupling configuration 40 includes a control terminal G2, through which the working state of the coupling configuration 40 can be controlled. The working state of the coupling configuration 40 depends on whether the MOSFET is in its on state or off state. Therefore, the MOSFET can include two different switching states, namely, the on state and the off state, and two different working states, namely, the first working state when the coupling configuration is in the first working state, and when the coupling device is in the first working state. The second working state in the second working state.

[0080] The working principle of the MOSFET will now be explained based on FIG. 3. For the purpose of illustration, it is assumed that the MOSFET is an n-type enhancement type MOSFET. However, the description provided below in this article is also applicable to the p-type MOSFET and the depletion type MOSFET_o[0081] Similar to a conventional MOSFET, the MOSFET can be switched on and off by applying an appropriate driving potential to the gate terminal G. When the MOSFET is switched on (in the on state), there is a conductive channel in the body region 13 between the source region 12 and the drift region 11 along the gate dielectric. When the MOSFET is turned off, the conduction channel of the ship's gate dielectric 22 is interrupted. When the MOSFET is off and a voltage is applied between the drain terminal D and the source terminal S (positive voltage in the case of n-type MOSFET, negative voltage in the case of p-type MOSFET), the depletion region expands in the drift region 11 . The depletion region, or the electric field associated with the depletion region, also causes carrier loss in the compensation region 31. Therefore, the dopant (doping charge) in the drift region 11 is "compensated" by the compensation dopant in the compensation region 31. The occurrence of this mechanism is independent of whether the coupling configuration 40 is in the first or second operating mode, that is, it is independent of whether the compensation region 31 is coupled to the body region 13 or the source electrode 51 accordingly.

[0082] The compensation effect explained above can provide a higher doping concentration in the drift region 11, without reducing the voltage blocking capability, resulting in a lower on-resistance than conventional (non-superjunction) components. The basic working principle of super junction devices is well known, so no further explanation is needed at this point.

[0083] When the MOSFET is in an off state, the compensation region 31 and the drift region include charges. These charges are positive in the n-doped drift region (in the form of a positively charged donor center) and negative in the p-doped compensation region (in the form of a negatively charged acceptor center), and make the depletion region in the drift region 11 and The compensation area 31 is expanded. When the MOSFET is driven to switch from the off state to the on state, two different situations may occur depending on whether the coupling configuration is in the first operating mode or in the second operating mode.

[0084] (a) When the coupling configuration 40 is in the first working mode, the compensation region 31 is electrically coupled to the source electrode 51, and the drift region

11 and the compensation region 31 are "discharged", so that the depletion region between the compensation region 31 and the drift region 11 is removed. This is equivalent to the operation of a conventional super junction device.

[0085] (b) When the coupling configuration 40 is in the second operating mode, so that the compensation region 31 is not electrically coupled to the source electrode 51 (floating), the compensation region 31 cannot be completely discharged, so that the compensation region 31 and the drift region 11 The depletion zone between the two cannot be completely removed. This may cause the conductive channel in the drift region 11 between the drain region 14 and the "channel region" to be partially or completely cut off, even if the MOSFET is in the on state. The channel region is a region of the body region 13 in which the conductive channel along the gate dielectric 22 can be controlled.

[0086] The MOSFET according to FIG. 3 has an output capacitance having an output capacitance value Coss according to the characteristics of FIG. 2, and the capacitance value drops significantly when the voltage reaches the threshold value Vdso. In the characteristic shown in Figure 2, the output capacitance value C°ss is lower than the threshold value

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The voltage of Vdso has a higher value, and the voltage higher than the threshold Vdso has a lower value, which is equivalent to the fact that when the voltage is lower than the threshold voltage Vdso, it needs to be higher than the higher voltage (that is, the voltage higher than the threshold voltage Vdso ), a higher charge is provided to the load path of the transistor, thereby increasing the voltage across the load path for a given voltage value ΔVds. The capacitance value at low voltage may be as high as 10 to 100 times the capacitance value at high voltage. Therefore, at low voltage, the charge used to increase the voltage for ΔVds is 10 to 100 times higher than the charge required at high voltage. A MOSFET of the type shown in Figure 3 can be designed to have a breakdown voltage between 50V and 2000V (2kV). The voltage Vdso when the output capacitance is reduced is, for example, between 5V and 80V, and more specifically, for this type of MOSFET, between 10V and 80V.

[0087] The mechanism leading to the above-explained voltage dependence of the output capacitance value in the MOSFET according to FIG. 3 will now be explained for (a) the case where the coupling configuration 40 is in the first operating state. When the MOSFET is in the off state, carriers are concentrated in the drift region 11 and the compensation region 31. In the on state, there is a junction capacitance with a huge capacitance between the compensation region 31 and the drift region 11. This capacitor significantly contributes to the drain-source capacitance Cds, and therefore, the output capacitance Coss of the MOSFET. When the MOSFET is turned off, that is, when the channel along the gate dielectric 16 is interrupted, these junction capacitances must be charged before the voltage crosses the drift region 11 (this is equivalent to removing the doped charge from the compensation region 31 and drift Region 11 is removed), therefore, the voltage between the drain terminal D and the source terminal S increases significantly. When the compensation zone 31 and the drift zone 11 have been charged, the depletion zone expands in the drift zone 11 and the compensation zone. At this time, when the compensation area 31 has been fully charged, the junction capacitance "disappears", resulting in a rapid drop in the output capacitance Coss. The slope of the drop of the output capacitance Coss is steep and occurs at the voltage Vdso shown in FIG. 2, which depends on the geometry of the compensation region 31 and its doping concentration, for example, between 5V and 80V. Vdso represents a specific value of the drain-source voltage Vds, at which the drift region 11 is completely consumed by the space charge region extending in the direction perpendicular to the current direction of the MOSFET.

[0088] The doping concentration of the drift region 11 is, for example, 10¹⁴(LE14) cm-³To 10% lE16) cm "3. The doping concentration of the compensation region 31 can be in the same range.

[0089] Compared with the conventional MOSFET, the super-junction device having the compensation region 31 that is charged when the MOSFET is turned off and discharged when the MOSFET is turned on as in the case (a) has a higher output capacitance Coss but a lower On resistance. When the compensation area 31 is not electrically coupled to the source electrode 51 as in the case (b), that is, when the compensation area 31 floats, the output capacitance Coss decreases. However, there is an increased on-resistance in this case. Therefore, through the controllable coupling configuration 40, the output capacitance and on-resistance of the MOSFET can be changed. This has the following trade-off: a decrease in output capacitance (which leads to a decrease in capacitance loss) is associated with an increase in on-resistance (which leads to a higher ohmic loss). The decrease in on-resistance (which leads to reduced ohmic losses) is associated with an increase in output capacitance (which leads to higher capacitance losses).

[0090] The operating principle described above for the n-type MOSFET is also applicable to the p-type MOSFET, wherein, in the p-type MOSFET, a single semiconductor region has a complementary doping type and the voltage polarity is reversed.

[0091] The compensation region 31 and the drift region 11 form a JFET (junction FET) between the body region 13 and the drain region 14. The circuit symbol of the FET is shown in FIG. 3. When the MOSFET is in the off state, there are two depletion regions that extend in the drift region. The first depletion region extends from the ρη junction between the body region 13 and the drift region 11, and the second depletion region extends from the compensation region 31 and The ρη junction between the drift regions 11 expands.

[0092] The MOSFET according to FIG. 3 can be realized using a plurality of identical structures (which are well-known transistor units). Only one transistor unit is shown in FIG. 3. Fig. 4 shows a schematic cross-sectional view of a MOSFET with a plurality of transistor cells. These transistor cells connect the source region 12 of each cell to the common source electrode 51, connect the gate electrode 21 of each cell to the common gate terminal G, and connect the drain region 14 and drift region 11 of each cell to the common drain. Terminal D, while connected in parallel. The drift region 11 and the drain region 14 are common to each transistor cell.

[0093] The coupling configuration 40 is configured to couple the compensation area 31 of each unit according to the control signal received at the control terminal.

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It is joined to at least one of the body region 13, the source region 12 and the source electrode 51. For this, the coupling configuration includes a plurality of coupling units, wherein each coupling unit is used to couple the compensation area 31 of at least one transistor unit to the body area 13, the source area 12 and the source electrode 51 of the transistor unit. In Figure 4, two coupling units 40ι, 40 are shown_η, Wherein each coupling unit is used to couple a compensation area 31 to a body area 13, a source area 12 and a source electrode 51. In the example shown in FIG. 4, one compensation region 31 and one body region 13 are common to two transistor cells. However, this is only an example. It is also possible to implement the transistor unit as only one compensation area 31, only one body area 13, and only one coupling unit allocated to one transistor unit.

[0094] The coupling configuration may be implemented such that all coupling units operate in the same working state (which is the first working state or the second working state). However, it is also possible to implement the coupling configuration 40 so that each coupling unit can independently operate in the first or second working state, so that some transistor units can operate with a floating compensation area 31, while other transistor units can operate And there is a compensation area 31 connected to the source electrode 51.

[0095] Each transistor unit can be realized by using a conventional transistor unit assembly shape. Figure 5 shows a schematic horizontal cross-sectional view of a MOSFET with elongated or strip-shaped cells. In this case, the source region 12 and the body region 13 in each unit have a striped geometric shape.

[0096] With reference to FIGS. 6 and 7, the transistor unit can also be implemented in a rectangular or square geometry (see FIG. 6) or in a hexagon (see FIG. 7) or any other polygonal geometry. In this case, the body region 13 has a rectangular or square, hexagonal or polygonal geometric shape.

[0097] FIGS. 5 to 7 show horizontal cross-sectional views of the MOSFET in section AA shown in FIG. 4. The compensation area 31 is not shown in these FIGS. 5 to 7. The geometric shape of the compensation area in the horizontal plane may correspond to the geometric shape of the body area 13. Therefore, in a MOSFET with a strip cell, the compensation area 31 may have a strip geometry, and in a MOSFET with a rectangular or square geometry, the compensation area 31 may have a rectangular or square geometry, and in a MOSFET with a hexagonal or square geometry. In a MOSFET with a polygonal unit, the compensation area 31 may have a hexagonal or polygonal geometric shape. In each of these cases, the compensation region 31 may be arranged below the body region 13 in the vertical direction of the semiconductor body 100, as shown in FIG. 4.

[0098] However, it is also possible to implement the geometry of the compensation area 31 to be different from the geometry of the body area 13. For example, the compensation area 31 may be implemented as a strip-shaped geometric shape, while the transistor unit has a rectangular, square, hexagonal or polygonal geometric shape. In addition, the compensation area 31 may be arranged not to be aligned with the body area 13, that is, the compensation area 31 is not necessarily arranged below the body area 13.

[0099] FIG. 8 shows a schematic vertical cross-sectional view of a MOSFET illustrating one example of implementing the coupling configuration 40. In this example, the compensation region 31 is disposed below the body region 13 and has a distance from the body region 13 in the vertical direction of the semiconductor body 100. The coupling configuration 40 (from which only one coupling unit is shown in FIG. 8) includes a control electrode 41 which is dielectrically insulated from the semiconductor body 100 by a control electrode dielectric 42. The control electrode 41 extends from the body region 13 or extends into the compensation region 31. The control electrode 41 extends through the portion 11 of the drift region 22 that separates the body region 13 from the compensation region 31. In this portion 11 of the drift region 22, a channel region 43 in a coupled configuration is formed between the body region 13 and the compensation region 31 along the control electrode dielectric 42.

[0100] The control electrode 41 is electrically connected to the control electrode G2 in a manner not shown in detail in FIG. 8. The control electrode 41 can be implemented with a conventional electrode material (such as metal) or a highly doped polysilicon semiconductor material (such as polysilicon). The control electrode dielectric 42 can be implemented in conventional dielectric materials, such as oxides, nitrides, or high-k dielectrics.

[0101] The control electrode 41 is used to control the inversion channel in the channel region 43 between the compensation region 31 and the body region 13. The channel is used for p-type carriers when the compensation region 31 and the body region 13 are p-type doped, and when the compensation region 31 and the body region 13 are n-type doped, it is used for n-type carriers. Current conduction channel. When driving by applying an appropriate driving potential to the control terminal G2

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When the electrode 41 is controlled to generate an inversion channel in the channel region 43, the coupling configuration 40 is in the first working state. In the n-type MOSFFT in which the source region 13 is n-type doped and the body region 13 is p-type doped, when the control terminal G2, the source region 12, and the source electrode 51 are respectively applied to the control terminal G2, the source region 12, and the source electrode 51, a source having a higher potential than that of the body region 13 is applied. At a low potential, an inversion channel is generated in the channel region 43 between the body region 13 and the compensation region 31. According to one embodiment, the voltage applied between the control terminal G2 and the source electrode 51 or the source terminal S in order to generate a conductive channel is in a range between -0.1V and -15V. In a p-type MOSFET in which the source region 12 is p-type doped and the body region 13 is n-type doped, the potential applied to the control terminal G2 is relative to the source potential in order to create a conductive channel in the channel region 13 It is a positive potential. The voltage applied between the control terminal G2 and the source terminal S is, for example, within a range between 0.1V and 15V.

[0102] When the control electrode 41 is driven so that there is no conductive channel along the control electrode dielectric 42 between the body region 13 and the compensation region 31, the coupling configuration 40 is in the second working state. In this case, the compensation area 31 is floating. When the absolute value of the voltage applied between the control terminal G2 and the source terminal S is lower than the threshold value, the coupling configuration 40 is in the second operating state. The threshold is, for example, between 0.5V and 2V.

[0103] The MOSFET according to FIGS. 3 to 8 can be used as an electronic switch for switching an electronic load like a conventional MOSFET, as already explained with reference to FIG. 1. However, the MOSFET according to FIGS. 3 to 8 has at least one control terminal in addition to the gate terminal G, through which the operating state can be changed, thereby separately adjusting the output capacitance and the on-resistance. When the coupling configuration 40 is in the first operating state, the MOSFET operates like a conventional super junction MOSFET. In this case, the compensation region 31 is electrically coupled to the body region 13 through the conductive channel along the control electrode dielectric 42 in the channel region 13. In addition, when the coupling configuration 40 works in the second working state so that the conductive channel between the body region 13 and the compensation region 31 is pinched off and the compensation region 31 is in a floating state, the MOSFET can achieve a reduced output capacitance. And the increased on-resistance works. In the second working state, the MOSFET can still work like a conventional super junction device, but it is a device with another set of electrical data, specifically another output capacitance and another on-resistance.

[0104] The geometry of the control electrode 41 and the control electrode dielectric 42 in the horizontal plane may correspond to the geometry of the transistor unit. This will be explained with reference to FIGS. 9 to 11, where FIGS. 9 and 11 show schematic horizontal cross-sectional views of MOSFETs having different cell geometries in horizontal cross-sections corresponding to the horizontal cross-section BB shown in FIG. 8.

[0105] FIG. 9 shows a horizontal cross-sectional view of a MOSFET having a stripe cell geometry, so that the body region 13 has a stripe geometry. The section BB does not pass through the body zone 13. However, for a better understanding, the position and geometry of the body region 13 are also shown in dotted lines in FIGS. 9 to 11.

[0106] Referring to FIG. 9, the compensation area 31, the control electrode 41, and the control electrode dielectric 42 also have a striped geometry. In the embodiment shown in FIG. 9, the width of the compensation area 31 is smaller than the width of the body area 13. The "width" of the connection refers to the geometric dimensions of the compensation area 31 and the body area 13 in a direction perpendicular to the axial direction of the compensation area 31 and the body area 13. However, the width of the compensation area 31 being smaller than the width of the body area is merely an example. It is also possible to implement the compensation area 31 and the body area 13 to have the same width, or implement the width of the compensation area 31 to be greater than the width of the body area 13. This can also be applied to other examples which will be described below with reference to FIGS. 10 and 11.

[0107] FIG. 10 shows a horizontal cross-sectional view of a MOSFET with a rectangular (especially square) cell geometry. In this example, the body region 13 has a rectangular shape, specifically a square geometric shape. The compensation area 31 also has a rectangular shape, specifically a square geometric shape. The control electrode 41 also has a rectangular shape, specifically a square geometric shape.

[0108] FIG. 11 shows an example in which the transistor cell has a hexagonal geometry, the compensation area 31 has a hexagonal geometry, and the control electrode 41 has a hexagonal geometry. In this connection, it should be noted that in addition to the hexagonal geometry, any other polygonal geometry can also be used.

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[0109] It is not mandatory to implement the body region 13, the compensation region 31, and the control electrode 41 into the same geometric shape. The geometric shape of the compensation area 31 may also be different from the geometric shape of the body area 13, and the geometric shape of the control electrode 41 may also be different from the geometric shape of the compensation area 31. For example, the following geometric shapes can be used independently for the body region 13, the compensation region 31, and the control electrode 41: rectangle, square, hexagon, polygon, and circle.

[0110] FIG. 12 shows a horizontal cross-sectional view of a MOSFET in which each transistor cell has a rectangular geometry (ie, the body region 13 has a rectangular geometry, and the compensation region 31 also has a rectangular geometry). The control electrode 41 has a striped geometry, so that one control electrode 41 is shared by several transistor units. The implementation of the compensation area 31 to have the same geometric shape as the body area 13 is merely an example. It is also possible to implement the body region 13 and the compensation region 31 to have different geometric shapes.

[0111] FIG. 13 shows an embodiment in which the compensation area 31 has a strip-shaped geometry and several control electrodes 41 each having a rectangular geometry are coupled to one compensation area 31. Instead of rectangular geometric shapes, circular, hexagonal or any other polygonal geometric shapes can also be used for the control electrode 41.

[0112] FIG. 8 only schematically shows the connection of the control electrode 41 to the control terminal G2. The control terminal G2 may be implemented as an electrode to which the position control electrode 41 not shown in the vertical cross-sectional view shown in FIG. 8 is arranged above the semiconductor body 100 and is connected.

[0113] FIG. 14 schematically shows a perspective cross-sectional view of a MOSFET with strip-shaped transistor cells to show one possible way of contacting the (buried) control electrode 41. In FIG. 14, only one transistor unit of the MOSFET is shown. The transistor unit has a striped geometry, and the compensation area 31 and the control electrode 41 also have a striped geometry. The control electrode 41 extends substantially parallel to the compensation area 31 and the body area 13 between the compensation area 31 and the body area 13. In this example, the control electrode 41 includes a connection electrode 44 extending through the body region 13 and the source region 12 in the vertical direction of the semiconductor body to a contact electrode 45, wherein the contact electrode 45 is connected to the control terminal G2 or forms the control terminal G2.

[0114] FIG. 15 shows a schematic vertical cross-sectional view of the MOSFET in a section CC cut through the region of the MOSFET in which the connection electrode 44 and the contact electrode 45 are arranged. It can be seen from FIG. 14 that the control electrode 41 and the connection electrode 44 are dielectrically insulated from the body region 13 and the source region 12 by the control electrode dielectric 42. The contact electrode 45 is disposed above the semiconductor body 100 and is electrically insulated from the gate electrode 21. The electrical insulation between the contact electrode 45 and the gate electrode 21 may be provided by the same insulating layer or the dielectric layer 23 disposed between the gate electrode 21 and the source electrode 51. Optionally, the control electrode dielectric 42 may also be arranged between the contact electrode 45 and the gate electrode 21.

[0115] The source electrode 51 is configured to have a distance from the contact electrode 45 in the lateral direction, and is electrically insulated from the source electrode 51 by an insulating layer. Referring to FIG. 15, the source region 12 and the gate electrode 21 may also be configured to be lower than the contact electrode. However, it is optional to provide the source region 12 and the gate electrode 21 below the contact electrode. According to another example, the source region 12 and the gate electrode 21 do not extend below the contact electrode 45. The control electrode 41, the connection electrode 44, and the contact electrode 45 may be formed of the same semiconductor material such as a metal or a highly doped polycrystalline semiconductor material. However, the electrodes 41, 44, and 45 may be formed of different electrode materials. In an unspecified manner, the contact electrode 45 may be connected to the control electrode 41 of the plurality of transistor units through the connection electrode 44.

[0116] In the example shown in FIG. 14, the control electrode 41 has an elongated (stripe) geometric shape and extends along the compensation area 31 and the body area, so that the compensation area 31 can be aligned with the body area along its full longitudinal length. 13 Electrical connection. However, this is only one possible example. Referring to FIG. 16, the control electrode 41 may be provided at only one position, or multiple control electrodes 41 may be provided at different positions along the compensation area 31. FIG. 16 shows a schematic perspective partial view of the MOSFET in which the control electrode 41 does not completely expand along the compensation area 31 but is only arranged below the connection electrode 44.

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[0117] According to an example, the MOSFET includes a transistor cell coupled to the body region 13 and the source electrode 51 through a coupling configuration 40, respectively, and a conventional transistor cell. The so-called "conventional transistor" is a transistor unit whose compensation area is permanently connected to the body area. For illustrative purposes only, a schematic perspective partial view of a conventional transistor cell having a stripe geometry is shown in FIG. 17. Of course, any other geometric shapes can also be used. In the transistor cell of FIG. 18, the compensation region 31 adjoins the body region 13 and is therefore electrically connected to the source electrode 51. In the conventional cell of FIG. 17, similar reference signs indicate similar regions of the transistor cells described with reference to FIGS. 3 to 16.

[0118] Hereinafter, the conventional transistor power supply will be denoted as a first type of transistor cell, and the transistor cell having a coupling configuration will be denoted as a second type of transistor cell. A single transistor cell can be implemented to include a common drift region and a common drain region.

[0119] The first type of transistor cell and the second type of transistor cell may be configured in the semiconductor body 100 in many different ways. According to the first embodiment shown in FIG. 19, the transistor cells of the first type and the transistor cells of the second type are alternately arranged. FIG. 18 shows a horizontal cross-sectional view of the cross-section corresponding to the cross-section BB in FIG. 8 and passing through the compensation areas 31 and 31 . In the embodiment of FIG. 19, the transistor cells and the compensation regions 31 and 31' have a striped geometry. However, any other cell geometry and compensation area geometry can also be used.

[0120] According to another embodiment shown in FIG. 19, which also shows a horizontal cross-sectional view of the semiconductor body, a group of several units of the second type (with the compensation area 31) are arranged adjacent to a group of several units. One type of unit (with compensation area 31').

[0121] According to one embodiment, in a MOSFET including a first type of transistor cell, the second type of transistor cell is implemented without a channel region, which means that there is no source region 12 and/or no gate electrode 21. A vertical cross-sectional view of a second type of transistor cell that does not include a source region is shown in FIG. 21. In this case, the gate electrode 21 (shown with a short line) is optional. In a MOSFET with first and second types of transistor cells, the second type of transistor cell (which is a cell whose compensation region is coupled to the source region or the body region through a coupling configuration) is implemented without a channel region. It is only used to adjust the output capacitance and on-resistance. When the MOSFET is in its on state, the current flowing through the drift region 11 is provided only through the channel region of the transistor cell of the first type. The "channel region" of the conventional cell is the region in the body region 12 from the source to the drift region 11 along the gate dielectric 22 of the conventional cell (see FIG. 17).

[0122] The operation principle of a MOSFET having first and second types of transistor cells will now be explained with reference to FIG. 21. FIG. 21 shows a circuit diagram representing the MOSFET 10. The circuit diagram includes: n first transistors 1π, ..., 1ΐη, each corresponding to a transistor unit of the first type or a group of transistor units of the first type; and m second transistors 121, ..., 12m , Each corresponding to a second type of transistor unit or a group of second type of transistor units. A single unit can be implemented as one of the methods described above.

[0123] The individual transistor units are connected in parallel. It is shown in FIG. 21, where the drain-source paths of the transistors 1π, ·T In, 121,..., 12m are connected in parallel, and the transistors have their gate terminals coupled together to form a gate terminal G. The transistor representing the second type of transistor unit has, in addition to the gate terminal, a control terminal for adjusting output capacitance and on-resistance. In the embodiment shown in FIG. 21, the second type of cell has its control terminals coupled together to form the control terminal G2 of the MOSFET_O

[0124] When the second type of cell is operated so that the coupling configuration is in the first working state, the MOSFET can work with the first on-resistance and the first output capacitance, so that the compensation area of the second type of cell is connected to a body area and source. The zone and the source electrode are electrically connected. When the second type of unit is operated so that the coupling configuration is in the second operating state, the MOSFET can operate with a second on-resistance higher than the first on-resistance and a second on-capacitance lower than the first on-capacitance, thereby Second type

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The compensation area of the unit is floating. The ratio between the first on-resistance and the second on-resistance and the ratio between the first on-capacitance and the second on-capacitance depend on the overall size of the active area of the first type of transistor unit and the first The ratio of the overall size of the effective area of the two types of transistor cells. For example, suppose a single unit has the same size. In this case, the effective size of the effective area of the entire area of the first type and a second type of unit cell, respectively, and the overall size of the number of units of the first type and a second type of cells proportional. According to one embodiment, the Acon/Aca size ratio between the overall size of the effective area of the transistor cell of the first type and the overall size of the effective area of the transistor cell of the second type is between 10:1 and 1:10, particularly It is between 2:1 and 1:2, or even between 1.5:1 and 1:1.5.

[0125] Referring to another example shown in FIG. 22, the MOSFET includes p (p22) control terminals G2i and G2p. Each control terminal G2i and G2p is used to control the working state of the coupling configuration of a group of units of the second type, wherein each group includes at least one unit of the second type. In the MOSFET shown in FIG. 22, by adjusting the number of cells of the second type operating in the first working state and the second working state, the on-resistance and the on-capacitance can be adjusted to P+1 different values, respectively.

[0126] In the previously described embodiment, the coupling configuration 40 functions like a switch, which electrically connects the compensation region 31 to one of the body region 13, the source region 12, and the source electrode 51 according to the driving signal applied to the control terminal. Float the compensation area.

[0127] According to another embodiment shown in FIG. 23, the coupling configuration 40 also controls the current that can flow between the compensation region 31 and one of the body region 13, the source region 12 and the source electrode 51. Therefore, the coupling configuration 40 can also be implemented as a variable resistor having a resistance controlled by the control signal applied to the control terminal G2. When the resistance of the variable resistor is controlled to be high, the compensation area 31 does not discharge or discharges very slowly when the MOSFET is turned on, and the compensation area 31 discharges quickly when the resistance is low. The variable resistor can be implemented to have the control electrode 41 and the dielectric shown in FIG. 8, wherein the compensation area 31 and the body area 13 or the source electrode can be adjusted by appropriately selecting the driving potential applied to the control electrode 41 Between the resistance.

[0128] The output capacitance Coss of the MOSFET not only affects the switching loss of the MOSFET, but also affects the dynamic behavior of the MOSFET, such as the slope of the rising and falling edges of the load current and drain-source voltage through the MOSFET when the MOSFET is turned on and off, Among them, the low output capacitance Coss can produce a steep slope. Adjusting the maximum value of the discharge current that can flow from the compensation area 31 to a low value can produce a low output capacitance during switching, and therefore can produce a steep switching slope. However, the compensation area 31 is discharged after a while, resulting in a low on-resistance after a delay time after switching.

[0129] The coupling configuration can also be implemented to have a current flow capable of controlling and limiting the compensation region 31 and one of the source electrode 51, the body region 13, the source region 12, and the gate electrode 21 according to the control signal applied to the control terminal G2. Circuit components. Specifically, the coupling configuration may be configured to limit the current flowing to or from the compensation area to a maximum value that depends on the control signal on the control terminal. Conventional controllable current limiters can be used in this connection.

[0130] With reference to the previous description, there is a trade-off between resistance loss and capacitance loss, where the trade-off depends on the load condition of the transistor. For example, the load condition is defined by the current flowing through the transistor in its conducting state, and/or by the switching frequency of the transistor's operation. For example, when the load current is high, the on-resistance needs to be reduced to reduce the resistance loss, even if this makes the total switching loss slightly increase. Although the capacitance loss has nothing to do with the current, the switching loss in the transition phase increases during the on period or at high load currents during the off period. Ohmic losses dominate the total losses at high load currents because they increase with the square of the load current. Therefore, according to one embodiment, the MOSFET is operated such that as the load current increases, the on-resistance decreases, and as the switching frequency increases, the output capacitance decreases.

[0131] The on-resistance can be reduced by driving the second type of transistor cells, thereby increasing the number of cells operating in the first working state. The output capacitance can be reduced by driving the second type of transistor unit, so that the second work

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The number of units doing state work has increased.

[0132] FIG. 24 shows a vertical cross-sectional view of a part of a transistor device (specifically, a vertical MOSFET) including a plurality of device cells (transistor cells). In this embodiment, each transistor cell includes a drain region 14, a drift region 11, a source region 12, and a body region 13 adjacent to the source region 12 and separating the source region 12 from the drift region 11. In FIG. 24, one transistor unit is represented by a dash-dotted line (according to the structure in the dashed-dotted line of FIG. 24, a "half cell" can also be represented). A single transistor unit shares the drift region 11 and the drain region 14. The drain region 14 may be adjacent to the drift region 11 (as shown in the figure). According to another embodiment (not shown), a field-stop region having the same doping type as the drift region 11 but a higher degree of doping may be configured between the drift region 11 and the drain region 14. Each transistor cell also includes a gate electrode 21 adjacent to the body region 13 and insulated from the body region 13 by a gate dielectric 22. The gate electrode 21 is a trench electrode in the embodiment of FIG. 24, which is disposed in the trench of the semiconductor body 100 and extends from the source region 12 into the drift region 11 along the body region 13 in the vertical direction of the semiconductor body 100.ofGrid electrode 21. The gate electrode 21 of each transistor cell is electrically connected to the gate terminal G (only shown schematically in FIG. 24).

[0133] In the semiconductor device of FIG. 24, as with each semiconductor device explained earlier and later explained, the drift region 11 may have a drift region 11 between the drain region 14 and the compensation region 31 and between two adjacent compensation regions 31. The doping concentration of the drift region 11 is different in the drift region portion 11' of the doping concentration. According to one embodiment, the doping concentration in the drift region portion 11 is lower than the doping concentration of the drift region 11 between two adjacent compensation regions 31.

[0134] Referring to FIG. 24, each transistor cell further includes a compensation area 31. The compensation region 31 has a doping type complementary to that of the drift region 11 and forms a pn junction with the drift region 11. Two (or more) transistor units can share one compensation area 31. This is shown in FIG. 24, where two adjacent transistor cells share a compensation region 31. In addition, two or more transistor units may share one gate electrode 21. In the embodiment of FIG. 24, two transistor cells share one gate electrode 21.

[0135] The source region 12 and the body region 13 of each transistor cell are connected to the source terminal S. In FIG. 24, the source electrode 51 electrically connected to the source region 12 and the body region 13 of one transistor cell is schematically shown. Optionally, a contact region 15 with the same doping type as the body region 13 but a higher degree of doping is arranged between the body region 13 and the source electrode 51.

24, the coupling configuration 40 is connected between the compensation area 31 and the source terminal S. Each coupling configuration 40 includes a channel region 43 of the same doping type as the compensation region 31 and connected between the compensation region 31 and the source terminal S. Alternatively, a contact region 46 of the same doping type as the channel region 43 but higher doped than the channel region 43 is used to connect the channel region 43 to the source terminal S. The doping concentration of the channel region 43 is, for example, between 1E14 cm "3 and 1E17 cm "3, and the doping concentration of the contact region 46 is, for example, between 1E18 cm.^-3And 1E21cm "3. The control terminal 41 is adjacent to the channel region 43 and is electrically insulated from the channel region 43 by the electrode dielectric 42. In this embodiment, the control electrode 41 includes at least a distance in the horizontal direction of the semiconductor body 100 Two control electrode portions, and the channel region 41 is located between the two. The coupling configuration is configured in the area of the surface of the semiconductor body 100, wherein the channel region 43 is electrically connected to the source terminal S on the surface. From this On the surface, the compensation region 31 is located lower than the channel region 43. In addition, in the embodiment of FIG. 24, the body region 13 is separated from the channel region 43 by the control electrode 41 and the control electrode dielectric 42, and the compensation region 31 There is a distance from the body area 13.

[0137] The control electrode 41, the control electrode dielectric 42 and the channel region 43 form a transistor, specifically, a depletion transistor, which is connected between the compensation region 31 and the control terminal G2. This transistor is controlled by the control terminal G2 connected to the control electrode 41. Although the transistor of the coupling region is implemented as a depletion transistor in the embodiment of FIG. 24 and other embodiments described below, the transistor is not limited to being implemented as a depletion transistor, but may also be implemented as any other type of transistor, such as Enhancement transistor or JFET (junction FET).

[0138] This transistor will be referred to as a coupling transistor hereinafter, and it can operate as when the channel region 43 is depleted (pinched off)

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A switch that isolates the compensation area 31 from the source terminal S at a time, or couples the compensation area 31 with the source terminal S when the channel area 43 is not depleted (not pinched off). In the n-type MOSFET, the coupling transistor of the coupling configuration 40 is a p-type transistor. The coupling transistor can be controlled by applying a control voltage based on the source terminal S to the control terminal G2.

[0139] The operating principle of the coupling transistor is explained below. For illustrative purposes only, it is assumed that the transistor is a p-type depletion transistor. The coupling transistor has a threshold voltage, which is a voltage that causes the coupling transistor to start conducting when applied between the control terminal G2 and the source terminal S. The threshold voltage of a P-type depletion transistor is a positive voltage that turns the transistor on when the control voltage is lower than the threshold voltage.

[0140] The coupling transistor may operate as a switch, which is either turned off or turned on with low on-resistance. When the coupling transistor is turned off, the compensation area 31 floats, and when the coupling transistor is turned on, the compensation area is connected to the source terminal. The p-type depletion transistor can be turned off by applying a control voltage (cut-off voltage) higher than the threshold voltage, and can be turned off by applying a control voltage (turn-on voltage) that is significantly lower than the threshold voltage and operating the transistor in the saturation region. The resistance is turned on. According to one embodiment, the cut-off voltage is zero. The threshold voltage of the coupling transistor can be adjusted by the doping concentration of the channel region 43, the width of the channel region 43, and the thickness of the control electrode dielectric 42. The width of the channel region 43 corresponds to the distance between the opposing portions of the control electrode 41. When the doping concentration increases, the threshold voltage increases, and when the width of the channel region 43 increases, the threshold voltage increases. The threshold voltage is, for example, a voltage between 5V and 15V.

[0141] According to another embodiment, the transistor of the coupling configuration does not operate as a switch, but operates as a variable resistor in the manner described with reference to FIG. 23. The coupling transistor may be operated as a variable resistor by a control voltage applied between the on-voltage and the off-voltage, where the resistance increases as the control voltage approaches the threshold voltage.

[0142] FIG. 25 shows an equivalent circuit diagram of one transistor unit of the transistor device of FIG. 24. This equivalent circuit diagram includes enhancement type MOSFET 2. 24, the enhancement mode MOSFET is formed by the gate electrode 21, the gate dielectric 22, the source region 12, the body region 13, and the part of the drift region 11 adjacent to the body region 13 oJFET 3 is connected in series with the drain-source path of the enhancement mode MOSFET 2. The JFET 3 is formed by the drift region 11, the compensation region 31 and the drain region 14, wherein the compensation region 31 forms the gate region of the JFET 3. The enhancement type MOSFET 2 and the first JFET 3 are connected in series between the load terminals (source and drain terminals S, D in the embodiment of FIG. 24) of the transistor device. Referring to FIG. 25, a depletion transistor, specifically, a depletion MOSFET, is connected between the source terminal S and the gate of JFET 3. This depletion transistor is a coupling transistor in a coupling configuration, and is composed of a control electrode 41, a control electrode dielectric 42 and a channel region 43. The gate of the depletion transistor 4 is connected to the control terminal G2. This depletion transistor is a P-type depletion transistor in the embodiment of FIG. 25.

[0143] Referring to FIG. 24, a plurality of transistor cells may be implemented in a transistor device (where each transistor cell has an equivalent circuit diagram according to FIG. 25). According to one embodiment, the coupling transistors connected between the compensation region 31 and the source terminal S have the same threshold voltage. According to another embodiment, there are at least two different sets of compensation regions 31, wherein the coupling transistor coupling one set of compensation regions to the source terminal S has the same depletion type as coupling the other set of compensation regions 31 to the source terminal S. The threshold voltage of the transistor is different from the threshold voltage. The operating principle of the transistor device thus realized is similar to that of the transistor device of FIG. 22, except that the transistor device according to FIG. 24 requires only one control voltage, where each coupling transistor is lower or higher than the respective control voltage according to whether the control voltage is lower or higher. The threshold voltage of the coupling transistor is turned on or off. As in the transistor device of FIG. 22, the transistor device of FIG. 24 may optionally include conventional transistor cells whose compensation region is permanently coupled to one of the source and gate terminals.

[0144] According to yet another embodiment, the coupling transistors of each transistor unit all have the same threshold voltage, and at least two control terminals for applying different control voltages are provided. The operating principle of the transistor device thus realized corresponds to the operating principle of the transistor device of FIG. 21.

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[0145] FIGS. 26 and 27 show cross-sectional views of two different embodiments of the transistor device of FIG. 24. In various embodiments, the transistor cell is an elongated transistor device having an elongated source region 12 and an elongated gate electrode 21. In the embodiment shown in FIG. 26, the control electrode portion 41 of each coupling transistor is an elongated electrode. Therefore, the channel region 46 is also an elongated semiconductor region, which is substantially parallel to the source region 12. In this embodiment, the compensation region 31 (not visible in FIG. 26) is also an elongated semiconductor region.

[0146] In the embodiment of FIG. 27, the compensation region 31 (shown by the dashed line in FIG. 27) is an elongated semiconductor region. However, one compensation region 31 is coupled to the source terminal S through several coupling transistors, wherein each coupling transistor has a ring-shaped control electrode 41, and each control electrode 41 surrounds one channel region 46. The specific form of the ring of the control electrode is arbitrary.

[0147] FIG. 28 shows a modification of the transistor device of FIG. 24. In the embodiment of FIG. 28, the channel region 43 is electrically connected to the compensation region 31 through a connection region 47 having the same doping type as the channel region 43 and the compensation region 31 but a higher doping concentration. The doping concentration of the connection region 47 is, for example, about 1E17 cm³. In FIG. 28 and in other cross-sectional views described below, the drain region of the transistor device is not shown.

[0148] FIG. 29 shows yet another embodiment of a transistor device including a coupling configuration with a coupling transistor. In this embodiment, the coupling configuration 40 is connected between the body region 13 and the compensation region 31, wherein the compensation region 31 is arranged below the body region 13 in the vertical direction of the semiconductor body. One end of the channel region 43 is adjacent to the body region 13, and the other end of the channel region 43 is adjacent to the compensation region 31 or the optional connection region 47. The optional connection region 47 has the same doping type as the compensation region 31 and the channel region 43, but it has a higher doping concentration.

[0149] Referring to FIG. 29, the control electrode 41 of the coupling transistor is implemented as a trench electrode, which respectively penetrates the body region 13 and the channel region 43 from the semiconductor body 100, and extends directly to or into the compensation region 31 Or optional connection area 47. The control electrode 41 is dielectrically insulated from these semiconductor regions by the control electrode dielectric 42.

[0150] In the embodiment of FIG. 29, the gate electrode 21 (of the enhancement mode MOSFET) is implemented as a planar electrode located on the surface of the semiconductor body 100 and extending from the source region 12 in the lateral direction of the semiconductor body 100. It extends along the body region 13 to the drain region 11, and is dielectrically insulated from these semiconductor regions by the gate dielectric 22. In this embodiment, a part of the drain region 11 extends to the surface of the semiconductor body 100.

[0151] The working principle of the transistor device of FIG. 29 is equivalent to the working principle of the transistor device of FIGS. 24 and 28. That is, the coupling configuration 40 with a coupling transistor provides a switch or a variable resistor between the source terminal S and the compensation region 31, and the source terminal S is electrically connected to the body region 13 through the contact region 15, wherein the variable resistance The resistance of the device can be adjusted by the control voltage applied between the control terminal G2 and the source terminal S. When the magnitude of the control voltage is higher than the threshold voltage of the depletion transistor, the compensation region 31 floats (electrically isolated from the body region 13). When the control voltage is lower than the threshold voltage, the depletion transistor acts as a resistor as explained with reference to FIGS. 23 and 24.

[0152] FIG. 30 shows yet another embodiment of a transistor device with a coupling configuration 40 including a coupling transistor. In this embodiment, the gate electrode 21 is implemented as a trench electrode that penetrates the source region 12 and the body region 13 from the surface of the semiconductor body 100 and extends straight to or into the drain region 11. The compensation region 31 has a distance from the gate electrode 21 in the lateral direction of the semiconductor body 100. The control electrode 41 of the coupling configuration 40 is implemented as a planar electrode, which is located on the surface of the semiconductor body 100 and extends from the contact region 15 along the channel region 43 to the compensation region 31 in the lateral direction of the semiconductor body 100. Optionally, in the surface region of the semiconductor body 100, a connection region 47 of the same doping type as the channel region 43 but with a higher doping concentration is adjacent to the channel region 43. Similar to the previously described embodiment, the body area 13 and the compensation area 31 have a distance.

[0153] FIG. 31 shows yet another embodiment of a transistor device. The transistor device of FIG. 31 is based on the transistor device of FIG. 24, and is different from the transistor device of FIG. 24 in that the field electrodes 25 and 48 electrically connected to the source terminal S are located at

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Below the gate electrode 21 and the control electrode 41. The field electrodes 25 and 48 are dielectrically insulated from the surrounding semiconductor regions by the field electrode dielectrics 26 and 49. The field electrode 26 below the gate electrode 21 is adjacent to the drain region 11, and the field electrode 48 below the control electrode 41 is adjacent to the compensation region 31 on one side and adjacent to the drain region 11 on the other side. The field electrodes 25 and 48 have a shielding function, and protect the gate dielectric 22 and the control electrode dielectric 42 from the dielectric electric field when the transistor device is in the off state. The connection between the field electrodes 25 and 48 and the source terminal S is only schematically shown in FIG. 31.

[0154] Quoting the description provided with reference to FIG. 24, the coupling transistor of the coupling configuration 40 can operate as a variable resistor that does not completely pinch off the electrical connection between the compensation region 31 and the source terminal S. The effect of providing a variable resistor between the compensation area 31 and the source terminal S has been explained with reference to FIG. 23. Invoking this description, when the transistor device is switched from the off state to the on state, the rate of discharge of the compensation region 31 can be adjusted by the control voltage applied to the control terminal G2. When the variable resistor is adjusted to have a very high resistance value, such as when the coupling transistor completely pinches off the channel region 43, the compensation region 31 cannot discharge when the transistor device is turned on. However, when the channel region between the compensation region 31 and the source terminal S is not completely pinched off (that is, when the control voltage is lower than the threshold voltage of the coupling transistor), the compensation region 31 discharges when the MOSFET is turned on. The discharge process is defined by the resistance value of the variable resistor (which can be implemented as a depletion transistor). In this case, the variable resistor determines the amount of charge that can flow from the compensation area to the source terminal within a predetermined period of time, wherein the charge flows to the compensation area 31 until the compensation area 31 is completely discharged.

[0155] FIG. 32 shows another embodiment of a transistor device. In this transistor device, not only can the amount of charge that can flow to the compensation area 31 be controlled within a predetermined period after the transistor device has been turned on, but also the total amount of charge that can flow out of the compensation area 31 can be controlled. After the transistor device has been turned on, controlling the charge flowing out of the compensation area 31 can adjust the output capacitance and therefore the on-resistance of the transistor device. Although in the previously described embodiment, the compensation area 31 is either left floating (resulting in low output capacitance but high on-resistance) or discharged (wherein the rate of discharge of the compensation area 31 can be changed), the transistor of FIG. 32 The compensation area 31 of the device can be partially discharged. Therefore, the output capacitance and on-resistance of the transistor device can be continuously changed. After the transistor device has been turned on, the amount of charge flowing out of the compensation area 31 is controlled by the two coupling transistors in the coupling configuration, namely the coupling transistor explained before (hereinafter referred to as the first coupling transistor) and the second coupling transistor .

[0156] In the embodiment of FIG. 32, the first coupling transistor is implemented as a depletion transistor. The embodiment of FIG. 32 is based on the embodiment of FIG. 24, so that everything that has been explained about the individual features of the transistor device of FIG. 24 is therefore applicable to the transistor device of FIG. 32. Similar to the transistor device of FIG. 24, the transistor device of FIG. 32 can be realized by using first coupling transistors with the same threshold voltage, using first coupling transistors with different threshold voltages, and using one or more control terminals G2.

[0157] In the embodiment of FIG. 32, the second coupling transistor is also implemented as a depletion transistor, and it includes adjacent to the second channel region 63 and is interposed between the second control electrode dielectric 62 and the second channel region 63. The second control electrode 61 is electrically insulated. The second channel region 63 is adjacent to the channel region 43 (which will be referred to as the first channel region hereinafter). In the embodiment of FIG. 32, the second control electrode 61 is located below the first control electrode 41 in the vertical direction of the semiconductor body 100, and is dielectrically insulated from the first control electrode 41 by a dielectric layer. The first channel region 43 is connected to the source terminal S directly or through an optional contact region 46, and the second channel region 63 is connected between the first channel region 43 and the compensation region 31. However, the order of having the first and second channel regions 43 and 63 connected between the source terminal S and the compensation region 31 may be changed to that which will be explained later herein. The first and second coupling transistors may be the same type of transistors. However, these coupling transistors can also be implemented as different types of transistors.

[0158] In the embodiment of FIG. 32, the transistor device further includes a field electrode 25 connected to the source terminal S and located below the gate electrode 21. However, the field electrode 25 is optional.

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[0159] FIG. 33 shows an equivalent circuit diagram of one transistor unit of the transistor device of FIG. 32. The equivalent circuit diagram of FIG. 33 is based on the equivalent circuit diagram of FIG. 25, and additionally includes a second coupling transistor 6 connected in series with the first coupling transistor 4 between the gate region of the JFET 3 and the source terminal S. The second coupling transistor 6 is also implemented as a depletion transistor, specifically, as a p-type depletion transistor. 32, the second coupling transistor 6 is formed by a second control electrode 61, a second control electrode dielectric 62, and a second channel region 63.

[0160] The doping concentration of the second channel region 63 may be equivalent to the doping concentration of the first channel region 43, or may be different from the doping concentration of the first channel region 43. The threshold voltage of the second coupling transistor can be adjusted by the distance between at least two opposite portions of the second channel region 63 and/or the second control electrode 61 and/or the thickness of the dielectric layer 62, and the second control electrode 63 It is arranged between these two opposing parts.

[0161] Hereinafter, the operating principle of the transistor device of FIGS. 32 and 33 will be explained. For the purpose of illustration, it is assumed that the transistor device is in an off state, so that the compensation area 31 has been charged. When the transistor device is turned on by applying a suitable driving voltage between the gate terminal G and the source terminal S, the control voltage between the control terminal G2 and the source terminal S determines the resistance of the first coupling transistor, and therefore defines the predetermined The amount of charge that can flow between the compensation area 31 and the source terminal S in a period of time. The second coupling transistor 6 defines the duration of the period during which charge can be transferred between the compensation region 31 and the source terminal S. The second coupling transistor 6 is controlled by the gate terminal G, and is turned off when the voltage between the gate terminal G and the source terminal S reaches the threshold voltage of the fourth transistor 6. When the transistor device is in the on state, the threshold voltage of the fourth transistor 6 is adjusted so that it is lower than the voltage finally applied between the gate terminal G and the source terminal S. For example, in the on state of the transistor device, the voltage (gate-source voltage) applied between the gate terminal G and the source terminal S is between 5V and 20V, in particular, between 10V and 15V. The threshold voltage of the second coupling transistor of the coupling configuration 40 is lower than this voltage. When the transistor device is to be turned on, the gate-source voltage is increased from the cut-off value to the on-value. The cut-off value is, for example, 0V in an n-type transistor device, and the turn-on value is equivalent to the previously described The final value. When the gate-source voltage increases, the second transistor of the coupling configuration is turned on until the gate-source voltage reaches the threshold of the second coupling transistor. During the period before the pinch-off of the second coupling transistor, the compensation area 31 can be discharged, wherein the amount of charge flowing from the compensation area 31 to the source terminal S within a predetermined period is defined by the first coupling transistor of the coupling configuration 40. After the second transistor has been pinched off, the compensation area 31 is independent of the control voltage applied between the control terminal G2 and the source terminal S and no longer discharges. In this way, in this embodiment, after the transistor device has been turned on, the amount of charge held in the compensation area can be controlled by the first and second coupling transistors.

[0162] FIG. 34 shows a vertical cross-sectional view of a transistor device according to another embodiment. The transistor device of FIG. 34 is based on the transistor device of FIG. 32 and additionally includes a connection area 47 between the second channel area 63 and the compensation area 31. The connection region 47 has the same doping type as the compensation region 31 and the first channel region 43 and the second channel region 63, but the degree of doping is higher.

[0163] FIG. 35 shows a vertical cross-sectional view of a transistor device according to another embodiment. In this embodiment, the first channel region 43 is arranged between the second channel region 63 and the compensation region 31. The channel region 63 is connected to the source terminal S either directly or via an optional contact region 65, wherein the optional contact region 65 has the same doping type as the second channel region 63, but the degree is higher. The connection area 47 between the first channel area 43 and the compensation area 31 is optional.

[0164] FIG. 36 shows an equivalent circuit diagram of one transistor unit of the transistor device of FIG. 35. This equivalent circuit diagram corresponds to the equivalent circuit diagram of FIG. 33. The difference is that in the series circuit with two coupling transistors between the source terminal S and the gate region (compensation region 31) of JFET3, the first and second coupling transistors The order of 4 and 6 are interchanged.

[0165] FIG. 37 shows another embodiment of a transistor device. In this embodiment, the gate electrode 21 is implemented as a trench electrode, and is adjacent to the body region 13 on one side of the trench, and adjacent to the second channel region 63 on the other side of the trench. Therefore, the gate electrode

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21 serves as the gate electrode of the MOSFET and the second control electrode of the second coupling transistor of the coupling arrangement 40 at the same time. The first control electrode 41 is positioned below the gate electrode 21 and adjacent to the first channel region 43. The first channel region 43 is adjacent to the second channel region 63, and is connected to the compensation region 31 either directly or via an optional connection region 47. As in the embodiment described with reference to FIGS. 32, 34 and 35, the compensation area 31 has a distance from the surface of the semiconductor body 100.

[0166] FIG. 38 shows another embodiment of a transistor device having a coupling configuration 40 that includes two transistors. In this embodiment, as in the embodiment of FIG. 37, the gate electrode 21 forms the gate electrode of the MOSFET and the second control electrode of the second transistor of the coupling configuration. The gate electrode 21 and the control electrode 41 of the first transistor of the coupling configuration 40 are spaced apart in the lateral direction of the semiconductor body 100, and both are implemented as trench electrodes. The gate electrode 21 is adjacent to the body region 13 on one side of the trench, and adjacent to the second channel region 63 on the other side of the trench. The second channel region 63 adjoins the first channel region 43 in the lateral direction of the semiconductor body 100. The first and second channel regions 43, 63 are connected between the source terminal S and the compensation region 31, among which the channel regions 43, 63 and the source terminal and the channel regions 43, 63 and the compensation region 31 The connecting areas 46 and 47 between are respectively optional. In this semiconductor device, the control electrode 41 controls the channel in the first channel region 43 when the semiconductor device is in the off state, specifically, controls the resistance (impedance) of the channel. The distance between the control electrode 41 and the gate electrode 21, the doping concentration of the first and second channel regions 43, 63, and the thickness of the dielectric layer 42 can be selected so that when the semiconductor device is in the on state, the gate The electrode 21 sandwiches the first channel region 43 and the second channel region 63.

[0167] Although various exemplary embodiments of the present invention have been disclosed above, it is easy for those skilled in the art to understand that various changes can be made without departing from the spirit and scope of the present invention. And changes to achieve some of the advantages of the present invention. It is obvious to those skilled in the art that other components that achieve the same function can be appropriately replaced. It should be pointed out that even if not explicitly mentioned, the features described with reference to a particular figure can also be combined with features in other figures. In addition, the method of the present invention can be implemented entirely by software using appropriate processor instructions, or can be implemented by combining hardware logic and software logic to achieve the same result. These changes made to the present invention fall within the protection scope of the claims of the present invention.

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