Method and system for utilizing dram components in a system-on-chip

Method and system for using dynamic random access memory component in system on chip

[0001] This application is a division of an invention patent with an application date of December 12, 2007, an application number of 200710199735. 1, and an invention title of "Method and System for Using Dynamic Random Access Memory Components in a System-on-Chip" please.

Technical field

[0002] The present invention mainly relates to integrated circuit (IC) design, and more particularly to a system-on-chip (SoC) design including core logic circuits, memory modules, and analog circuits with switched capacitors.

Background technique

[0003] In the IC industry, SoCs typically include digital logic circuits, memory modules, and analog circuits. The logic circuit includes core transistors and I/O or peripheral transistors. The core transistor can be a number of high-speed transistors with thin gate dielectric materials. I/O transistors can be several low-speed transistors with thick gate dielectric materials. A memory module, such as a DRAM cell array, includes many memory cells, and each memory cell typically includes an access transistor and a storage capacitor, such as a metal-insulator-metal capacitor. The thickness of the equivalent silicon dioxide layer of the gate dielectric material of the access transistor is designed to be thicker than the equivalent silicon dioxide thickness of the core logic transistor to prevent leakage current that hinders the function of the DRAM cell. The storage capacitor carries a bit of information of 0 or 1. When the storage capacitor is charged with electrons, it represents logic 1. When the storage capacitor is empty, it represents logic 0. The access transistor allows the control circuit to read or write the capacitance. Due to the current leakage of the capacitors, the control circuit needs to recharge or update all capacitors with logic 1 by reading the cells and then writing logic 1 to them. This update operation automatically occurs thousands of times every second. When the DRAM cells are out of power, their data will disappear. Analog circuits often include switched capacitor circuits, which include two switched capacitors, two switched transistors, and an operational amplifier. In order for the switched capacitor circuit to work properly, the capacitance ratio of the two switched capacitors needs to be maintained at a very precise value.

[0004] By convention, although the transistors of the analog switched capacitor circuit and the transistors in the digital logic circuit are manufactured substantially during the same process, the capacitor manufacturing process of the switched capacitor circuit is separate from the storage capacitor manufacturing process of the memory cell. This will increase manufacturing costs and reduce yield, which is becoming increasingly important in newer semiconductor process technologies, such as the 90nm generation.

[0005] Moreover, the conventional manufacturing process of the switched capacitor circuit constructs the switched capacitor in a planar manner rather than a vertical manner. Therefore, conventional switched capacitors are large in size and often occupy a large area.

[0006] Therefore, there is a need to design a method and system for an SoC including a logic circuit, a memory module, and an analog circuit. The SoC effectively utilizes the wiring area and has a low manufacturing cost.

Summary of the invention

[0007] A system-on-chip semiconductor circuit, including: a logic circuit having a first transistor (core logic transistor) with a first gate dielectric material; at least one dynamic random access connected to the logic circuit A memory cell, the at least one dynamic random access memory cell having at least one storage capacitor and at least one second transistor with a second gate dielectric material; and, an analog circuit that operates with the logic circuit and the memory cell, The analog circuit has at least one switched capacitor and at least one third transistor with a third gate dielectric material; wherein, the switched capacitor is manufactured by substantially the same process steps as the storage capacitor, and therefore, the switched capacitor and the storage capacitor The capacitance is essentially

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They have the same structure, and each capacitor is formed in a two-dimensional array composed of capacitor units, wherein an outer row or column of the array contains capacitor units that are not used to provide any function.

[0008] However, the structure and method of operation of the present invention, as well as other objectives and advantages, can be understood from the following specific embodiments in conjunction with the accompanying drawings.

Description of the drawings

[0009] FIG. 1 is a circuit diagram of a switched capacitor circuit according to an embodiment of the present invention;

[0010] FIG. 2 is a diagram showing the cell capacitance distribution on a 12-inch wafer;

[0011] FIG. 3 is a structure diagram of a metal-insulator-metal (MiM) capacitor of a switched capacitor according to an embodiment of the present invention;

[0012] FIG. 4 is a diagram of a 7X7 capacitor array according to an embodiment of the present invention;

[0013] FIG. 5 is a schematic diagram showing the center arrangement of a plurality of capacitor arrays according to an embodiment of the present invention.

Detailed ways

[0014] The present invention discloses a method and system for using embedded DRAM cells in system-on-chip (SoC) applications. A DRAM cell typically has at least one access transistor and at least one storage capacitor. The storage capacitor is typically a high area efficiency capacitor, such as a vertically constructed metal-insulator-metal (MiM) capacitor. Because the SoC always has a DRAM module, in order to reduce the manufacturing cost and improve the area efficiency, the transistors and capacitors of the analog part of the SoC and the transistors and capacitors of the memory module need to be formed by the same process.

[0015] FIG. 1 is a switched capacitor circuit 100 of the SoC analog part of an embodiment of the present invention. The switched capacitor circuit 100 includes two switched capacitors 102 and 104, two switched transistors 106 and 108, and an operational amplifier (op-amp )110. Those skilled in the art can understand that the switches 106 and 108 can be implemented by many transistors. In order for the switched capacitor circuit 100 to work normally, the capacitance ratio of the switched capacitors 102 and 104 needs to be maintained at a very accurate value. During operation, the switching transistors 106, 108 are designed to be selectively turned on and off in order to charge the switched capacitors 102, 104 to provide a value equal to Vin*(Cio₄/C102) is the output voltage Vout, where Vin represents the input voltage, C102 represents the capacitance of the capacitor 102, and Ci(m represents the capacitance of the capacitor 104.

[0016] The present invention simplifies the process of manufacturing SoC. In the process, at least one non-core logic circuit (such as 1/0), at least one memory module, and at least one analog circuit are involved. In order to reduce manufacturing costs and improve area efficiency, in SoC, at least one analog circuit, such as a switched capacitor circuit, will be manufactured using the same process used to manufacture DRAM modules.

[0017] In this embodiment, the switched capacitors 102, 104 are manufactured by essentially the same process as the storage capacitors in the DRAM cell. Therefore, the structure of the switched capacitors 102 and 104 is similar to that of a DRAM storage capacitor. The switched capacitors can be metal-insulator-metal (MiM) capacitors, polymer-insulator-polymer (PIP) capacitors or trench capacitors. In order to provide high-precision capacitance matching, the switched capacitors 102 and 104 are preferably crown-type MiM capacitors. Table 1 below shows that for the same area, compared to the traditional planar MiM capacitor, the crown-type MiM capacitor can store a considerable amount of charge.

[0018] Table 1

[0019]

<td></td><td>Traditional MiM (flat type)</td><td>1Τ-ΜΐΜ (crown type)</td>

<td>capacitance</td><td>4.8pf</td><td>15pf</td>

<td>STD deviation</td><td>0.3%</td><td>0.17%</td>

<td>area</td><td>-3000um²</td><td>-3000um²</td>

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[0020] FIG. 2 shows a cell capacitance distribution diagram of a cell on a 12-inch wafer. The average capacitance per 100 units is 5.35fF, which is -3 at 5.2fF. ,+3 at 5.5fF. , Among them, the sigma standard deviation (.) is equal to 0.055fF. If many units are used as one unit, the distribution will be narrower. For example: Connect about 1000 5fF units together to make a 5pF unit of switched capacitor circuit capacitance. The standard deviation will be reduced to l/sqrt(N) = 1/sqrt (1000/100) or 1/3.1 of the cell capacitance. One standard deviation of the average capacitance ratio will decrease from 0.05/3. L = 0.016f to 5.35f, which is about 0.30%. In other words, the worst-case mismatch can be controlled below 0.30% or 8-bit accuracy, which is good enough for most switched capacitor circuits. The above data is based on a wafer. The actual circuit size is several hundred microns. It can be understood that a transistor with a thicker gate dielectric material can be an access transistor of an embedded DRAM cell or even an I/O transistor of a logic circuit, which is not a core part of the logic circuit design.

[0021] In the embodiment shown in FIG. 1, the analog circuit components, such as the switching transistors 106, 108 and the switching capacitors 102, 104 are formed by the same process used to manufacture the DRAM module. As a result, the gate dielectric material layer of the switching transistors 106, 108 Compared with the core logic circuit transistor, it has a relatively thicker EOT. During manufacturing, the SoC needs to comply with certain predetermined design rules and conditions. For example: If a non-high-K material with a dielectric constant less than 8 is used for the gate dielectric material, EOT needs to be equal to or less than 25A. If a non-high-K material with a dielectric constant greater than 8, EOT needs to be equal to or less than 50A_o

[0022] Because the switching transistors 106, 108 and the switched capacitors 102, 104 are manufactured using a DRAM manufacturing process, instead of using a single set of analog circuit technology, the manufacturing cost and cycle of the switched capacitor circuit 100 can be greatly reduced. For example, when the SoC chip is manufactured with a 90nm node technology process, the following table 2 shows that compared with the traditional method, the proposed embodiment of the present invention can save 4 photolithography masks (ie: N-well, P-well) , N-type LDD and P-type LDD ion implantation mask).

[0023] Table 2

[0024]

<td></td><td>SoC manufactured with the proposed embodiment of the present invention</td><td>SoC manufactured by traditional methods</td>

<td>Required mask</td><td>A mask</td><td>A+4 mask</td>

<td>manufacturing cost</td><td>X</td><td>X+10%</td>

<td>Manufacturing cycle</td><td>Y days</td><td>Y+10 days</td>

[0025] Saving 4 photolithography masks can reduce the manufacturing cost by 10% and the manufacturing cycle of 10 days, respectively. The switching transistor 108 has a gate dielectric material that is relatively thicker than the transistor of the core logic circuit. The thick gate dielectric material is designed to prevent leakage currents that hinder the function of the DRAM. The thicker gate dielectric material transistors can be used in any analog circuit without adding additional costs because they are manufactured using the same DRAM process. For example: This thicker oxide device can also be used as a decoupling capacitor and feedback filter (loop filter) in phaselock-loops. In addition, although the EOT of the thick and thin gate transistors may be different, in order to simplify the manufacturing process, their manufacturing materials may be the same.

[0026] FIG. 3 is a cross-section 300. According to an embodiment of the present invention, the cross-section 300 shows how to use the MiM structure 302 of a DRAM cell as a capacitor in the switched capacitor circuit shown in FIG. 2. Metal-insulator-metal (MiM) structures have been used to form capacitors because of their low interface response characteristics, which can improve capacitor performance. In the cross section 300, the MiM structure 302 is formed as a part of the DRAM memory cell 304 and is connected between the active area 306 and the contact hole 308. The DRAM memory cell 304 is disposed on a substrate, and the substrate includes a semiconductor material, such as glass, bulk silicon or SOI °MiM structure 302 can be formed by damascene or photolithography/plasma process. The bottom or top electrode can be made of metal-containing materials, such as aluminum alloy or copper. Due to the high capacitance ratio per unit area of the MiM structure 302, it is ideal to use them as charge pumps or switched capacitors as unit capacitors in SoC applications. Such MiM capacitors can be formed in the following specific arrangements to reduce process variation.

[0027] FIG. 4 is a two-dimensional capacitor array 400. According to an embodiment of the present invention, the capacitor array 400 is implemented in a SoC.

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The current 7 X 7MiM capacitor unit 404. Each MiM unit in the capacitor array is connected to an adjacent MiM unit through interconnection (not shown). The MiM cell ring on the outer part of the capacitor array is not used to provide functions, but is implemented together with dummy cells to ensure that all internal cells 402 are uniformly performed during the printing and etching processes with a very low defect rate. These dummy cells can function as decoupling capacitors if needed.

[0028] It is worth noting that the capacitor array can typically be constructed with a capacitance of 0.5 pF or 1 pf. It is also worth noting that the 7X7 format is only an example, and the capacitor array can be in various modes different from those shown in FIG. 4.

5 is a schematic diagram 500, according to an embodiment of the present invention, the schematic diagram 500 shows a central capacitor wiring structure including capacitor arrays 502, 504, 506, 508 used on SoC. In this embodiment, each capacitor array 502, 504, 506, 508 is the same as the capacitor array 400 in FIG. 4, and when used together, they are used to construct the capacitors 102, 104 used in the switched capacitor circuit 100 shown in FIG._οFor example, each capacitor 102, 104 is formed by two equal capacitor arrays placed and connected diagonally to each other. Capacitor 102 is formed by connecting capacitor arrays 502 and 508 diagonally (the line 510 represents their connection), and capacitor 104 is formed by connecting capacitor arrays 504 and 506 diagonally (the line 512 represents their connection). And formed. By constructing the capacitor in this way, any process variation in the horizontal, vertical, or diagonal directions can be eliminated, so that the capacitance ratio between the capacitors 102 and 104 can be kept stable. It is understandable that, in order to eliminate process variation in the horizontal, vertical or diagonal directions, other symmetrical arrangements of capacitor wirings can also be used based on a reference center point. For this application, this arrangement refers to a center-symmetric arrangement. It is worth noting that the virtual ring in FIG. 4 does not need to surround the units 502, 504, 506, and 508 individually, but can surround them as a whole.

[0030] In the SoC, other components, such as the transistors in the logic circuit I/O area and the PLL circuit feedback filter, can be manufactured with the same mask used to manufacture the thick oxide transistors of the embedded memory components, and the total manufacturing cost can be greatly reduced. .

[0031] The above description provides many different embodiments or embodiments that implement different features of the present invention. Specific examples of components and processes are described to help clarify the present invention. Of course, they are only examples, not limiting the invention described in the claims.

[0032] Although only one or more specific embodiments are used to illustrate and describe the present invention. However, since other changes and structures can be made that do not depart from the idea of the present invention and the equivalent scope of the claims, they are not intended to be limited by the details shown. Correspondingly, a wide range of dependent claims can be constructed in a manner consistent with the scope of the present invention, as described in the claims.

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