Method for manufacturing chip elements provided with wire insertion grooves

Manufacturing method of chip component equipped with wiring insertion grooveTechnical field

[0001] The present invention relates to microelectronic chip components whose maximum dimensions can be less than the order of millimeters, and which are fixed to conductive wirings used to, for example, supply power to the chips.

Background technique

[0002] As described in the patent application WO2009112644, FIG. 1 shows a perspective view of a chip component 10 fixed to two parallel wirings 12a and 12b. The element 10 has a substantially parallelepiped shape, and its two opposite side surfaces are each provided with parallel grooves 14 a, 14 b extending over the entire length of the element 10. Each of these slots accommodates its own wiring 12a and 12b_o

[0003] The wirings 12a and 12b generally play a role of electrical connection, for example, supplying current to a light emitting diode formed in a chip of the element 10. Thereby, the wirings 12a and 12b are conductive and are electrically connected to the chip through the conductive bump 16 formed on the side wall of each groove. The width of the groove and the height of the bump 16 are selected according to the diameter of the wiring 12 so that each wiring is sandwiched between the bump and the opposite side wall of the groove 14.

[0004] Elements of the type shown in FIG. 1 are usually made in two parts. The first part 18a corresponds to the bottom third of the element and is formed by a chip. The second part 18b corresponds to the remaining top part of the element and forms a protective cover. The active surface of the chip facing the cover 18b includes bumps 16 and forms the first sidewall of the groove 14. The cover 18b has a T-shaped cross-section so that it can form the second side wall and bottom of the groove.

[0005] Since the chip component 10 is small, the assembly of the cover 18b to the chip 18a will cause some problems. In particular, it is difficult to maintain the separation distance between the side walls of the groove 14 in a repeatable manner. As described in the aforementioned patent application WO2009112644, it is desirable to fix the wiring 12 between the bump 16 on one side of the groove and the opposite side wall on the other side of the groove by being flexibly clamped in the groove. If the separation distance is too large, the wiring 12 will not be clamped. If the separation distance is too small, the wiring cannot be inserted into the slot without damaging the element 10.

Summary of the invention

[0006] Therefore, it is desirable to seek a method capable of ensuring a repeatable and precise separation distance between the side walls of the groove.

[0007] In order to meet this requirement, a method for manufacturing a chip component provided with a groove is provided. The method includes the following steps: a conductive circuit is provided on an interconnect substrate, and the conductive circuit is arranged to align the active surface of the chip. The contact area is connected to the area corresponding to the first wall of the groove; at the area corresponding to the first wall of the groove, contact bumps are grown on the conductive path by electrodeposition; the chip is assembled on the substrate via its active surface to Make the sidewall of the chip form the bottom of the groove; process the chip through the back surface of the chip parallel to the substrate, and measure the distance between the back surface of the chip and the contact bump at the same time; stop processing when the measured distance reaches the required value And assembling by joining the board to the back surface of the chip to form the second wall of the groove.

[0008] According to an embodiment of the method, the assembly stage includes the following steps: applying some polymerizable adhesive to the back surface of the chip at the liquefaction temperature of the adhesive; placing the board under a pressure On the chip, to obtain a minimum thickness of the adhesive between the board and the chip and squeeze out the excess adhesive; and heat the adhesive to the polymerization temperature while maintaining the pressure.

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[0009] According to an embodiment of the method, the back surface of the board or chip is provided with a cavity designed to collect excess adhesive squeezed out by the pressure.

[0010] According to an embodiment, the method includes the following steps: depositing a continuous conductive bottom layer that promotes electrodeposition and covers the substrate and the conductive circuit; Growing micro-inserts on the continuous bottom layer; growing contact bumps on the continuous bottom layer; removing excess continuous bottom layer; and assembling the chip on the substrate so that the contact area of the chip is pressed on the micro-insertion.

Description of the drawings

[0011] Through the following description of the specific embodiments, other advantages and features will become more clear and obvious. The specific embodiments are only given for the purpose of non-limiting examples and are shown in the accompanying drawings. :

[0012] FIG. 1 shows a perspective view of a chip component fixed to two wirings, and FIG. 1 has been described previously;

[0013] FIG. 2 shows a front view of an embodiment of a chip element including a chip connected to an interconnect substrate via its active surface; and

[0014] FIGS. 3a to 3e show manufacturing steps of a chip component of the type shown in FIG. 2.

Detailed ways

[0015] FIG. 2 shows an embodiment of a specific type of chip component seeking to improve groove width accuracy.

[0016] In this chip component, the chip 20 is directly connected to the interconnection substrate 22 via its active surface (ie, the surface on which the circuit is made) according to a technology generally called flip chip. Thus, the side walls of the chip 20 form the bottom of the grooves 14a and 14b, and the portion of the substrate 22 protruding with respect to the chip forms the first wall of the groove. The opposing second wall of the groove is formed by the protruding part of the plate 24 which is fixed by being glued to the back surface of the chip 20.

[0017] The substrate 22 includes a conductive track 26 on its upper surface, and the conductive track 26 is designed to connect the contact area of the chip 20 to the bumps 16 provided on the first wall of the groove 14. The contact area of the chip 20 is connected to the conductive circuit 26 through solder beads 28 or any other member suitable for flip-chip technology. These solder beads are also used to fix the chip. The coating material 30 fills the space between the chip 20 and the substrate 22 and embeds the solder beads 28.

[0018] As shown, the wires 12a and 12b are preferably sandwiched between the bump 16 and the opposite wall of the groove 14 (ie, the wall defined by the plate 24). As mentioned before, if the separation distance between the bump and the opposite wall is too large, the wiring 12 will not be clamped. If the separation distance is too small, the wiring cannot be inserted into the slot without damaging the components. Therefore, the assembly method of chip components must ensure that the separation distance has sufficient accuracy.

[0019] The constraining factor of the size between the bump 16 and the opposite wall of the groove includes a plurality of elements, specifically the bump 16, the solder bead 28, the chip 20, and the adhesive layer between the chip 20 and the board 24. The sum of the dimensional uncertainties of all these components will make it impossible to obtain the desired accuracy in a repeatable manner, unless special care is taken.

[0020] Here, a specific selection of a manufacturing method that can achieve the required accuracy in a repeatable manner is proposed. Specifically, the contact bump 16 is manufactured by electrodeposition. Although this method is not very precise, the height of the bumps has consistent characteristics across the entire processed wafer. After the chip is assembled on its substrate, the chip is ground through its back surface and the height between the bump and the back surface is measured at the same time. Grinding stops when the measurement corresponds to the required size. The measurement is performed in a conventional manner by a comparator or profilemeter. Then, the board 24 is bonded to the back surface of the chip 20 by a method capable of obtaining an adhesive layer of the smallest thickness.

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[0021] FIGS. 3a to 3e show various steps of a method of manufacturing a chip component of the type shown in FIG. 2. This method is suitable for manufacturing several chip components on a silicon wafer, where the silicon wafer is designed to form the interconnect substrate 22 of the chip components.

[0022] In FIG. 3a, a substrate 22 made of silicon, for example, is covered by a full-wafer insulating layer 32 made of silicon oxide, on which a full-wafer insulating layer 32 has been formed, for example, made of aluminum.Guidecircuit 26. Designed to facilitate electrodeposition and cover the conductive circuit with a whole wafer continuous bottom layer 34 made of, for example, titanium and copper alloys.

[0023] A micro-insert 36 designed to make contact with the chip is formed on the continuous bottom layer 34 by electrodeposition at a suitable portion of the conductive circuit 26. This becomes an advantageous alternative to solder beads to connect the chip to the substrate. This solution enables a thinner interface (between 2 and 10 um) and thus makes it less sensitive to humidity (smaller lateral exchange surface).

[0024] In FIG. 3b, bumps 16 are formed by electrodeposition. To this end, a cross-linkable resin layer 38 is deposited on the continuous bottom layer 34, and then exposed and etched to remove the resin at the bump positions. The bumps are grown on the continuous bottom layer 34 by electrodeposition at these positions. The height of the bump depends on the time of electrodeposition. The thickness of the resin has no effect-it only needs to be larger than the required height of the bump 16.

[0025] Electrodeposition is preferably performed with two materials. First deposit for example a sickle layer above 15 pm, then for example

The gold layer above 3um promotes contact with the wiring 12 (Figure 2).

[0026] In FIG. 3c, the excess resin and the continuous bottom layer 34 are removed. Thus, bumps 16 and micro-inserts 36 remain on the continuous bottom layer of material islands and are in electrical contact with circuit 26.

[0027] Although the height of the bumps 16 cannot be obtained with the required accuracy, the height of the bumps 16 can be made uniform across the entire processing wafer.

[0028] In FIG. 3d, the chip 20 is assembled on the substrate 22, and the contact area of the active surface of the chip 20 is placed on the microinsert 36. The contact is established by applying sufficient pressure on the chip to allow the microinsert to partially enter the contact area of the chip. The coating material 30 is added to the space between the chip 20 and the substrate 22. The coating material also used here to fix the chip on the substrate is preferably a polymerizable glue or resin.

[0029] Then, by grinding or any other suitable processing form, the height of the chip 20 is reduced from its back surface. The initial height of the chip is indicated by a dashed line. During the grinding process, the distance between the back surface of the chip and the apex of the bump 16 is measured. When the required distance d is reached, the grinding stops. This distance corresponds to the diameter of the wire 12 to be inserted into the groove. Current machining tools allow this distance to be monitored and focused with an accuracy that fully meets the requirements described here.

[0030] In FIG. 3e, a plate 24 made of glass, for example, is attached to the back surface of the chip 20 by bonding. It is desirable that the adhesive seal layer 40 has the smallest thickness so that its deviation hardly affects the final distance obtained between the bump 16 and the board 24. For this, bonding is performed by thermal compression.

[0031] A suitable dose of adhesive (eg epoxy E505-EP0TECNY) drops are deposited on the back surface of the chip 20, or a uniform layer is spin-coated on the board 24. The dosage of the adhesive is preferably to cover the entire top surface of the chip 20 without spilling onto the bumps 16 after bonding.

[0032] The plate 24 is placed on the chip 20 with sufficient pressure to squeeze most of the adhesive to the edge of the chip. The pressure is maintained during the curing process of the adhesive, and the curing process of the adhesive preferably includes two temperature plateaus. For E505 resin, the first platform is maintained at 50 to 90°C for 10 to 30 minutes, and is designed to liquefy the adhesive to facilitate the migration of the adhesive. The second platform is kept above 90°C for 10 to 60 minutes and is designed to polymerize the adhesive.

[0033] In order to further facilitate the reduction of the thickness of the adhesive sealing layer, as shown, a cavity is provided at the bottom of the plate 24

surface. For example, the cavity in the form of a groove formed by a saw may also be provided on the back surface of the chip 20. By accumulating excess adhesive, these cavities shorten the migration path of the extruded adhesive.

[0034] Through these different measures, an adhesive sealing layer with a thickness of about 1 μm is obtained, and the adhesive sealing layer can be more effective than the bump

The dimensional tolerance required for the separation distance between 16 and the plate 24 is repeated with a significantly smaller dimensional tolerance.

[0035] It can be seen that although the different steps of FIGS. 3a to 3e are described with respect to a single chip element, the different steps of FIGS. 3a to 3e can be advantageously applied to the chip element matrix made of the wafer forming substrate 20. The grinding operation is performed on the group of assembled chips 20. A board 24 having the same size as the matrix is placed on the group of chips 20. Each chip component is finally separated by dicing.

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