Method for identifying connected device and electronic device using the same

Resistive random access memory and its manufacturing method technical field

[0001] The present invention relates to an integrated circuit device, and more particularly, to a non-volatile memory having a resistive memory cell therein.

Background technique

[0002] Generally, Resistive Random Access Memory (ReRAM) is a type of non-volatile memory that uses the principle that resistance characteristics change with applied voltage. ReRAM is a type of memory that utilizes the The on/off state of the current caused by the magnitude of the applied voltage. These ReRAMs have various advantages: relatively fast access time, low power consumption, and reduction of process failures due to a simple memory cell structure.

[0003] As shown in FIG. 1A, an example of ReRAM is named by Herner et al.^u"NONVOLATILE MEMORY CELL COMPRISING A DIODE AND ARES I STANCE-SWITCHING MATERIAL" was disclosed in US Patent Application Publication No. 2006/0250837.

[0004] Referring to FIG. 1A, the diode 16 and the resistive switching element 18 are stacked between the bottom conductor 12 and the top conductor 14, thereby forming a storage layer 20. Multiple storage layers 20 are stacked to form a high-density monolithic three-dimensional storage array. FIG. 1B schematically shows the resistance random access memory 10 having the above-mentioned monolithic three-dimensional memory array.

[0005] Referring to FIG. 1B, when the resistance random access memory 10 is implemented by forming a three-dimensional memory array 30, the number of process steps required for stacking N memory layers may be equal to the value "NXS", which is the value "NXS" is formed by forming One storage layer 20 defines the product of the number S of process steps required for multiple memory cell blocks and the number N of stacked storage layers. In other words, as the number of stacked layers increases, the number of process steps also increases linearly.

[0006] The bottom conductor 12 and the top conductor 14 extend in orthogonal directions, and a memory cell is formed at the intersection between them. Generally speaking, the bottom conductor 12 may form a word line, and the top conductor 14 may form a bit line. For example, when the number of word lines 12 is K and the number of bit lines 14 is M, the number of memory cell blocks formed on one memory layer 20 is KXM. In this way, when the number of stacked memory layers 20 is N, the number of memory cell blocks to be formed is ΝΧΚΧΜ. [0007] The number of decoders required to access KXM memory cell blocks on one storage layer 20 is "Κ+ Μ", which is the sum of the number K of word lines 12 and the number M of word lines 14. If N memory layers 20 are stacked, the number of decoders may be the value "(ΝΧΚ) + (ΝΧΜ)", which is the number of stacked word lines 12 "ΝΧΚ" and the number of stacked bit lines 14 "ΝΧΜ" Sum. In other words, as the number of stacked layers increases, the number of decoders also increases linearly. Therefore, forming a decoder requires an area and this number of process steps.

Summary of the invention

[0008] Embodiments of the present invention provide a resistance random access memory capable of realizing a high-density memory array and a manufacturing method thereof.

[0009] Embodiments of the present invention also provide a resistive random access memory having a stack of bit lines and a comb-shaped word line and a method for manufacturing the same. In the bit line stack, a plurality of local bit lines are stacked vertically, and the comb-shaped word A plurality of partial word lines vertically provided between the bit line stacks among the lines are electrically connected to each other.

[0010] The embodiment of the present invention provides a method of manufacturing a resistance random access memory, the method includes: forming a bit

Line stacking, in which a plurality of local bit lines are vertically stacked on the substrate; forming a word line including a plurality of local word lines and connecting lines, the plurality of local word lines are stacked in a vertical direction toward the bit line The connecting line extends in a horizontal direction to connect a plurality of partial word lines to each other; and a resistive storage film between the bit line stack and the word line is formed.

[0011] In some embodiments, the method may further include: forming a bit line stack; forming a resistance storage film covering the bit line stack; depositing a conductive material on the resistance storage film; and forming a word line by patterning the conductive material.

[0012] In other embodiments, the method may further include: forming a bit line stack; forming a resistance storage film covering the bit line stack; depositing an insulating material on the resistance storage film; and forming an exposed resistance storage film by patterning the insulating material The trench; and the word line is formed by depositing conductive material in the trench.

[0013] In still other embodiments, the method may further include: forming a bit line stack; depositing an insulating material on the substrate; forming a trench exposing the bit line stack by patterning the insulating material; forming a resistive memory in the trench Thin film; and forming a word line on the resistive storage film by depositing conductive material in the trench.

[0014] In still other embodiments, the method may further include: forming a switching film between the resistance storage film and the word line.

[0015] In other embodiments, forming a bit line stack may include: forming a stack in which a plurality of insulating layers and a plurality of conductive layers are selectively deposited on a substrate; and forming a hard mask on the stack Patterns; and patterning the stacked body by etching using the hard mask pattern as a mask.

[0016] An embodiment of the present invention provides a resistance random access memory, which includes: a stack of bit lines extending in a first horizontal direction and provided with a plurality of local bit lines stacked vertically on a substrate; word lines, A plurality of local word lines and connecting lines are provided, the plurality of local word lines are vertically arranged at the side of the bit line stack, and the connecting lines extend along a second horizontal direction crossing the first horizontal direction to connect the plurality of local word lines. The lines are connected to each other; and a resistive storage film is provided between the bit line stack and the word line.

[0017] In another embodiment, the connection lines may be arranged to be stacked across the bit lines.

[0018] In another embodiment, the bit line stack may further include a hard mask pattern on the topmost layer thereof.

[0019] In another embodiment, the resistance random access device may further include a switching film between the resistance storage film and the word line.

Description of the drawings

[0020] The drawings are included to provide a further understanding of the present invention, and are incorporated into and constitute a part of the present invention. The drawings illustrate exemplary embodiments of the present invention and together with the description serve to explain the principles of the present invention. In the drawings: [0021] FIG. 1A is a perspective view showing a resistance random access memory according to a conventional technology;

[0022] FIG. 1B is a circuit diagram schematically showing a memory array of a stacked resistive random access memory according to the conventional technology;

[0023] FIG. 2A is an equivalent circuit diagram showing a resistance random access memory according to an exemplary embodiment of the present invention; [0024] FIGS. 2B and 2C are circuit diagrams showing a part of FIG. 2A;

[0025] FIG. 3A is a perspective view showing a resistance random access memory according to a first exemplary embodiment of the present invention; [0026] FIG. 3B is a perspective view including a cross-section taken along line 1-1 of FIG. 3A;

[0027] FIG. 3C is a perspective view showing the memory cell block of FIG. 3A;

[0028] FIG. 4A is a perspective view showing a resistance random access memory according to a second exemplary embodiment of the present invention; [0029] FIG. 4B is a perspective view including a cross-section taken along line 11-11 of FIG. 4A;

[0030] FIG. 5A is a perspective view showing a resistance random access memory according to a third exemplary embodiment of the present invention;

[0031] The perspective view of FIG. 5B includes a cross-section taken along the line mm of FIG. 5A;

[0032] FIG. 5C is a perspective view showing the memory cell block of FIG. 5A;

[0033] FIG. 6A is a perspective view showing a resistance random access memory according to a fourth exemplary embodiment of the present invention;

[0034] The perspective view of FIG. 6B includes a cross-section taken along line IV-IV of FIG. 6A;

[0035] FIG. 7A is a perspective view showing a resistance random access memory according to a fifth exemplary embodiment of the present invention;

[0036] The perspective view of FIG. 7B includes a cross-section taken along line VV of FIG. 7A;

[0037] FIGS. 8A to 8G are cross-sectional views showing a method of manufacturing a resistance random access memory according to the first exemplary embodiment of the present invention;

[0038] FIGS. 9A to 9D are cross-sectional views showing a method of manufacturing a resistance random access memory according to a second exemplary embodiment of the present invention;

[0039] FIGS. 10A to 10D are cross-sectional views showing a method of manufacturing a resistance random access memory according to a third exemplary embodiment of the present invention;

[0040] FIGS. 11A to 11D are cross-sectional views showing a method of manufacturing a resistance random access memory according to a fourth exemplary embodiment of the present invention;

[0041] FIGS. 12A to 12G are cross-sectional views showing a method of manufacturing a resistance random access memory according to a fifth exemplary embodiment of the present invention;

[0042] FIGS. 13A to 13G are cross-sectional views showing a method of manufacturing a resistance random access memory according to a sixth exemplary embodiment of the present invention;

[0043] FIGS. 14A and 14B are diagrams showing current-voltage curves of the switching film according to the first exemplary embodiment of the present invention;

[0044] FIG. 15A is a block diagram showing a memory card including a resistance random access memory according to an exemplary embodiment of the present invention; and

[0045] FIG. 15B is a block diagram showing an information processing system suitable for a resistance random access memory according to an exemplary embodiment of the present invention.

Detailed ways

[0046] Hereinafter, a resistance random access memory and a method of manufacturing a resistance random access memory according to exemplary embodiments of the general inventive concept of the present invention will be described with reference to the accompanying drawings.

[0047] The advantages and features of the general inventive concept of the present invention and the method for accomplishing them can be more easily understood by referring to the following detailed description of the preferred embodiments and the accompanying drawings. However, the general inventive concept of the present invention can also be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that these disclosures are thorough and complete and fully convey the idea of the present invention to those skilled in the art, and the present invention will only be defined by the appended claims. The same reference numerals refer to the same elements throughout.

[0048] Equivalent circuit diagram

[0049] FIG. 2A shows an equivalent circuit diagram of a resistance random access memory according to an exemplary embodiment of the present general inventive concept; the circuit diagrams of FIGS. 2B and 2C show a part of FIG. 2A.

[0050] Referring to FIG. 2A, the resistance random access memory 1 may include a three-dimensional (3D) cross-point structure. In this 3D cross-point structure, each memory cell block is defined in each cross point between a word line and a bit line, and these memory cell blocks

Arranged in three dimensions.

[0051] For example, the resistance random access memory 1 may include a plurality of word lines W1, W2, W3, and W4 to form a YZ plane and a plurality of bit lines B1, B2, and B3 to form an XZ plane. The word lines W1 to W4 and the bit lines B1 to B3 may serve as electrodes. As another example, the resistance random access memory 1 may include a plurality of bit lines W1, W2, W3, and W4 forming a YZ plane and a plurality of word lines B1, B2, and B3 forming an XZ plane. The former example will be described here, and the latter example can be applied to the following description.

[0052] The word lines W1 to W4 may be oriented in the X-axis direction, and conversely, the bit lines B1 to B3 may be oriented in the Y-axis direction. The word lines W1 to W4 intersect the bit lines B1 to B3, thereby forming a plurality of crossing points. The memory cell block 2 can be defined in each of these intersections. The X-axis direction, the Y-axis direction, and the Z-axis direction may be substantially at right angles to each other, and the YZ plane may be at right angles to the XZ plane.

[0053] Each of the word lines W1 to W4 may be configured in a comb shape. For example, the first word line W1 includes a plurality of word lines W1, KW12, W13 and W14 (hereinafter referred to as local word lines) extending in the Z-axis direction, and these local word lines W11 to W14 may pass through the first word lines W11 to W14 extending in the Y-axis direction. The connecting wires W10 are electrically connected to each other. Thus, the first word line W1 can be constructed by the YZ plane. Similarly, the second word line W2 includes a plurality of local word lines W21. W22, W23 and W24 extending in the Z-axis direction, and these local word lines W21 to W24 can be mutually extended by a second connection line W20 extending in the Y-axis direction. Electric connection. Thus, the second word line W2 can be constructed by the YZ plane. The above description can also be applied to the third word line W3 and the fourth word line W4. Although only four word lines W1 to W4 are shown in the exemplary embodiment of the present invention, the number of word lines may be arbitrary. For example, the number of word lines may be Ko, that is, the word lines may be designated WK (where K is 1, 2, 3, and 4 in this exemplary embodiment).

[0054] The first bit line B1 of the plurality of bit lines B1, B2, and B3 includes a plurality of bit lines B11, B12, B13, and B14 (hereinafter referred to as local bit lines) extending in the X-axis direction, and these local bit lines The lines B11 to B14 may be stacked in the Z-axis direction. The second bit line B2 includes a plurality of local bit lines B21, B22, B23, and B24 extending in the X-axis direction, and these local bit lines B21 to B24 may be oriented in the Z-axis direction. The above description can also be applied to the third bit line B3. Although only three bit lines B1 to UB3 constructed from four layers (that is, the number of local bit lines) are shown in the present exemplary embodiment, the number of bit lines and the number of layers may be arbitrary. For example, the number of bit lines may be M, and each bit line may be constructed of N layers. That is, the bit line may be designated as BMN (where M is 1, 2, and 3, and N is 1, 2, 3, and 4 in this exemplary embodiment). [0055] The first bit line B1 may be disposed to pass between the first local word line W11 and the second local word line W12 of the first word line W1. Therefore, the first partial word line W11 and the second partial word line W12 of the first word line W1 cross the plurality of partial bit lines B11 to B14 of the first bit line B1 at right angles, and the memory cell block 2 can be defined at these crossings. Point in each of them. Similarly, the second partial word line W12 and the third partial word line W13 of the first word line W1 may be the same as the multiple partial word lines of the second bit line B2. The part lines B21 to B24 cross at right angles, and the third and fourth local word lines W13 and W14 of the first word line W1 may cross the plurality of local bit lines B31 to B34 of the third bit line B3 at right angles. The crossing points of the first to third bit lines B1 to B3 and the second to fourth word lines W2 to W4 may be the same as the crossing points between the first to third bit lines B1 to B3 and the first word line W1. Mode structure.

[0056] In the memory cell block 2, one local bit line B11 may cross the first local word line W11 and the second local word line W12. From a geometric point of view, as shown in FIG. 2B, two memory cells C1 and C2 can be defined on both sides of the local bit line B11. But from the circuit point of view, the two memory cells C1 and C2 can be regarded as one memory cell due to the same operation at the same time. As a result, the number of memory cells may be the number of bit lines multiplied by the number of word lines.

[0057] As an example, when K word lines cross M bit lines and when each of the M bit lines is composed of N layers,

The number of memory cells can be ΝXKXMo. In the case that the decoder is used to access the memory cells, the number of decoders required to access K word lines can be K, and the number of decoders used to access the M composed of N layers respectively. The decoder required for each bit line can be NXM. Thus, the total number of decoders is K+(ΝΧΜ)_ΟThe following table 1 is used to compare the structural characteristics of the resistance random access memory 1 and the stacked resistance random access memory 10 described with reference to FIGS. 1A and 1B. Both memories 1 and 10 are stacked in N layers.

[0058] Table 1

[0059]

<td></td><td>Resistance Random Access Memory 10</td><td>Resistive random access memory 1</td>

<td>Number of storage units</td><td>ΝΧΚΧΜ</td><td>ΝΧΚΧΜ</td>

<td>Number of word lines</td><td>ΝΧΚ</td><td>Κ</td>

<td>Number of bit lines</td><td>ΝΧΜ</td><td>ΝΧΜ</td>

<td>Number of decoders</td><td>(ΝΧΚ) + (ΝΧΜ)</td><td>Κ+ (ΝΧΜ)</td>

<td>Number of process steps</td><td>NXS</td><td>S</td>

[0060] Referring to Table 1, although the resistance random access memory is implemented by stacking the same layers to define the same number of memory cell blocks, the number of word lines of the resistance random access memory 1 is compared with that of the resistance random access memory 10. It can be understood that the number of decoders of the resistance random access memory 1 is significantly reduced compared to the resistance random access memory 10. These differences will become larger as the number of stacks N increases. Moreover, as will be described later with reference to 8A to 8G, it can also be understood that the number of process steps required to define the memory cell blocks three-dimensionally arranged in the resistance random access memory according to the exemplary embodiment of the present invention is reduced to the present. Technical 1/Νο

[0061] As shown in FIG. 2B, the memory cells C1 and C2 may include resistance elements that store information using variable characteristics of resistance. Alternatively, as shown in FIG. 2C, the memory cells C1 and C2 may further include a selection unit capable of selecting a resistance element.

[0062] The resistance random access memory 1 can be implemented in the following various structures and manners.

[0063] First device example

[0064] FIG. 3A is a perspective view showing a resistance random access memory according to the first exemplary embodiment of the present invention; the perspective view of FIG. 3B includes a cross-section taken along line I-1 of FIG. 3A; and a perspective view of FIG. 3C The storage unit block is shown.

[0065] Referring to FIG. 3A, the resistance random access memory 100 may include a plurality of bit line stacks 150 each having a plurality of bit lines located on a substrate 110, a plurality of bit line stacks 150 intersecting the plurality of bit line stacks 150 at substantially right angles. A word line 172, a resistive storage film 160 provided between the plurality of bit line stacks 150 and the plurality of word lines 172.

[0066] In another example, the resistance random access memory 100 may include: a plurality of word line stacks 150, each having a plurality of word lines; and a plurality of bit lines 172, and the plurality of word line stacks 150 at substantially right angles cross. In this example, a resistive storage film 160 is provided between the plurality of word line stacks 150 and the plurality of bit lines 172 crossing each other. The former example will be described in this article, and the latter example can be used in the following description.

[0067] Each bit line stack 150 may be formed by vertically stacking a plurality of conductive layers 132 and 134 extending in the horizontal direction. For example, each bit line stack 150 may be formed by stacking a plurality of conductive layers 132 and 134 in the Z-axis direction.

to make. The plurality of conductive layers 132 and 134 may extend in the X direction. The plurality of bit line stacks 150 correspond to the plurality of bit lines B1 to B3 of FIG. 2A, and the plurality of conductive layers 132 and 134 correspond to the plurality of local bit lines B11 to B34 of FIG. 2A. The bit line stack 150 may include a first insulating layer 122 and a second insulating layer 124. The first insulating layer 122 electrically insulates the first conductive layer 132 from the substrate 110, and the second insulating layer 124 electrically insulates the first conductive layer 132 from the second insulating layer. The conductive layer 134 is electrically insulated. The bit line stack 150 may further include a hard mask pattern 140 stacked on the second conductive layer 134, that is, the topmost layer of the bit line stack 150. Herein, for convenience, the conductive layers 132 and 134 may be used together with the term "local bit line". [0068] Each word line 172 may include a plurality of conductive layers 172a and conductive layers 172b. The conductive layer 172a may extend in a vertical direction from the side of the bit line stack 150. The conductive layer 172b may extend in a horizontal direction across the bit line stack 150. The plurality of conductive layers 172a may be electrically connected to each other through the conductive layer 172b. For example, each word line 172 may have a comb structure in which a plurality of conductive layers 172a extending in the Z-axis direction to fill the space between the bit line stacks 150 are electrically connected to each other through one conductive layer 172b extending in the Y-axis direction.

[0069] The plurality of word lines 172 correspond to the plurality of word lines W1 to W3 of FIG. 2A, and the plurality of conductive layers 172a extending in the Z-axis direction correspond to the plurality of local word lines W11 to W44 of FIG. 2A, along the Y-axis direction. The extended plurality of conductive layers 172b correspond to the plurality of connecting lines W10 to W40 in FIG. 2A_oHere, the conductive layer 172a may be used with the term "local bit line" for convenience; the conductive layer 172b may be used with the term "connecting line".

[0070] The resistive memory film 160 may be provided to cover the substrate 110 including the bit line stack 150. For example, the resistive memory film 160 may be a continuous plate along the extension direction (X-axis direction) of the bit line stack 150, along the local word A continuous plate along the extending direction (Z-axis direction) of the wire 172a and a continuous plate along the extending direction (Y-axis direction) of the connecting wire 172b.

3A and 3B, the bit line stack 150 may be oriented in the Y-axis direction to form an XZ plane, and the word line 172 may be oriented in the X-axis direction to form a YZ plane. The bit line stack 150 and the word line 172 may cross each other such that the plurality of partial word lines 172 a are oriented in the Y-axis direction to fill the space between the bit line stack 150. Therefore, the intersections between the plurality of local bit lines 132 and 134 and the plurality of local word lines 172a are three-dimensionally arranged so that the memory cell block 102 is defined in each intersection. In the memory cell block 102, the resistive storage film 160 may serve as an information storage layer, which is a resistive element for storing information according to the variable characteristics of resistance, and the local word line 172a and the local bit lines 132 and 134 may serve as electrodes.

[0072] Referring to 3C, as described with reference to FIG. 2B, since the local word lines 172 are arranged on the left and right sides of any one of the local bit lines 134 according to the geometric perspective view, the two memory cells C1 and C2 can be defined in one In the storage unit block 102. However, from the circuit point of view, the two memory cells C1 and C2 can be considered as one memory cell due to the same operation at the same time.

[0073] By applying a read voltage to the selected word line and the selected bit line, a read operation can be performed on the memory cell formed at the intersection between the selected word line and the selected bit line. In the read operation, by floating the unselected word line, it is possible to prevent current from flowing between the selected bit line and the unselected word line. A programming operation is performed on the memory cell formed at the intersection between the word line and the bit line by grounding all the word lines and applying a programming voltage to the selected bit line. When all word lines are grounded and programming voltage is applied to all bit lines, the so-called blanket program can be formed at the intersections between all word lines and all bit lines. Implemented on the storage unit. This can be effectively used to implement block unit erasing operations.

[0074] Second device example

[0075] FIG. 4A is a perspective view showing a resistance random access memory according to a second exemplary embodiment of the present invention; the perspective view of FIG. 4B includes a cross-section taken along line II-II of FIG. 4A. The resistance random access memory of the second exemplary embodiment of the present invention is equivalent to and similar to the resistance random access memory of the first exemplary embodiment of the present invention described with reference to FIGS. 3A to 3C.

Take the memory. Thus, the same components will be briefly described or omitted and different components will be described in detail.

4A and 4B, the resistance random access memory 200 is similar to the resistance random access memory 100 according to the first exemplary embodiment of the present invention described with reference to FIGS. 3A to 3C. That is, the resistance random access memory 200 may have a 3D cross point structure, in which a plurality of bit line stacks 150 each having a plurality of local bit lines 132 and 134 and a plurality of comb word lines 172 each having a plurality of local word lines 172a are on the substrate 110 Cross at roughly right angles. A memory cell block 103 similar to that shown in FIG. 3C may be defined in each intersection.

[0077] The resistive storage film 162 may be provided between the bit line stack 150 and the word line 172. The resistance storage film 162 may be provided in a strip shape. For example, the resistive memory film 162 may be discontinuous along the extension direction (X-axis direction) of the bit line stack 150, and may be continuous along the extension direction (Z-axis direction) of the local word line 172a, and along the connecting line The extension direction (Y-axis direction) of 172b may be continuous. That is, each resistive storage film 162 may be a strip-like structure clearly disposed under each word line 172.

[0078] According to an exemplary embodiment of the present invention, when the memory cells in the selected word line 172 are programmed and/or erased, the memory cells in the remaining unselected word lines 172 can be prevented from being unintentionally programmed. And/or erase. Therefore, the erroneous operation of the resistance random access memory 200 can be reduced.

[0079] Third device example

[0080] FIG. 5A is a perspective view showing a resistance random access memory according to a third exemplary embodiment of the present invention; the perspective view of FIG. 5B includes a cross-section taken along the line 111-111 of FIG. 5A; and the perspective view of FIG. 5C The storage unit block is shown. The resistance random access memory of the third exemplary embodiment of the present invention is equivalent to and similar to the resistance random access memory of the first exemplary embodiment of the present invention described with reference to FIGS. 3A to 3C. Thus, the same components will be briefly described or omitted and different components will be described in detail.

5A, the resistance random access memory 300 is similar to the resistance random access memory 100 according to the first exemplary embodiment of the present invention described with reference to FIGS. 3A to 3C. That is, the resistance random access memory 300 may have A 3D cross-point structure in which a plurality of bit line stacks 150 each having a plurality of local bit lines 132 and 134 and a plurality of comb word lines 172 each having a plurality of local word lines 172a are arranged at substantially right angles on the substrate 110 cross.

[0082] The resistive storage film 160 may be provided between the bit line stack 150 and the word line 172. The resistance storage film 160 may be formed as a continuous plate. The switching film 190 may be further provided between the bit line stack 150 and the word line 172. For example, the switching film 190 may be provided between the resistive storage film 160 and the word line 172 in the form of a continuous plate.

[0083] The switching film 190 may be used as a switching element or a selection element for switching or selecting the resistance storage film 160. The switching film 190 has current-voltage characteristics as shown in FIG. 14A and may be an element capable of causing current to flow in one direction. For example, the switching film 190 may be a diode or a varistor (variable resistor), which can make a current flow when the applied voltage is greater than a specific value, but cannot make the current flow when the applied voltage is less than a specific value. As another example, the switching film 190 may be an element having current-voltage characteristics as shown in FIG. 14B. For example, the switching film 190 may be a threshold switching element that cannot make current flow when the applied voltage is within a range of a specific value, and can make current flow when the applied voltage is greater than or less than a specific value.

[0084] Alternatively, when the resistance random access memory 300 includes a plurality of word line stacks 150, a plurality of bit lines 172, and a resistance storage film 160 therebetween, the switching film 190 may be provided on the word line stack 150 and Between the resistance storage films 160.

[0085] Referring to FIGS. 5A and 5B, the plurality of word lines 172 intersect the bit line stack 150 at substantially right angles, so that the plurality of partial word lines 172a fill the space between the bit line stack 150. Therefore, the multiple local bit lines 132 and 134 and the multiple local word lines

The intersections between 172a are arranged three-dimensionally so that the memory cell block 104 is defined in each intersection. In the memory cell block 104, the local word line 172a and the local bit lines 132 and 134 may serve as electrodes, and the resistive storage film 160 may serve as an information storage layer, which is a resistive element for storing information according to the variable characteristics of resistance, and The switch film 190 can be used as a selection element for selecting a resistance element.

[0086] Referring to FIG. 5C, from a geometric point of view, two memory cells C1 and C2 may be defined in one memory cell block 104. But from the perspective of the circuit, due to the same operation at the same time, the two memory cells C1 and C2 can be considered as one memory cell.

[0087] Fourth device example

[0088] FIG. 6A is a perspective view showing a resistance random access memory according to a fourth exemplary embodiment of the present invention; the perspective view of FIG. 6B includes a cross-section taken along line IV-IV of FIG. 6A. The resistance random access memory of the fourth exemplary embodiment of the present invention is equivalent to and similar to the resistance random access memory of the first exemplary embodiment of the present invention described with reference to FIGS. 3A to 3C. Thus, the same components will be briefly described or omitted and different components will be described in detail.

6A, the resistance random access memory 400 is similar to the resistance random access memory 100 according to the first exemplary embodiment of the present invention described with reference to FIGS. 3A to 3C. That is, the resistance random access memory 400 may have A 3D cross-point structure in which a plurality of bit line stacks 150 each having a plurality of local bit lines 132 and 134 and a plurality of comb word lines 172 each having a plurality of local word lines 172a are arranged at substantially right angles on the substrate 110 cross.

[0090] The resistive storage film 162 may be provided between the bit line stack 150 and the word line 172. The resistance storage film 162 may be provided in a strip shape clearly disposed under the word line 172. The switching film 192 may be further provided between the bit line stack 150 and the word line 172. For example, the switching film 192 may be provided between the resistance storage film 162 and the word line 172 in the form of a strip.

[0091] Referring to FIGS. 6A and 6B, the plurality of word lines 172 intersect the bit line stack 150 at substantially right angles, so that the plurality of partial word lines 172a fill the space between the bit line stack 150. Therefore, the intersections between the plurality of local bit lines 132 and 134 and the plurality of local word lines 172a are arranged three-dimensionally, so that a memory cell block 105 similar to that shown in FIG. 5C is defined in each intersection.

[0092] Fifth device example

[0093] FIG. 7A is a perspective view showing a resistance random access memory according to a fifth exemplary embodiment of the present invention; the perspective view of FIG. 7B includes a cross-section taken along the line VV of FIG. 7A. The resistance random access memory of the fifth exemplary embodiment of the present invention is equivalent to and similar to the resistance random access memory of the first exemplary embodiment of the present invention described with reference to FIGS. 3A to 3C. Thus, the same components will be briefly described or omitted and different components will be described in detail.

7A, the resistance random access memory 500 is similar to the resistance random access memory 100 according to the first exemplary embodiment of the present invention described with reference to FIGS. 3A to 3C. That is, the resistance random access memory 500 may have A 3D cross-point structure in which a plurality of bit line stacks 150 each having a plurality of local bit lines 132 and 134 and a plurality of comb word lines 172 each having a plurality of local word lines 172a are arranged at substantially right angles on the substrate 110 cross.

[0095] The resistive storage film 164 may be provided between the bit line stack 150 and the word line 172. The resistive storage film 164 may include: a first layer 164a, clearly disposed under the word line 172; and a second layer 164b, covering the side of the word line 172. The first layer 164a may have a strip shape covering the bit line stack 150 under the word line 172. The second layer 164b may have a vertical plate shape covering the side of the local word line 172a and the side of the connection line 172b. That is, the resistive storage film 164 may be further provided on the side surface of the word line 172. Therefore, as shown in FIG. 7B, the resistive storage film 164 may surround the periphery of the local word line 172a. A switching film may be further provided between the resistance storage film 164 and the word line 172.

[0096] Referring to FIGS. 7A and 7B, the plurality of word lines 172 intersect the bit line stack 150 at substantially right angles, so that the plurality of local word lines 172a fill the space between the bit line stack 150. Therefore, the intersections between the plurality of local bit lines 132 and 134 and the plurality of local word lines 172a are arranged three-dimensionally, so that a memory cell block 106 similar to that shown in FIG. 3C is defined in each intersection.

[0097] First manufacturing example

[0098] FIGS. 8A to 8G are cross-sectional views showing a method of manufacturing a resistance random access memory according to the first exemplary embodiment of the present invention.

[0099] Referring to FIG. 8A, a stacked body may be formed on the substrate 110. The stacked body includes an insulating layer group 120 provided with a plurality of insulating layers 122 and 124 and a conductive layer group 130 provided with a plurality of conductive layers 132 and 134. As an example, the first insulating layer 122, the first conductive layer 132, the second insulating layer 124, and the second conductive layer 134 are sequentially formed on the substrate 110 such as a silicon wafer. Optionally, at least one insulating layer and at least one conductive layer may be selectively stacked on the second conductive layer 134. The insulating layer group 120 may be formed by depositing an insulating film. For example, the insulating layer group 120 may be deposited by silicon oxide (for example, Si.?) or silicon nitride (for example, SiN, Si₃N₄Or SiON) formed. The conductive layer group 130 may be formed by depositing or growing a conductive film such as a metal or conductive oxide layer. For example, the conductive layer group 130 may be deposited or grown YBCO (for example, YBa₂Cu₃0₇), Pt, Ir, Cu, Ag, Au or polysilicon doped with impurities.

[0100] The hard mask pattern 140 may be formed on the conductive layer group 130 to be used as a mask in an etching process (bit line etching process) for defining a bit line. For example, the hard mask pattern 140 may be provided to extend on the second conductive layer 134 in the X-axis direction. The hard mask pattern 140 may be used as a hard mask for a subsequent etching process (word line etching process) for forming a word line without being removed after the bit line etching process. The hard mask pattern 140 can be formed by depositing titanium nitride (such as TiN), silicon nitride (such as SiN, Si₃N₄Or SiON) or silicon oxide (for example, Si0₂)form.

[0101] Referring to FIG. 8B, the conductive layer group 130 and the insulating layer group 120 may be continuously patterned through a bit line etching process using the hard mask pattern 140 as a mask, resulting in the formation of a plurality of bit line stacks 150. According to this exemplary embodiment of the present invention, the bit line etching process may adopt a reactive ion etching (RIE) process.

[0102] The bit line stack 150 includes a first insulating layer 122, a first conductive layer 132, a second insulating layer 124, and a second conductive layer 134, which are sequentially stacked, and may have barriers or walls extending in the X-axis direction. The form is provided. The hard mask pattern 140 may be further provided in the bit line stack 150.

[0103] The first insulating layer 122, the first conductive layer 132, the second insulating layer 124, and the second conductive layer 134 may be self-aligned through a bit line etching process.

[0104] The patterned first conductive layer 132 and the second conductive layer 134 correspond to bit lines, that is, local bit lines B11 to B34 extending in the X-axis direction of FIG. 2A. In addition, the plurality of bit line stacks 150 correspond to the plurality of bit lines B1 to B3 forming the XZ plane in FIG. 2A. According to this exemplary embodiment of the present invention, as shown in FIG. 2A, all the bit lines B1 to B3 may be formed by a single bit line etching process.

[0105] Referring to FIG. 8C, the resistance storage film 160 may be formed by depositing a resistance storage material. The resistance storage film 160 may be formed by a deposition process suitable for depositing a thin film. For example, the resistive storage film 160 may be formed through a chemical vapor deposition process to cover the bit line stack 150 having a relatively uniform thickness.

[0106] The resistance storage material forming the resistance storage film 160 may include a material having a bistable resistance state, where the resistance may be reversibly changed with an applied voltage. For example, the resistive storage material may include giant magnetoresistance materials, high-temperature superconducting materials, metal oxides, or chalcogenides. For example, the metal oxide may include oxides of Ni-, Ti-, Zr-, Hf-, Co-, Fe-, Cu-, Al-, Nb-, V-, and Cr-, or a combination thereof.

[0107] Referring to FIG. 8D, the conductive layer 170 may be formed by depositing a conductive material on the entire substrate 110. The conductive layer 170 may be formed by depositing or growing the same or similar material as the conductive layer group 130. For example, the conductive layer 170 may be formed of YBCO, Pt, Ir, Cu, Ag, Au, or impurity-doped polysilicon. The mask pattern 180 may be formed on the conductive layer 170 as a mask in an etching process (word line etching process) for defining a word line. After the photoresist is provided on the conductive layer 170, the mask pattern 180 may then be formed by patterning the photoresist. The mask pattern 180 may be provided in the form of a plurality of lines extending in the Y-axis direction. Some of the several mask patterns 180 are partially shown in FIG. 8D for ease of description.

[0108] Referring to FIG. 8E, the conductive layer 170 may be selectively removed through a word line etching process. The plurality of word lines 172 may be formed through a word line etching process. The resistive storage film 160 may not be removed during the word line etching process. The word line etching process may adopt a reactive ion etching (RIE) process.

[0109] The word line 172 may be provided in a comb-like form to form a YZ plane. For example, the word line 172 may include a plurality of local word lines 172a and a connecting line 172bo. The plurality of local word lines 172a fill the space between the bit line stack 150 and extend in the Z-axis direction, while the connecting line 172b extends in the Y-axis direction to each other. A plurality of local word lines 172a are electrically connected.

[0110] The plurality of word lines 172 correspond to the plurality of word lines W1 to W3 in FIG. 2A. In the case of comparing one of the word lines 172 with the first word line W1 in FIG. 2A, the plurality of local word lines 172a correspond to the local word lines W11 to W14 in FIG. The first connection line W10. According to an exemplary embodiment of the present invention, a plurality of word lines 172, that is, all the word lines W1 to W3 in FIG. 2A, may be formed through a single word line etching process.

[0111] Referring to FIGS. 8F and 8G, the insulating layer 182 may be formed between the word lines 172 by depositing an insulating material. This can also be implemented as a resistive random access memory 100 including a plate-shaped resistive memory film 160 as shown in FIG. 3A. The insulating layer 182 may be deposited by silicon nitride (for example, SiN>Si₃N₄Or SiON), or, preferably by depositing silicon oxide with excellent insulating properties (for example, Si0₂)form. Some of the word line 172 and the insulating layer 182 are partially shown in FIG. 8F for ease of description.

[0112] According to an exemplary embodiment of the present invention, all bit lines (B1 to B3 of FIG. 2A) may be formed by the single bit line etching process described with reference to FIG. 8B, and all word lines (W1 of FIG. 2A) To W3) can be formed by the single word line etching process described with reference to FIG. 8E. Therefore, although the number of stacked bit lines is becoming more and more, compared with the conventional technology, the number of process steps can be reduced by a single bit line etching process.

[0113] For example, assuming that the number of process steps required for forming the memory layer is set to S and the number of stacks is set to N, then it is used to form a resistance random access according to the conventional technique shown in FIG. 1B. The number of process steps required for the memory 10 is SXN, but the number of process steps for forming the resistance random access memory 100 according to this exemplary embodiment of the present invention is S. That is, according to the manufacturing method of this exemplary embodiment of the present invention, the stacked storage layers can be formed with the number of process steps required to form one storage layer.

[0114] Second manufacturing example

[0115] FIGS. 9A to 9D are cross-sectional views showing a method of manufacturing a resistance random access memory according to a second exemplary embodiment of the present invention. The manufacturing method of the second exemplary embodiment of the present invention is the same as and similar to the manufacturing method of the first exemplary embodiment of the present invention described with reference to FIGS. 8A to 8G. Therefore, the same process will be briefly described or omitted and different processes will be described in detail.

[0116] Referring to FIG. 9A, a plurality of bit line stacks 150, a resistive storage film 160, and a plurality of word lines 172 are formed in the same or similar process as described with reference to FIGS. 8A to 8E. That is, a plurality of bit line stacks 150 are formed on the substrate 110, a resistance storage film 160 is formed to cover the plurality of bit line stacks 150, and a plurality of word lines 172 are formed on the resistance storage film 160.

on.

[0117] In the same or similar manner as described with reference to FIGS. 8A to 8B, after sequentially depositing the plurality of conductive layers 132 and 134, the plurality of insulating layers 122 and 124, and the hard mask pattern 140, the plurality of bit lines The stack 150 may be formed by a bit line etching process. The bit line stack 150 may be formed to extend in the X-axis direction.

[0118] The resistance storage film 160 may be formed in the same or similar manner as described with reference to FIG. 8D, for example, by depositing a material in which the resistance is reversibly changed depending on the applied voltage. The resistive storage film 160 may be formed in the form of a plate covering the bit line stack 150 conformally.

[0119] In the same or similar manner as described with reference to FIGS. 8D to 8E, after the metal or conductive material is deposited on the resistive storage film 160, the plurality of word lines 172 may pattern the deposited material through a word line etching process And formed. The word lines 172 may be provided in a comb shape, so that a plurality of local word lines 172a extending in the Z-axis direction are electrically connected to each other by a connection line 172b extending in the Y-axis direction.

[0120] Referring to FIG. 9B, a portion of the resistance storage film 160 exposed between the word lines 172 may be further removed. This removal process may be a dry etching process, for example, a reactive ion etching process. This allows the plate-shaped resistive storage film 160 to be implemented as a strip-shaped resistive storage film 162 explicitly disposed under the word line 172. During the selective etching process for forming the strip-shaped resistive storage film 162, the bit line stack 150 may be exposed, but the second conductive layer 134 may be protected by the hard mask pattern 140.

[0121] Referring to FIGS. 9C and 9D, the insulating layer 182 may be formed in the same or similar process as described with reference to FIGS. 8F and 8G, for example, by depositing an insulating material between the word lines 172. As a result, the resistance random access memory 200 including the strip-shaped resistance storage film 162 shown in FIG. 4A can be realized.

[0122] Third Manufacturing Example

[0123] FIGS. 10A to 10D are cross-sectional views showing a method of manufacturing a resistance random access memory according to a third exemplary embodiment of the present invention. The manufacturing method of the third exemplary embodiment of the present invention is the same and similar to the first exemplary embodiment of the present invention described with reference to FIGS. 8A to 8G. Therefore, the same process will be briefly described or omitted and different processes will be described in detail.

[0124] Referring to FIG. 10A, a plurality of bit line stacks 150 and a resistive storage film 160 are formed in the same or similar process as described with reference to FIGS. 8A to 8E. That is, a plurality of bit line stacks 150 are formed on the substrate 110, and the resistive storage film 160 is formed to cover the plurality of bit line stacks 150. In addition, the switching film 190 may be formed to cover the resistance storage film 160. The resistance storage film 160 is provided in the form of a plate in the same or similar manner as described with reference to FIG. 8C.

[0125] The switching film 190 may serve as an element for switching or selecting the resistance storage film 160. The switching film 190 may be formed of a material capable of causing current to flow in one direction. For example, as shown in FIG. 14A, when the applied voltage is greater than a specific value, the current can flow and when the applied voltage is less than the specific value, the current cannot flow. material. That is, a switching thin film 190 may be able to utilize a material be a metal oxide varistor, e.g., ZnO, SrTiO3, or BaTi () 3, is formed. As another example, the switching film 190 may be formed of a material that cannot make current flow when the applied voltage is within a specific value range, but can make current flow when the applied voltage is greater than or less than a specific value (as shown in FIG. 14B). The switching film 190 may be formed of a tunnel insulating material or chalcogenide as a threshold switching element. The switching film 190 may be provided in the form of a plate to uniformly cover the resistance storage film 160.

[0126] Referring to FIG. 10B, a plurality of word lines 172 may be formed on the switch film 190 in the same or similar process as described with reference to FIGS. 8D and 8E in the same or similar manner as described with reference to FIGS. 8D and 8E. After the metal or conductive material is deposited on the switching film 190, the plurality of word lines 172 can be patterned by using a word line etching process to pattern the deposited material.

Material and formed. The word line 172 may be provided in a comb-like form such that a plurality of partial word lines 172a extending in the Z-axis direction are electrically connected to each other by one connecting line 172b extending in the Y-axis direction.

[0127] Referring to FIGS. 10C and 10D, the insulating layer 182 may be formed in the same or similar process as described with reference to FIGS. 8F and 8G, for example, by depositing an insulating material between the word lines 172. As a result, the resistance random access memory 300 including the plate-shaped resistance storage film 160 and the switching film 190 shown in FIG. 5A can be realized.

[0128] Fourth Manufacturing Example

[0129] FIGS. 11A to 11D are cross-sectional views showing a method of manufacturing a resistance random access memory according to a fourth exemplary embodiment of the present invention. The manufacturing method of the fourth exemplary embodiment of the present invention is the same and similar to the first exemplary embodiment of the present invention described with reference to FIGS. 8A to 8G or the third exemplary embodiment of the present invention described with reference to FIGS. 10A to U 10D example. Therefore, the same process will be briefly described or omitted and different processes will be described in detail.

[0130] Referring to FIG. 11A, the plurality of bit line stacks 150 and the plate-shaped resistance storage film 160 may be formed in the same or similar process as described with reference to FIGS. 8A to 8C, and the plate-shaped switching film 190 may be formed to cover the resistors. Storage film 160. In addition, a plurality of word lines 172 may be formed on the switching film 190 ±o in the same or similar manner as described with reference to FIGS. 8D and 8E.

[0131] Referring to FIG. 11B, a portion of the plate-shaped switch film 190 exposed between the word lines 172 may be selectively removed, thereby forming a strip-shaped switch film 192. Simultaneously or successively, portions of the plate-shaped resistance storage film 160 exposed between the word lines 172 may be selectively removed, thereby forming a strip-shaped resistance storage film 162. This allows the plate-shaped switching film 190 and the plate-shaped resistance storage film 160 to be implemented as the strip-shaped switching film 192 and the strip-shaped resistance storage film 162 that are clearly disposed below the word line 172. During the selective etching process for forming the strip-shaped resistive storage film 162, the bit line stack 150 may be exposed, but the second conductive layer 134 may be protected by the hard mask pattern 140.

[0132] As another example, any one of the plate-shaped switch film 190 and the plate-shaped resistance storage film 160 may be implemented in a strip shape. For example, a portion of the plate-shaped switch film 190 exposed between the word lines 172 may be selectively removed, thereby forming a strip-shaped switch film 192. As a result, the plate-shaped resistance storage film 160 and the strip-shaped switching film 192 defined between the word lines 172 can be realized.

[0133] Referring to FIGS. 11C and 11D, the insulating layer 182 may be formed in the same or similar process as described with reference to FIGS. 8F and 8G, for example, by depositing an insulating material between the word lines 172. As a result, the resistance random access memory 400 including the strip switch film 192 and the strip resistance storage film 162 shown in FIG. 6A can be realized.

[0134] Fifth manufacturing example

[0135] FIGS. 12A to 12G are cross-sectional views showing a method of manufacturing a resistance random access memory according to a fifth exemplary embodiment of the present invention. The manufacturing method of the fifth exemplary embodiment of the present invention is the same and similar to the first exemplary embodiment of the present invention described with reference to FIGS. 8A to 8G. Therefore, the same process will be briefly described or omitted and different processes will be described in detail.

[0136] Referring to FIG. 12A, the insulating layer group 120 provided with a plurality of insulating layers 122 and 124 and the conductive layer group 130 provided with a plurality of conductive layers 132 and 134 are formed by the same or similar process as described with reference to FIG. 8A On the substrate 110. The plurality of insulating layers 122 and 124 and the plurality of conductive layers 132 and 134 may be selectively stacked. The hard mask pattern 140 may be formed on the conductive layer group 130. For example, the hard mask pattern 140 may extend in the X-axis direction.

[0137] Referring to FIG. 12B, the conductive layer group 130 and the insulating layer group 120 may be continuously patterned in the same or similar process as described with reference to FIG. 8B, for example, by using the hard mask pattern 140 as a mask. The line etching process (reactive ion etching process) is continuously patterned. As a result, a plurality of bit line stacks 150 can be blocked by extending along the X-axis direction.

Or wall form is provided. The first insulating layer 122, the first conductive layer 132, the second insulating layer 124, and the second conductive layer 134 may be self-aligned through a bit line etching process.

[0138] Referring to FIG. 12C, an insulating material layer 180 may be formed on the entire substrate 110, and a mask pattern 184 may be formed on the insulating material layer 180. The insulating material layer 180 may be formed by depositing silicon oxide (e.g., Si.?) )form. After the photoresist is provided on the insulating material layer 180, a mask pattern 184 may be formed by patterning the photoresist. The mask pattern 184 may be provided in the form of a plurality of lines extending in the Y-axis direction perpendicular to the hard mask pattern 140.

[0139] Referring to FIG. 12D, the damascene pattern 115 may be formed through an etching process (trench etching process) using the mask pattern 184 as a mask. The plurality of strip-shaped insulating layers 182 and the plurality of trenches 174 may be formed by selectively removing the insulating material layer 180 using a trench etching process. The insulating layer 182 covers a part of the bit line stack 150, and a trench 174 is provided between the insulating layers 182 to expose the bit line stack 150. The trench 174 provides an area in which a word line is formed. The bit line stack 150 is protected by the hard mask pattern 140 during the trench etching process. The trench etching process may be a dry etching process, for example, a reactive ion etching process.

[0140] Referring to FIG. 12E, a resistance storage film 164 may be formed in the trench 174. For example, the resistive storage film 164 may be formed by depositing a giant magnetoresistive material, a high-temperature superconducting material, a transition metal oxide, or a chalcogenide in the trench 174. According to this exemplary embodiment of the present invention, the resistive memory film 164 may be divided into a first layer 164a and a second layer 164b. The first layer 164a is provided in the form of a strip to cover the bit line stack 150, and the second layer 164b is a vertical plate. The form of is provided at the side of the insulating layer 182.

[0141] Referring to FIGS. 12F and 12G, the word line 172 may be formed in the trench 174. The word line 172 may be provided in a comb shape extending in the Y-axis direction. For example, the trench 174 may be filled by depositing a conductive material (for example, metal or impurity-doped polysilicon) on the substrate 110. Alternatively, the conductive material deposited on the insulating layer 182 may be removed using chemical mechanical polishing (CMP). As another example, the selection element film may be further formed in the trench 174 before forming the word line 172 and after forming the resistive storage film 164. Through the above-described damascene process, the resistance random access memory 500 shown in FIG. 7A can be realized.

[0142] Sixth Manufacturing Example

[0143] FIGS. 13A to 13G are cross-sectional views showing a method of manufacturing a resistance random access memory according to a sixth exemplary embodiment of the present invention. The manufacturing method of the sixth exemplary embodiment of the present invention is the same and similar to the first exemplary embodiment of the present invention described with reference to FIGS. 8A to 8G. Therefore, the same process will be briefly described or omitted and different processes will be described in detail.

[0144] Referring to FIG. 13A, the insulating layer group 120 provided with a plurality of insulating layers 122 and 124 and the conductive layer group 130 provided with a plurality of conductive layers 132 and 134 may be performed in the same or similar process as described with reference to FIG. 8A Formed on the substrate. The plurality of insulating layers 122 and 124 and the plurality of conductive layers 132 and 134 may be selectively stacked. The hard mask pattern 140 extending in the X-axis direction may be formed on the conductive layer group 130.

[0145] Referring to FIG. 13B, the conductive layer group 130 and the insulating layer group 120 may be continuously patterned in the same or similar process as described with reference to FIG. 8B, for example, by using the hard mask pattern 140 as a mask. The line etching process (reactive ion etching process) is patterned. The plurality of bit line stacks 150 may be provided in the form of barriers or walls extending in the X-axis direction. The first insulating layer 122, the first conductive layer 132, the second insulating layer 124, and the second conductive layer 134 may be self-aligned through a bit line etching process.

[0146] Referring to FIG. 13C, the resistive memory film 160 may be formed in the same or similar process as described with reference to FIG. 8C, for example, by depositing a resistive memory material on the substrate 110 to cover the bit line stack 150. Resistance memory thin

The film 160 may cover the bit line stack 150 as uniformly as possible through a chemical vapor deposition process. Alternatively, the switching film may be further formed on the resistance storage film 160.

[0147] Referring to FIG. 13D, an insulating material layer 180 may be formed on the substrate 110, and a mask pattern 184 may be formed on the insulating material layer 180. The insulating material layer 180 may be formed by depositing silicon oxide (for example, Si.?) . After the photoresist is provided on the insulating material layer 180, a mask pattern 184 is then formed by patterning the photoresist. The mask pattern 184 may be provided in the form of a plurality of lines extending in the Y-axis direction perpendicular to the hard mask pattern 140.

[0148] Referring to FIG. 13E, the damascene pattern 115 may be formed through an etching process (trench etching process) using the mask pattern 184 as a mask. The plurality of strip-shaped insulating layers 182 and the plurality of trenches 174 may be formed by selectively removing the insulating material layer 180 using a trench etching process. The insulating layer 182 covers a part of the bit line stack 150, and a trench 174 is provided between the insulating layers 182 to expose the bit line stack 150.

[0149] Referring to FIGS. 13F and 13G, the word line 172 may be formed in the trench 174. The word line 172 may be provided in a comb shape extending in the Y-axis direction. For example, the trench 174 may be filled by depositing a conductive material (for example, metal or impurity-doped polysilicon) on the substrate 110. Alternatively, the conductive material deposited on the insulating layer 182 may be removed using chemical mechanical polishing (CMP). Through the metal damascene process described above, the resistance random access memory 100 shown in FIG. 3A can be realized.

[0150] Applicable examples

[0151] FIG. 15A is a block diagram showing a memory card including a resistance random access memory according to an exemplary embodiment of the present invention.

[0152] Referring to FIG. 15A, the resistance random access memory 1210 according to various exemplary embodiments of the present invention may be applied to the memory card 1200. For example, the memory card 1200 includes a memory controller 1220 for controlling data exchange between the host and the resistance random access memory 1210 as a whole. The SRAM 1221 is used as an operating memory of the central processing unit 1222. The host interface 1223 has a data exchange protocol of a host connected to the memory card 1200. The error correction code 1224 detects and corrects errors in the data read from the resistance random access memory 1210. The memory interface 1225 is connected to the resistance random access memory 1210. The central processing unit 1222 generally performs a control operation for exchanging data of the storage controller 1220.

[0153] FIG. 15B is a block diagram showing an information processing system suitable for a resistance random access memory according to an exemplary embodiment of the present invention.

[0154] Referring to FIG. 15B, the information processing system 1300 may include a storage system 1310 provided with a resistance random access memory according to an exemplary embodiment of the present invention. The information processing system 1300 includes a mobile device or a computer. For example, the information processing system 1300 further includes a modem 1320, a central processing unit 1330, a RAM 1340, and a user interface 1350, which are electrically connected to the storage system 1310 through the system bus 1360. The storage system 1310 can store data processed by the central processing unit 1300 or external input The data. The information processing system 1300 may be provided as a solid state drive (SSD), a camera image sensor, and other application chipsets. For example, the storage system 1310 may be configured as a solid-state hard disk. At this time, the information processing system 1300 can stably and reliably store a large amount of data in the storage system 1310.

[0155] According to the present invention, the bit lines can be vertically stacked by a single etching process, and the comb-shaped word lines crossing the bit lines at right angles can be formed by a single etching process. As a result, the 3D cross-point structure can be formed by the number of process steps required to form one memory layer, thereby realizing a high-density multi-layer memory array using simplified processes. In addition, since the comb-shaped word lines are formed, the number of word lines can be reduced, thereby reducing the number of decoders connected to the word lines. Therefore, the process can be simplified and the device size can be reduced.

[0156] The present invention can be beneficially used not only in the semiconductor industry for manufacturing semiconductor memory, but also

Used in the manufacturing industry of electronic products using the semiconductor memory.

[0157] Although the general inventive concept of the present invention has been described in conjunction with the embodiments of the present invention shown in the drawings, the present invention is not limited thereto. It is obvious to those skilled in the art that various substitutions, modifications and changes can be made to it without departing from the scope and spirit of the present invention.

[0158] This application claims the priority of Korean Patent Application 10-2009-0002756 filed on January 13, 2009, the contents of which are disclosed herein by reference.