MOS device with schottky barrier controlling layer

With Schottky key-course barrier MOS device

[0001] Overlapping quotation of related equipment

[0002] The application of; unsettled the patented claim No.11/900,616 and business on September 11, 2007 submitted is a part of POWER MOS DEVICE continue apply, which is; the patented claim No.l on February 11, 2005 submitted 1/056,346 (present's emitting patent is 7,285,822), server is a continuation application of POWER MOS DEVICE, stemming from the goals, a wherein the two literature.

technical field

[0003] The invention relates to a metal oxide semiconductor device and manufacturing method.

background technology

[0004] The power MOS device common and an electronic circuit. Is fixed by using the possibly, anticipation different the component. A display application of the DC-DC converter, comprising (is further low-end called FET) and synchronous rectification comprising a power MOS device, with the power MOS device used control switch (is further high-end called FET). Low-end FET claim usual a first resistor, so that the number of obtaining good power switch power. High-end FET claim usual small grid capacitor, a straight split-second-selection and good performance.

[0005] The conducting resistor (Rdsrai) value of transistor is usually proportional with the channel (L); the active units in length unit area (W) is a reverse ratio. Selecting when the Rdsra value, claim consider the balance between performance and fault voltages. In turn to reduce the Rdsrai value, capable of reducing channel of by using shallow source and main body, and capable of reducing unit is added the length unit area units. The, and a plurality of the puncture phenomenon, the length L is usually limited. Wherein length unit area units further process for manufacturing and lower configured to the supply unit area and main body area good contact is limited. Along with the enhanced of the length and density unit, a gate capacitor is added. In turn to reduce the consumption of switch, compared with low device capacitor is preferably. The multiple applications (such as, synchronous rectification), a memory charging and main body diode forward voltage drop is in that the power consumption. The factors with a limited and performance of DMOS power device.

[0006] Are anticipated: The several the first resistor and a capacitor grid DMOS power device which is lower than the level of can reach, a reliability and power dissipating of power supply switch can improve. Parts is further provided possibly: Develops the practical technology, the process of the improved reliably the DMOS power device.

invention content

[0007] Therefore, the invention claims a semiconductor device and manufacturing method thereof, a a reliability and power dissipating improved power switch.

[0008] On one surface, the invention claims a formed on the semiconductor substrate semiconductor device, comprising: drain electrode; The covering the drain of epitaxial layer,And a source area, comprising: A main body, wherein the main body is mounted on the epitaxial layer, and main body is of a surface; Supply, a power supply, the body, and from the main body is of a surface extend to the main body; The gate groove; the grid groove is extended to the epitaxial layer,A gate, wherein the gate cover is arranged in the gate groove; With the source region contact to the groove; and source region contact the groove through the source and main body extends to the drain electrode; And a supply contact area electrode, and source region contact electrode is mounted to the source region contact of the groove; and source region contact electrode and drain electrode are formed Schottky diode; And Schottky barrier key-course, wherein the barrier Schottky key-course is mounted on to the source region contact the groove which is arranged in the epitaxial layer.

[0009] On the other side, method for the invention claims a method for manufacturing semiconductor device, comprising: The gate groove of the epitaxial layer of the semiconductor substrate; The gate groove deposition gate material; The main body; Forming source,The source region contact to the groove; and source region contact the groove through the source and main body extends to the drain electrode; Deposition Schottky barrier; key-courseAnd a source area contact of the groove at the electrode.

Brief description for drawings

[0010] Embodiments and a lower the digital attached to various embodiments of claimed invention is.

[0011] Image 1A-1F of multiple pair of dissipation metal oxide semiconductor components' embodiments.

[0012] Digital 2) is in a voltage drop () buck converter circuit demonstration's schematic drawing.

[0013] Digital is 3 to show for constructing DMOS device manufacturing process the current position of embodiment.

[0014] Image 4A-4U of manufacture MOS device component cross - section view of displaying manufacturing process specifically.

[0015] Image 5A-6B of manufacturing a joint which is connected to the second embodiment.

[0016] Digital 7-10 of manufacturing process of second the improved; the improvements used for certain embodiments to further the device performance.

detailed description of illustrated embodiments

[0017] The invention can realize with the method comprises for realizing method, device and system, the combination and function adding the medium (such as, function adding storage medium) or a computer network (, and program directive is transmitted optical link or information link transmission). The double-folded indicating, and realize, any other surface according or the invention can use, can be called technology. Is described groove is configured end of the duty module via (such as a memory or) associated comprises a common module (which is assigned time end of a temporary configuration duty) further comprises a personal module (that is filled with task). Usually, wherein the range invention, the process step's device according publicizes capable of changing.

[0018] The invention the specific description of one or more embodiment distributed on the invention principle's attached with digitally given the following a. Although and such embodiment to the invention; the invention is interposed between adjacent one embodiment. Range of this invention is only defined by claim, and invention cover or more of substitute mode, to improve and equate internet. Is a pair of wire details to provide the integrated battery of this invention the following description. The details are in demonstration's target for powering, and invention can realize 1-8, has further no need the fastening bolts and multiple or completely. Is a transparent target, a involving the diaphragm technical field male knowledge's the technical material zero-halogen type detailed description, to prevent the invention unwanted the outer surface of confusion.

[0019] The metal oxide semiconductor device and manufacturing. Stemming from demonstration's target, wherein the edges discussed the main body in detail the N channel device, comprising an N-TYPE material to the source and drain electrode and N-TYPE made of a. Are is suitable the common process and structure is a P-TYPE channel device.

[0020] Image 1A-1F of multiple pair of dissipation metal oxide semiconductor components' embodiments. Image IA is DMOS device the cross - section of view embodiment. The display, a device 100 and a drain electrode, which is in N+ semiconductor substrate 103 backs. The drain electrode of extending to the substrate 103, the lower layer of N_ semiconductor 104. The gate groove of the epitaxial layer 104 (etching such as 111, 113 and 115). The gate oxide layer (121) and grid groove. The gate 131, 133 and 135 are located in the gate groove 111, 113 and 115; and a oxide layer and epitaxial layer insulating. The grid is made of such as polycrystalline silicon (polytetrafluoro) conductive material; and an oxide layer is made of such as oxidization thermal insulating material. , A gate 111 groove is arranged on the end part, specifically the end part of the further comprises a gate and metal grid lead (gaterarnier 131). Stemming from the volume, 113 and 115 compares the active gate groove; the grid lead groove 111) is wider, and is deeper. Further, the gate lead groove (111) and adjacent active groove (in the shell is groove (113) is a limiting 113 and 115 between every is greater than the active gate groove.

[0021] Source area 150a_150d inserted in the main body part are 140a_140d. The source area extends from the main body upper surface of the main body of automatic. Although body area of the gate each poured into, and source region poured into the active gate groove of merely, which are not pour into grid lead groove base. The pores in the embodiment, such as 133 with a voltage the gate to go of the surface, the gate ceiling surface substantially electrode is extended on the inserting active body top surface. Such for ensuring with the crossed of gate region and source, wherein allows the source region ratio with the hollow tube gates element source area is), and such configuration is efficiency and performance of component. The gate polysilicon ceiling surface; the source of the main body is the quantity of portion is connected in aggregate of different embodiment to change. A certain embodiments, element gate/of the main body area upper surface without from the source region; and converter main body area upper surface is a hollow area supply.

[0022] During operation, the drain electrode of the main body area played the role of a diode, a called body diode. The medium material layer (160) are arranged on the gates, wherein in turn to gate region and source of body and insulating. The dielectric materials and formed with the insulating of the main body part and source region is connected with the gates, such as 160a-160c. Pneumoelectric layer is a heat oxidization, low-temperature oxide and boron phosphorus quartz glass.

[0023] Magnetism contact groove 112a_112b formed between the source the active gate with each area and main body area. The grooves are called the source region to the contact surface, wherein the groove of with the source region (is formed by source area and main body area). For example, and 112a groove is extended by source and main body, formed with the groove source area and 150a_150b body area 140a-140b. On the top, forming, a gate lead 131 the groove 117 not arranged on arranged on the source region; therefore, the groove 117) is provided with the source region contact the groove. The grooves are 117 called gate contact groove or a gate guide groove, wherein connected to the metal layer 172a surface of the gate of the groove. Grooves between 111 and 113 and 115; the third dimension (is not shown), slot is the active gate the grid wave is 133 and 135. Metal layer 172a and metal layer 172b wall, metal layer 172b through the groove 112a-112b connected to the area and main body part, a driving power supply. The pores in the display, a source area contact a groove and gate contact groove is substantially the depth same.

[0024] A device with 100 to the source region contact groove 112a_112b, they are shallower than the main body. The configuration is provided with a puncturing performance, a lower resistor and lower leakage current. Additionally, wherein the active contact groove and gate contact groove is made of a process to form, thereby solution with the same depth, therefore with the active contact surface of the main body is shallower than can avoid the gate contact through groove is such as 131 gate conductive.

[0025] The pores in the display, a FET channel/main body is source of the main body/drain electrode connection with the source region gate groove wall and. In a short channel region device, and drain electrode of enhanced voltage between the source, exhausts the area of, and finally possibly and source combination. The phenomenon, a called the puncture, a degree of the channel that can reduce. A certain embodiments, to prevent penetrated, method of such as along with source area of the P-TYPE material and groove wall of 170a-170d area end of the heavy doped to form a P+ area. The P+ area avoiding exhausting area is invade the source region. , Wherein sometimes the pour into a called resistor is arranged at pour into or avoiding penetrated pour into. A certain embodiments, resistor is realized to declare arranged on the line, P+ area and a and adjacent and/or to the manufacturing aims at capability and P+ wall doped seepage to control a channel region is provided with such. A certain embodiments, the second contact groove and without aim through the contacting end is self-alignment bars, and arranged on the contact surface between the joint and connected with each centre. Enhancements in the structure of the channel to reduce, so on length unit area charging in is only lower than thereof, and ideal with an inner on the minimum charging in structure for avoiding penetrated to circuit. An improved the main body contact resistance; the resistance arranged on injecting further wherein the upper very shallow trench the short and device possibly is. The pores in the embodiment, and 112a-112b groove is shallower than body area 140a-140d, and is not of the main body area. Network first resistor and Rdsra grid capacitor is reduced.

[0026] 117 And method to form the contact of the contact surface 112a_112b and gate groove. In a source area, wherein when injecting of the side of the contact groove, and is along the base of the contact groove; therefore the electrode and N-layer drain electrode of 104 contact. The electrode and drain electrode of formed with Schottky diode (together and main body diode in). Schottky diode reduced the charging bars of the main body diode forward voltage drop and a latch, so MOSFET is the efficient. Schottky of a pulse forming the N-layer drain electrode contact and is used to form of 180a-180b to the P+ main body and N+ supply a metal rod of ohmic contact. Such as titanium and a (PT) and dysprosium) are) and wolfram (W) or any other metal suitable for a. A certain embodiments, metal layer (172) are made of aluminium or a Ti/TiN/Al laminated.

[0027] Schottky diode leakage current and Schottky barrier high relative. Along with enhanced of blocking-up, the leakage current reducing, and forward voltage drop is added. The pores in the display, a front of the source region groove 112a-112b base injecting thin adulterant layer, Schottky key-course barrier 190a-190b capable of the (is further Shannon called (Shannon) is) to form the lower electrode contact. The display, the adulterant provided with a epitaxial layer are long, and belongs to the P-TYPE. Shannon injecting with shallowly, and is lower dose; Therefore, the winding wire, and a nothing is connected with the biasing. The barrier Schottky key-course is for controlling the Schottky barrier height, wherein containing end and a better to control the leakage current, and improves Schottky diode recovering the reverse. The following description forming Schottky barrier key-course the detail.

[0028] Image IB is DMOS device the cross - section view in one embodiment. A device 102 and a Schottky barrier key-course, 190a-190b arranged at the source region and groove of the base. The display, a gate contact groove 117 depths connected with the source region of the groove 112a-112b depth is different. With the source region contact the groove is deeper than body area 140a-140d, and has the source region to the contact surface extend superstructure the main body area. Active wherein a groove is deep, therefore the active contact groove is provided with multiple region of the side manufacturing ohmic contact, and branches a better non-clamp induction the switch (UIS) ability. Moreover, wherein a gate contact groove is shallower than the active contact groove; the gate contact groove is too to penetrate possibly the gate of polysilicon during etching process; the ends are relatively shallow gate for silicon's component (such as, using such process manufacturing device, namely, the process for a gate polysilicon of the main body top surface extend) is provided.

[0029] Image IC is DMOS components In one embodiment. The display, a gate contact groove and 117 is the source region contact groove 112a-112b with different depth. Intervals; each of the source region contact the groove has not is inconsistent, wherein the depth groove is parallel to change the base of the. And the following is more detailed of; and source region contact the groove is provided with two steps crafts to form, so the first contact opening (e.g. 120a-120b,) ranges from the second contact opening (e.g. 119a-119b, mm. With the source region contact groove the outline of the licence greater ohmic contact area, and arranged on a resistor adding 170a-170d better backoff puncture, and improved element UIS ability. Shannon injecting of the second contact side wall and base body, formed with Schottky key-course barrier 190a-190b.

[0030] Image 1D-1F to are adding body diode DMOS element embodiment water-blocking. The component 106, 108 and 110 are shallowly than a main body region and source region contact the groove. A certain embodiments, the body area thin layer covers with the source region groove base and epitaxial layer, which is body/drain electrode embedded to the low injection diode. Thin Ticeng the thickness and doped layer (the Thin Ticeng between a source area and groove and drain electrodes) is adjusted, so the reverse transistor, the Thin Ticeng almost exhausts, wherein the forward transistor, the comparing is not interconnected. A certain embodiments, the thickness layer portion is 0.01 to 0.5 μ and. Wherein the current carrier reduced enormously, therefore the component 106, 108 and 110 the integrated of the low injection diode of the regular main body are provided with the modification of performance. Is appropriately control the Thin Ticeng the ACK/NAK, injecting body diode is connected to a water-blocking with Schottky diode suitable performance, a coefficients of with is: Wherein a omit the formation of Schottky barrier key-course, and simplified process according with.

[0031] Digital is 2 to show the buck converter circuit demonstration's schematic drawing. The display, as the circuit 200 is used for high-end FET device 201 and low-end FET 207 device. The high-end 201 device comprises a transistor and 202 body 204 diode. The low-end device 207 and an 100, 102 or 104 part of such as a position fixing 1A-1F realizing. The component (207) comprises a transistor 208, body diodes 210 and Schottky diode 212. Load comprises inductor 214 capacitors, 216 and 218 resistor. During normal operation, a device 201) is transmitted the power from the input source of the switching-on the load. To make the current ascend to the inductor. When the component 201 switching circuit, the current inductor position flow, and towards the direction of the component 207 body 210 diodes. The short the same; the control circuit with the device breakovers 207, wherein the first transistor 208 trenches, and significantly of the component 208 drain electrode of supply terminal from voltage drop. The is a Schottky diode situations 212, wherein for charging of the main body diode conveyance consumption and device for removal 207 body diodes (210) with large possibly. The, a Schottky diode 212 framework in component, 207 and a Schottky diode with low voltage sheet, drop the conveyance consumption of a enormously. Cottons is lower than the main body diode combination voltage drop of the Schottky diode forward low voltage drop; a Schottky diode thereof, there is no memory charging to pour, and further improving consumption of the diode resumed to involve.

[0032] Digital is 3 to show for constructing DMOS device manufacturing process the current position of embodiment. To 302, and grid groove of the epitaxial layer of the semiconductor substrate. The 304, gate is deposited on grid groove. To 306 and 308; and main body and source. To 310; and groove. A lower is more detailed of; a certain embodiments, and source region to the contact surface and gate region groove in steps; A certain embodiments, groove formed in the stepped, to obtain has different. The 312, electrode contact arrangement in a contacting surface. Process 300) which can, use to generate MOS element different embodiment, 102-110 with such as points as 1A-1F.

[0033] Image 4A-4U is the same as view member, of manufacture the display manufacturing process of MOS device of detail. The display, an n-type semiconductor substrate (. i.e, wherein grows with N-layer epitaxial layer is N+ silicon chip) is service network and drain electrode.

[0034] Image 4A-4J of the formation of gate. The position 4A, a surface or thermal oxidization, 400) of the SiO2 layer is the P-TYPE substrate 402. Of various embodiments, the thickness of the silica 100 A-30000 A 0.01-0.99. The thickness of the is. The thickness can be fixed with the gate of anticipation time adjustment high. Light to slushing compound layer 404 spin cover is oxide layer is; and a groove cover calling function and.

[0035] The position, 4B SiO2 is exposed area of the removal, the inner side of the SiO2 upper cover (410) is silicon etching. The position 4C, anisotropic etching silicon, a left of such as 420 each. Gate is deposited on groove. Then forming the groove gate is coloured with a substrate upper surface vertical side. The position 4D, 410 and ration is SiO2 the upper cover the returning etching, so the groove wall of later etching steps coloured with the upper cover side of the retaining aims. SiO2 the shielding material of the embodiment using, wherein for SiO2 upper cover etching a support connection with each synchronize cover of the ventilation groove wall. And a, capable of the material. The tradition the other types' the material for upper cover etching, such as Si3N4, a support connection with the curvature groove wall of etching, the ends of the gate the following steps unsatisfactory.

[0036] The image 4E, isotropically etching substrate is groove base rounding. A certain embodiments, groove is an 0.5-2.5 μιη is a deep, an is 0.2-1.5 μιη layers; The sizes of is further. Providing a flat surface of the growing gate medium material, growing SiO2 sacrifice is 430 to groove. Adhesive, a wet etching process removal sacrifice layer. The 2.4g position, heating growing SiO2 is 432 to groove and dielectric materials.

[0037] The digital 4 to Η deposition, polysilicon 440 a groove. The case, a polysilicon is doped gain to the pneumoelectric grid resistor. A certain embodiments, deposition polycrystalline silicon strata time and doping in (in-situ). A certain embodiments, and doping to the polysilicon the postdepositional. The digital 41; and etching to form such as with 442 to voltage a polysilicon layer is SiO2 rotation angle. On, the gates upper surface 444) are opposite to the SiO2 upper surface (448) is located hollow; The, is fixed in the upper shielding layer is 410; the gates upper surface (444) can be higher than the silicon the upper layer (446). A certain embodiments, wherein the polysilicon loop comprises a etching is a guard. A certain embodiments, wherein the polysilicon loop comprises a etching uses the middle to prevent the surface of the following main body are in process of add-on. The image 4J, removal SiO2 upper cover. A certain embodiments; and etching to receive the removal upper cover. The bottom-linked the top surface of the etching process scram, wherein the metal polysilicon door; the surface of the substrate (pour with the source adulterant and main body adulterant) is extended. A certain embodiments, gate extend substantially 300 A-20000 A on the surface of the substrate. The values and is further. For SiO2 upper cover and other embodiments, wherein a claims a anticipation quantity gate to form the Si surface of the controllable method. Then, and growing shielding oxide on the wafer. The process of with hollow gate polysilicon device of simplifying in aggregate method thereof. For example, a certain embodiments, during forming a groove for optical to the slushing composite cover or very thin SiO2 upper cover, and gate polysilicon for obtaining therefore it from the surface Si.

[0038] Digital 4 Κ -4 Ν of the formation of source and main body. The digital 4 to Κ, and main body cover 450 to the slushing compound layer end of the conducting is an optical the main body is. The concealed area is not poured into a main body adulterant. Such as boron ion's adulterant poured into. A certain embodiments of here is not shown, wherein an of the main body preventing the internet 450 situations end of the main body is pour into, wherein a form a continuous body area of the active each. The image 4L, removal light sending the slushing parallel, and main body adulterant diffusion with the heating board is connected with sometimes of called the main body is motor body (a) process to inject. , Then is formed body area 460a_460d. A certain embodiments, is used to pour into the main body adulterant the energy portion is 30 to 600keV, dosage of an 5el2-4el3 ion /cm2, and terminal main body has for obtaining portion of 0.3-2.4 μ and. By changing factor, comprising injecting energy, dosage and diffusion temperature, a straight different depth. During dispersing process, comprising form an oxide layer and 462.

[0039] The image 4M; and source cover 464 end of the conducting to the slushing compound layer is an optical. The pores in the embodiment, the source cover 464 to prevent from among the active each any area. A certain embodiments, the source cover (464) is not shown) filled with the propping to the central region between each active. No pour for eliminating area of the source 466 adulterant. The display, a silicon the arsenic ions permeating eliminating out zone, not to form a N+ supply. A certain embodiments, a injecting supply adulterant energy portion is 10 to IOOkeV, the dosage of an Iel5-lel6 ion /cm2, the source depth and obtaining portion of 0.05-0.5 μιη. Capable of changing the factor, such as doped energy and dosage, realizing has further to reduce. The pneumoelectric testing, an injection technologies is a. The digital 4 to Ν, a removal light sending the slushing compound; heating board is the casting body by source technique supply adulterant and diffusion. The drive source, layer (e.g. BPSG,) is 465 arrangement in a round top surface, and a line, a certain embodiments can wherein densification.

[0040] Image 40-4T of the formation of the groove and injecting of each pair of contact groove. The digital 40, wherein the slushing compound layer (472) deposited on medium, and a contact surface calling function and. Executing the first contact etching to form a groove 468 and 470. A certain embodiments, first contact groove has a 0.2-2.5 μ and.

[0041] The image 4P, removal light to the slushing compound layer, an ion for by injecting shell the groove 470) is region to form a puncturing for preventing layer. A certain embodiments, using dosage portion of the l_5el5 ion /cm2 boron ion. Adding energy portion is 10-60keV. A certain embodiments, using dosage portion is l_5el5 ion /cm2, adding panel is a 40-100keV ion BF2. A certain embodiments, injecting BF2 and boron to form a puncturing for preventing layer. Adding dip angle of an 0-45 degrees. The image 4Q, and diffusion to infusion.

[0042] The image 4R, and second contact etching. Wherein the etching process will not affect the dielectric layer, therefore the second contact etching no need the extra cover. A certain embodiments, a deep groove is 0.2-0.5 μ and. A wire preventing to the numbers eating-thrown, an connection resistor is arranged at infusion 474a-474b of the groove wall. The image 4S, and ion implantation to form a low dose shallow Schottky N-TYPE barrier 476 key-course. A certain embodiments, using dosage, adding the energy 2ell-3el3 ion /cm2 the or boron BF2 the IO-IOOkeV. The image 4T, activation Schottky barrier key-course through diffusion. Arranged on a resistor injecting compares, a Schottky barrier key-course need to compare the low dose, and which is provided with a low doped and thin input down. A certain embodiments, a Schottky barrier key-course portion is 0.01-0.05 μιη is thicker. The barrier Schottky key-course adjustable blocking-up, wherein infusion adjusting and semiconductor on the surface of the electrode contact.

[0043] The image 4U, of the alarm device 490. The metal layer deposited 478 and etching the pneumoelectric condition, and a polypropylene. Manufacturing 480 the deactivated opening of the deposition passivation layer. Is further in the is set to be used to achieve manufacturing the additional, such as grinding board and back end metal deposits.

[0044] May use process capable of the. For example, a component in working drawing 1D-1F fixing 106-110, for modifying to the main body injected technology for digital 4 to Κ pores, and an of the source region there is no body to prevent the internet. The main body adulterant poured into, a cover exposition region and direct forming continuous body area in the resistor. During contacting etching, the etching groove is than a main body base region and depth, so the main body layer is lower than the groove. A line, can pass through the active contact groove only etching the main body, a and drain electrode area, is the solar and adulterant with good control additional body doped to pour into to pass through the groove wall and base of the film body layer.

[0045] A certain embodiments, to form a Schottky barrier key-course, deposited such as SiGe narrowband are made by chemical vapor deposition, cambium of the epitaxial layer upper surface. A certain embodiments, narrowband notch material layer is a loo A to 1000 and A 0.01-0.99 the. For example, and A 200 rich silicon SiGe layer in certain embodiments. A certain embodiments, rich silicon SiGe layer comprises Si 80% and 20% Cover. A certain embodiments, calling function end of in-situ doping of the 2el7-2el8/Cm3 concentration the narrowband notch material layer of the N adulterant. Then, the deposition low-temperature oxide layer and narrowband gap layer, and the conducting to form the upper cover to the low-temperature oxide layer, in the groove etching to the epitaxial layer is. During doing etching process, the upper cover for protecting the narrowband gap layer component.

[0046] Image 5A-6B of manufacturing a joint which is connected to the second embodiment. For example, image 5A and puncturing for preventing diffusion layer (see the position 4Q). And the second contact surface to recipients of the light 502 end of the conducting to the slushing compound layer, for gate 504 groove. The image 5B, a second etching increase with the source region to the contact surface 506 depths. And the removal light sending the slushing parallel, and is the same and 4T position in the manner of 4S time to pour into a Schottky key-course barrier. Completed the position of the substrate comprises a joint metal deposits and passivation (see the position 4U). The device for obtaining is similar to the position IB device 102, the gate groove is provided with the source region and groove has different. By using in aggregate of the second contact groove etching's independent cover, is realized different gate groove and source region contact the groove has, so that the gate groove contact is shallowly, and a relax when the worry of gate polysilicon during etching. , Wherein usually using the technical to bind the short gate polysilicon device, comprising with the gate polysilicon embodiment of the substrate surface extending.

[0047] Image 6A further disposed on the puncture for preventing diffusion layer (see the position 4Q). And the second contact surface to recipients of the light 602 end of the conducting to prevent the gate groove to the slushing compound layer (604), so the bottom of the source region of the contact surface is 606 to form of a first etching contact is a contact hole. The position 6B, and second contact etching, form, deep trench narrower 608 component. The removal light sending the slushing parallel, and embodiments of the position of 4S-4U step. The device for obtaining is similar to position IC 103.

[0048] Digital 7-10 of manufacturing process of second the improved; the improvements can use in certain embodiments to further the device performance.

[0049] Digital 7 cooling is connected to the improved the is connected to form a gate points (accessed); and front tank body preventing the middle position (4K) performing etching. Coated with an epitaxial layer; the surface of the epitaxial layer both are long injecting 702 in. A certain embodiments, A Nengliang, low dose (5ell-lel3,200-600keV boron) are used for forming of the main body injecting are uniformly injecting 702 in. Injecting uniform thickness is used to of the epitaxial layer arced, wherein it is that the epitaxial layer semi-polarity exchange. Poured into uniformly provided in the main body is arced main body base region; and notably which is added in Rdsra condition to the breakdown voltage.

[0050] Digital 8 cooling is connected to the improved the is connected with Shannon deposition injecting position (4S), a position (4T) performing etching of the activation. The epitaxial layer profile of injecting injecting to of the source region and lower groove. The epitaxial layer profile of injecting provided with a epitaxial layer are long. A certain embodiments, A Nengliang, low dose or boron BF2 (e.g., 5ell-lel3, 60-300keV) is used to pour into. The inject of the epitaxial layer arced, it does not changing the epitaxial layer, polarity and strengthened a breakdown voltage.

[0051] Digital 9 cooling is connected to the improved the is connected with Shannon deposition injecting position (4S), a position (4T) fails wherein activating time. A Nengliang, the dosage (Iel2-5el3,60_300keV) boron poured into to form a P-TYPE island 902, wherein the P-TYPE island 902) are located below the contact surface of the P-TYPE epitaxial layer, and spacer connected with the main body area. The floating TYPE island is around a breakdown voltage.

[0052] Digital 10 cooling a second the improved is connected to form the groove shape (40); and front connecting Shannon and injecting position (4P). Wherein the angle incisive the overhead, charging with high electric field and a breakdown voltage, therefore with a groove base angle 1002a-1002b rounding to reduce the accumulation of charging and improving breakdown voltage.

[0053] Although stemming from transparent in the volume, where the embodiment of multiple details; the invention is interposed between adjacent a detail and methods. A with a groove which to realize the invention. The embodiment of publicizes is installed schematic, which is restrictive.