Synchronizing of a digital signal using a PCR program clock reference

FIRST DIGITAL SIGNAL SYNCHRONIZATION USING PCR PROGRAM CLOCK REFERENCE Technical Field The present invention relates to a digital signal receiving system, a digital signal receiving device, a host device, and a semiconductor integrated circuit suitable for receiving digital signals in a moving object.

BACKGROUND In recent years, thanks to the development of digital technology that digitizes various information signals such as video and audio signals, digital broadcasting systems have been put into practical use, as well as analog TV broadcasting. In this digital broadcasting system, the MPEG2 system has been used. In the MPEG2 system, content data such as digitized video and audio data is packaged into transport data stream packets (also known as "TS packets") o TS packets are multiplexed and transmitted as digital broadcast transmission data Streaming. A television set capable of receiving digital TV broadcasts and analog TV broadcasts has been developed, as well as receivers dedicated to digital TV broadcasts, called set-top boxes, which allow viewers to watch digital broadcasts.

In digital broadcasting systems, research on terrestrial digital broadcasting has progressed. Especially in recent years, there is a strong demand for mobile objects in the market, such as mobile phones. In consideration of these circumstances, mobile terminal equipment for terrestrial digital broadcasting is currently being developed.

There are some well-known memory cards in the field of mobile device objects, such as smart media and secure digital (SD) cards (hereafter these devices are sometimes referred to as "electronic cards"). These memory cards can be detachably connected to mobile phones, digital cameras, and so on. In addition, it has been proposed to configure a special memory card to equip a general memory card (see Japanese Unexamined Patent Document No. 2003-234935) with a radio communication function or a position determination function, such as a global positioning system (GPS). Hereinafter, this type of special memory card is referred to as a "special memory card". Components for realizing special functions are incorporated into this special memory card.

Fig. 17 is an explanatory diagram showing an example of a mobile phone as a conventional mobile terminal device. The mobile phone is configured to detachably connect a memory card or a special memory card. Referring to FIG. 17, a conventional mobile terminal device includes a phone body 90, a key input portion 92 that allows the user to perform input operations (such as entering a phone number and names of various operations), a display portion 91 that informs the user about communication and other information, The antenna 93 used to transmit/receive data and various processing circuits (not shown) provided in the phone body 90 ο mobile phone

200480018523.3 The first chapter has a connection part 94 on the upper part of the phone body 90 to detachably connect the memory card. With this arrangement, when the user inserts the memory card into the connecting portion 94, the user can use the phone body 90 in a manner of combining the mobile phone and the memory card.

For example, when a user inserts a memory card storing image data into the connection part 94 and inputs a command indicating image display through the keyboard input part 92, an image corresponding to the designated image data stored in the memory card can be displayed on the display part 91 display. In addition, when the user inserts the special memory card 95 into the connection portion 94, the user can use the phone body 90 in a manner of combining the functions of the mobile phone and the special memory card. For example, when a user inserts a special memory card 95 carrying a GPS function into the connecting part 94, the position of the mobile phone determined by the GPS can be displayed on the display part 91, and the user can notify the designated location of the mobile phone through the mobile phone function. square. Therefore, it has been proposed to configure the system such that the host device function and the special memory card function are combined with each other, the host device has the inherent functions of the mobile phone, and the connection portion 94 is used as an interface with the special memory card 95.

As terrestrial digital broadcasting is put into practical use, it has become easier to receive digital broadcasting through mobile objects. In view of this, there is a demand for digital broadcasting receivers or digital broadcasting receiving systems that can use such mobile objects in the market. Specifically, a mobile phone or personal digital processing (PDA) that can receive digital broadcasts, a car navigation system that can receive digital broadcasts, and a digital broadcast receiving system that connects terrestrial digital broadcast receivers with mobile phones or navigation systems are needed. Taking these aspects into consideration, the market requires a digital broadcast receiving system in which special memory cards have a digital broadcast receiving function and mobile terminal devices (such as mobile phones used as host devices) are interconnected with each other so that users can receive and watch digital broadcasts.

However, when establishing a digital broadcast receiving system in which a special memory card has a digital broadcast receiving function and host devices are interconnected with each other, the following disadvantages should be considered.

First of all, because devices such as mobile objects are produced under the premise of portability, their essence is to meet the requirements for miniaturization, lightness, and reduction of power consumption.

In addition, a bigger problem must be overcome: how to synchronize the clocks in the special memory card and the host device with each other. Specifically, there is a great need to develop a situation where radio wave reception conditions are degraded, such as when the host device (or receiver) is powered on or when the host device is located in a valley of a high-rise building, and when the user switches channels, or the like , The technology to restore the clock synchronization between the special memory card and the host device.

If the data including clock information can be sent from the special memory card to the host device without delay, the latter problem can be solved. However, in most cases, the interface of the special memory card represented by the SD card uses asynchronous

200480018523.3 No. Communication. Therefore, the timing of sending data from the special memory card to the host device (or receiving data by the host device is not constant, that is, constantly changing. In other words, data transfer time is required until the host device receives data from the special memory card. Therefore, in When the user switches channels, for example, because the clock information transmitted from the special memory card is received by the host device with a time lag corresponding to the data transfer time, the time will be delayed. In addition to the above shortcomings, since the data transfer time is not constant, It is difficult to synchronize the clocks in the special memory card and the host device with each other.

SUMMARY OF THE INVENTION In consideration of the above problems in the prior art, the purpose of the present invention is to provide a digital signal receiving system, which is configured as a digital signal receiving device configured as a special memory card, and the host devices are interconnected with each other for safe recovery The special memory card is synchronized with the clock in the host device, even under weak radio reception conditions, and provides digital signal receiving devices, host devices, and semiconductor integrated circuits that constitute the host device.

To accomplish the above object, according to one aspect of the present invention, a digital signal receiving system is provided that includes: a digital signal receiving device for receiving a digital communication signal, having a function of generating a clock signal based on PCR data included in the communication signal, and more The function of sending data stream signals and clock signals in the form of information packets. The data stream signals include communication signals; and the host device is used to receive the data stream signals and clock signals from the digital signal receiving device through the interface part. The digital signal receiving device includes: The receiving STC counter is used to count the number of clock signals and output the counter value as the received STC data; the deviation detector is used to calculate the difference between the received STC data and the PCR data as the difference data, and detect the value exceeding the predetermined value based on the difference data The frequency deviation of the clock signal; and the deviation processor, which is used to transmit the deviation information data obtained according to the received STC data and PCR data to the host device. If the deviation detector detects a frequency deviation exceeding a predetermined value, it is set in the receiving STC counter Set PCR data, the host device includes: host STC counter, used to count the clock number of the clock signal transmitted from the digital signal receiving device, and output the counter value as host STC data; STC correction unit, if the deviation detector detects more than a predetermined value The frequency deviation is calculated based on the host STC data and deviation information data, and. Set the correction data in the host STC counter so that the counter value set in the receiving STC counter is consistent with the counter value set in the host STC counter.

These and other objects, features, viewpoints and advantages of the present invention are read in the following embodiments and

200480018523.3 It will be more clear after the attached figure.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the entire configuration of a digital broadcast receiving system according to Embodiment 1 of the present invention.

2 is a block diagram showing the detailed configuration of the digital broadcast receiving system according to the first embodiment of the present invention.

3 is a block diagram showing the detailed configuration of an STC recovery unit in the digital broadcast receiving system according to the first embodiment of the present invention.

4 is an explanatory diagram showing an example of the communication format of data transferred from the packet transfer unit in the digital broadcast receiving system according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram showing the sequence of how to reset the counters in the receiver and the host device in the digital broadcast receiving system in the first embodiment of the present invention.

6 is an explanatory diagram showing the sequence of how to transfer the transmission data stream from the receiver in the digital broadcast receiving system to the host device in the first embodiment of the present invention.

7 is a graph showing how the STC data value changes when the same value is set in the counters of the receiver and the host device in the digital broadcast receiving system according to the first embodiment of the present invention.

FIG. 8 is a block diagram showing the detailed configuration of the digital broadcast receiving system according to the second embodiment of the present invention.

9 is an explanatory diagram showing an example of the communication format of data transferred from the packet transfer unit in the digital broadcast receiving system according to the second embodiment of the present invention.

10 is a graph showing how the STC data value changes when the same value is set in the counters of the receiver and the host device in the digital broadcast receiving system according to the second embodiment of the present invention.

FIG. 11 is a block diagram showing an example of functional blocks constituting the semiconductor integrated circuit used in the present invention.

FIG. 12 is a block diagram showing another example of functional blocks constituting the semiconductor integrated circuit used in the present invention.

FIG. 13 is a block diagram showing another example of functional blocks constituting the semiconductor integrated circuit used in the present invention.

14 is a diagram showing another example of the functional blocks constituting the semiconductor integrated circuit used in the present invention

200480018523.3 Block diagram.

15 is a block diagram showing another example of functional blocks constituting the semiconductor integrated circuit used in the present invention.

Fig. 16 is an explanatory diagram showing a digital broadcast receiving system embodying the present invention.

Fig. 17 is an explanatory diagram showing a conventional device in which a special memory card is used with a mobile phone.

DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. Hereinafter, the embodiment will be explained through an example of digital broadcasting in digital communication. However, it should be understood that the present invention is not limited to this.

The MPEG2 system is considered to be the basic system, which is used to enable digital broadcasting stations (transmitters) to send digital broadcasting to digital broadcasting receivers (receivers), and to enable digital broadcasting receivers to receive digital broadcasting. In this system, the broadcasting station encodes Individual materials, such as independent video and audio data, while maintaining the correlation between the materials. According to the transmission media format suitable for the data stream, the encoded individual data streams (data strings) are each multiplexed by a multiplexer Used to send the data stream to the receiver. The sent multiplexed data stream is separated into individual data streams, such as video stream and audio stream, by the separator. These individual data streams are sent to the decoder respectively, and the decoders are in turn independent of each other. Decode data streams locally, such as video data streams and audio data streams. The decoded data is output to output devices, such as monitors and speakers.

In the MPEG2 system, it is important to accurately send clock information for synchronizing the clock from the transmitter to the receiver.

In order to complete this task, it is necessary to set the reference clock and synchronize the clocks in the transmitter and the receiver with each other. In view of this, the broadcasting station (encoder) transmits PCR (program clock reference) data to the receiver (decoder). The PCR data is the information used to set and calibrate the STC (system time clock) value, and the STC value is used for broadcasting The reference clock of the station needs value. After receiving the PCR data, the receiver generates a clock synchronized with the clock set in the broadcasting station. In this configuration, the clock in the receiver is generally corrected based on the difference between the PCR and the STC regenerated in the receiver.

In addition to the above, separate data streams such as video data streams and audio data streams need to be synchronized with each other in data stream playback. Therefore, information called a time stamp is added to each data stream. The time stamp indicates at what timing the data stream is decoded and replayed. A time stamp is added to the unit (access unit) used for decoding/playing back the data stream. There are two timestamps: one is about the time of replay/output

200480018523.3 The third management information is called PTS (representing time stamp), and the other is the time management information about decoding, called DTS (decoding time stamp).

The PTS is designed to reproduce and output the PTS-bearing access unit when the STC in the receiver conforms to the PTS. On the other hand, DTS is provided to solve the situation where the video data playback/output sequence needs to be changed. In other words, DTS is provided to solve the situation where the decoding order and the playback/output order are different from each other. Taking this into consideration, the system is configured to add two time stamps (PTS and DTS) to the access unit if the PTS is different from the DTS, and if the PTS and DTS match each other, then only the PTS is added to the access unit.

Hereinafter, the preferred embodiments of the present invention will be described with reference to the drawings and through digital broadcasting examples.

[Embodiment 1] Fig. 1 is a block diagram showing the entire configuration of a digital broadcast receiving system according to Embodiment 1 of the present invention. First, the entire configuration of the digital broadcast receiving system as the first embodiment will be explained with reference to FIG. 1.

The digital broadcast receiving system as the first embodiment includes a digital broadcast receiving device 10 (hereinafter also referred to as "receiver 10"), a host device 20, and a digital interface 30 (hereinafter also referred to as "digital I/F 30"). The receiver 10 is suitable for receiving digital broadcasting and decoding a transport data stream signal (hereinafter also referred to as "TS" or "transport data stream") according to the received signal. The host device 20 is adapted to receive the decoded transport data stream from the receiver 10, and decode signals such as video and audio signals according to the received transport data stream. The digital interface 30 is suitable for transmitting/receiving transmission data streams and digital signals between the receiver 10 and the host device 20.

The digital interface 30 is adapted to transfer high-resolution video signals and multi-channel audio signals in a digital format in a state of maintaining quality without compressing the signals. An example of the digital interface 30 is HDMI (High Definition Multimedia Interface), which is an interface designed for digital consumer electronic products. HDMI is an interface designed for audio-visual equipment, in which the DVI (Digital Visual Interface) specification for connecting a personal computer and a monitor has been modified. Because the video signal and audio are transmitted through a single cable, HDMI does not have the disadvantages of traditional analog cable systems.

In addition, the digital broadcast receiving system in this embodiment has the functions of supplying a clock signal from the receiver 10 to the host device 20 together with the transmission data stream through the digital I/F 30, and sending information about the synchronization of the clock signal in the receiver 10 and the host device 20. The characteristics of the information of the signal.

The receiver 10 in this embodiment is an electronic card constructed as a multi-purpose memory card.

200480018523.3 The first memory card has the function of receiving digital broadcasting. Using a mobile terminal device, that is, a mobile object such as a mobile phone or a PDA used in a digital broadcast receiving system, as the host device 20 is very advantageous to provide the effects and operations of the present invention.

An example of an electronic card is an SD card. SD card is a flash memory card with mature copyright protection function, but the size is only the size of a postage stamp. SD card is a large-capacity electronic card, suitable for recording images, movies, music, etc. in digital cameras.

The receiver 10 is configured such that the tuner section 11 applies processing such as demodulation and error correction to the digital broadcast wave received by the antenna in order to output a demodulated signal. The demodulated signal from the tuner section 11 is sent to the transport stream receiving section 12 (hereinafter also referred to as "TS receiving section 12").

The TS receiving section 12 receives the demodulated signal from the tuner section 11, and restores the transmission data stream based on the demodulated signal. The transport data stream is composed of a specific number of transport data stream packets (hereinafter sometimes referred to as TS packets") obtained by packaging content data such as video and audio data of digital broadcasting programs. The TS receiving part 12 detects the composition transmission Each TS packet of the data stream, and extracts the information needed especially for synchronization. Each TS packet consists of a header part used to store management data related to the TS packet, and used to store program content data and information about the program And so on the data part of the composition.

The header part includes the sink byte indicating the front end of the TS packet, and the packet identification information (hereinafter also referred to as "PID information") as the TS packet identification number. The TS receiving section 12 identifies the TS packet by detecting the sink byte indicating the front end of the TS packet. The TS receiving section 12 uses PID information to extract TS packets containing PCR-related information, which is necessary for regenerating the clock. The PCR information is information related to the clock in the broadcasting station of digital broadcasting. After extracting the TS packet containing PCR information, the TS receiving section 12 notifies the clock processing section 14 of the PCR information stored in the data section of the TS packet. The TS receiving part 12 provides the decoded transport data stream to the interface part 13 (also referred to as the "1/F part 13").

The clock generation unit 141 generates a clock signal required for digital processing in the receiver 10.

The clock processing part 14 receives the PCR information from the TS receiving part 12, and uses the PCR information and the clock generation unit 141 to cooperate to regenerate (ie, copy) a clock synchronized with the clock in the broadcasting station. The clock reproduced in the clock processing section 14 is transferred to the I/F section 13.

In addition, when synchronization is not established due to weak radio wave reception conditions in clock regeneration, the clock processing section 14 detects a synchronization failure. Similarly, the clock processing section 14 will include deviation information data

The additional information of 200480018523.3 is notified to the TS receiving part 12. When synchronization is not established, the deviation information data is information related to clock regeneration conditions. After receiving the additional information including the deviation information data, the TS receiving section 12 generates additional data storing the additional information. The TS receiving section 12 attaches the additional data to the decoded transport data stream, and supplies the transport data stream together with the additional data to the I/F section 13. The process of detecting synchronization failure and additional information will be described in detail later.

The additional data may be attached to the data portion of the additional information packet, rather than attached to the transmission data stream. Alternatively, the additional data may be attached between consecutively sent information packets without being packaged or stored in the additional information packet. Alternatively, the additional data may be sent in parallel with the packet transmission immediately after the synchronization failure is detected.

The I/F section 13 is an interface provided in the receiver 10 for performing communication with the host device 20, transmitting clock signals, and the like. The I/F section 13 serves as a receiving interface. The receiver 10 transmits the regenerated clock signal and the reset signal to the host device 20 through the I/F section 13, and the transmission data stream including additional information. The I/F section 13 transmits notification data to the host device 20 to notify the status of each process in the receiver 10. The host device 20 transmits command data for controlling the receiver 10 to the I/F section 13. In response to the received command data, the I/F section 13 notifies each section in the receiver 10 of command information specifying processing and the like based on the content of the command data.

The I/F section 23 is an interface provided in the host device 20 for performing communication with the receiver 10, receiving clock signals, and the like. The I/F section 23 serves as a host interface. The host device 20 receives the clock signal and the reset signal through the I/F part 23, and also has a transmission data stream including additional information. In addition, the host device 20 receives notification data from the receiver 10, and the notification data includes information related to each processing state in the receiver 10. The I/F section 23 sends command data for the host device 20 to control the receiver 10 to the receiver 10. The I/F section 23 notifies each section in the host device 20 of the content of the notification data as notification information.

The TS decoding section 22 separates the transport data stream supplied to the I/F section 23 into video packets containing video data, audio packets containing audio data, and information packets containing output information about data reception and the like. At this time, the TS decoding section 22 provides the decoder section 21 with packets containing content data of each program, such as video packets and audio packets, as a packaged elementary data stream called PES. PES consists of information packets containing content data.

The decoder section 21 receives a PES composed of video packets and audio packets supplied from the TS decoding section 22. The decoder part 21 extracts the video stored in the data part of each packet.

200480018523.3 Frequency data and audio data, and decode each video signal and audio signal for output to the monitor and speaker.

The clock processing part 24 receives the clock signal transmitted from the receiver 10, and generates the clock signal in the host device 20 according to the received clock signal. The clock processing section 24 resets counters and the like provided in the clock processing section 24 in response to receiving a reset signal from the receiver 10.

The TS decoding section 22 extracts additional data from the transport data stream that has been sent to the I/F section 23, and supplies the extracted additional data to the clock processing section 24. The clock processing section 24 extracts deviation information data from the supplied additional data. The clock processor part 24 updates the count value of the counter provided in the clock processor part 24 based on the deviation information data, and restarts counting from the updated count value.

As described above, the digital broadcast receiving system in this embodiment is configured such that the receiver 10 and the host device 20 are interconnected with each other through the digital I/F 30. In this embodiment, the transmission data stream carrying additional information, clock signals, reset signals, notification data, and command data is transmitted between the receiver 10 and the host device 20 through the digital I/F 30.

Hereinafter, the configuration of the digital broadcast receiving device 10 and the host device 20 in the digital broadcast system according to the first embodiment of the present invention will be described in detail with reference to the block diagram of FIG. 2.

First, the detailed configuration of the receiver 10 is explained. The tuner section 11 in FIG. 1 is constituted by the tuner unit 111 shown in FIG. 2. The TS receiving part 12 in FIG. 1 is composed of the TS input unit 121, the PCR extraction unit 122, the TS accumulation unit 123, and the packet management unit 124 shown in FIG. The I/F section 13 shown in FIG. 1 is composed of a packet transfer unit 131, a notification unit 132>clock output unit 133, and a command receiving unit 134 shown in FIG. The clock processing section 14 shown in FIG. 1 is composed of the R_STC counter 142, the STC restoration unit 143, the additional information attachment unit 144, and the reset processing unit 145 shown in FIG.

Referring to FIG. 2, the tuner unit 111 is adapted to apply processing such as demodulation and error correction to the digital broadcast wave received by the antenna, and output a demodulated signal to the TS input unit 121.

After receiving the demodulated signal from the tuner unit 111, the TS input unit 121 decodes the transport data stream according to the demodulated signal. The decoded transport data stream is supplied from the TS input unit 121 to the PCR extraction unit 122.

The PCR extraction unit 122 detects the PID information of each TS packet in the provided transport data stream, and extracts the TS packet containing PCR information based on the PID information. In addition, the PCR draw sheet

200480018523.3 The first element 122 extracts PCR information stored in the extracted TS packet, and informs each STC recovery unit 143 and R_STC counter 142 of the extracted PCR information as PCR data. In addition, the PCR extraction unit 122 provides the TS accumulation unit 123 with the transport data stream that has been supplied from the TS input unit 121.

The TS accumulation unit 123 is a packet buffer for temporarily and cumulatively storing a predetermined number of TS packets included in the transport data stream. The TS accumulation unit 123 continuously stores the TS packets supplied from the PCR extraction unit 122 in accordance with the command sent from the packet management unit 124. In addition, in response to receiving a command to attach additional information from the information packet management unit 124, the TS accumulation unit 123 stores additional data including the additional information provided from the additional information attaching unit 144, and TS packets. The transport data stream composed of TS packets and additional data is supplied from the TS accumulation unit 123 to the packet transfer unit 131. Next, the packet transfer unit 131 transmits the transport data stream and additional information to the host device 20, and responds to the packet read command , Which is one of the command information transmitted from the command receiving unit 134.

The clock generation unit 141 generates a clock signal required for digital processing in the receiver 10. At this time, the frequency of the clock signal generated by the clock generating unit 141 corresponds to the difference data transmitted from the STC recovery unit 143. The clock generation unit 141 converts the difference data into a control voltage through a digital-to-analog (D/A) converter or through a combined pulse width modulator (PWM) and a low-pass filter. In addition, the clock generation unit 141 converts the difference data into a control voltage according to the control voltage and, if necessary, The oscillation frequency of the voltage controllable crystal oscillator is controlled by devices such as loop filters. The clock generating unit 141 outputs the signal output from the voltage controllable crystal oscillator as a clock signal through a buffer or other device as needed. Therefore, the clock generating unit 141 generates a clock signal according to the difference data so as to transmit the clock signal to various parts in the receiver 10.

The R_STC counter 142 is a counter used to generate a system time clock (hereinafter also referred to as "STC"), and the system time clock is used to generate a reference clock. The R_STC counter 142 is used as a reception STC counter. The R_STC counter 142 performs counting by counting the clock signal continuously output from the clock generating unit 141 via the clock input terminal (CK). The R_STC counter 142 outputs the count data indicating the number of times the clock signal is counted to the count output terminal (OUT) as the received STC data so as to provide the STC recovery unit 143 with the received STC data. The R_STC counter 142 has a reset input terminal (R), a load input terminal (L), and a load data input terminal (IN).

The R_STC counter 142 is notified of the reset from the reset processing unit 145 through the reset input terminal.

200480018523.3 The first signal. After receiving the reset signal, the R_STC counter 142 sets the count data output from the count output terminal to an initial value, such as zero.

After receiving a deviation detection signal (described later) from the STC recovery unit 143 through the load input terminal, the R_STC counter 142 reads PCR data from the PCR extraction unit 122. The R_STC counter 142 receives PCR data through the load data input terminal. The R_STC counter 142 sets the count data output from the count output terminal to the value of the read PCR data.

The STC recovery unit 143 reads the received STC data from the R_STC counter, and reads the PCR data from the PCR extraction unit 122. Next, the STC restoration unit 143 calculates the difference between the received STC data and the PCR data, and sets the difference as the difference data. In addition, the STC recovery unit 143 uses the difference data to detect synchronization failure or clock generation abnormality.

FIG. 3 is a block diagram showing the details of the STC recovery unit 143. 3, the difference detector 431 of the STC recovery unit 143 calculates the difference between the received STC data and the PCR data, and provides the difference as the difference data to the deviation detector 432 and the clock generation unit 14L·deviation detector 432 for reading The difference data transmitted from the difference detector 431, and the predetermined allowable upper limit and allowable lower limit regarding the difference data. In the case where the frequency deviation detected based on the difference data is greater than the predetermined value, that is, if the difference data exceeds the range defined by the upper limit and the lower limit, the deviation detector 432 outputs a deviation detection signal. Specifically, the deviation detector 432 monitors the deviation corresponding to the difference between the received STC data and the PCR data, and if the difference data is higher than the upper limit or lower than the lower limit, it is judged that a synchronization failure or abnormality has occurred during clock regeneration.

If the deviation detector 432 determines that a synchronization failure or abnormality has occurred during clock regeneration, the deviation detector 432 notifies the load input terminal of the R_STC counter 142 of a deviation detection signal indicating synchronization failure detection.

The deviation detector 432 can monitor the absolute value of the difference data, and if the absolute value of the difference data exceeds the allowable upper limit, it outputs a deviation detection signal.

In response to the frequency deviation detection by the deviation detector 432, the STC recovery unit 143 reads the received STC data and PCR data, stores these data as deviation information data, and sets the PCR data in the R_STC counter 142. Therefore, the STC restoration unit 143 also functions as a deviation processor.

In this way, the clock generation unit 141, the R_STC counter 142, and the STC recovery unit 143 establish a clock regeneration loop to generate a clock signal synchronized with the reference clock set in the broadcasting station according to the PCR data transmitted from the PCR extraction unit 122. Therefore, the connection from the PCR extraction unit 122

200480018523.3 After receiving the PCR data, the difference detector 431 of the STC recovery unit 143 calculates the difference between the received STC data and the PCR data.

In the case where the value of the PCR data is greater than the value of the received STC data, for example, a control voltage corresponding to the value of the difference data is applied to the voltage controllable crystal oscillator. Therefore, the frequency of the clock signal generated in the clock generating unit 141 is increased, and the counting rate of the R_STC counter 142 is correspondingly increased. As a result, the value of the received STC data is closer to the value of the PCR data, and ultimately the two are the same. As described above, performing loop control every time the PCR extraction unit 122 extracts PCR data makes it possible to lock the clock generation loop, so that the value of the PCR data and the value of the received STC data coincide with each other. Therefore, the clock signal generated in the clock generating unit 141 is synchronized with the reference clock in the broadcasting station. In digital broadcasting systems, 27 MHz is usually used as the frequency of the clock signal.

In addition, as described above, if the deviation detector 432 determines that the value of the difference data exceeds the range defined by the allowable upper limit and the allowable lower limit, the deviation detector 432 of the STC recovery unit 143 notifies the R_STC counter 142 of the deviation detection signal. Setting the value of PCR data in the R_STC counter 142 according to the deviation detection signal helps to shorten the time from unlocking the clock regeneration loop (the state in which the value of the received STC data deviates from the value of the PCR data) to locking (the value of the received STC data and the value of the PCR data). Value consistent state) required time.

Specifically, if the deviation detector 432 detects that the difference data exceeds the allowable range, such detection means that the value of the received STC data and the value of the PCR data are very different from each other. In this case, if you try to use only the clock regeneration loop to make the value of the received STC data consistent with the value of the PCR data, it will take a while to lock the clock regeneration loop. In this embodiment, if the PCR data value deviates far from the value of the received STC data, the PCR data value is set in the R_STC counter 142, and the R_STC counter 142 restarts counting the clock signal from the PCR data value. This arrangement can shorten the time required from unlocking of the clock regeneration loop to locking.

The deviation detection signal and the difference data output from the STC restoring unit 143 are also sent to the additional information attaching unit 144. In addition, the difference data is attached to the transmission data stream as additional information to be provided to the host device 20.

In this embodiment, the case where difference data regarding synchronization failure or clock regeneration abnormality is used as deviation information data is explained. The present invention is not limited to this configuration. When the frequency deviation of the clock signal is detected, the deviation information data may be received STC data and PCR data. The details of this change will be explained later.

200480018523.3 As described above, the deviation detection signal and the difference data are sent from the STC restoring unit 143 to the additional information attaching unit 144. The additional information attachment unit 144 attaches the provided difference data to the transmission data stream as deviation information data. The deviation information data includes information indicating the frequency deviation of the clock signal that the deviation detector 432 has detected. The additional information attachment unit 144 generates additional information, which is used to attach deviation information data (difference data) to the transport data stream decoded by the TS input unit 121.

The additional information includes difference data and a valid flag, and the valid flag indicates whether the deviation detection signal (difference data) is valid. In response to receiving the deviation detection signal, the additional information attachment unit 144 sets the valid flag to, for example, "1", which indicates that the deviation detection signal is valid, and generates additional data as additional information along with the provided difference data. On the other hand, if the deviation detection signal is not detected, the additional information attaching unit 144 generates additional data while the valid flag is set to, for example, "0", which indicates that the deviation detection signal (difference data) is invalid. The additional information attachment unit 144 supplies the generated additional data to the TS accumulation unit 123.

The packet management unit 124 manages each TS packet supplied from the PCR extraction unit 122 to the TS accumulation unit 123 and the additional data sent from the additional information attaching unit 144. According to a predetermined format, the packet management unit 124 controls the TS accumulation unit 123 to attach additional data to each TS packet extracted by the TS extraction unit 122. In addition, the packet management unit 124 checks whether a certain number of packets to be transferred to the host device 20 have been accumulated in the TS accumulation unit 123. After confirming that the packet transfer preparation work has been completed, the packet management unit 124 causes the TS accumulation unit 123 to provide the packet transfer unit 131 with the packet.

The clock output unit 133 is an interface for transmitting the clock signal generated in the clock generation unit 141 to the host device 20.

The notification unit 132 is an interface for sending notification data to the host device 20, and the notification data includes information related to each processing state in the receiver 10. For example, the packet management unit 124 notifies the notification unit 132 that the packet transfer preparation has been completed. After receiving the notification, the notification unit 132 notifies the host device 20 of the completion of the packet transfer work. Alternatively, after receiving the deviation detection signal, the information packet management unit 124 may notify the host device 20 of the deviation detection through the notification unit 132.

The command receiving unit 134 is an interface for receiving command data for controlling the receiver 10 that has been transmitted from the host device 20. In response to receiving a packet from the host control unit 291 of the host device 20

200480018523.3 includes the command data of the reset signal. For example, the command receiving unit 134 notifies the reset processing unit 145 of the reset signal. In addition, in response to receiving command data requesting packet transfer from the host control unit 291 of the host device 20, for example, the command receiving unit 134 notifies the packet transfer signal to the packet transfer unit 131. The packet transfer unit 131 is used to transfer the packet to the host device. 20 An interface for transmitting a transmission data stream including additional data. In response to receiving the packet transfer signal from the command receiving unit 134, the packet transfer unit 131 transfers the packet that has been accumulated in the TS accumulation unit 123 to the host device 20.

4 is an explanatory diagram showing an example of the communication format of data to be transferred from the packet transfer unit 131. Referring to FIG. 4, TS1 to TS5 each represent a TS packet decoded by the TS input unit 121. In this example, data is transferred in the form of five TS packets. As described above, in the case where the deviation detector 432 detects the frequency deviation of the clock signal, the additional data generated in the additional information attaching unit 144 is attached to the transmission data stream. The additional data includes a valid flag indicating whether the deviation detection signal (difference data) is valid, and deviation information data. The packet transfer unit 131 transfers the transmission data stream carrying additional data to the host device 20 bit by bit according to the communication format defined above.

Next, the detailed configuration of the host device 20 shown in FIG. 2 will be explained. The I/F section 23 in FIG. 1 is composed of a packet receiving unit 231, a notification receiving unit 232, a clock input unit 233, a command transmission unit 234, and a reset receiving unit 235 shown in FIG. The TS decoding section 22 shown in FIG. 1 is composed of the additional information extraction unit 222 and the PES processing unit 221 shown in FIG. 2. The clock processing unit 24 shown in FIG. 1 is composed of the STC correction unit 241 and the H_STC counter 242 shown in FIG. 2.

The decoder section 21 shown in FIG. 1 is composed of the audio decoder 212 and the video decoder 211 shown in FIG. 2. The host control unit 291 shown in FIG. 2 is a control unit that controls each part of the host device 20, generates command information representing a command, and transmits it to each part of the receiver 10.

Referring to FIG. 2, the packet receiving unit 231 is an interface for receiving a transmission data stream including additional data from the packet transfer unit 131 of the receiver 10. The packet receiving unit 231 provides the additional information extracting unit 222 with the received transmission data stream.

The command transmission unit 234 is an interface for transmitting command data that enables the host device 20 to control the receiver 10. In response to receiving command information from the host control unit 291, the command transmission unit 234 transmits the command data based on the command information to the command receiving unit 134° command transmission of the receiver 10

200480018523.3 The sending unit 234 sends command data indicating resetting the counter, transferring information packets, etc., to the command receiving unit 134.

The notification receiving unit 232 is an interface for receiving notification data, and the notification data includes information related to the status of each process in the receiver 10. The notification receiving unit 232 receives the notification data transmitted from the notification unit 132 of the receiver 10 and transmits the notification data to the host control unit 291 as notification information. For example, the notification receiving unit 232 is notified that the preparation for TS packet transfer has been completed in the TS accumulation unit 123.

The clock input unit 233 is an interface for receiving the clock signal generated in the clock generation unit 141 of the receiver 10. The clock input unit 233 receives the clock signal transmitted from the clock output unit 133 of the receiver 10. After receiving the clock signal from the clock input unit 133, the clock input unit 233 transmits the clock signal to the clock input terminal of the H_STC counter 242.

The reset receiving unit 235 is an interface for receiving the reset signal transmitted from the reset processing unit 145 of the receiver 10. In this embodiment, the reset receiving unit 235 is specifically connected to the reset processing unit 145 in order to receive the reset signal from the reset processing unit 145. Alternatively, the interrupt connection provided for controlling the communication between the host device 20 and the receiver 10 may be used to receive the reset signal. In an alternative, an element corresponding to the reset processing unit 145 may be provided in the host device 20, and an element corresponding to the reset receiving unit 235 may be provided in the receiver.

The additional information extraction unit 222 extracts additional data from the transmission data stream provided by the packet receiving unit 231. The additional information extraction unit 222 supplies the extracted additional data to the STC correction unit 241. The additional information extraction unit 222 supplies the transmission data stream provided by the packet receiving unit 231 to the PES processing unit 221.

The PES processing unit 221 separates the provided transport data stream into a video packet containing video data, an audio packet containing audio data, and an information packet containing information about data reception and the like. Subsequently, the PES processing unit 221 isolates the information packets containing the content data of each program, such as video information packets and audio information packets, to reconstruct the PES. The PES processing unit 221 provides the reconstructed PES to the video decoder 211 and the audio decoder 212._OPES contains the above timestamp, namely PTS (and DTS)_O The additional information extraction unit 222 and the PES processing unit 221 constitute a data stream decoding part, which is used to decode the data carried in the transmission data stream transmitted from the host interface.

The video decoder 211 extracts the video information packet from the provided PES, and extracts the video information packet from the

200480018523.3 The first video data decodes the video signal, and outputs the decoded video signal to the monitor and other equipment. The audio decoder 212 extracts audio information packets from the provided PES, decodes audio signals from the audio data in the audio information packets, and outputs the decoded audio signals to devices such as speakers. The timing of reproducing and outputting video and audio data is controlled by the above-mentioned PTS (and DTS).

As explained later, the video decoder 211 and the audio decoder 212 receive STC data from the H_STC counter 242 of the host device 20. The system is configured to output video and audio data from the monitor and speaker respectively when the STC data is consistent with the PTS.

The STC correction unit 241 extracts valid flags and difference data from the additional data provided by the additional information extraction unit 222. The STC correction unit 241 receives counter data from the count output terminal of the H_STC counter 242 as the host STC data. In response to receiving the count data, the STC correction unit 241 performs a specific calculation according to the host STC data and the difference data, and sets the calculation result as the correction data. The STC correction unit 241 provides correction data to the load data input terminal of the H_STC counter 242.

The STC correction unit 241 checks the validity of the extracted valid flag. If the difference data is confirmed to be valid through the status of the valid flag, the STC correction unit 241 judges that the frequency deviation of the clock signal has been detected. Next, the STC correction unit 241 outputs the load data to the load data input terminal of the H_STC counter 242, so as to set the correction data provided to the load data input terminal in the H_STC counter 242.

On the other hand, if the difference data is confirmed to be invalid by the status of the valid flag, the STC correction unit 241 judges that the frequency deviation of the clock signal is not detected. Then, the STC correction unit 241 continues to control without detecting the deviation, and does not output load data to the load data input terminal of the H_STC counter 242.

The H_STC counter 242 is a counter for generating a system time clock (STC) in the host device 20. The H_ST counter 242 serves as a host STC counter. The clock signal generated in the clock generating unit 141 of the receiver 10 is transmitted to the clock input terminal (CK) of the H_STC counter 242 through the clock output unit 133 and the clock input unit 233. The H_STC counter 242 performs counting by counting the clock signal. In addition, the H_STC counter 242 outputs count data indicating the number of count clock signals from the count output terminal (OUT) of the H_STC counter 242 as the host STC data, and provides the host STC data to the STC correction unit 241, the video decoder 211, and the audio The decoder 212.

200480018523.3 No.

The H_STC counter 242 has a reset input terminal (R), a load input terminal (L), and a load data input terminal (IN). The H_STC counter 242 notifies the reset signal from the reset receiving unit 235 through the reset input terminal. In response to receiving the reset signal, the H_STC counter 242 sets the count data sent from the count output terminal to an initial value, such as zero.

In response, the load signal is received from the STC correction unit 241 through the input terminal, and the H_STC counter 242 receives correction data from the STC correction unit 241 through the load data input terminal. Next, the H_STC counter 242 sets the count data transmitted from the count output terminal to a value corresponding to the correction data.

Next, the operation of the digital broadcast receiving system having the above arrangement will be explained with reference to FIGS. 5 and 6.

FIG. 5 is an explanatory diagram showing the sequence of how to reset the R_STC counter 142 of the receiver 10 and the H_STC counter 242 of the host device 20. FIG. 6 is an explanatory diagram showing the sequence on how to transfer the decoded transmission data stream from the receiver 10 to the host device 20.

In the digital broadcast receiving system of this embodiment, when the power of the receiver 10 and the host device 20 are turned on, the transmission data stream from the tuner unit 111 is changed, in response to channel switching, or in a similar situation, the execution shown in FIG. 5 is executed. The reset process shown. For example, when switching channels in response to the user's instruction, the host control unit 291 detects the switching and starts the reset process for initialization.

First, the host control unit 291 issues a reset command for resetting the R_STC counter 142 to the command transmission unit 234 (step S100). In response to receiving the reset command, the command transmitting unit 234 transmits the command data indicating the reset command to the command receiving unit 134 (step S102). The command receiving unit 134 analyzes the received command data, and if it determines that the command data includes a reset command, it will The reset signal is transmitted to the reset processing unit 145, thereby resetting the R_STC counter 142 (step S104). The reset processing unit 145 resets the R_STC counter 142 according to the reset signal transmitted from the command receiving unit 134 (step S106). Next, the reset processing unit 145 notifies the reset receiving unit 235 that the R_STC counter 142 has been reset (step S108). For example, the reset notification may be transmitted from the receiver 10 to the host device 20 through the reset signal line. After receiving the reset notification, the reset receiving unit 235 performs reset processing on the H_STC counter 242 (step S110).

In this embodiment, implementing the above reset processing enables the reset processing unit 145 to perform the reset processing in synchronization with the R_STC counter 142 and the H_STC counter 242. Thereby, the R_STC counter 142 and the H_STC counter 242 are initialized so that these counters 142 and 242 continue to calculate the same counter value. Alternatively, the host control unit 291 may use the command transmission unit 234 and the command receiving unit

200480018523.3 The first element 134 notifies the reset processing unit 145 of the reset signal, and resets the H_STC counter 242 at the same time.

As described above, the R_STC counter 142 of the receiver 10 and the H_STC counter 242 of the host device 20 are simultaneously reset when the power of the host device 20 and the receiver 10 are started or when the channel is switched. Therefore, resetting the R_STC counter 142 of the receiver 10 and the H_STC counter 242 of the host device 20 at the same time enables the clock processing section 14 of the receiver 10 and the clock processing section 24 of the host device 20 to start clock processing under the same conditions. In other words, in the digital broadcast receiving system of the present embodiment, the R_STC counter 142 of the receiver 10 and the H_STC counter 242 of the host device 20 are configured to count the same clock signal generated in the clock generating unit 141.

In addition, the R_STC counter 142 and the H_STC counter 242 output the same counter value at the same counting rate because the R_STC counter 142 and the H_STC counter 242 start counting from the same initial value through the reset process. In this way, if abnormalities such as weak radio wave reception conditions are not detected after the host device 20 and the receiver 10 are powered on or after the channel is switched, the R_STC counter 142 and the {LSTC counter 242 continue to count clock signals under the same conditions. Therefore, the digital broadcast receiving system of this embodiment continues to operate normally, such as the transfer of the decoded transmission data stream from the receiver 10 to the host device 20.

FIG. 6 is an explanatory diagram showing the sequence on how to transfer the decoded transmission data stream from the receiver 10 to the host device 20. The packet management unit 124 monitors whether the preparation for packet transfer has been completed, for example, whether a certain number of TS packets have been accumulated in the TS accumulation unit 123. After confirming that the TS packet transfer has been completed, the packet management unit 124 notifies the notification unit 132 of the completion of the packet transfer preparation. Next, the notification unit 132 notifies the host control unit 291 of the completion of the preparation through the notification receiving unit 232 (step S200).

In response to the reception preparation completion notification, the host control unit 291 performs control to receive the TS packet, and issues a TS packet read command to the command transmission unit 234 (step S202). Next, the command transmitting unit 234 transmits the command data indicating the TS packet read command to the command receiving unit 134 (step S204). Subsequently, the command receiving unit 134 analyzes the received command data, and if it determines that the received command data includes TS information The packet read command notifies the packet transfer instruction signal to the packet transfer unit 131, thereby instructing to start transferring the TS packets accumulated in the TS accumulation unit 123 (step S206). Next, the packet transfer unit 131 transfers the TS packets accumulated in the TS accumulation unit 123 to the packet receiving unit 231 (step S208). In this way, the packet including the additional data

200480018523.3 The first decoded transmission data stream is transferred from the receiver 10 to the host device 20.

If abnormalities such as weak radio wave reception conditions occur after the power of the host device 20 and the receiver 10 are turned on or the channel is switched, errors may occur in the decoded transmission data stream. In this case, the value of each data carried in the transmission data stream may deviate from the normal value, and the PCR extraction unit 122 may extract PCR data that exceeds the normal value range. If this happens, the received STC data transmitted from the R_STC counter 142 and the PCR data transmitted from the PCR extraction unit 122 may differ greatly. In other words, the data transmitted from the difference detector 431 of the STC recovery unit 143 may exceed the allowable range of the deviation detector 432, and as a result, the deviation detector 432 outputs a deviation detection signal.

In response to the output of the deviation detection signal from the deviation detector 432, the PCR data transmitted from the PCR extraction unit 122 is set in the R_STC counter 142. As described above, the arrangement of the receiver 10 in this embodiment is advantageous for shortening the time required for unlocking and locking of the clock regeneration loop.

In response to setting PCR data in the R_STC counter 142, the R_STC counter 142 starts to calculate the counter value from the value of the PCR data set. In other words, after the PCR data is set in the R_STC counter 142, the R_STC counter 142 of the receiver 10 and the H_STC counter 242 of the host device 20 continue to count counter values different from each other. Accordingly, it is necessary to synchronize the clock in the clock processing section 14 of the receiver 10 and the clock in the clock processing section 24 of the host device 20 with each other, and restart or restore the clock processing sections 14 and 24 to their normal operations.

To perform the above control, the digital broadcast receiving system of the present embodiment is configured to control the receiver 10 to attach difference data corresponding to the deviation information data to the transmission data stream as additional information, and control the host device 20 to extract the difference data from the additional information and combine The correction is performed so that the counter value in the H_STC counter 242 and the counter value of the R_STC counter 142 are the same or substantially the same as each other when using the extracted difference data.

More specifically, referring to the operation of the receiver 10, if the deviation detector 432 outputs a deviation detection signal, the deviation detection signal and the difference data are transmitted to the additional information attachment unit 144. After receiving the deviation detection signal, the additional information attachment unit 144 will be effective The flag is set to indicate a state where the difference data is valid, and the difference data and the valid flag are provided to the TS accumulation unit 123. The packet management unit 124 checks whether a certain number of TS packets have been accumulated in the TS accumulation unit 123, so as to transfer the TS packets to the host device 20, and if it judges that the preparation for the packet transfer is completed, it then transfers to the packet transfer unit 131 Provide TS information package. At this time, since additional data is also accumulated in the TS accumulation unit 123, the additional data is also provided to the packet transfer unit 131. Therefore, it includes

200480018523.3 A certain number of packets of the first additional data are transferred from the packet transfer unit 131 to the packet receiving unit according to the sequence shown in FIG. 6.

With reference to the operation of the host device 20, a specific number of packets received in the packet receiving unit 231 are supplied to the additional information extraction unit 222 together with additional data. The additional information extraction unit 222 then extracts the additional data from the provided transmission data stream, and The difference data and the valid flag included in the additional data are supplied to the STC correction unit 241. Next, the STC correction unit 241 performs a predetermined calculation based on the difference data transmitted from the additional information extraction unit 222 and the host STC data transmitted from the H_STC counter 242. In addition, the STC correction unit 241 sets the calculation result value in the H_STC counter 242.

For example, suppose that the value of the received STC data and the value of PCR data are "STC1" and "PCR1" respectively when a deviation is detected. Then the difference data value is "(PCR1-STC1)". The "(PCR1-STC1)" value is transferred to the STC correction unit 241 as additional information. The STC correction unit 241 adds the difference data to the host STC data set in the H_STC counter 242. Specifically, if the host STC value set in the H_STC counter 242 is "STC1 + n", the calculation result of the STC correction unit 241 is "STC1 + n + (PCR1-STC1)". Therefore, the STC correction unit 241 sets the counter value "PCR1 + n" in the H_STC counter 242.

On the other hand, the value of the received STC data in the R_STC counter 142 is set to "PCR1 + n" when the STC correction unit 241 corrects the counter value in the set H_STC counter 242. In this way, the counter value in the H_STC counter 242 of the host device 20 is corrected, so that the counter value in the H_STC counter 242 is consistent with the counter value in the R_STC counter 142. This means that the processing of the clock processing section 14 of the receiver 10 is synchronized with the processing of the clock processing section 24 of the host device 20, and the clock processing sections 14 and 24 restart or resume their normal operations.

FIG. 7 is a graph showing how to change the value of the STC data in the R_STC counter 142 and the H_STC counter 242. Figure 7 shows how the value of the STC data in the R_STC counter 142 and the H_STC counter 242 changes over time, where the axis of abscissa represents time, and the axis of ordinate represents the value of STC data in the R.STC counter 142 and H_STC counter 242 .

Referring to FIG. 7, the R_STC counter 142 and the H_STC counter 242 are reset at time T0 according to the sequence shown in FIG. 5. Therefore, the same initial value is set in the R_STC counter 142 and the H_STC counter 242, so that the R_STC counter 142 and the H_STC counter 242 restart their counting operations in synchronization with each other. Next, as shown in FIG. 7, it is assumed that the deviation detector 432

200480018523.3 A synchronization failure in clock regeneration was detected at time T1.

Here, it is assumed that the value of the received STC data and the value of the PCR data are "STC1" and "PCR1" respectively when the deviation is detected. That is, at time Ή, "PCR1" is set as the value of PCR data in the R_STC counter 142. Then, the R_STC counter 142 counts the counter value from "PCR1" starting from time T1. On the other hand, the H_STC counter 242 continues to calculate the value of the counter in the same manner as before the deviation was detected. Accordingly, the difference data "(PCR1 STC1)" is generated in the STC restoring unit 143. Since the difference data is transferred to the STC correction unit 241 through the additional information attachment unit 144, the information packet transfer unit 131, and the information packet reception unit 231, a certain amount of data transfer time is required. Taking this into consideration, the difference data is supplied to the STC correction unit 241 at time T2.

Due to the need for the aforementioned transfer time n, at time T2, the value of the STC data in the R_STC counter 142 is set to "(PCR1 + n)", and the value of the STC data in the H_STC counter 242 is set to "(STC1 +n)" . At this time, the STC correction unit 241 adds the difference data, that is, "(PCR1-STC1)" to the value in the H_STC counter 242. The calculation result is "(PCR1 + η)". In this way, the STC data of the same value as the value set in the R_STC counter 142, that is, "(PCR1 + n)" is set in the H.STC counter 242 by the STC correction unit 241.

In the above example, the case where the difference data representing the value of "(PCR1-STC1)" is transferred from the receiver 10 to the host device 20 as additional information is explained. The invention is not limited to this example. Alternatively, "PCR1" as the value of PCR data and "STC1" as the value of received STC data may be set independently of each other when a deviation is detected.

In the above variation example, the STC correction unit 241 extracts the difference data "PCR1" and "STC1" from the additional data provided by the additional information extraction unit 222. The STC correction unit 241 calculates the "(PCR1-STC1)" value by subtracting the received STC data from the PCR data, and adds the difference data, that is, the "(PCR1-STC1)" value, to the value set in the H_STC counter 242 "( STC1 + η)". Therefore, the STC correction unit 241 sets the addition result "PCR1 + η" in the H_STC counter 242 as correction data.

As another alternative, the difference data value received in the receiver 10 may be "(STC1 PCR1)". In this changed arrangement, the STC correction unit 241 subtracts the difference data from the "(STC1 + η)" value set in the H_STC counter 242, and sets the subtraction result "(PCR1 + η)" as the correction in the H_STC counter 242 data.

In this embodiment, it is explained that the difference data is attached to the transport data stream as additional information.

200480018523.3 The second information, in order to transfer the transmission data stream and additional information. Alternatively, the difference data, that is, the PCR data obtained at the deviation detection time and the received STC data, may be transferred from the notification unit 132 independently of each other. As yet another alternative, an interface dedicated to this type of data transfer can be provided. In short, any arrangement is applicable, as long as the deviation information data of the same value of "PCR1 + n" as the received STC data set in the R_STC counter 142 can be transferred from the receiver 10 to the STC correction unit 241.

Since interfaces such as SD cards use asynchronous communication as described above, the data transfer time η is not constant. However, according to the embodiment of the present invention, the clocks in the receiver and the host device can be synchronized with each other without depending on the data transfer time n. In other words, the present invention can be applied to any arrangement, regardless of whether the interface with the receiver and the host device adopts synchronous or asynchronous communication.

In this embodiment, the additional information attachment unit 144 responds to receiving the deviation detection signal from the deviation detector 432, and sets the valid flag to a state indicating that the difference data is valid, and when there is no deviation detection signal, sets the valid flag to indicate that the difference data is invalid. status. In both cases, the system is configured to generate deviation information data including the difference data, and the deviation information data is transmitted to the host device. However, the present invention is not limited to the above arrangement. As an alternative, the additional information attachment unit 144 may specifically generate deviation information data, in response to receiving the deviation detection signal from the deviation detector 432, and transmit the deviation information data to the host device.

[Embodiment 2] In the first embodiment, the situation described is that the difference data, such as "(PCR-STC)", is transferred from the receiver 10 to the host device as additional information so that the counter values of the receiver and the host device are mutually exclusive Unanimous.

In this embodiment, an arrangement is explained to make the counter values in the counters of the receiver and the host device coincide with each other, even if the difference data is not accurately sent to the transmission line because of a problem with the transmission line used to transmit the transmission data stream signal including the difference data Host device.

FIG. 8 is a block diagram showing the configuration of a digital broadcast receiving device and a host device in a digital broadcast receiving system according to the second embodiment of the present invention. The functional components in FIG. 8 are identified by the same reference numerals as those in FIG. 2 and have the same functions as the components in FIG. 2, therefore, detailed descriptions thereof will be omitted here. The second embodiment shown in FIG. 8 differs from the first embodiment shown in FIG. 2 in the following three functional components, namely, an ID counter 146, a cumulative information storage unit 147, and an ID judgment

200480018523.3 The breaking unit 243.

The ID counter 146 is configured to increment the counter value by one every time the deviation detection signal is transmitted from the STC restoring unit 143 to the additional information attaching unit 144. Specifically, the ID counter 146 is a functional part that counts the number of times when the difference between the STC data and the PCR data exceeds the allowable range. The ID counter functions as a counter part.

Whenever the counter value in the ID counter 146 is incremented by 1, the counter value of the ID counter 146 is recorded in the communication ID included in the additional data. The additional data is transferred from the receiver 10 to the host device 20. The ID judgment unit 243 described later judges whether the host device 20 has securely acquired all difference data, including PCR data, based on the communication ID included in the additional data.

The cumulative information storage unit 147 is configured to cumulatively store the difference data each time the deviation detection signal and the difference data are transferred from the STC restoring unit 143 to the additional information attachment unit 144. For example, suppose that the difference data is "(PCR-STC)" during deviation detection, where PCR represents the PCR data value, and STC represents the received STC data value. Then, the accumulated information attaching unit 147 accumulates and stores the difference data transmitted together with the offset detection signal each time the offset detection signal is notified to the additional information attaching unit 144^u(PCR-STC)".

Therefore, the cumulative information storage unit 147 cumulatively stores the difference data transmitted together with the deviation detection signal each time the deviation detection signal is notified to the additional information attachment unit 144. Hereinafter, the difference data transmitted together with the deviation detection signal when the deviation detection signal is notified to the additional information attaching unit 144 is referred to as the "current value", and the difference data that has been stored in the accumulated information storage unit 147 is referred to as the "cumulative value". ".

The ID judgment unit 243 is a functional part that judges whether the host device 20 has safely acquired all difference data including PCR data. The ID judgment unit 243 functions as a judgment unit. The determination is made based on the communication ID included in the additional data extracted by the additional information extraction unit 222. The number of times when the difference between received STC data and PCR data has exceeded the allowable range is recorded in the communication ID. In other words, the counter value calculated by the ID counter 146 is sequentially recorded in the communication ID.

The ID judging unit 243 compares the communication ID read last time by the ID judging unit 243 with the communication ID currently read by the ID judging unit 243. If the current communication ID and the last communication ID are serial numbers, the ID judgment unit 243 judges that the host device 20 has successfully acquired all the difference data including PCR data. On the other hand, if the current communication ID and the last communication ID are not serial numbers, the ID judgment unit 243 judges that the host device 20 has not acquired all the difference data including PCR data. according to

200480018523.3 The first judgment result judges whether the current value or the accumulated value is used as the difference data included in the additional data.

Specifically, if it is determined that the host device 20 has successfully acquired all the difference data including PCR data, the current value is adopted as the difference data. In this case, the current value is transmitted to the STC correction unit 241 through the additional information extraction unit 222, so that the host STC counter, that is, the counter value in the HJTC counter 242, and the receiving STC counter, that is, the counter value in the R_STC counter 142 are consistent with each other. . On the other hand, if it is judged that the host device has not acquired all the difference data including the PCR data, the failure cannot be compensated for only by using the current value as the difference data and by performing calculation. In the latter case, the accumulated value is used as the difference data, and a specific calculation is performed to make the counter value in the H_STC counter 242 and the counter value in the R_STC counter 142 match.

Next, the flow of a method for setting the same counter value in the R_STC counter 142 and the H_STC counter 242 will be explained with reference to FIG. 8.

First, the tuner unit 111 of the receiver 10 applies processing such as demodulation and error correction to the digital broadcast wave received by the antenna in order to output a demodulated signal. The demodulated signal is sent from the tuner unit 111 to the TS input unit 121. After receiving the demodulated signal from the tuner unit 111, the TS input unit 121 decodes the transmission data stream according to the demodulated signal. The decoded transport data stream is supplied to the PCR extraction unit 122.

The PCR extraction unit 122 detects the PID information of each TS packet carried by the provided transport data stream, and extracts the TS packet containing PCR information based on the PID information. In addition, the PCR extraction unit 122 extracts PCR information from the extracted TS packet, and notifies the STC recovery unit 143 and the R_STC counter 142 of the extracted PCR information as PCR data. In addition, the PCR extraction unit 122 provides the TS accumulation unit 123 with the transport data stream that has been provided by the TS input unit 121.

The clock generation unit 141 receives the difference data from the STC restoration unit 143 and generates a clock signal having a frequency corresponding to the difference data. The clock generation unit 141 transfers the generated clock signal to the R_STC counter 142. In addition, the clock generation unit 141 transmits the generated clock signal to the clock output unit 133, which is a receiving interface for transmitting the clock signal to the host device 20. The clock signal transferred to the clock output unit 133 is transferred to the clock input unit 233, which is a host interface for receiving the clock signal. Subsequently, the clock signal is transferred from the clock input unit 233 to the clock input terminal of the H_STC counter 242.

The R_STC counter 142 receives the clock from the clock generation unit 141 through the clock input terminal (CK)

200480018523.3 No. signal, and count by counting the clock signal. The R. STC counter 142 outputs the count data indicating the clock signal counter value from the count output terminal (OUT) as the received STC data in order to provide the STC recovery unit 143 with the received STC data.

The R_STC counter 142 receives the deviation detection signal from the STC recovery unit 143 through the load input terminal (L). In response to receiving the deviation detection signal, the R_STC counter 142 obtains PCR data from the PCR extraction unit 122 through the load data input terminal (IN). Therefore, the acquired PCR data is set in the R_STC counter 142 so that the PCR data will be output from the count output terminal as count data.

The STC recovery unit 143 obtains the received STC data from the R...STC counter 142, and obtains the PCR data from the PCR extraction unit 122, obtains the difference between the PCR data and the received STC data, and sets the difference as the difference data.

As described above, the clock generation unit 141, the R_STC counter 142, and the STC recovery unit 143 constitute a clock generation loop for generating a clock signal synchronized with the reference clock transmitted from the digital broadcasting station.

As explained with reference to FIG. 3, the STC recovery unit 143 detects synchronization failure or abnormality in clock regeneration based on the difference data. For example, in a case where the difference between the received STC data and the PCR data is set as the difference data, the STC restoration unit 143 monitors whether the difference data is within the allowable range defined by the predetermined upper limit and the predetermined lower limit. If it is detected that the difference data exceeds the allowable range, the STC recovery unit 143 determines that a synchronization failure or abnormality has occurred, and outputs a deviation detection signal to the load input terminal of the R.STC counter 142. The STC restoring unit 143 transmits the deviation detection signal and the difference data to the additional information attaching unit 144 after detecting that the difference data exceeds the allowable range. The STC restoration unit 143 can monitor the absolute value of the difference data, and if the absolute value of the difference data exceeds the allowable upper limit, it outputs a deviation detection signal.

The additional information attaching unit 144 generates additional information for attaching deviation information data (difference data) to the transport data stream decoded by the TS input unit 121. The additional information includes difference data and a valid flag, and the valid flag indicates whether the difference data is valid. The effective mark operation mode is that if the deviation detection signal is notified, the mark is changed to a state that shows that the difference data is valid, and if there is no deviation detection signal, the mark is changed to a state that shows that the difference data is invalid.

The additional information attaching unit 144 performs the following processing based on the deviation detection signal and the difference data transmitted from the STC restoring unit 143. First, in response to receiving the deviation detection signal, the additional information attaching unit 144 controls the ID counter 146 to increment the counter value by one. Next, the additional information attachment unit

200480018523.3 No.

144 records the counter value set in the ID counter value 146 in the additional information.

Now, FIG. 9 shows an example of the communication format for transferring data from the packet transfer unit 131. Referring to FIG. 9, TS1 to TS5 each represent a TS packet decoded by the TS input unit 121. As described above, in the case where the STC restoring unit 143 detects a deviation, the additional information attaching unit 144 attaches the additional information to the transport data stream.

For example, the additional information is configured to write the current value of the difference data in the first footnote, and write the accumulated value of the difference data in the second footnote. The accumulated value of the difference data is the value stored in the accumulated information storage unit 147. The communication ID carrying the counter value in the ID counter 146 is written between the first footnote and the second footnote. The communication ID is updated every time a deviation is detected.

In addition to the difference data, the first footnote and the second footnote each contain at least one valid flag, and the valid flag indicates whether a deviation detection signal has been notified, that is, whether the difference data is valid. The information packet transfer unit 131 transfers the transmission data stream carrying additional data to the host device 20 bit by bit according to the communication format defined above. In addition, the additional information attachment unit 144 provides the difference data to the accumulated information storage unit 147. Since the cumulative information storage unit 147 cumulatively stores the difference data supplied from the additional information attachment unit 144 one by one, the last supplied difference data is cumulatively stored in the cumulative information storage unit 147. For example, suppose that the difference data for the nth deviation detection is "(PCRn-STCn)", where "PCRn" represents the value of PCR data, "STCn" represents the value of the received STC data, and n is an integer representing the number of deviation detections . Then, the accumulated information attaching unit 147 accumulates and stores the difference data "(PCR-STC)" transmitted together with the offset detection signal every time the offset detection signal is notified to the additional information attaching unit 144.

Here, it is assumed that the cumulative value of the difference data stored in the cumulative information storage unit 147 at the time of deviation detection at the (x-1)th time is "SUM", and the difference data notified at the time of deviation detection of the X time is "(PCRx -STCx)", where X is an integer representing the number of deviation detections. In this case, the cumulative information storage unit 147 performs calculation: SUM + (PCRx-STCx), and stores the calculation result therein. In this way, the cumulative information storage unit 147 cumulatively stores the difference data transmitted together with the deviation information signal each time the deviation detection signal is notified to the additional information attachment unit 144. The additional information attaching unit 144 adds the accumulated difference data to the additional information.

The additional information attachment unit 144 provides additional information to the TS accumulation unit 123. The additional information includes the last provided difference data (the current value of the difference data), and an ID representing the number of deviation detection times.

200480018523.3 The counter value in the counter 146 and the cumulative value of the difference data. At this time, the additional information attaching unit 144 notifies the packet management unit 124 that additional information has been provided to the TS accumulation unit 123.

The packet management unit 124 controls the TS accumulation unit 123 so that the additional information supplied from the additional information attachment unit 144 is attached to each TS packet transferred from the PCR extraction unit 122. In response to receiving the control command from the packet management unit 124, the TS accumulation unit 123 stores the additional information provided from the additional information attachment unit 144 together with the TS packet provided from the PCR extraction unit 122.

The packet management unit 124 checks the TS accumulation unit 123 as to whether a certain number of packets to be transferred to the host device 20 have been accumulated in the TS accumulation unit 123. After confirming that the packet transfer preparations have been completed, the packet management unit 124 causes the TS accumulation unit 123 to provide the packet transfer unit 131 with a transport data stream composed of TS packets and additional information. At this time, the packet management unit 124 notifies the notification unit 132 that the packet transfer preparation has been completed.

In response to the reception notification, the notification unit 132 notifies the notification reception unit 232, which is the host interface, that the packet transfer preparation has been completed. Next, the notification receiving unit 232 transfers the notification to the host control unit 291. In response to the notification that the reception packet is ready to be completed, the host control unit 291 issues a TS packet read command to the command transmission unit 234. As a result, the command transmission unit 234 transmits the command data, that is, the TS packet read command, to the command reception unit 134. The command receiving unit 134 analyzes the received command data, and if it determines that the received command data includes a TS read command, it notifies the packet transfer unit 131 of the packet transfer instruction signal. Thus, the packet transfer unit 131 transfers the TS packets accumulated in the TS accumulation unit 123 to the packet receiving unit 231. In this way, the decoded transmission data stream including the additional data is transferred from the receiver 10 to the host device 20 according to the above-mentioned processing procedure. The packet receiving unit 231 supplies the transmission data stream transferred from the packet transfer unit 131 to the additional information extraction unit 222, and the additional information extraction unit 222 sequentially supplies the transmission data stream to the PES processing unit 221.

The PES processing unit 221 separates the provided output data stream into a video packet containing video data, an audio packet containing audio data, and an information packet containing information about data reception and the like. Subsequently, the PES processing unit 221 isolates packets containing content data of each program, such as video packets and audio packets, to reconstruct the PES. The PES processing unit 221 will reconstruct the PES

200480018523.3 is supplied to the video decoder 211 and the audio decoder 212. The additional information extraction unit 222 extracts additional information from the transport data stream provided by the packet receiving unit 231. As shown in FIG. 9, the additional information includes a communication ID carrying the number of deviation detection times, as well as a valid flag, the current value of the difference data, and the cumulative value of the difference data. The additional information extracted by the additional information extraction unit 222 is provided to the ID judgment unit 243, and the ID judgment unit 243 sequentially judges whether the host device 20 has safely acquired all the difference data including PCR data.

The ID judgment unit 243 reads the current counter value in the ID counter 146 by searching for the communication ID included in the additional data extracted by the additional information extraction unit 222. Here, the ID judgment unit 243 compares the counter value read last time by the ID judgment unit 243 with the counter value currently read. If it judges that these counter values are sequence integers, the judgment result indicates that the host device 20 has accurately acquired all the difference data including PCR data. On the other hand, if it judges that the counter value is a non-sequence integer, the judgment result indicates that the host device 20 failed to obtain all difference data including PCR data. Next, it is determined whether to adopt the current value or the accumulated value as the difference data included in the additional data according to the judgment result.

Specifically, it is assumed that the STC recovery unit 143 detects the third synchronization failure or abnormality, that is, deviation. In this case, the counter value in the ID counter 146 is set to "3", and similarly, the value "3" is recorded in the communication ID included in the additional information. In addition, the cumulative information storage unit 147 cumulatively stores the current value of the difference data: "SUM3OPCRC3-STC3)". Here, SUMn=PCRn-STCn, where n is an integer representing the number of deviation detections. The transport data stream carrying the counter value and the difference data is provided to the TS accumulation unit 123₀ Then, the communication ID in the transmission data stream is provided to the ID judgment unit 243 through the packet transfer unit 131, the packet reception unit 231, and the additional information extraction unit 222. The ID judgment unit 243 compares the currently stored value "2" with the value "3" recorded in the communication ID. The comparison results show that these numbers are serial integers. Therefore, the ID judgment unit 243 judges that the host device 20 has safely acquired all the difference data including PCR data, increments the current storage value by 1, thereby setting the value "3", and requests the additional information extraction unit 222 to read and write the additional information. A footnote information.

After receiving the command, the additional information extraction unit 222 provides the STC correction unit 241 with the current value of the difference data written in the first footnote. The STC correction unit 241 extracts the current value of the valid flag and difference data from the provided additional information: "SUM3UPCR3-STC3)".

Therefore, in a similar manner as described in the first embodiment, the H_STC count of the host device 20 is

200480018523.3 The counter value in the first device 242 can be calibrated and consistent with the counter value in the R_STC counter 142 of the receiver 10. Subsequently, it is assumed that the STC restoration unit 143 detects the fourth deviation. In this case, the counter value in the ID counter 146 is incremented to "4" by the additional information attaching unit 144. The value of the communication ID recorded in the additional information is updated to "4" as the counter value increases. At the same time, the cumulative information storage unit 147 cumulatively stores the current value of the difference data: "SUM4UPCR4-STC4)". Next, the transport data stream carrying the counter value and the difference data is supplied to the TS accumulation unit 123. Here, it is assumed that the host device 20 fails to receive the transmission data stream due to the data communication failure between the packet transfer unit 131 and the packet reception unit 231. In this case, the ID judgment unit 243 cannot retrieve the data contained in the transmission data stream. The communication ID, as a result, continues to store the value "3".

Subsequently, it is assumed that the STC restoration unit 143 detects the fifth time deviation. Next, the counter value in the ID counter 146 is incremented to "5" by the additional information attaching unit 144. The value of the communication ID recorded in the additional information is updated to "5" as the counter value increases. At the same time, the cumulative information storage unit 147 cumulatively stores the current value of the difference data: "SUM5UPCR5-STC5)". Next, the transport data stream carrying the counter value and the difference data is provided to the TS accumulation unit 123₀ Then, the communication ID in the transmission data stream is provided to the ID judgment unit 243 through the packet transfer unit 131, the packet reception unit 231, and the additional information extraction unit 222. The ID judgment unit 243 compares the currently stored value "3" with the value "5" set in the communication ID. The comparison results show that these values are not serial integers. Therefore, the ID judging unit 243 judges that the host device 20 has failed to obtain all the difference data including PCR data, increments the current stored value to the currently stored value set in the communication ID, that is, "5", and requests to read the additional information first. A command of the information stored in a footnote is notified to the additional information extraction unit 222. In response to receiving the command, the additional information extraction unit 222 supplies the difference data written in the first footnote to the STC correction unit 24. The STC correction unit 241 extracts the valid flag and the difference data cumulative value from the provided additional information: "SUM1+SUM2+SUM3 +SUM4+SUM5". After that, processing is performed in a similar manner as described in the first embodiment, so that the counter value in the H_STC counter 242 of the host device 20 can be corrected to be consistent with the counter value in the R_STC counter 142 of the receiver 10.

Next, the calibration flow will be explained with reference to FIG. 10. FIG. 10 is a graph showing how the STC data value changes in the R_STC counter 142 and the H_STC counter 242. Figure 10 shows how the STC data values in the R_STC counter 142 and the H_STC counter 242 change over time, where the abscissa axis represents time, and the ordinate axis represents the R_STC counter 142 and H_STC counter

200480018523.3 No.

The value of the STC data in 242.

Referring to FIG. 10, the R_STC counter 142 and the H_STC counter 242 are reset at time T according to the sequence shown in FIG. 5. Therefore, the same initial value is set in the R_STC counter 142 and the H_STC counter 242, so that the R_STC counter 142 and the H_STC counter 242 restart their counting operations in synchronization with each other. Next, as shown in FIG. 10, it is assumed that a synchronization failure in clock regeneration is detected by the deviation detector 432 at time T1.

Here, it is assumed that the received STC data value and PCR data value are "STC1" and "PCR1" respectively when the deviation is detected. That is, at time T1, "PCR1" is set as the PCR data value in the R_STC counter 142. Then, the R_STC counter 142 counts the counter value from "PCR1" starting from time T1. On the other hand, the H_STC counter 242 continues to calculate the counter value in the same manner as before the deviation was detected.

At this time, the difference data generated in the accumulated information storage unit 147 is the current value of the difference data: "SUM1UPCR1-STC1)". Since the difference data is transferred to the STC correction unit 241 through the additional information attachment unit 144, the information packet transfer unit 131, and the information packet reception unit 231, a certain data transfer time and other conditions are required. Taking this into consideration, the difference data is supplied to the STC correction unit 241 at time T2. The data transfer time nl is required for the above reasons. At time T2, the STC data value in the R_STC counter 142 is set to "(PCR1 + nl)", and The STC data value in the H_STC counter 242 is set to "(STC1 + nl)".

In the first embodiment, at time T2, the STC correction unit 241 adds the difference data, that is, "(PCR1-STC1)", to the value in the H_STC counter 242. Therefore, the STC data of the same value as the value set in the R_STC counter 142, that is, "(PCR1 +n)" is set in the H_STC counter 242 by the STC correction unit 241.

However, in the second embodiment, the difference data is not accurately transmitted to the host device 20 at time T2 due to the transmission failure of the transmission line used to transmit the data stream signal including the difference data. That is, the host device 20 failed to obtain the difference data at time T2. However, the H_STC counter 242 and the R_STC counter 142 continue to calculate the same counter value regardless of the transmission failure.

Subsequently, it is assumed that the deviation detector 432 has detected a synchronization failure in clock regeneration at time T3, as shown in FIG. 10.

Here, at time T3, the value of the received STC data is "STC2UPCR1 + nl + t)",

200480018523.3 No.

The value of PCR data is "PCR2". In other words, "PCR2" as the value of PCR data at the deviation detection time is set in the R.STC counter 142. Therefore, the R_STC counter 142 starts counting from "PCR2" at time T3, and the H_STC counter 242 continues to count as before.

At this time, the difference data generated in the cumulative information storage unit 147 is the cumulative value of the difference data: "SUM1+SUM2 UPCR1-STC1 + PCR2-STC2)". The difference data is supplied to the STC correction unit 241 at time T4. In addition, since a specific data transfer time n2 is required, the STC data values in the R_STC counter 142 and the H_STC counter 242 are set to "(PCR2 + .n2)" and "(STC1 + n1 + t + n2)" at time T4, respectively.

If the STC correction unit 241 adds the above-mentioned difference data to the value of the STC data in the H_STC counter 242, because "STC2" is equal to "(PCR1 + nl + t)", the addition result is "(PCR2 + n2)". Therefore, the STC data value set in the H_STC counter 242 is consistent with the R_STC counter 142.

As described above, in the second embodiment, the cumulative value of the difference data generated in the cumulative information storage unit 147 can be used to make the counter values in the R_STC counter 142 and the H_STC counter 242 consistent with each other, even if the host device 20 fails to acquire all Difference data.

As described above, since the counter values in the receiver 10 and the host device 20 coincide with each other, the video and audio data can be played safely. Specifically, the video decoder 211 extracts a video packet from the provided PES, decodes the video signal according to the video data in the video packet, and outputs the decoded video signal to a monitor or other equipment. Similarly, the audio decoder 212 extracts audio information packets from the provided PES, decodes audio signals according to the audio data in the audio information packets, and outputs the decoded audio signals to devices such as speakers.

In this embodiment, it is explained that the accumulated value "(PCR-STC)" of the difference data is transferred from the receiver 10 to the host device 20 as additional information. The present invention is not limited to the above configuration. As an alternative, the accumulated value of PCR data obtained at the deviation detection time and the accumulated value of received STC data may be transferred. As another alternative, the STC correction unit 241 may use the accumulated value "(STC-PCR)" of the difference data to perform the subtraction.

In this embodiment, it is explained that the difference data is attached to the transmission data stream as additional information in order to transfer the transmission data stream and the additional information. The present invention is not limited to the above configuration. Alternatively, the difference data, that is, the PCR data obtained at the deviation detection time and the received STC data, may be transferred from the notification unit 132 independently of each other. Another alternative is to provide dedicated data for this type of

200480018523.3 Data transfer interface. In short, any configuration can be applied, as long as the deviation information data of the same value as the value of the received STC data set in the R_STC counter 142 can be transferred from the receiver 10 to the STC correction unit 241.

[Embodiment 3] In the above embodiment, the receiver 10 and the host device 20 are configured such that each element or block (functional component) having a certain function in the receiver 10 and the host device 20 can be constituted by a single semiconductor integrated circuit . As yet another alternative, some components may constitute a single semiconductor integrated circuit. For example, the semiconductor integrated circuit may be a large-scale integrated circuit (LSI). In the first or second embodiment, some elements constituting the host device 20 may constitute functional blocks. For example, the host device 20 can be classified into the following four functional blocks. The first functional block is a counter correction block, which is composed of an additional information extraction unit 222, an STC correction unit 241, and an H_STC counter 242. The second functional block is the control block, which is composed of the host control unit 291. The third functional block is an interface block, which is composed of a packet receiving unit 231, a notification receiving unit 232, a clock input unit 233, a command transmission unit 234, and a reset receiving unit 235. The fourth functional block is a decoder block, which is composed of a video decoder 211, an audio decoder 212, and a PES processing unit 221.

Fig. 11 is a block diagram exemplarily showing the entire configuration of the digital broadcast receiving system according to the third embodiment of the present invention. The configuration shown in FIG. 11 is substantially the same as that shown in FIG. 2 showing the receiver 10 and the host device 20, except that in the host device 20 in the third embodiment, it is suggested that some elements or functional parts constituting a single semiconductor integrated circuit are surrounded by rectangular dashed squares. outer.

In the example of FIG. 11, the semiconductor integrated circuit is composed of a counter correction block in the host device 20, that is, an additional information extraction unit 222, an STC correction unit 241, and an H_STC counter 242.

The semiconductor integrated circuit with the above configuration plays an important role in the host device 20 for synchronizing the clocks in the receiver 10 and the host device 20, as described in the first or second embodiment. Specifically, the additional information extraction unit 222 in the semiconductor integrated circuit extracts the valid flag and difference data from the receiver 10 to be transmitted to the STC correction unit 241. If it judges that the received valid flag indicates that the difference data is valid, the STC correction unit 241 performs calculations based on the difference data and the host STC data. Next, the STC correction unit 241 sets the calculation result in the H_STC counter 242 as correction data. Therefore, in this embodiment, the clock can be executed between the receiver 10 and the host device 20.

200480018523.3 No. synchronization.

As a modified configuration, as shown in FIG. 12, the semiconductor integrated circuit may be constituted by a function block corresponding to the counter correction block shown in FIG. 11 and a control block constituted by the host control unit 291. This change configuration allows the host control unit 291 to transmit command data, such as a reset command, or to control various components or functional components, so that the semiconductor integrated circuit can be used as an active circuit for controlling various components or functional components.

As in Fig. 12, it is recommended that the components constituting the semiconductor integrated circuit be surrounded by the rectangular dashed squares in Fig. 13 (Fig. 14 and Fig. 15).

Specifically, as another modified configuration with reference to FIG. 13, the semiconductor integrated circuit may be composed of elements corresponding to the core components (counter correction block) surrounded by the rectangular dotted square in FIG. 11, the packet receiving unit 231, the notification receiving unit 232, The clock input unit 233 and the command transmission unit 234 are constituted. In other words, the core components, the control block, and the interface block serving as an interface to the receiver 10 constitute a semiconductor integrated circuit. This configuration does not need to provide an additional interface outside the semiconductor integrated circuit.

As another configuration, referring to FIG. 14, the semiconductor integrated circuit may be composed of an element corresponding to the element surrounded by a rectangular dashed square in FIG. 13 and the reset receiving unit 235.

As another configuration, referring to FIG. 15, the semiconductor integrated circuit may be composed of elements corresponding to the elements surrounded by the rectangular dotted square in FIG. 14, the PES processing unit 221, the video decoder 211, and the audio decoder 212. In other words, the core components, control block, interface block, and decoder block constitute the semiconductor integrated circuit in FIG. 15. This configuration does not need to provide an additional decoder outside the semiconductor integrated circuit.

As mentioned above, combining several components (functional parts) into one functional block and fabricating the one or more functional blocks into a single semiconductor integrated circuit can reduce the block size and achieve high-speed processing. In addition, compared with the case where each element (functional component) is composed of a single semiconductor integrated circuit, there is no connection failure or less connection failure, and no adjustment between the elements is required. Therefore, the use of the semiconductor integrated circuit constructed as above can provide the host device with stable operation and the clock synchronization function of the present invention.

In addition, by excluding the control block constituted by the host control unit 291 from the functional blocks constituting the semiconductor integrated circuit shown in FIGS. 13, 14, and 15, it becomes possible to manufacture passive circuits.

The components or functional parts to be incorporated into the semiconductor integrated circuit are just some examples. Applicable

200480018523.3 Incorporate functional components other than the above functional components or exclude the configuration of some of the above functional components. As yet another alternative, in the same way as in the host device, some elements (functional parts) constituting the receiver in the present invention may be combined into a single semiconductor integrated circuit.

As described above, according to the digital broadcast receiving system of the present invention, if abnormalities such as weak radio wave reception conditions occur, first set the extracted PCR data in the R_STC counter 142 as the receiving STC counter. Transfer the deviation information data including PCR data to the host device 20_oThe STC correction unit 241 corrects the counter value in the H_STC counter 242 as the host STC counter so that the counter value in the H_STC counter 242 is consistent with the counter value in the R_STC counter 142. Therefore, in the digital broadcast receiving system of the present invention, clock synchronization can be restored (restarted) at high speed while decoding video and audio data with high precision.

Specifically, in the digital broadcast receiving system of the present invention, the host device 20 is configured to perform each digital processing using a clock signal that has been resynchronized in the receiver 10, thereby sharing the same clock in the receiver 10 and the host device 20 signal. This configuration does not require clock regeneration in the host device 20, and can quickly use the clock signal that has been resynchronized in the receiver 10. In addition, since there is no need to provide a clock generating unit in the host device 20, this configuration helps reduce the number of components, reduce power consumption, and reduce the size of the host device 20. Therefore, the present invention facilitates the establishment of a digital broadcast receiving system using portable components such as mobile devices.

FIG. 16 is an explanatory diagram implementing a digital broadcast receiving system using a receiver 10 (special memory card) detachably connected to a host device 20 (moving object). 16, the special memory card 310 corresponding to the receiver 10 is inserted into the memory card mounting part 330 of the mobile phone serving as the host device 20 through the interface to the special memory card 310.

16, the host device 20 is composed of a phone body 320, a key input portion 322 that allows the user to perform input operations (such as entering a phone number and names of various operations), a display portion 321 for displaying information about communication, etc., An antenna 323 for transmitting/receiving data and various processing circuits (not shown) provided in the phone body 320 are constituted. The processing circuit has various functions of the host device 20 described with reference to FIG. 2.

The mounting part 330 for receiving the special memory card 310 (having a function of receiving digital broadcasting) is formed on the upper part of the phone body 320. The special memory card 310 has a card body 311, which has the function of the receiver 10 described with reference to FIG. 2, and an antenna 312 for transmitting/receiving digital broadcasting. Specifically, the special memory card 310 is an electronic card that has the ability to decode received digital broadcast waves and

200480018523.3 The function of transmitting the decoded signal as a data stream signal in the form of the first number of information packets.

The mounting part 330 is adapted to implement the signal or data connection represented by the digital interface 30 (see Figure Do, specifically, the receiver 10 and the host device 20 pass through the I/F part 13 of the receiver 10 and the I/F part of the host device 20). The F part 23 is interconnected with each other through the digital interface 30. The receiver 10 and the host device 20 are interconnected with each other through the digital interface 30 so that the receiver 10 can transmit to the host device 20 the transport data stream decoded in the TS receiving part 12, The clock signal generated in the clock generating unit 141 and the deviation information data stored in the additional information attaching unit 144 serving as a deviation processor.

The electronic card represented by the special memory card 310 may be an SD card, which has the function of decoding the received digital broadcast wave and transmitting the decoded signal in the form of a certain number of information packets as a data stream signal. The data stream signal, clock signal, and deviation information data to be transmitted from the SD card can be sent through a data line defined according to the SD card specifications or through a data line and a command line.

The use of data lines defined in accordance with the SD card specifications facilitates effective use of mature copyright protection functions and the inherent high-speed information communication functions of SD cards.

With the above configuration, when the user, for example, inserts the special memory card 310 having the function of the receiver 10 into the mounting part 330, the user can use the phone body 320 in a manner that combines the functions of the mobile phone and the receiver 10. In other words, by inserting the special memory card 310 having the function of the receiver 10 into the mounting portion 330 of the phone body 320, the digital broadcasting program that has been received in the special memory card 310 can be displayed on the display portion 321.

In this way, when the user of the host device 20 wishes to watch the digital broadcast, the user can watch the digital broadcast by connecting the digital broadcast receivable special memory card 310 in the mounting portion 330 of the phone body 320. On the other hand, when the user does not want to watch digital broadcasting, the user can use the phone body 320 as a normal mobile phone by detaching the special memory card 310 from the mounting part 330. Alternatively, the phone body 320 may be used as a normal mobile phone with a special memory card 310 inserted into the phone body 320 mounting portion 330. Needless to say, a memory card such as a general-purpose SD card can be installed in place of the special memory card 310, so that the phone body 320 can be used in a combination of mobile phone functions and memory card functions. Referring to FIG. 16, it is explained that the host device is a mobile phone. Case. Alternatively, the host device may be a mobile device other than a mobile phone, such as a PDA, digital camera, or navigation system. As yet another alternative, the present invention can be applied to non-mobile devices such as set-top boxes.

200480018523.3 Section [Modifications and Changes] In the first and second embodiments, the system is configured such that the host control unit 291 detects channel switching in response to the user's designation, and performs reset processing for initialization. The present invention is not limited to the above configuration. The system can be configured such that the signal indicating the deviation detection in the receiver 10 can be sent to the host control unit 291 of the host device 20 through a transmission line different from the transmission line used to transmit the transmission data stream. In the above change configuration, if the STC recovery unit 143 detects When there is an abnormality such as a synchronization failure, the STC recovery unit 143 notifies the additional information attachment unit 144 of the deviation detection signal. Next, the additional information attaching unit 144 notifies the notification unit 132 of the detection result on whether the additional information attaching unit 144 has received the deviation detection signal through the information packet management unit 124. In response to the reception notification, the notification unit 132 as the reception interface transmits a notification to the notification reception unit 232 as the host interface. Then, the notification receiving unit 232 transfers the notification to the host control unit 291.

The host control unit 291 then analyzes the detection result on whether the deviation detection signal has been detected, and if it judges that the deviation detection signal has been detected, it issues a reset command to the command transmission unit 234. Thus, the command transmission unit 234 transmits the command data, that is, the reset command, to the command reception unit 134. The command receiving unit 134 then analyzes the received command data, and if it determines that the command data includes a reset command, it notifies the reset processing unit 145 of the reset signal. In response to receiving the notification, the reset processing unit 145 resets the R_STC counter 142.

Subsequently, the reset processing unit 145 notifies the reset receiving unit 235 of the reset of the R_STC counter 142. For example, the notification may be transmitted from the receiver 10 to the host device via the reset signal line

20. In response to receiving the notification that the R_STC counter 142 has been reset, the reset receiving unit 235 performs resetting of the H_STC counter 242. Thus, the counter values in the R_STC counter 142 of the receiver 10 and the H_STC counter 242 of the host device 20 are substantially simultaneously set to the initial value, for example, zero.

In the above embodiment, it is described that the receiver 10 transmits to the host device 20 a transport data stream that has been decoded in the receiver 10, and additional information is attached. The present invention is not limited to the above configuration. A data stream signal in a PES format or a segmented format that has been reproduced from the decoded transport data stream signal can be sent together with the additional information.

In the above embodiments, it is explained that the present invention is applied to the MPEG2 system in digital broadcasting.

200480018523.3 The first situation. The present invention is not limited to the above configuration, and can be applied to general digital communication systems, including systems that distribute and receive digital content through a network.

[Simple Description of Embodiments] The following is a brief description of embodiments of the present invention.

(1) A digital signal receiving system, including: a digital signal receiving device for receiving digital communication signals, having the function of generating a clock signal based on PCR data included in the communication signal, and sending a data stream in the form of multiple information packets The function of signal and clock signal, data stream signal includes communication signal; and host device, used to receive data stream signal and clock signal from digital signal receiving device through the interface part, digital signal receiving device includes: receiving STC counter, used to calculate clock The number of signal clocks and output the counter value as the received STC data; a deviation detector to calculate the difference between the received STC data and the PCR data as the difference data, and detect the frequency deviation of the clock signal exceeding a predetermined value based on the difference data; and The deviation processor is used to transmit the deviation information data obtained according to the received STC data and PCR data to the host device. If the deviation detector detects a frequency deviation exceeding a predetermined value, the PCR data is set in the receiving STC counter. The host device includes : The host STC counter is used to count the clock number of the clock signal transmitted from the digital signal receiving device, and output the counter value as the host STC data; STC correction unit, if the deviation detector detects a frequency deviation exceeding a predetermined value, it will be based on the host STC data and deviation information data calculate the correction data, and set the correction data in the host STC counter to Then the counter value set in the receiving STC counter is consistent with the counter value set in the host STC counter.

In the above configuration, if abnormalities such as weak radio wave reception conditions occur, the digital signal receiving device sets the extracted PCR data in the receiving STC counter. After the PCR data is set in the receiving STC counter, the receiving STC counter continues to count from the value of the PCR data, and the digital signal receiving device transfers the deviation information data obtained according to the received STC data and the PCR data to the host device. The host STC counter continues to count the number of clocks of the clock signal transmitted from the digital signal receiving device, and the digital signal receiving device performs the above operations. Therefore, the difference in the counter value between the reception STC counter and the host STC counter becomes constant regardless of the elapse of time. In other words, the difference in the counter value does not depend on the transfer time of the deviation information data transmitted from the digital signal receiving device to the host device.

200480018523.3 No.

The STC correction unit uses the deviation information data to correct the counter value in the STC counter of the host, so that the counter value set in the STC counter of the host is consistent with the counter value set in the receiving STC counter. This ensures that the clock between the digital signal receiving device and the host device is resynchronized.

In addition, since the digital signal receiving device and the host device use the same clock signal, there is no need to provide a clock generation function in the host device, which helps reduce power consumption and reduce the size of the digital signal receiving system.

(2) The digital signal receiving system is a digital signal receiving system (1), in which the deviation information data is the value accumulated since the first deviation is detected. The digital signal receiving device also includes a counter part, which starts from the first deviation detection Count the number of deviation detections, and the host device also includes a judging unit, which accumulates and stores the number of deviation detections transmitted one by one from the digital signal receiving device, and compares the stored deviation detection storage times with the latest deviation detection transmitted from the digital signal receiving device The number of times, if the stored deviation detection times and the last times of deviation detection are not serial integers, the deviation information data is set as the correction data.

In the above configuration, if abnormalities such as weak radio wave reception conditions occur, the digital signal receiving device sets the extracted PCR data in the reception STC counter. After the PCR data is set in the receiving STC counter, the receiving STC counter continues to count from the value of the PCR data, and the digital signal receiving device transfers the deviation information data obtained according to the received STC data and the PCR data to the host device. The deviation information data is a value accumulated since the deviation was first detected. The host STC counter continues to count the number of clocks of the clock signal transmitted from the digital signal receiving device, and the digital signal receiving device performs the above operations.

With the above configuration, even if the difference data is not accurately sent to the host device due to problems related to the transmission line used to transmit the transmission data stream signal carrying the difference data, the STC correction unit can use the deviation information data to correct the counter in the host STC counter Value so that the counter value set in the host STC counter is consistent with the counter value set in the receiving STC counter, because the deviation information data is the accumulated value since the deviation is first detected. Therefore, this configuration can safely resynchronize the clocks in the digital signal receiving device and the host device.

(3) The digital signal receiving system is a digital signal receiving system (1) or (2), in which the STC correction unit calculates the difference between the PCR data and the received STC data, performs predetermined calculations based on the difference data and the host STC data, and sets the host STC The calculation result in the counter is set as the correction data, PCR

200480018523.3 The first data and the received STC data are provided as deviation information data.

In the above configuration, the receiving device independently provides PCR data and STC data as deviation information data to the host device, the PCR data is clock information related to the transmitter of the digital signal, and the STC data is the clock signal related to the receiving device. The STC correction unit of the host device calculates the difference between the PCR data and the received STC data, generates correction data for synchronizing the clocks in the receiving device and the host device according to the difference, and sets the correction data in the host STC counter. Thereby, the counter value in the host STC counter and the counter value in the receiving STC counter can be consistent with each other. In addition, since the STC correction unit performs calculations required for clock synchronization, this configuration makes it easy to change or expand functions.

(4) The digital signal receiving system is a digital signal receiving system (3), in which the STC correction unit calculates the difference by subtracting the received STC data from the PCR data, performs the calculation by adding the difference to the host STC data, and sets the host STC counter The calculation result in is set as correction data, PCR data and received STC data are provided as deviation information data.

In the above configuration, the receiving device provides PCR data as clock information related to the transmitter of the digital signal and received STC data as the clock signal related to the receiving device to the host device independently of each other as deviation information data. The STC correction unit of the host device calculates the difference by subtracting the received STC data from the PCR data, and adds the difference to the host STC data. Since the STC data value is used in both the receiving device and the host device, this configuration can set the same counter value in the host STC counter as the receiving STC counter.

(5) The digital signal receiving system is a digital signal receiving system (1) or (2), in which the STC correction unit obtains the difference between the PCR data and the received STC data, performs predetermined calculations based on the difference data and the host STC data, and sets the host STC The calculation result in the counter is set as the correction data, and the difference between the PCR data and the received STC data is supplied as the deviation information data.

In the above configuration, the receiving device calculates the difference between PCR data as the clock information related to the transmitter of the digital signal and the received STC data as the clock signal related to the receiving device, and provides the difference to the host device as Deviation information data. This configuration helps to reduce the amount of deviation information data. The STC correction unit performs a predetermined calculation according to the difference and the host STC data, generates correction data for synchronizing the clocks in the receiving device and the host device, and sets the correction data in the host STC counter. This configuration can set the same count value in the host STC counter as in the receiving STC counter.

200480018523.3 Article (6) The digital signal receiving system is a digital signal receiving system (5), in which the STC correction unit obtains the difference by subtracting the received STC data from the PCR data, and performs the calculation by adding the difference to the host STC data, and the host STC The calculation result in the counter is set as the correction data, and the difference of the received STC data by subtracting the PCR data is provided as the deviation information data.

In the above configuration, the receiving device calculates the difference by subtracting the received STC data as the clock signal related to the receiving device from PCR data that is the clock information related to the transmitter of the digital signal, and provides the difference as the deviation information data to the host equipment. This configuration helps to reduce the amount of deviation information data. The STC correction unit adds the difference as deviation information data to the host STC data. Since the value of STC data is used in both the receiving device and the host device, this configuration can set the same counter value in the host STC counter as the receiving STC counter.

(7) The digital signal receiving system is any one of the digital signal receiving systems (3) to (6), in which the deviation information data is sent from the digital signal receiving device to the host device through the interface part, and at the same time attached to the data stream signal.

In the above configuration, there is no need to provide an additional transmission line for transmitting deviation information data from the receiving device to the host device. In addition, the communication signal and the deviation information data are included in the signal data stream signal. Compared with the case where the communication signal and the deviation information data are transmitted separately, the correlation between the communication signal and the deviation information data is ensured. This configuration can accurately reproduce video and audio data based on, for example, a decoded data stream signal.

(8) The digital signal receiving system is a digital signal receiving system (7), in which the deviation detector detects the frequency deviation of the clock signal based on the difference data.

The above configuration can use the circuit used in the ordinary MPEG2 system, and is designed to synchronize the clock based on the difference between PCR data as the clock information related to the transmitter of the digital signal and the STC data as the clock signal related to the receiving device, This contributes to the simplification of the circuit structure.

(9) The digital signal receiving system is a digital signal receiving system (8) in which if the difference data exceeds the range defined by a predetermined lower limit and a predetermined upper limit, the deviation detector outputs a deviation detection signal indicating deviation detection in the frequency of the clock signal.

In the above configuration, since the lower limit and the upper limit can be selectively set, the deviation can be effectively detected by correctly setting the allowable range. In addition, the above configuration makes it easy to determine where the value of the difference data is within the allowable range. This contributes to the simplification of the circuit structure.

(10) The digital signal receiving system is a digital signal receiving system (9), in which the digital signal receiving

200480018523.3 The first device also includes an additional information attachment unit. The additional information attachment unit sets a flag indicating whether the deviation information data is valid, and attaches additional information including the flag and deviation information data to the data stream signal.

In the above configuration, the additional information attaching unit is configured to include information on whether the additional information is valid in the data stream signal according to the deviation information, not to mention attach the additional information to the data stream signal. This configuration clarifies the criteria for determining the validity of the additional information by the host device, which helps suppress error handling.

(Π) The digital signal receiving system is a digital signal receiving system (10), in which the host device also includes an additional information extraction unit, and the additional information extraction unit extracts additional information attached to the data stream signal, and extracts the deviation information data from the additional information Provided to the STC correction unit, the data stream signal is transmitted from the digital signal receiving device to the host device through the interface part.

In the above configuration, the additional information extraction unit can isolate the communication signal when extracting the additional information from the data stream signal. This configuration can transmit additional information required for clock synchronization and data required for communication and playback to each functional unit independently of each other.

(12) The digital signal receiving system is a digital signal receiving system (11), in which the digital signal receiving device also includes a command receiving unit, and the command receiving unit receives command data from the host device for controlling each process in the digital signal receiving device, and notification Unit, the notification unit notifies the host device of the information transmitted from the digital signal receiving device, and the host device also includes a command transmission unit, which transmits to the digital signal receiving device command data for controlling each process in the digital signal receiving device, and notification The receiving unit informs the receiving unit to receive the information transmitted from the digital signal receiving device.

The above configuration enables the host device to transmit command data for controlling each process in the digital signal receiving device, such as a reset command, to the digital signal receiving device through the command transmitting unit and the command receiving unit. In addition, this configuration enables the receiving device to transmit information to the host device through the notification unit and the notification receiving unit, such as a notification that the packet transfer preparation has been completed.

(13) The digital signal receiving system is a digital signal receiving system (12), in which the digital signal receiving device also includes a reset processing unit, and the reset processing unit resets the receiving STC counter to a predetermined initial state in response to the reception by the command receiving unit A reset signal transmitted from the host device, and a reset signal indicating reset is output to the host device. The host device further includes a reset receiving unit. The reset receiving unit resets the host STC counter according to the reset signal transmitted from the reset processing unit. Reset to pre

200480018523.3 The initial state is determined.

In the above configuration, the reset processing unit sets an initial value, such as zero, in the receiving STC counter in response to receiving the reset signal from the host device. Subsequently, the reset processing unit transmits the reset signal to the reset receiving unit, and the reset receiving unit sets the same value in the host STC counter as the receiving STC counter, that is, the initial value, such as zero. Thus, an initial value, such as zero, is set in the receiving STC counter and the host STC counter at the same time. This configuration can effectively perform clock synchronization in each counter after the counter enters its initial state.

(14) The digital signal receiving system is any one of the digital signal receiving systems (1) to (13), in which the digital signal receiving device and the host device are interconnected with each other through a digital interface.

Since the above configuration can transmit a data stream signal from the receiving device to the host device without signal compression, and is in a digital format, signal degradation can be suppressed.

(15) The digital signal receiving system is a digital signal receiving system (14), in which at least data stream signals, clock signals and deviation information data are sent through a digital interface.

In the above configuration, clock synchronization is established between the receiving device and the host device through a clock signal. If it is detected that there is a deviation in the frequency of the clock signal in the receiving device, the clock is resynchronized according to the deviation information data. As a result, the playback of the data stream signal is restored to normal operation.

(16) The digital signal receiving system is any one of the digital signal receiving systems (1) to (15), in which the digital signal receiving device is formed as an electronic card.

In the above configuration, an electronic card equipped with a digital signal receiving function is installed in the host device so that the host device can receive digital signals. In addition, this configuration can flexibly deal with changes in various specifications or standards and version updates on digital communications by exchanging electronic cards without changing the host device.

(17) The digital signal receiving system is a digital signal receiving system (16), in which the electronic card is configured as an SD card.

The above configuration can establish a small digital signal receiving system with large capacity, improved reliability in information protection functions, and use of the inherent functions of the SD card.

(18) The digital signal receiving system is a digital signal receiving system (17) in which at least a data stream signal, a clock signal, and deviation information data are sent from an SD card as a digital signal receiving device through a data line defined in accordance with the SD card specification.

The above configuration can establish a digital signal receiving system with mature copyright protection function and SD card inherent high-speed information communication function.

200480018523.3 Article (19) A digital signal receiving device suitable for receiving digital communication signals, having the function of generating a clock signal based on PCR data included in the communication signal, and having the function of sending data stream signals and clock signals in the form of multiple information packets, The data stream signal includes a communication signal. The digital signal receiving device is configured to establish a digital signal receiving system by interconnecting via the host device interface part. The host device is suitable for receiving the data stream signal and clock signal from the digital signal receiving device via the interface part. Digital signal The receiving device includes: receiving STC counter, used to calculate the number of clocks of the clock signal and outputting the counter value as received STC data; deviation detector, used to calculate the difference between the received STC data and PCR data as the difference data, and detect according to the difference data The deviation in the frequency of the clock signal exceeding a predetermined value; and a deviation processor for transmitting deviation information data obtained based on the received STC data and PCR data to the host device. If the deviation detector detects a frequency deviation exceeding the predetermined value, then Set PCR data in the receiving STC counter.

In the above configuration, if an abnormality such as a weak radio wave reception condition occurs, the digital signal receiving device is operated to set the extracted PCR data in the reception STC counter. The digital signal receiving device transfers the deviation information data to the host device. Thus, the host device is operated to use the deviation information data to correct and set the same counter value in the host STC counter as in the receiving STC counter.

(20) The digital signal receiving device is a digital signal receiving device (19), in which the deviation information data includes receiving STC data and PCR data.

In the above configuration, the receiving device provides PCR data as clock information related to the transmitter of the digital signal and STC data as the clock signal related to the receiving device to the host device independently of each other as deviation information data. In other words, since the clock synchronization calculation using these data is implemented in the host device, the receiving device can be used with various types of host devices.

(21) The digital signal receiving device is a digital signal receiving device (19), in which the deviation information data includes the difference between the PCR data and the received STC data.

In the above configuration, the receiving device calculates PCR data as clock information related to the transmitter of the digital signal, and reception STC data as the clock signal related to the receiving device, and provides the difference to the host device as deviation information data. This configuration helps to reduce the amount of deviation information data.

(22) The digital signal receiving device is a digital signal receiving device (20) or (21).

200480018523.3 The first part of the mouth sends the deviation information data from the digital signal receiving device to the host device, and at the same time attaches to the data stream signal.

In the above configuration, there is no need to provide an additional transmission line for transmitting deviation information data from the receiving device to the host device. In addition, the communication signal and the deviation information data are included in the signal data stream signal. Compared with the case where the communication signal and the deviation information data are transmitted separately, the correlation between the communication signal and the deviation information data is ensured. This configuration can accurately reproduce video and audio data based on, for example, a decoded data stream signal.

(23) The digital signal receiving device is a digital signal receiving device (22), in which the deviation detector detects the frequency deviation of the clock signal based on the difference data.

The above configuration can use the circuit used in the ordinary MPEG2 system, and is designed to synchronize the clock based on the difference between PCR data as the clock information related to the transmitter of the digital signal and the STC data as the clock signal related to the receiving device, This contributes to the simplification of the circuit structure.

(24) The digital signal receiving device is a digital signal receiving device (23), wherein if the difference data exceeds the range defined by the predetermined lower limit and the predetermined upper limit, the deviation detector outputs a deviation detection signal indicating the frequency deviation detection of the clock signal.

In the above configuration, since the lower limit and the upper limit can be selectively set, the deviation can be effectively detected by correctly setting the allowable range. In addition, the above configuration makes it easy to determine where the value of the difference data is within the allowable range. This contributes to the simplification of the circuit structure.

(25) The digital signal receiving device is a digital signal receiving device (23), in which if the absolute value of the difference data exceeds a predetermined upper limit, the deviation detector outputs a deviation detection signal indicating frequency deviation detection of the clock signal.

In the above configuration, since the upper limit is selectively set, the deviation can be effectively detected by appropriately setting the upper limit. In addition, since only the absolute value of the difference data is monitored, this configuration contributes to the simplification of the circuit structure.

(26) The digital signal receiving device is a digital signal receiving device (24) or (25), which further includes an additional information attachment unit for setting a flag indicating whether the deviation information data is valid, and will include additional information including the flag and the deviation information data The information is attached to the data stream signal.

In the above configuration, the additional information attaching unit is configured to include information on whether the additional information is valid in the data stream signal according to the deviation information, not to mention attach the additional information to the data stream signal. This configuration makes it clear about the criteria for the host device to determine the validity of the additional information,

200480018523.3 This helps suppress error handling.

(27) The digital signal receiving device is a digital signal receiving device (26), and further includes a command receiving unit for receiving command data from the host device for controlling each process in the digital signal receiving device, and a notification unit for receiving The information transmitted by the digital signal receiving device is notified to the host device.

In the above configuration, the command receiving unit and the notification unit are used as part of the receiving interface. This configuration can effectively send command data from the host device to the receiving device, and send information from the receiving device to the host device.

(28) The digital signal receiving device is a digital signal receiving device (27), and further includes a reset processing unit for resetting the receiving STC counter to a predetermined initial state, and outputting a reset signal indicating reset to the host device.

In the above configuration, the operation receiving device outputs a reset signal to the host device while resetting the receiving STC counter. This configuration enables the host device to reset the host STC counter synchronously with the receiving STC counter. As a result, an initial value, such as zero, can be set in the receiving STC counter and the host STC counter at the same time.

(29) The digital signal receiving device is a digital signal receiving device (28), in which the digital signal receiving device can be connected to the host device through a digital interface by sending at least the data stream signal, clock signal and deviation from the digital signal receiving device through the digital interface Information data to the host device.

In the above configuration, since the data stream signal can be sent from the receiving device to the host device without signal compression and in a digital format, signal degradation can be suppressed. In addition, a clock signal is used to establish clock synchronization between the receiving device and the host device. If the deviation of the clock signal frequency in the receiving device is detected, the clock resynchronization is implemented according to the deviation information data. As a result, the playback of the data stream signal is restored to normal operation.

(30) The digital signal receiving device is any one of the digital signal receiving devices (19) to (29), wherein the digital signal receiving device is formed as an electronic card.

In the above configuration, since the receiving device includes an electronic card equipped with a digital signal receiving function, the digital signal can be received by installing the electronic card in the host device. In addition, this configuration can flexibly deal with changes in various specifications or standards and version updates on digital communications by exchanging electronic cards without changing the host device.

(31) The digital signal receiving device is a digital signal receiving device (30), in which the electronic card is configured

200480018523.3 The first SD card.

The above configuration can build a small digital signal receiving device with large capacity, improved reliability in terms of information protection function, and use of the inherent functions of the SD card.

(32) The digital signal receiving device is a digital signal receiving device (31) in which at least a data stream signal, a clock signal, and deviation information data are sent from the digital signal receiving device through a data line defined in accordance with the SD card specification.

The above configuration can establish a digital signal receiving device with mature copyright protection function and SD card inherent high-speed information communication function.

(33) A host device configured to establish a digital signal receiving system by interconnecting the interface part of a digital signal receiving device suitable for receiving digital communication signals, and having the function of generating a clock signal according to PCR data included in the communication signal, and It has the function of transmitting data stream signals and clock signals in the form of multiple information packets. The data stream signals include communication signals. The host device is suitable for receiving data stream signals and clock signals from the digital signal receiving device via the interface part. The host device includes: receiving STC The counter is used to count the number of clock signals of the clock signal and output the counter value as the received STC data; the deviation detector is used to calculate the difference between the received STC data and the PCR data as the difference data, and detect the clock signal exceeding the predetermined value according to the difference data The frequency deviation; and the deviation processor, used to transmit the deviation information data obtained according to the received STC data and PCR data to the host device. If the deviation detector detects a frequency deviation exceeding a predetermined value, the PCR data is set in the receiving STC counter The host device includes: a host STC counter, used to count the clock number of the clock signal transmitted from the digital signal receiving device, and output the counter value as the host STC data; STC correction unit, if the deviation detector detects a frequency deviation exceeding a predetermined value , The correction data is calculated according to the host STC data and deviation information data, and the host STC counter Set the correction data inside so that the counter value set in the receiving STC counter is consistent with the counter value set in the host STC counter.

In the above configuration, the host device uses the deviation information data transmitted from the digital signal receiving device to perform correction so that the counter value in the host STC counter is consistent with the counter value in the receiving STC counter. As a result, clock resynchronization is established between the digital signal receiving device and the host device. Since the same clock signal is commonly used for the receiving device and the host device, this configuration contributes to the reduction of power consumption and the size of the host device.

(34) The host device is the host device (33), in which the STC correction unit calculates PCR data and connects

200480018523.3 For the difference between the received STC data, perform a predetermined calculation based on the difference data and the host STC data, and set the calculation result in the host STC counter as the correction data, and the PCR data and the received STC data are supplied as the deviation information data.

In the above configuration, the host device independently receives PCR data as clock information related to the digital signal transmitter and STC data as the clock signal related to the receiving device as deviation information data. The STC correction unit of the host device calculates the difference between the PCR data and the received STC data, generates correction data for synchronizing the clocks in the receiving device and the host device according to the difference, and sets the correction data in the host STC counter. Thereby, the counter value in the host STC counter and the counter value in the receiving STC counter can be consistent with each other. In addition, since the STC correction unit performs calculations required for clock synchronization, this configuration makes it easy to change or expand functions.

(35) The host device is the host device (34), in which the STC correction unit calculates the difference by subtracting the received STC data from the PCR data, performs the calculation by adding the difference to the host STC data, and sets the calculation result in the host STC counter to Correction data, PCR data and received STC data are provided as deviation information data.

In the above configuration, the host device independently receives PCR data as clock information related to the digital signal transmitter and STC data as the clock signal related to the receiving device as deviation information data. The STC correction unit of the host device calculates the difference by subtracting the received STC data from the PCR data, and adds the difference to the host STC data. Since the STC data value is used in both the receiving device and the host device, this configuration can set the same counter value in the host STC counter as the receiving STC counter.

(36) The host device is the host device (33), where the STC correction unit obtains the difference between the PCR data and the received STC data, performs a predetermined calculation based on the difference data and the host STC data, and sets the calculation result in the host STC counter as correction Data, the difference between PCR data and received STC data is provided as deviation information data.

In the above configuration, the host device receives the difference between PCR data as clock information related to the digital signal transmitter and STC data as the clock signal related to the receiving device as deviation information data. This configuration helps to reduce the amount of deviation information data. The STC correction unit performs a predetermined calculation according to the difference and the host STC data, generates correction data for synchronizing the clocks in the receiving device and the host device, and sets the correction data in the host STC counter. This configuration can set the same count value in the host STC counter as in the receiving STC counter.

200480018523.3 No. (37) The host device is the host device (36), in which the STC correction unit obtains the difference by subtracting the received STC data from the PCR data, performs the calculation by adding the difference to the host STC data, and calculates the result in the host STC counter It is set as correction data, and the difference of the received STC data by subtracting from the PCR data is regarded as the deviation information data.

In the above configuration, the host device receives the difference obtained by subtracting the received STC data as the clock signal related to the receiving device from the PCR data that is timing information related to the digital signal transmitter as the deviation information data. This configuration helps to reduce the amount of deviation information data. The STC correction unit of the host device adds the difference as deviation information data to the host STC data. Since the STC data value is used in both the receiving device and the host device, this configuration can set the same counter value in the host STC counter as the receiving STC counter.

(38) The host device is any one of the host devices (34) to (37), in which the deviation information data is transmitted from the digital signal receiving device to the host device through the interface part while being attached to the data stream signal.

In the above configuration, there is no need to provide an additional transmission line for sending deviation information data from the receiving device to the host device. In addition, the communication signal and the deviation information data are included in the signal data stream signal. Compared with the case where the communication signal and the deviation information data are transmitted separately, the correlation between the communication signal and the deviation information data is ensured. This configuration can accurately reproduce video and audio data based on, for example, a decoded data stream signal.

(39) The host device is a host device (38), in which the host device can be connected to the digital signal receiving device through a digital interface in a manner that at least the data stream signal, clock signal and deviation information data transmitted from the digital signal receiving device are in the host device It can be received via a digital interface.

In the above configuration, since the data stream signal can be sent from the receiving device to the host device without signal compression and is in a digital format, signal degradation can be suppressed. In addition, the clock signal is used to establish clock synchronization between the receiving device and the host device. If a deviation in the frequency of the clock signal in the receiving device is detected, the clock is resynchronized according to the deviation information data. As a result, the playback of the data stream signal is restored to normal operation.

(40) The host device is a host device (39), wherein the host device is configured to receive at least a data stream signal, a clock signal, and deviation information data transmitted from a digital signal receiving device formed as an electronic card.

In the above configuration, clock synchronization is established between the receiving device and the host device through a clock signal.

200480018523.3 First, if a deviation in the frequency of the clock signal in the receiving device is detected, the clock will be resynchronized according to the deviation information data. As a result, the playback of the data stream signal is restored to normal operation. In addition, the unit can flexibly deal with changes in various specifications or standards and version updates on digital communications by exchanging electronic cards without changing the host device.

(41) The host device is the host device (40), in which the electronic card is configured as an SD card.

The above configuration can provide a host device for a small digital signal receiving system with large capacity, improved reliability in terms of information protection function, and use of the inherent functions of the SD card.

(42) The host device is a host device (41), in which the host device receives at least a data stream signal, a clock signal, and deviation information data through a data line defined in accordance with the SD card specification.

The above configuration can provide a host device for the digital signal receiving system with mature copyright protection function and the inherent high-speed information communication function of SD card.

(43) The host device is a host device (42), wherein the host device includes a command transmission unit that transmits command data for controlling each process in the digital signal receiving device to the digital signal receiving device, and a notification receiving unit, Used to receive information from digital signal receiving equipment.

In the above configuration, the command receiving unit and notification receiving are used as part of the host interface. This configuration can effectively send command data from the digital signal receiving device to the host device, and send information from the host device to the digital signal receiving device.

(44) A semiconductor integrated circuit used to manufacture a host device. The host device is adapted to receive data stream signals and clock signals from the digital signal receiving device through the interface part in the digital signal receiving system. The digital signal receiving system is configured as the host device and The digital signal receiving devices are interconnected with each other through the interface part. The digital signal receiving device is adapted to receive digital communication signals, has the function of generating a clock signal according to the PCR data included in the communication signal, and has the ability to transmit data stream signals in the form of multiple information packets and The function of the clock signal, the semiconductor integrated circuit is suitable for manufacturing the host device, the host device can be connected with the digital signal receiving device, the digital signal receiving device includes: receiving STC counter, used to calculate the number of clock signals of the clock signal and output the counter value as receiving STC data ; Deviation detector, used to calculate the difference between the received STC data and PCR data as the difference data, and detect the frequency deviation of the clock signal exceeding a predetermined value based on the difference data; and the deviation processor, used to transmit to the host device according to the received STC Data and the deviation information data obtained from PCR data. If the deviation detector detects a frequency deviation exceeding a predetermined value, the PCR data is set in the receiving STC counter. The semiconductor integrated circuit includes: the host STC counter to calculate the slave number

200480018523.3 The first word signal receives the clock number of the clock signal transmitted by the device, and outputs the counter value as the host STC data; STC correction unit, if the deviation detector detects a frequency deviation exceeding a predetermined value, it will be calculated based on the host STC data and deviation information data Correct the data and set the correction data in the host STC counter so that the counter value set in the receiving STC counter is consistent with the counter value set in the host STC counter.

The above configuration is conducive to reducing the size of the host device and achieving high-speed processing for resynchronizing the clocks in the digital signal receiving device and the host device. In addition, compared with the case where the receiving STC counter and the STC correction unit are provided independently of each other, there is no connection failure or less failure, and there is no need to receive control between the STC counter and the STC correction unit.

(45) A semiconductor integrated circuit is a semiconductor integrated circuit (44), and it also contains an interface unit provided in the host device for receiving data stream signals, clock signals, and deviation information data from a digital signal receiving device.

The above configuration does not need to provide an additional host interface outside the semiconductor integrated circuit.

(46) A semiconductor integrated circuit is a semiconductor integrated circuit (44) or (45), and it also contains a decoder for decoding data stream signals and outputting decoded signals.

The above configuration does not need to provide an additional decoder outside the semiconductor integrated circuit.

(47) A semiconductor integrated circuit is any one of semiconductor integrated circuits (44) to (46), and also includes a control unit for controlling each unit in the host device, and generating and sending digital signal to each unit in the receiving device Output command information indicating the command.

In the above configuration, the semiconductor integrated circuit has an active function of transmitting various command information.

Although the present invention has been described in detail, the above description is only an example of various aspects of the present invention, and the present invention is not limited to these embodiments. It needs to be explained that the present invention contains many unexplained modifications and changes, as long as these modifications and changes do not depart from the scope of the present invention.

Industrial Applicability The digital signal receiving system, digital signal receiving device, host device, and semiconductor integrated circuit of the present invention are useful in industry because even if abnormalities such as weak radio reception conditions occur, the receiving device and the host device can be resynchronized It can reduce power consumption and reduce the size of digital signal receiving systems, receiving equipment, host equipment and semiconductor integrated circuits.

200480018523.3