Nonvolatile memory array, programming and manufacturing method

FIELD OF THE INVENTION The present invention relates to a non-volatile memory semiconductor device and a method of manufacturing a non-volatile memory semiconductor device, in particular, it relates to a non-volatile memory semiconductor device having two bits per cell and a non-volatile memory. A gate (nand) M trap memory, and a non-volatile memory semiconductor device with a two-bit NAND gate trap memory per cell is manufactured.

2. Description of the Related Art Non-volatile memory (NVM) refers to a semiconductor memory, which can continuously store information even when the power source is removed from a device containing a memory unit such as a non-volatile memory. Non-volatile memory includes mask read-only memory (mask ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM) o Non-volatile memory can generally program, read and/or erase data, and the programmed data can be stored for a long time before erasing, even up to 10 years.

Nitrided read only memory (NROM) is a type of electrically erasable programmable read only memory that uses charge trapping to store data. Nitride read-only memory is generally composed of a metal oxide semiconductor field effect transistor (MOSFET). The metal oxide semiconductor field effect transistor has an ΟΝΟ (oxygen, nitrogen oxide) layer of semiconductor material on the gate and source/drain. between. When the device is programmed, the nitride layer in the oxygen·nitrogen-oxygen layer can "trap charge (electrons). The ability of the charge to be localized into the nitrided material, which stores the charge without causing significant lateral movement of the charge through Nitride layer. Nitride read-only memory uses a relatively thick channel oxide layer, which generally has a negative impact on the time to erase the memory cell. Nitride read-only memory can be compared with known floating gate memory cells, in which the floating electrode It is conductive, and the charge is laterally distributed throughout the floating gate and the charge is transferred through the channel oxide layer. The programming of the charge trapping layer in the nitride read-only memory cell (ie charge injection) can be done by various carrier injection methods , Such as channel hot electron injection (CHE), source terminal injection (SSI) or channel initial secondary electrons

200610128843.5 (CHISEL) implementation, in which all electrons are injected into the nitride layer. Erase is performed by applying a positive gate voltage, which promotes holes to tunnel through the oxygen·nitrogen-oxide top dielectric layer from the gate. Erasing (ie, charge removal) in a nitride read-only memory device is generally performed by band-to-band hot hole tunneling (BTBHHT). However, the band-to-band hot hole tunneling effect erases many reliability problems of the nitrided read-only memory device, and causes the degradation of the nitrided read-only memory device, that is, the charge loss after multiple program/erase cycles. Reading is performed in the forward or reverse direction. The localized charge trapping technique allows two separate bit cells, thus creating an overlap in memory density. The nitride read-only memory can be repeatedly programmed, read, erased, and/or reprogrammed by a known voltage application technique.

Nitride read-only memory has attracted attention because of its two-bit operation per cell and simple production process. However, nitride read-only memory memory suffers from functional limitations, such as size reduction due to short channel effects and source/drain punchthrough. A general nitride read-only memory memory is disclosed in US Patent No. 5,768,192 (Eitan ^'192 Patent), the content of which is incorporated herein by reference. The source/drain formation of the nitride read-only memory is generally implanted into the P-well by a monument. This doping is heavily doped and the source/drain junction is deep to generate channel hot electron injection for programming and interband hot holes for erasing. Therefore, even for the virtual ground array structure, the cell size of the nitride read-only memory cell is about 8F2-10F2, where F is the characteristic size. The heavy and deep source/drain limits the size of the nitride read-only memory cell. Furthermore, the large hot electron programming current makes the parallel programming of the kilobyte (kB) level difficult, which will limit the application of data flash memory.

Another general electrically erasable programmable read-only memory is a metal-nitrogen-oxide-semiconductor (MNOS) memory cell. A general metal oxynitride-oxide-semiconductor memory cell includes a very thin layer of insulating material, such as a silicon dioxide (SiO2) layer, to separate the silicon nitride charge storage area from the gate and well area of the semiconductor device. By applying a positive voltage to the gate electrode to force the source and drain well regions to face a lower voltage, the metal-nitrogen-oxide semiconductor device is programmed. By applying a higher voltage to the gate, an electric field is generated, so that the oxide layer is tunneled to the nitride layer in the well region and the rest of the semiconductor. In order for electrons to tunnel through the oxide layer, the oxide layer must be relatively thin, such as 20·30 angstroms (A).

Another well-known electrically erasable programmable read-only memory is a silicon-oxygen-nitrogen-oxygen-silicide (SONOS) memory cell. Figure 1 illustrates the commonly known silicon, oxygen-nitrogen, oxygen-silicide equipment

200610128843.5 No.

110. The well-known silicon-oxygen-nitrogen-oxygen-silicide device 110 includes a silicon substrate 111, a source electrode 114, a drain electrode 112, a well region 115, and a first oxide layer 120 on top of the well region 115. The nitrided charge storage layer 124 is provided on the first oxide layer 120, and the second oxide layer 130 is provided on the nitrided charge storage layer 124. The polysilicon gate 125 is placed on top of the oxygen-nitrogen-silicon stack 120, 124>130. By providing the second oxide layer 130 on top of the nitride layer 124, during the programming operation, the ability to control charge storage or trapping in the nitride layer 124 can be improved. Furthermore, the second oxide layer 124 prevents voids. Holes enter the lower gate 125. A non-volatile memory cell using asymmetric charge trapping is disclosed in Eitan, No. 192 patent.

The full content of US Patent No. 6,011,725 (Eitan's <725 patent) is incorporated herein by reference, which provides a detailed comparison of a variety of known non-volatile memory technologies including distributed programming, erasing, and reading technologies. Eitan's Patent No. 725 also discloses a type of silicon-oxygen-nitrogen-oxygen-silicon memory cell that can store two data bits through localized charge storage technology.

In order to program the first bit of the generally known silicon-oxygen-nitrogen-oxygen-silicon device 110, a programming voltage is applied to the drain 112 and the gate 125, and the source 114 is grounded. The programming voltage generates vertical and horizontal electric fields from the source 114 to the drain 112 along the length of the channel 105, and when the electrons move along the length of the channel 105, the electrons gain energy to transition through the potential energy barrier caused by the bottom oxide layer 120 , And to the nitrided charge storage layer 124 where electrons are trapped or stored. These accelerated electrons that generate transitions are called hot electrons. Since the nitrided charge storage layer 124 is not really conductive, electrons cannot diffuse to the entire nitrided charge storage layer 124, but are still trapped in a local area close to the drain 112. Similarly, in order to program the second bit of the commonly known silicon-oxygen-nitrogen-oxygen-silicon device 110, a programming voltage is applied to the source 114 and the gate 125, and the drain 112 is grounded. The programming voltage generates vertical and lateral electric fields from the drain 112 to the source 114 along the length of the channel 105. The electric field causes the attracted electrons to travel from the drain 112 to the source 114, and when the electrons move along the length of the channel 105, the electrons gain energy to "transition" the potential energy barrier caused by the bottom oxide layer 120, and the electrons are trapped or trapped. Stored nitride charge storage layer 124₀Since the nitrided charge storage layer 124 is not really conductive, electrons cannot diffuse to the entire nitrided charge storage layer 124, but are still trapped in a local area close to the source 114. In order to be able to erase the memory, the programming period must be restricted because when the programming voltage is continuously applied, the width of the charge trapping area becomes wider and therefore it is difficult to erase.

200610128843.5 NAND flash memory has become the main technology of data flash memory because of its smaller cell size, faster programming speed and serial reading. However, when the size design drops below 70nm, the floating gate type NAND gate encounters functional limitations. In addition to its poor durability, the interference effect of the parasitic capacitance between adjacent floating gates seriously deteriorates the distribution of the cell threshold voltage. The silicon-oxygen-nitrogen-oxygen-silicide NAND flash memory does not have this technical limitation (design regulations produced in less than 70nm). However, silicon-oxygen-nitrogen··oxy-silicide NAND flash memory generally has poor charge retention, which prevents the use of silicon·oxygen-nitrogen-oxygen-silicide NAND flash memory in high-density NAND flash memory. Door flash memory.

What is expected is to provide a non-volatile memory with a two-bit per cell NAND gate nitridation trap memory, and it is also expected to provide a non-volatile memory that has more silicon-oxygen-oxynitride-silicon NAND gates. The memory has better data retention.

SUMMARY OF THE INVENTION Generally speaking, the present invention includes a nonvolatile memory array including a semiconductor substrate having a main surface, a first source/drain region in a portion of the semiconductor substrate close to the main surface, and The semiconductor substrate is close to the second source/drain region in a part of the main surface. The second source/drain region is separated from the first source/drain region. The well region is located in a portion of the semiconductor substrate close to the main surface between the first source/drain region and the second source/drain region. A plurality of memory cells are located on the main surface of the semiconductor substrate and located on the well region between the first source/drain region and the second source/drain region. Each memory cell includes a first oxide layer formed on the main surface of the semiconductor substrate; a charge storage layer located on the first oxide layer opposite to the main surface of the semiconductor substrate; and a second oxide layer located opposite to the main surface of the semiconductor substrate. On the charge storage layer on the main surface of the semiconductor substrate. The first oxide layer is placed on the portion of the main surface close to the well region. A plurality of word lines are located on the second oxide layer opposite to the main surface of the semiconductor substrate.

The present invention also includes a method for programming non-volatile memory cells in a memory array. The memory array includes a semiconductor substrate, a first source/drain region, a second source/drain region, and a first source/drain region. A well region between the electrode and the second source/drain region, a plurality of memory cells located between the first source/drain region and the second source/drain region on the semiconductor substrate, and a plurality of memory cells The corresponding memory cells are associated with multiple word lines and are located in multiple

200610128843.5 Multiple current control lines on either side of each word line of the first word line, each memory cell includes a first oxide layer above the well region, a charge storage layer above the first oxide layer, and The second oxide layer above the charge storage layer. The method includes: applying a positive word line programming voltage to a word line, the word line is located on each memory cell to be programmed; applying a reference voltage to the well area; and applying a current control line programming voltage to a current control line, the current control line The memory cell to be programmed on the side closest to the second source/drain. The method also includes applying a source/drain programming voltage to the first source/drain, and connecting the second source/drain to a reference voltage. The source/drain programming voltage effectively generates electron tunneling from the second source/drain. The source/drain passes through the well region to the charge storage layer to program the first bit.

The present invention also includes a method of forming a non-volatile memory array, including: providing a semiconductor substrate, the semiconductor substrate having a main surface; forming a first source/drain region in a portion of the semiconductor substrate close to the main surface; and A second source/drain region is formed at a part of the semiconductor substrate close to the main surface. The first source/drain region is separated from the second source/drain region. The well region is defined by a portion of the semiconductor substrate close to the main surface between the first source/drain region and the second source/drain region. The first oxide layer is deposited on a portion of the main surface close to the well region. The charge storage layer is formed on the first oxide layer opposite to the main surface of the semiconductor substrate. The second oxide layer is deposited on the charge storage layer opposite to the main surface of the semiconductor substrate. Part of the first oxide layer, the charge storage layer and the second oxide layer are etched to form a plurality of respective memory cells between the first and second source/drain regions. A plurality of word lines are formed, and each word line is connected to a plurality of memory cells.

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing invention content and implementation manners will be more clearly understood through the accompanying drawings. In order to illustrate the present invention, a preferred embodiment of the drawings is shown. However, the present invention is not limited to the precise arrangement and description shown in the figure.

Figure 1 is an enlarged partial cross-sectional view of a known non-volatile memory (NVM) cell with a charge storage layer between the oxide layers; Figure 2 is a preferred embodiment of the present invention with a two-bit NAND gate per cell A schematic diagram of the non-volatile memory (NVM) unit of the trapped memory; FIG. 3 is a flow chart of the memory read method according to a preferred embodiment of the present invention

200610128843.5 Figure; Figure 4 is a flowchart illustrating a method for programming a memory according to a preferred embodiment of the present invention; Figure 5 is a flowchart illustrating a method for erasing a memory according to a preferred embodiment of the present invention; Figure 6 is Figure 2 The top view of the array; Fig. 7 is an enlarged partial cross-sectional view of the local bit lines of the array of Fig. 6 along line 7-7; Fig. 8 is a flowchart illustrating a memory programming method according to a preferred embodiment of the present invention; Fig. 9 is Fig. 2 is an enlarged partial cross-sectional view of the non-volatile memory, illustrating the programming of the first bit of a specific cell; Fig. 10 is a partial cross-sectional enlarged view of the non-volatile memory of Fig. 2, illustrating the programming of the second bit of the specific cell; 11 is a partial cross-sectional enlarged view of the non-volatile memory of FIG. 2 to illustrate reading the first bit of a specific cell; FIG. 12 is a partial cross-sectional enlarged view of the non-volatile memory of FIG. 2 to illustrate the first bit of reading a specific cell 2 bits; and FIG. 13 is a partial cross-sectional enlarged view of the non-volatile memory of FIG. 2, illustrating the erasing of the first and second bits of a specific cell.

Drawing number description

110 silicon-oxygen-oxynitride-silicide memory cell

<td>111</td><td>Silicon substrate</td><td colspan="2">114 source</td>

<td>112</td><td>Drain</td><td colspan="2">115 well area</td>

<td>120</td><td>First oxide layer</td><td>124</td><td>Nitrided charge storage layer</td>

<td>125</td><td>Polysilicon gate</td><td>130</td><td>Second oxide layer</td>

<td>105</td><td>Channel</td><td>202</td><td>Semiconductor substrate</td>

<td>205</td><td>Well area</td><td>212</td><td>Second source/drain</td>

214 First source/drain 220 First oxide layer

224 Nitrided charge storage layer 230 Second oxide layer

200610128843.5 No.

245 dielectric spacer 266 memory cell

251&gt; 252 Main surface of contact window 202a

200 non-volatile memory NAND gate nitridation trap memory semiconductor array

LBL1, LBL2, LBL3, LBL4 local bit lines

BSL1, BSL2, BSL3, BSL4 block selection line

WLA, WLB, WLC word line

CCLA, CCLB, CCLC, CCLn current control line

Specific implementations of MBLA and MBL2 metal bit lines The specific terms used in the following are only for convenience and not limitation. The words "right", "Boo", "lower suction" and "higher" indicate the direction of the reference device in the figure. The words inward and outward respectively indicate the geometric center of the object facing or away from the description and labeling part. These terms include the above-mentioned specific characters, other Words with derivative and similar meanings. Furthermore, the word one used in the claims and their corresponding meanings means at least one.

1) Micrometer (μ m) is 10,000 angstroms (A) or 1000 nanometers (nm).

As used herein, references to conductivity will be limited to the illustrated embodiment. However, those skilled in the art know that it is possible to switch between p-type conductivity and n-type conductivity, and the device is still functionally correct (ie first or second conductivity type). Therefore, the reference to η or ρ used herein can also be represented by substitution of η and ρ or ρ and η.

Furthermore, η+ and ρ+ denote heavily doped η and ρ regions, respectively; η++ and ρ++ denote very heavily doped η and ρ regions, respectively; η· and ρ- denote lightly doped η, respectively And ρ regions; η-- and ρ...respectively represent very lightly doped η and ρ regions. However, this relatively mixed term should not be regarded as a limitation.

Refer to the drawings in detail, in which similar device symbols in all the figures represent similar devices. Figures 2 and 7 to Figure 13 show a non-volatile memory (NVM) NAND gate nitridation trap memory semiconductor array 200 according to a preferred embodiment of the present invention, which includes two bits-bit A and bit BofMemory unit 266.

Specifically, FIG. 2 shows a schematic diagram of a non-volatile memory array 200. The non-volatile memory array 200 includes a NAND trap memory cell 266. Each memory

200610128843.5 The first unit 266 is configured to store two bits, bit A and bit Bo. The nonvolatile memory array 200 includes a plurality of local bit lines LBL1, LBL2, LBL3, LBL4, and a plurality of block selection lines BSL1, BSL2, BSL3, BSL4, Multiple word lines WLA, WLB^WLC, multiple current control lines CCLA, CCLB, CCLC, CCLn, and multiple metal bit lines MBLA, MBL2. Each word line WLA-WLC is separated from each current control line CCLA-CCLn by a dielectric spacer 245 (FIGS. 6-7).

The word line WLA-WLC is preferably formed of doped or undoped polysilicon, and the thickness is between 500-1500 angstroms. The current control lines CCLA-CCLn are preferably formed of doped or undoped polysilicon, and the thickness is between 500-1500 angstroms.

FIG. 6 is a top view of a portion of the non-volatile memory array 200. As shown in FIG. FIG. 7 is a partially enlarged cross-sectional view of the local bit lines of the array of FIG. 6 along the line 7-7. As best shown in FIG. 7, the non-volatile memory array 200 includes a semiconductor substrate 202, a first source/drain 214, a second source/drain 212, and a well region 205. The semiconductor substrate 202 is relatively It is preferably undoped or doped silicon, but the semiconductor substrate 202 can be made of other semiconductor materials, which does not deviate from the embodiment of the present invention. Each memory cell 266 includes a first oxide layer 220 on top of the well region 205, a nitrided charge storage layer 224 on the first oxide layer 220, and a second oxide layer on the nitrided charge storage layer 224 230. The representative word line WLA-WLC is located on top of the oxygen-nitrogen-oxide (ΟΝΟ) stack 220, 224 230 of each memory cell. The second oxide layer 230 insulates the nitrided charge storage layer 224 from the underlying word line WLA-WLC. The metal bit lines MBLA and MBL2 are respectively connected to the source/drain 212 and the source/drain 214 through the contact windows 251 and 252, respectively. The general areas in the nitrided charge storage layer 224 storing charges in the first bit-bit A and the second bit-bit B are covered and shown with the device code-bit A and the bit B, respectively. It can be understood that it is stored in the nitride storage layer 224 The shape of the area surrounded by the medium charge may or may not be accurately described geometrically. It can be understood that in FIG. 7, the first and final current control lines CCLn cover the first and second source and drain regions 214, 212 to ensure that the first and second source and drain regions 214, 212 are opposite to each other. The local bit lines LBL1-LBL4 are connected.

The block selection lines BSL1-BSL4 can be used to switch the bias voltages of the first source/drain 214 and the second source/drain 212. The current control line CCLA-CCLn controls the programming current and also assists the inversion including the first and second source/drain 214, 212.

200610128843.5 The second dielectric layer 245 is preferably formed of silicon oxide (SiOx) and has a thickness of 70-150 angstroms. The first oxide layer is preferably formed of silicon oxide (SiOx) and has a thickness of 30-60 angstroms. For example, the first oxide layer 220 may be formed of silicon dioxide (SiO2) and the like. The nitrided charge storage layer 224 may be formed of silicon nitride (S13N4) or the like. Of course, other general non-conductive charge storage materials can be used for the charge storage layer 224. The second oxide layer is preferably formed of silicon oxide (SiOx) and has a thickness of 40-80 angstroms. For example, the second oxide layer 230 may be formed of silicon dioxide (SiO2) and the like.

It can be understood that the two-bit memory cell 266 according to the present invention may be symmetrical. Therefore, the words "source and drain" may be confused with known one-bit devices. For the first bit of each memory cell 266-bit A, During programming and reading operations, the source/drain 214 serves as the drain terminal, and the source/drain 212 serves as the source terminal. Similarly, for the second bit-bit B of each memory cell 266, during programming and reading During the operation, the source/drain 212 serves as the drain terminal, and the source/drain 214 serves as the source terminal. Therefore, it can be understood that the source and drain terminals 212, 214 are the first in the second bit-bit B. Bit-the inversion of the source and drain terminals 212, 214 in bit A.

In order to program multiple memory cells at the first time, a negative Fuller-Nordham (FN) reset is required to increase the Vt of the entire memory cell 266. FIG. 8 shows the steps of performing the reset of the negative gate voltage FN injection.

Referring to FIGS. 4 and 9 to 10, the two bits A and B for programming the memory cell 266 will be described. The programming method is the LC source terminal injection (SSI) method.

In order to program the first bit A, a relatively high positive bias is applied to the word line WLA, and the control line CCLA is turned on relatively weakly. For example, a programming voltage of about 8-12 volts direct current (DC) may be applied to the word line WLA, and about 0.7-2 volts direct current (DC) may be applied to the CCLA₀The other word lines WLB-WLC and current control lines CCLB-CCLn are fully turned on. For example, about 10-15 volts of direct current may be applied to other word lines WLB-WLC, and about 6-9 volts of direct current may be applied to the current control lines CCLB-CCLn. The block selection line BSL2 and the block selection line BSL3 are turned on. The drain programming voltage is applied to the metal bit line MBL1, so to the source/drain region 214, the drain programming voltage may be in the range of about 4-6 volts direct current. The source programming voltage is applied to the metal bit line MBL2, and therefore to the source/drain region 212. The rho well 205 is grounded (ie, about 0 volts direct current). Source programming voltage is about

200610128843.5 No. ground or approximately 0 volts direct current. Therefore, in this configuration, the source/drain region 212 serves as a source for programming, and the source/drain region 214 serves as a drain for programming. FIG. 9 schematically shows the through channel formed between the source/drain region 212 and the memory cell 266 under the word line WLA. The area close to the source/drain area 212 within the nitrided charge storage area 224 becomes an injection point where hot electrons are trapped, thereby defining the first bit-bit A for programming.

Similarly, in order to program the second bit B, a relatively high positive bias is applied to the word line WLA, And the control line CCLB is relatively weakly turned on. For example, a programming voltage of about 8-12 volts direct current (DC) may be applied to the word line WLA, and about 0.7-2 volts direct current may be applied to other word lines WLB and WLC of CCLBo, and the current control lines CCLA, CCLC-CCLn are Fully open. For example, about 10-15 volts of direct current may be applied to other word lines WLB and WLC, and about 6-9 volts of direct current may be applied to the current control line CCLA, CCLC-CCLno block selection line BSL2 and block selection line BSL3 to turn on. The drain programming voltage is applied to the metal bit line MBL2, so to the source/drain region 212, the drain programming voltage may be in the range of about 4-6 volts direct current. The source programming voltage is applied to the metal bit line MBL1, so the source/drain region 214op well 205 is grounded (ie, about 0V DC). The source programming voltage is about ground or about 0 volts DC. Therefore, in this configuration, the source/drain region 214 serves as a source for programming, and the source/drain region 212 serves as a drain for programming. FIG. 10 schematically shows the through channel formed between the source/drain region 214 and the memory cell 266 under the word line WLA. The area near the source/drain area 214 in the nitrided charge storage area 224 becomes an injection point where hot electrons are trapped, thereby defining the second bit B for programming.

With reference to FIGS. 3 and 11 to 12, the two bits A and B for reading the memory cell 266 will be described.

In order to read the first bit A, a read bias voltage between the programming voltage and the erase voltage Vt is applied to the word line WLAo. For example, the read voltage may be between about 1-5 volts direct current, and other words The line WLB-WLC and the current control line CCLA-CCLn are fully open. For example, about 10-15 volts of direct current may be applied to other word lines WLB-WLC, and about 6-9 volts of direct current may be applied to the current control line CCLA-CCLno. The block selection line BSL2 and the block selection line BSL3 are turned on. The source voltage is applied to the metal bit line MBL2, so to the source/drain region 212, the source read voltage may be approximately grounded or approximately

200610128843.5 No.

0 volts direct current. The drain read voltage is applied to the metal bit line MBL1, and therefore to the source/drain region 214o ρ well 205 is grounded (ie, about 0V DC). After that, the current in the channel 205 is detected. If the first bit-bit A is programmed (ie logic 0), the current in the channel 205 will be very low, if the first bit-bit A is not programmed (ie logic 1), then the current in the channel 205 The current will be high. By connecting the source/drain region 212 to the reference or ground, and connecting the source/drain region 214 to a positive voltage, the drain induced energy barrier decay (DIBL) effect overcomes the electric field barrier. The battery barrier is If bit B is programmed, it is established by electron injection.

Similarly, in order to read the second bit B, a read bias voltage between the programming voltage and the erase voltage Vt is applied to the word line WLAo. For example, the read voltage may be between about 1-5 volts DC , Other word lines WLB-WLC and current control lines CCLA-CCLn are fully open. For example, about 10-15 volts of direct current may be applied to other word lines WLB-WLC, and about 6-9 volts of direct current may be applied to the current control line CCLA-CCLno. The block selection line BSL2 and the block selection line BSL3 are turned on. The source voltage is applied to the metal bit line MBL1, so to the source/drain region 214, the source read voltage may be approximately grounded or approximately 0V DC. The drain read voltage is applied to the metal bit line MBL2, and therefore to the source/drain region 212. The ρ well 205 is grounded (that is, about 0 volts direct current). After that, the current in the channel 205 is detected. If the second bit-bit B is programmed (ie logic 0), the current in the channel 205 will be very low, if the second bit-bit B is not programmed (ie logic 1), then the current in the channel 205 The current will be high. By connecting the source/drain region 214 to a reference or ground, and connecting the source/drain region 212 to a positive voltage, the DIBL effect caused by the drain can prevent the second bit effect from occurring.

Referring to FIGS. 5 and 13, the two bits-bit A and bit B of the memory cell 266 for erasing will be described.

In order to erase the first and second bits A and B of the memory cell 266, a negative erase voltage is applied to all word lines and current control lines CCLA-CCLno ρ well 205 is grounded or a negative erase voltage is applied. For example, if a voltage between -10 to -15 volts direct current is applied to the word line WLA-WLC, a voltage of about 5-10 volts direct current is applied to the p well 205. However, if a voltage between -15 to 20 volts direct current is applied to the word line WLA-WLC, the ρ well 205 is grounded. The final result is that there is a negative potential difference between the p well 205 and the word line of -15 to -20 volts direct current. All BSL1 to BSL4 are open.

200610128843.5 The present invention also includes a method of forming a non-volatile memory array 200. Refer to Figure 7, The method includes providing a semiconductor substrate 202 including a main surface 202a. A first source/drain region 214 is formed in a portion of the semiconductor substrate 202 close to the main surface 202a, and a second source/drain region 212 is formed in a Part of the semiconductor substrate 202 is close to the main surface 202a. The first source/drain region 214 is separated from the second source/drain region 212. The first oxide layer 220 is located on the main surface 202 a of the substrate 202 close to the well region 205. The charge storage layer 224 is formed on the first oxide layer 220 relative to the main surface 202 a of the semiconductor substrate 202. The second oxide layer 230 is located on the charge storage layer 224 relative to the main surface 202 a of the semiconductor substrate 202. Part of the first oxide layer 220, the charge storage layer 224, and the second oxide layer 230 are etched to form a plurality of independent memory cells 266 between the first and second source/drain regions 214, 212. A mask (not shown) may be used to perform this etching. A plurality of word lines WLA-WLC are formed, and each word line is connected to a group of a plurality of memory cells 266. The multiple control lines CCLA-CCLn are formed on each side of the multiple word lines WLA-WLC. The insulator 245 surrounds the plurality of word lines WLA-WLC and the plurality of control lines CCLA-CCLn. The non-volatile memory array 200 may be an N-channel device, such as doping and/or Two n-type regions of the first and second source/drain regions 214, 212 are implanted, and the well region 205 of the p-type region is left in the semiconductor substrate 202. The non-volatile memory array 200 can also be a p-channel device, and the first and second source/drain regions 214, 212 are manufactured by, for example, doping and/or implantation, and two p-type regions are left, and n-type regions are left. The well region 205 is in the semiconductor substrate 202. Grooves (not clearly shown) may be formed in the semiconductor substrate 202 for the expected first and second source/drain regions 214, 212, and then depending on the material of the substrate 202, the n-type or p-type material , Such as heavily doped n-type or p-type polysilicon and the like are refilled in the groove.

The respective layers 220, 224, 230 and the lines WLA-WLC, CCLA-CCLn, BSL1-BSL4, and LBL1-LBL4 can be formed in any known technique. For example, various layers 220, 224, 230 may be grown or deposited, and the deposition may be chemical vapor deposition (CVD), physical vapor deposition (PVD), evaporation, sputtering, and the like. The pattern may be formed on the surface of the semiconductor substrate by photolithography or photomask (mask) technology. Etch back various layers 220, 224, 230 and lines WLA-WLC, CCLA-CCLn^ BSL1-BSL4, LBL1-LBL4 possible

200610128843.5 No. through mechanical etching or chemical etching and/or chemical mechanical etching (CMP) etc. A layer of polysilicon may be deposited on it and polished with CMP. Perform another photolithography or photomask and etching step to generate bit lines BSL1-BSL4 and control lines CCLA-CCLno Perform oxide filling or deposition steps to isolate each bit line BSL1-BSL4 and control lines CCLA-CCLn_oThe contacts 271 and 272 are then formed by etching and metallization. Furthermore, well-known doping, heat treatment, diffusion, etching, layering, grooves, grinding, etc. may be used in the manufacture of the nonvolatile memory array 200 without departing from the scope of the present invention.

The NAND gate nitridation trap memory array according to the preferred embodiment of the present invention is easy to shrink in size, at least partly due to the field inversion source/drain, which is used to replace the implanted buried diffusion source/drain. Drain to improve short channel effect and penetration. The gate-controlled low-current source extreme hot electron injection programming method is used in the preferred embodiment to reduce the programming current and increase the programming speed. The negative gate voltage FN erasing method is used in the preferred embodiment to increase the erasing speed and improve the data retention capability.

Based on the above, it can be seen that the present invention relates to a nonvolatile memory semiconductor device having a two-bit per cell NAND gate nitride trap memory and the manufacture of a nonvolatile memory semiconductor device having a two-bit per cell NAND gate nitride trap memory Method of memory semiconductor device. It can be understood by those skilled in the art that the foregoing embodiments can be changed without departing from the broad content of the invention. Therefore, it can be understood that the present invention is not limited to the foregoing specific embodiments, but covers modifications within the spirit and scope of the present invention defined by the claims.

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