Method for reducing coupling effect between nonvolatile memory storage cell

The present invention relates to a non-volatile memory and its operation in general. More specifically, it relates to a method for reducing storage in a memory storage element. The technology of the influence of the data on the data read from other storage elements.

BACKGROUND OF THE INVENTION The principles of the present invention can be applied to different types of non-volatile memories, including those existing and those newly developed using new technologies in the future. However, the specific application of the present invention here is based on electrically erasable programmable only Read the memory (EEPR0M) to illustrate, where the storage element is a floating gate (FG) (floating gate).

The field effect of coupling between adjacent FGs is described in US Patent No. 5,867,429 by Jian Chen and Yupin Fong, and the invention is hereby incorporated in its entirety as a reference."As a result of improved integrated circuit manufacturing technology, when the size of the memory cell array is changed When it decreases, the degree of coupling will inevitably increase. The problem obviously arises when two groups of adjacent memory cells are programmed at different times. A group of cells are programmed to increase the charge of its FG corresponding to a group of data ( charge) level·After the second group of cells are programmed with the second group of data, the charge level (level) read from the FG in the first group of cells is often due to the generation of the second group of FGs coupled to the first group The effect of the load becomes inconsistent with the programmed result. This is called the Yupin effect. The aforementioned Patent No. 5867429 suggests either to physically isolate the two sets of FGs, or to isolate them from the first set of FGs. When reading the value, the charge effect of the second group of FG is taken into account.

This effect appears in different types of flash EEPROM cell arrays. A design of a NOR array connects its memory cells between adjacent bit (row) lines, and connects the control gate to the word (column) line. Each cell includes a with or without and The floating gate transistor of the series selection transistor, or two floating gate transistors separated by a single selection transistor. Examples of such an array and its application in a storage system are listed in the following SanDisk It is mentioned in the companys patents and unauthorised applications, and these related documents are also referred to here: Patent No. 5095344,

02143467.0 p.

5172338, 5602987, 5663901, 5430859, 5657332, 5712180, 5890192, and 6151248, and the serial number submitted on February 17, 2000 is 09/505555, and the serial number submitted on September 22, 2000 is 09 / 667334 patent application.

A design of a NAND array is with a series of memory cells, such as 16 or 32 memory cells connected in series between a bit line and a reference potential through a selection transistor located at either end. The word lines are in different series. The array is connected to the control grid. Examples of this arrangement and its operation are mentioned in the following Toshiba US patents or unlicensed applications, and these documents are also referenced in full here: No. 5570315, 5774397 and 6046935 and serial number 09/667610.

In today's commodities, it is the most common practice to store a single bit of data into each floating gate by operating in binary mode. The two ranges of the threshold level of the floating gate transistor are set as the storage level. One The threshold level of a floating gate transistor corresponds to the level of charge stored on its floating gate.In addition to reducing the size of the memory array, the trend is to increase this by storing more than one bit of data on each floating gate transistor. The density of data stored on the memory array. This is achieved by defining more than two threshold levels for each floating gate transistor as the storage state. Four such states (2 bits of data for each floating gate) are included in In the existing products, more storage error states, such as 16 states per storage element, are also considered. Each floating gate transistor has a total range of threshold level voltage (limiter), within which it can be actually operated, and the range is divided into multiple defined states and margins between states So that they can be clearly distinguished from each other, the usual operation of this type of non-volatile memory is to erase the memory cell block first before reprogramming it. The cells in the block are then erased separately Programming becomes the state represented by the input data to be stored. Programming usually involves alternately making requests to a large number of memory cells while programming voltage pulses and reading their states separately to determine whether each cell has reached its predetermined level. For those The programming of cells that are confirmed to have reached their predetermined threshold level will stop, while programming for other programmed cells will continue at the same time, until all those cells are programmed when the number of storage states of a unit storage element is increased. At that time, the time to perform programming will become longer because the smaller voltage range of each state requires higher programming accuracy. This will have a significant negative impact on the storage system.

The narrower range of the defined floating gate storage level caused by multi-state operation increases the sensitivity level of the charge of the second group of storage elements loaded on the adjacent second group of storage elements that are programmed later. For example, when the first group is When reading, the charge on the second group will cause an error when reading the state of the first group. From the adjacent

02143467.0 The field coupled to the first storage element can greatly affect the read state, at least one set of stored data will cause errors. If the number of error bits remains within the capability of the Error Correction Code (ECC), these errors can still be corrected, but if the number of errors exceeds that limit, other structures and/or operating techniques must be used. The technology disclosed in the aforementioned U.S. Patent No. 5867429 is suitable for multi-array situations, but it is hoped that another technology can be provided to enable the working effect of the field coupled between adjacent floating gates." SUMMARY OF THE INVENTION Since then, according to a basic aspect of the present invention, after the second adjacent storage element is programmed, the first group of storage elements are reprogrammed to their desired state. Since periodically reading the state of the cell is part of the programming process, Used to determine when to stop, so reprogramming will add the necessary charge to the first group of storage elements to compensate for the field effect of the coupling between adjacent storage elements that are programmed later. An alternating pulse and a conventional programming operation The read sequence can be used to reprogram the first group of memory cells, which occurs when the influence of the second group of adjacent programmed memory elements occurs. Although it will still be affected by the charge of the adjacent cells, but later on The reading of the first group of storage elements will be affected by the charge of adjacent cells. It becomes more accurate due to reprogramming being taken into account. In order to avoid having to keep a data buffer large enough to hold the data programmed in the first channel to be used in the second programming channel and stored by the first channel The data can be read from the memory with adjusted read margin, and the data is reprogrammed in the second channel. According to the second basic aspect of the present invention, the programming of the storage element that is programmed to the same state The level distribution is compressed (compact) by reprogramming some storage elements on one side of the distributed state to another distributed state. "The stored elements in a given state are read and those whose programming level is lower than the distributed state" The storage element of a predetermined threshold is given further programming in order to raise its level above the predetermined threshold, which has the effect of reducing the programming window required for each memory state, thereby allowing additional states to be included and / Or additional space is provided between the states. Such compression can be performed independently in the manner mentioned in the previous paragraph, but preferably can also be used as part of the reprogramming step. In fact, the second programming channel should be in the same group of cells Appears immediately after the first programming, in order to narrow the programming level distribution state to a range that takes into account the obvious expansion of these distribution states that occur after the adjacent cells are programmed. The step size increase of the programming pulse voltage level Can be set to high The normal level of the first programming channel, in order to quickly program a group of cells to its initial level in a wide distribution state, and then the usual small incremental voltage increases the programming pulse in the second channel to reduce

02143467.0 The first expansion of those distributions. These technologies can quickly achieve performance improvement through the narrow voltage threshold distribution states of programming memory cells." According to another aspect of the present invention, according to an existing multi-state programming technology, adjacent memory cells The sequence of programming can be implemented in such a way that the Yupin effect of cross-coupling between such adjacent cells is minimized. According to the existing programming technology, the first group of alternating adjacent cells in a row or column is used in the first programming step , Are partially programmed to become the first data bit level, and the remaining second group of alternating cells are then partially programmed to the first data bit level of those cells in a similar manner, and then completed with the second It data bit of each cell The programming of the first group, and finally, the programming of the second group is completed with its second bit. But in order to minimize the Yupin effect between the storage elements in these cells, according to the third aspect of the present invention, each bit is An independent step is programmed to the first group of cells, and then the second group of cells is programmed with its two data bits in an independent step. This technology is especially suitable for, but not limited to, when programming NAND memory." This technology can be used independently or together according to the first and/or second basic aspects of the present invention summarized above, so as to cancel the Yupin effect of coupling between adjacent storage elements at different levels.

Other aspects of the present invention, characteristics and advantages are described in the following exemplary embodiment section, which is described with reference to the following drawings.

BRIEF DESCRIPTION OF THE DRAWINGS] is a block diagram of a non-volatile memory with various characteristics of the present invention; FIG. 2 is a diagram illustrating the existing circuit and organization structure when the memory array in FIG. 1 is of the NAND type; Fig. 3 is a cross-sectional view of the NAND-type memory array located on the semiconductor substrate along the column direction; Fig. 4 is a cross-sectional view of the memory array in Fig. 3 along the area 4-4; Fig. 5 is a cross-sectional view of the memory array in Fig. 3 Fig. 6 is an example operating voltage table I of the NAND memory array in Fig. 2-5; Fig. 7 describes another feature of the NAND memory array in Fig. 2-5; Fig. 8 shows In the four-state operation, the exemplary existing distribution state of the threshold voltage of the NAND memory array in Figs. 2-5; Fig. 9A shows a waveform signal of a programming voltage; Fig. 9B shows the response to programming with the voltage pulse shown in Fig. 9A The existing voltage threshold response of the memory cell array in Figure 2-5;

02143467.0 Figures 10A and 10B are the state of the voltage national value level distribution, which is used to illustrate the financial and technical phases of programming the squeezer cell array shown in Figure 2-5. The memory cell array shown in FIGS. 2-5 has an effect on the threshold value distribution; FIG. 12 shows the effect of Yupin on the threshold value distribution state of the memory cell array shown in FIGS. 2-5 when programming using the first technique according to the present invention; Fig. 13 shows the steps of programming the memory cell array shown in Figs. 2-5 according to the first technique shown in Fig. 12. Fig. 14A shows the waveform signal of the programming voltage according to the programming method shown in Fig. 13 Fig. 14B shows the voltage threshold level response of the memory cell array shown in Figs. 2-5 to the programming pulse of Fig. 14A according to the programming method shown in Fig. 13; Fig. 15A shows the voltage threshold level response of the memory cell array shown in Fig. 13 Another waveform signal of the programming voltage; Figure 15B shows the voltage level response of the memory array shown in Figure 2-5 to the set of alternate programming pulses in Figure 15A according to the programming method shown in Figure 13; Figure 16 Shows the effect of Yuin on the threshold distribution state of the cell array shown in FIGS. 2-5 when programming using the second ^ technique according to the present invention; FIG. 17 shows the first technique based on the results shown in FIG. 16 Steps for programming the memory cell array shown in Figs. 2-5; Fig. 18 shows the Yupin effect on the threshold distribution state of the memory cell array shown in Figs. 2-5 when using a variational programming according to the second technique of the present invention; Fig. 19 shows the result according to the result shown in Fig. 18 The first technique for programming the memory cell array shown in FIGS. 2-5. FIG. 20 shows that the memory cell array shown in FIGS. 2-5 is thresholded when the third technique according to the present invention is used for programming. Yupin effect of the distribution state; FIG. 21 is a F-th sub-flow chart of the first exemplary embodiment of the method for programming the memory array shown in FIGS. 2-5; FIG. 22 is a comparison of the memory array shown in FIGS. 2-5 The second part of the flowchart of the first exemplary embodiment of the programming method; FIG. 23 is the F-th sub-flow chart of the second exemplary embodiment of the method of programming the memory array shown in FIGS. 2-5; 24 is the second exemplary embodiment of the method for programming the memory array shown in FIGS. 2-5

02143467.0 The second part of the flowchart; FIG. 25 is the F-th sub-flow chart of the third exemplary embodiment of the method for programming the memory array shown in FIGS. 2-5 when combined with FIG. 21; 22 when combined, the second part of the flowchart of the third exemplary embodiment of the method for programming the memory array shown in FIGS. 2-5; FIG. 27 is the second part of the flowchart of the memory array shown in FIGS. 2-5 when combined with FIG. 23 The F-th sub-flow chart of the fourth exemplary embodiment of the method for programming the array; FIG. 28 is a diagram of the fourth exemplary embodiment of the method for programming the memory array shown in FIGS. 2-5 when combined with FIG. 24 The second part of the flowchart; Figure 29 illustrates a programming sequence using the third and fourth embodiments; Figure 30 shows the T?th minute of the method of reading data from the memory array shown in Figures 2-5; And Figure 31 shows the second part of the method of reading data from the memory array shown in Figures 2-5. DETAILED DESCRIPTION OF THE EMBODIMENTS Examples of non-volatile memory systems refer to Figures]-7. In order to provide specific examples, a specific non-volatile memory capable of implementing different aspects of the present invention is illustrated. Figure 1 is a flash memory system Block diagram. A memory cell array 1 including a plurality of memory cells arranged in a matrix consists of a column control circuit 2, a row control circuit 3, c source control circuit 4 and cp-well control circuit 5 to control. Column control circuit 2 is connected to the bit line (BL) of the memory cell array 1 in order to read the data stored in the memory cell (M), in the programming Determine the state of the memory cell (M) during operation, and control the potential level of the bit line (BL) to promote or inhibit programming. The row control circuit 3 is connected to the word line (WL) to select one of the word lines (WL), provides a read voltage, provides a programming voltage, the voltage is combined with the bit line potential level controlled by the column control circuit 2, and the ρ area formed in the memory cell (M) (marked in Figure 3 An erase voltage is applied to the voltage of the "cp well"). The c source control circuit 4 controls the common source line connected to the memory cell (M) (marked as "c-source" in Figure 2). cp-well control Circuit 5 controls the cp-trap voltage.

The data stored in the memory cell (M) is read by the column control circuit 2, and is output to the external I/O line through an I/O line and a data input/output buffer 6. To be stored on the memory cell The programming data is input to the input/output buffer 6 through an external I/O line, and is transferred to the column control circuit 2. The external I/O line is connected to a controller 20

02143467.0 The command data of the first control flash memory device is input to a command interface, which is connected to the external control line connected to the controller 20. The command data tells the flash memory what operation is requested. The input command is transmitted to the control column control The circuit 2, the row control circuit 3, the c source control circuit 4, the bp-well control circuit 5, and the state machine 8 of the data input/output buffer 6 can output the state data of the flash memory, such as ready/busy or pass /failure.

The controller 20 is connected to or can be connected to a main system, the main system can be a personal computer, a digital camera personal digital assistant. The main system issues instructions, such as storing or reading data to/from a memory array, And separately provide or receive such data. The controller converts such commands into command signals that can be interpreted and executed by the command circuit 7. The controller usually also includes user data for writing or reading from the memory array Buffer memory. A typical memory system includes an integrated circuit chip 21, the chip 21 includes a controller 20, and one or more integrated circuit chips 22, each of which includes a memory array and related control, input/output, and State machine circuit. Of course, the development trend is to integrate the memory array and the system control circuit into one or more integrated circuit chips. The memory system can be embedded in the main system as its Y point, or it can be included in one that can be inserted into the main system. On a memory card that matches the socket and can be removed. Such a card can include the entire memory system, or a controller and a memory array, and other peripheral related circuits can be on a separate card.

Referring to FIG. 2, an exemplary structure of the memory array 1 is illustrated. A NAND flash EEPROM is described as an example. In a specific example, the memory cell (M) is divided into 1024 blocks. The data stored in each block is erased at the same time and the block becomes a simultaneously erasable unit The smallest unit. In each block in this example, there are 8512 columns that are divided into even columns and odd columns. The bit lines are also divided into even bit lines (BLw) and odd bit lines (BLo). Each gate electrode is connected The four serial memory cells connected to the word line (WL0 to WL3) form a NAND cell. The _ terminals of the NAND cell are connected to a first selection transistor (S) connected to a first selection gate line (SGD) On the corresponding bit line (BL), the other terminal is connected to a second selection gate line (SGS) via a gate electrode. The second selection transistor (S) is connected to the c source. Four floating gate transistors are shown in the cell, but in practice, a larger number of transistors are usually used, such as & 16 or even 32.

In a user data reading and programming operation, in this example, 4256 cells (Μ) are selected at the same time. The selected cells (Μ) have the same word line (WL), such as WL2, and the same type

02143467.0 The first bit line (BL), such as even-numbered bit lines BLeO to BLe4255. Therefore, 532-bit data can be read or programmed at the same time. The 532B read or programmed at the same time logically becomes one page. Therefore, one block At least eight pages can be borrowed. When each memory cell (M) stores two bits of data, that is, when a multi-level cell, _ block can store 16 pages with two bits per cell. In this embodiment , The storage element of each memory cell, here is that the floating gate of each memory cell stores two bits of user data. Figure 3 shows a cross-sectional view of the NAND cell schematically shown in Figure 2 along the bit line (BL) direction. A p-type region cp well 11 is formed on the surface of a P-type semiconductor substrate 9, The cf well is sealed by an n-type region 10 to electrically insulate the cp well from the p-type substrate. The n-type region 10 is connected to the first metal through a first connection hole (CB) and an n-type diffusion layer 12 The cp trap line made of Μ0. The p-type region c-p well 11 is connected to the cp well line through a first connection hole (CB) and a p-type diffusion layer 13. The cp well line is connected to the cp well control circuit 5 (Figure 1) "each memory cell Both have a floating gate (FG) that stores a certain amount of charge corresponding to the data stored in the cell, the word line (WL) forms the gate, and the drain and source electrodes are both composed of a p-type diffusion layer 12. Floating The gate (FG) is formed on the surface of the cp well through a tunnel oxide film (14). The word line (WL) is laminated on the floating gate (FG) through an insulating film (15). The source electrode passes through the second selection transistor (S) And the first connection hole (CB) is connected to the common source line (c-source) made of the first metal (M0). The common source line is connected to the c-source control circuit (4). The drain electrode is connected to the On the bit line (BL) made of the second metal (Ml), the connection is through the first selection transistor (S), the first connection hole (CB), the middle wiring of the first metal (M0) and the second Connection hole (VI). The bit line is connected to the column control circuit (2).

Figures 4 and 5 respectively show a cross-sectional view of a memory cell (part 4-4 in Figure 3) along the word line (WL2) and a selection transistor (part 5-5 of Figure 3). Each column has The material such as shallow trench insulation (STI) through a trench formed on the substrate and filled with an insulating material may be shallow trench insulation (STI). The floating gate is insulated from each other by the STI and the insulating film 15 and the word line (WL), Recently, the space between the floating gates will be less than 0.1 lum, and the capacitive coupling between the floating gates has also increased. Due to the formation process of the gate electrode (SG) of the selection transistor (S) and the floating gate (FG) Same as the word line (WL), so the layered gate structure will be displayed. These two selection grid lines (SG) are separated at the end of the line.

Table I in FIG. 6 shows a situation where a voltage is applied to operate the memory cell array 1 in a specific example. The floating gate of each memory cell stores two bits, with states TT, T0", "01", and "00". The table shows when the word line "WL2 and the bit line "BLe are selected to enter

02143467.0 The situation of reading and programming the first row. By increasing the cp well to the deletion voltage of 20V and grounding the word line (WL) of the selected block, the data of the selected block is deleted. Because of the words of the unselected block The line (WL), bit line (BL), select line (SG) and c-source are all in a floating state, so these are all raised to about 20V due to capacitive coupling with the cp well. In this way, Only when a strong electric field is applied to the tunnel oxide film 14 (FIG. 4 and FIG. 5) of the selected memory cell (M), the data of the selected memory cell will be affected by the tunnel current flowing through the tunnel oxide film 14. Delete. The deleted unit, in this example, is in one of the four possible programming states, namely "11".

In order to store electrons in the floating gate (FG) during the programming process, the selected word line WL2 is connected to the programming pulse Vpgm-h, while the bit line Ble is selected to be grounded. On the other hand, in order to prohibit the memory cells in which programming should not occur ( Μ) the programming occurs, the corresponding bit line Ble is connected to the power supply Vdd like the unselected bit line Bio, for example, 3V. The unselected word lines WL0, WL1 and WL3 are all connected to 10V, and the first select gate ( SGD) is connected to Vdd, and the second select gate (SGS) is grounded. Therefore, the channel potential of the programmed memory cell (M) is set to 0V. The channel potential at the program prohibition portion is increased to about 6V due to capacitive coupling with the word line (WL). As described above, only one channel is applied to the tunnel oxide film 14 of the memory cell (M) during the programming process. The strong electric field has a delete effect on the current flowing through the tunnel oxide film 14 in the opposite direction, and then the logic state changes from "11" to one of the other states T0, "01", or "00".

In the read and verify operation, the selected gate (SGD and SGS) or unselected word line (WLO, WL1, WL2) is raised to a read pass voltage of 4.5V to make it a pass gate. Select The word line (WL2) is connected to a voltage, and the voltage level is set according to each read and verify operation in order to determine whether the national value voltage of the connected memory cell has reached such a level. For example, in READ10 In operation, the selected word line WL2 is grounded to detect whether the threshold voltage is higher than 0V. In this read state, it can be said that the read level is 0V. In the VERIFY01 operation, the selected word line WL2 is connected to 2.4V, Use this to verify whether the national value voltage has reached 2.4V. In this verification state, it can be said that the verification level is 2.4V.

The selected bit line (BLe) is precharged to a high level, such as 0.7V. If the threshold voltage is higher than the read or verify level, due to the non-conductive memory cell (M), the potential level of the connected bit line (BLe) will remain This high level" On the other hand, if the threshold voltage is lower than the read or verify level, due to the conductive memory cell (M), the potential level of the connected bit line (BLe) will be reduced to a level of, for example, less than 0.5V Such a low level. Further details of the read and verify operations will be described below." Figure 7 shows a fraction of the column control circuit 2 shown in Figure 1. Each pair of bit lines (BLe and BLo) are

02143467.0 is connected to the data storage section 16 including two data storage (DS1 and DS2) registers, each of which can store one bit of data. The data storage section 16 reads out the potential level of the selected bit line (BL) in a read or verify operation and stores data in a binary manner, and controls the bit line voltage in a program operation. The data storage part 16 is selectively connected to the selected bit line (BL) by selecting the _ signals of "EVENBL" and "0DDBL". The data storage part 16 is also connected to the I/O line in order to output the read data and Store programming data. The I/O line is connected to the data input/output buffer 6 as described in Figure 1 above.

Normal operation of the memory system Figure 8 shows the threshold voltage distribution state of the memory cell array 1 when each floating gate memory element stores two bits of data in each memory cell (M), that is, four data states. Curves 25 represents the distribution state of the threshold level V? of the cells inside the array 1 in the deleted state (TT data state), which is a negative threshold voltage level·Threshold voltage distribution state curve of the memory storing T0" and TT user data respectively 26 And 27, displayed as being between 0V to IV and IV to 2V. Curve 28 shows the cell distribution state programmed to the "01" data state, and the highest threshold voltage level of the read pass voltage is set to be higher than 2V and lower At 4.5V.

Each of the 2 bits stored in each individual memory cell (M) is from a different logical page in this example. That is, each of the two bits stored in each memory cell is Carry logical page addresses that are different from each other. The right bit shown in Figure 8 is accessed when the lower page address (=0, 2, 4,, 16, 382) is entered. The bits on the left are in higher page addresses (=1, 3, 5,...,

17, 383) is accessed when entered.

In order to provide improved reliability, it is best to make the independent distribution states close (narrow the distribution states), because a closer distribution state will bring a wider read width (distance between them). According to the present invention, the distribution The state width is tightened without limiting the reduction of programming speed.

According to the article titled "Fast and Accurate Programming Method for Multilevel NAND EEPROM, Pages 129-130, VLSI Technical Essays 1995 Catalogue", this article is included as a reference in this article, which will The distribution state is limited to 0.2V width, which requires that the usual repeated programming pulses are increased by 0.2V between the step lengths. In order to limit the distribution state to 0.05V width, a step length pulse increase of 0.05V is required. In order to increase with such a small step size Programming the cell will result in a 4 times increase in programming time. However, according to the main aspect of the present invention, as described below, such a significant increase in programming time does not reduce the width of the threshold voltage distribution state.

02143467.0 Figures 9A and 9B respectively show the existing programming pulse technology and the threshold distribution width of the cell programmed to a specific state. Figure 9A shows a waveform signal of a programming voltage Vpgm. The programming voltage Vpgm is divided into multiple pulses, and each pulse is incremented by 0.2V. It can be said that a Vpgm step size is 0.2V. In this example, the starting level of Vpgm is 12V. The threshold voltage of the fastest programming memory cell The change is represented by the white square in Figure 9B. The fastest programming memory cell reaches the first pass verification level after the 14V pulse. The maximum width of the result distribution state is ^£ = 0.2/ During the inter-pulse phase, the programming verification operation Is executed. This means that the programming level of each cell being programmed is simultaneously read during each programming pulse to determine whether it is equal to or greater than the verification level to be programmed. If the threshold value of a given memory cell is determined If the voltage has reached the verification level, remove Vpmg by increasing the voltage of the bit line until the series of cells of a given cell are connected from 0V to Vdd. The programming of other programmed cells continues until they reach their verification level in turn Until the last programming pulse of the cell, when the threshold voltage changes from lower than the verification level to higher than this level, the drift of the threshold voltage is equal to the step value of Vpgm 0.2V. In this way, the threshold voltage is controlled Within a 0.2V width.

Figures] 0A and] 0B show the specific prior art for programming the above-mentioned type of 4-state NAND memory cell array. In the first programming channel, the threshold level of the cell is set according to the bits from the lower logic page. If that The bit is T, and since that state is the result of having been deleted earlier, nothing will happen. However, if the bit is "0", the cell level is raised to the first programming state 34. This will end the first programming channel. In the second programming channel, the cell's net value level is stored in the cell according to the higher logic page. If it is T, the cell will not be programmed because it is in state 33 or 34. These states depend on the programming of the lower page bits, each with the upper page Bit "1". If the upper page bit is "0", the cell will be programmed for the second time. If the first channel causes the cell to remain in the deleted state 33, the cell is programmed from this state to the highest state 36, as shown in Figure 10B. As shown by the arrow. If the cell is programmed to state 34 due to the first programming channel, then the cell is further programmed from this state to state 35 in the second channel, as shown by the programming lower arrow in Figure 10B. The result is to program the cell to the specified state without changing the programming result of the first channel to store "0" from the previous page.

Of course, if the memory is operated according to more than four states, there will be multiple distributions in the internal window of the set voltage threshold of the memory cell, which is equal to the number of states. Further, even though each distribution state is Is assigned a specific bit combination, but different bit combinations can also be assigned, here

02143467.0 In the first case, the state between programming can be different from that shown in Figures 10A and 10B. There is such a change in the Toshiba patent referenced in the background art.

Generally, the cells that are programmed at the same time alternate along the word line. FIG. 11 shows three memory cells 41, 42 and 43 among a plurality of cells arranged along a word line 44. A set of alternating cells, including cells 41 and 43, which store the bits of logical pages 0 and 2 ("even pages"), and another alternating cell, including cell 42, which stores logical pages] and 3 ("odd pages") Bit. This results in programming at least 4 pages of data on a row of memory cells in a complete programming cycle that repeats the sequence of 4 pages of data at a time.

In the first programming step performed on at least Tp divided memory cells in a row with reference to Figures 10A and 10B above, the bits from the lower page 0 are first programmed to the first group of independent alternating cells and then from the lower page] The bit to be programmed into a separate second alternate unit. After these steps, the programming state distributions "11" (and the deleted state) and "10" of pages 0, 2 and pages 1, 3 all exist as solid lines as shown in Figure 11. The bits from the higher page 2 are then programmed to the first group of alternating cells, followed by the final step of programming the higher page 3 to the second group of alternating cells. Due to the above-mentioned Yupin effect, the apparent distribution of "11" and "10" states becomes slightly wider than the threshold distribution shown by the solid line that exists after its programming, as shown by the wider dash-dotted line. This is because when the data programming of the low page 0 and] is initially carried out in an environment where there are no adjacent floating gates including the high load levels representing the states "00" and "01". The broadening of the initial distribution state shown occurs when neighboring cells are programmed to their higher threshold level state. Furthermore, because the adjacent floating gate is written by data from page 3 in order to increase its charge level to the "00" and "01" states of odd-numbered pages, the higher states "00" and "00" of pages 0 and 2 are "01" will also be affected by the effect of this appearance widening.

The effect of this broadening of the appearance is to add a limit to the number of states in which the memory may be manipulated, and create other operational constraints. This needs to maintain a sufficiently large margin between the state distributions so that the states of a wider display distribution can be clearly distinguished in the data read operation. Only the last two programmed states in pages 1, 3 without dashed threshold level divergence as shown in Figure 11 will not be affected by the Yupin effect, because the charge levels of adjacent floating gates will not change anymore. s reason. As shown in FIG. 10B, the "00" and "01" states of the memory cell storage bits from pages 1, 3 shown in FIG. 11 are programmed last. As for the other six cell storage bit states from pages 0, 2 and 1, 3, due to the electric field coupling between the floating gates, the subsequent programming of adjacent cells affects the threshold voltage distribution.

02143467.0 New Editing Technique Example Figure 12 illustrates the two improved effects of the above-mentioned programming technique with reference to Figures 9-11. First, the order in which the pages are programmed is changed so that the first two pages of data bits to be programmed are written into one column The first alternate memory cell is followed by writing the following two data bits to the second alternate cell. This will have the effect of removing the two additional programming states from the Yupin effect. Secondly, the initial state distribution is shrunk (compressed) so that the appearance broadening phenomenon still produced by the Yupin effect still makes the effective distribution state width smaller, preferably not exceeding the actual distribution state of the first programming. Each of the above advantages can be achieved independently, or be used at the same time. Figure 12 shows an example of its common use.

When the same data page set for the first and second groups of alternate memory cells is programmed as shown in Figure 11, the _th improvement shown in Figure 12 is to sequentially change the data from pages 0 and 2 The data is written to the first group of cells, and then the data from the 1st and 3rd pages are written to the second group of cells. That is to say, the four pages of data are not written alternately to the first and second and select : Cells, as in the example in Figure 11, but before the second button is programmed with any data, the first group is programmed with two pages of data. The second group of alternate memory cells is then programmed with the third and fourth pages of data. The result is As shown in the figure, the Yupin effect related to the state T0 of the memory cell memory page 1, 3 is eliminated. This is because the floating gate charge level of the adjacent first group of alternate memory cells (memory pages 0, 2) is in the second The group cells are not increased after being programmed by data pages 1, 3. All three programming states of pages 1, 3 will not produce the Yupin effect, thereby reducing the possibility of incorrectly reading the stored data pages 1, 3 .

But because after the first group of cells are programmed by data pages 0, 2, and the second group of alternate memory cells are programmed by data pages 1, 3, the storage state of the first group will be affected by the Yipin effect. In order to overcome this problem first The threshold voltage distribution state of the group cell is compressed. Referring to FIG. 10A, the initial programming of data page 0 will produce the distribution state 51. However, before the data page 2 is programmed, the distribution state is reprogrammed to reduce the width of the distribution state, as shown in curve 52 As shown. After the programming of all 4 pages is completed, the Yupin effect will cause the display range of the state threshold distribution "10" to expand to the range shown by the curve 53. The display distribution state 53 must be controlled to be equal to or less than the original The range of distribution status 51.

After data page 0 is programmed and compressed, when data page 2 is programmed to one of the programming states "00" and "01", the same processing is performed. The data is first written to the first group of alternating cells and compressed and The Yupin effect is effectively extended from the subsequent programming process of the adjacent second set of alternating cells.

Figure 13 shows the execution steps to achieve one of the two compression state distributions shown in Figure 12. The state is first programmed with data for the first verification level 61. That is, every programming voltage pulse is applied to

02143467.0 After the first programmed cell reaches this state, those cells are read by applying appropriate voltage conditions to them to determine whether the threshold voltage level of a single cell reaches or exceeds level 61₀If this is the case, programming will stop. If not, an additional programming pulse will be applied and the status will be read again. The result is that a group of memory cells are programmed to a given state with a voltage threshold distribution state as shown by curve 62. As described above, the width of the distribution state 62 is controlled by the value of the applied programming pulse, initially the voltage change between pulses.

In order to shrink the distribution, after all the cells are programmed to this state at the same time, their state is read by using a threshold level 63 that is slightly lower than the isopole 61. This distinguishes those cells programmed to other states by reading only those cells programmed to one state of interest. Or, if the data can be obtained through a register. By using the threshold voltage verification level 64 higher than the first verification level 61 and restricting it to the distribution 62, the second pass (second pass) of those units to this state will be performed. The effect of this second process operation is to reprogram those cells that are lower than the programming threshold voltage level of the level 64 to be higher than the verification level 64, as shown in the distribution state 65. It can be seen from FIG. 13 that the actual threshold level distribution state anvil is narrower than the initial distribution state 62. When other adjacent cells are programmed by increasing their stored charge levels, the displayed distribution state will be broadened due to the Yupin effect, as shown in the distribution state 66. The width of the displayed distribution state 66 is smaller than the width without the second programming process, and its number is approximately equal to the difference between the verification levels 61 and 64.

FIGS. 14A and 14B show an improvement of the programming method described with reference to FIGS. 9A and 9B including the second programming step described with reference to FIG. 13. The use of the second pass channel (second a write) step, and the different check levels of the first channel (61) and the second it channel (64) are displayed. The threshold voltage change of the fastest programmed memory cell is represented by the white box shown in FIG. 14B, and the slowest part is represented by the black box. The first programming channel (first channel writing) is similar to the existing programming steps, but uses a relatively low verification level 61. The verification level 64 used for the second programming channel can be the same as the one currently used. The level is the same.

When the threshold voltage changes as a result of a programming pulse from being lower than the Tt-th track verification level 61, the threshold voltage drift in this example is the same as the ΔVpgm step value 0.2V. In this case, the threshold voltage is controlled within the distribution 62 having a width of 0.2V, which is the same as the prior art, but due to the lower verification level 61, the distribution state is placed at a position lower than the result from the prior art.

After the writing of the first channel is completed and before the writing of the second channel is started, those memory cells with a verification level 61 higher than that of the first channel write and lower than the verification level 64 of the second channel write become the second channel The goal of writing. If the fastest programmed memory cell reaches the Tt after e.g. a 13.8V pulse

02143467.0 The verification level 61 of the first write, the starting Vpmg level of the second write is set to 13.4V or lower than 13.4V, thereby reducing the threshold voltage drift to less than 0.2V. In this example, The initial programming voltage Vpmg level written by the second channel is set to 13.4V, but the first channel writes 12V. When the threshold voltage of the unit channel is written by the second channel due to a programming write, it is lower than the calibration level. When the verification level 64 becomes higher than this level, the threshold voltage drift is kept below 0.05V. Thus, the threshold voltage distribution of the target memory cell is controlled within a range of 0.05V width, which is much higher than Existing technology. In this way, if the verification level 61 written in the first channel is at least 0.15V smaller than the verification level 64 written in the second channel, the total width of the threshold voltage distribution is 0.05V.

In this example, the maximum Vpgm level written by the second channel will be 0.2V higher than that written by the first channel in the worst case. This is because the verification level higher than 0.15V is used in the second channel. In addition, since the start Vpgm of the second channel write can be much higher than the first channel write, the second channel write time is usually shorter than the first channel write. Therefore, it can be seen that the threshold voltage is changed by two programming channels The execution cost required to reduce the distribution width from 0.2V to 0.05V is less than double the programming time. In the existing programming technology that uses the 0.05V Vpgm step size to achieve the same compressed programming distribution width, the programming time is more When the width is 0.2V, the time used is extended by 4 times. The programming time required by the two-programming channel technology is almost twice as fast as the time required to achieve the same threshold voltage distribution using the prior art.

Figures 15A and 15B correspond to Figures 14A and 14B, respectively, and show an improvement in which the ΔVpgm step size of the first programming channel becomes larger. This is to reduce the programming time, while the second programming channel remains the same to define a narrower In this example, the Vpgm step length of the first channel write is increased from 0.2V to 0.4V. The verification level of the first channel write is reduced to 0.2V, and the first channel writes and the second channel writes at the same time. The difference between the verification levels of the channel write is increased from 0.2V to 0.35V. The extension of 0.2V is equal to the difference in the step size of ΑΥρδίη (0.4V-0. 2V). Programming of the first channel write and the second channel write The starting level of the voltage Vpgm is the same as the 0.2V step size Vpgm example shown in FIG. 14A. The writing duration of the first channel is reduced by about half, which is compared with the 0.2V step size Vpgm shown in FIGS. 14A and 14B. The programming time of the example has been reduced by more than 25%.

In each of FIGS. 14A and 15A, the first few programming pulses written by the first channel can also be formed without the time (not shown) in between in order to read and verify the programming level on the target memory cell. This is because Almost no target unit can reach its set national value in the first few pulses. This can also be done with the first few pulses written in the second channel. As a result, the programming time can be further reduced.

The above-mentioned specific embodiment with reference to FIGS. 12-15 is completed after the initial programming, and after the execution of the adjacent

02143467.0 Before the programming of the first unit, and thus before the initial programming state is distorted by the Yupin effect, the programming step is used to compress the programming distribution state. In the embodiment described below with reference to Figures 16-18, the distributed state compression reprogramming step Occurs when all states have been initially programmed, so that due to the Yupin effect, the distortion of the threshold level distribution state has already existed at a later stage. "Refer to Figure] 6, a programming technique is explained, in which pages 0 and 2 are First, program to the first group of alternating storage elements in a row, and then program pages 1, 3 to the second group of alternating storage elements in the same row. Because one group is fully programmed with data from all pages before another group of storage elements is programmed, there will be no post-programming pages that appear due to the Yupin phenomenon, in this case pages 1, 3 The phenomenon that the state distribution of, becomes wider. However, because of the capacitive coupling of the adjacent first and second groups of alternating storage elements along the selected word line, such a first programming page, here is page 0, 2 , The display expansion of the state distribution will also occur. A way to correct the display distribution drift of pages 0 and 2 is to use the same check level and reprogram the first group of storage elements with the same data in the usual way. This will lead to Page 0, The state distribution of 2 drifts because its reprogramming is performed under the influence of the charge level of the adjacent storage element. The new reprogramming distribution then corrects the initial programming data, in this example it is Yupin of page 0, 2, effect.

However, it is often desirable to compress the state distribution while reprogramming. This will not lead to performance degradation, because the main step of compression is to reprogram with a different check level. This has been explained with reference to Figure 13, where compression reprogramming occurs before the adjacent storage element is programmed, thus affecting the Compressed state distribution. In the programming sequence shown in Figure 16, compression reprogramming occurs after the adjacent storage elements are programmed.

In the programming sequence shown in Figure 17, the process of compressing and reprogramming the state distribution of data pages 0 and 2 is shown. After the initial use of the check level 71 to program pages 0 and 2, and after the page 1 , 3 Before programming, the distribution of each state is shown in curve 72. After pages 1, 3 are programmed, the distribution will become wider, as shown in curve 75. In this state, read cells using read level 73 In addition, a check level 74 is used for reprogramming, and the result is the display distribution state as shown by the curve 76, and the actual distribution state is shown by the dot-dash line 77. The applied programming and reprogramming pulses are as shown in Fig. 14A Similar to. The predetermined compression is performed through the displayed distribution state 76 that is narrower than the displayed distribution state 75.

Figures 18 and 19 show the same programming sequence and reprogramming steps corresponding to Figures 16 and 17, except that the programming voltage pulse (first channel write) used for initial programming is increased by 0.4V at each pulse,

02143467.0 The first reprogramming voltage pulse (second channel write) is increased by 0.2V for each pulse, as shown in Figure 15A. The higher Vpgm on the initial programming channel shortens the programming and reprogramming process required to complete time.

Figure 20 shows another possible programming technique using different aspects of the present invention. The method includes the steps described with reference to Figures 12 and 13, followed by a second re-reading of the initial data pages 0 and 2 Additional steps of programming. This second reprogramming occurs when the other data pages 1, 3 have been programmed, and does not need to include compression of the state distribution, but it can be done.

Although the exemplary embodiments according to the first two aspects of the present invention are described in conjunction with a flash EEPROM system with a NAND memory cell array structure, it should be recognized that these and other aspects of the present invention can be applied to any flash memory. Structure (such as a flash EEPROM system with a NOR memory cell structure) or other types of non-volatile memory, in which there will be some coupling between storage elements that affect the display distribution of storage levels representing the same memory state, and hope The effect can be reduced. Example, the nitrile method Figure 21 shows an exemplary algorithm for programming the even-numbered rows of the lower page according to the technique described with reference to Figures 12, 13 and 14. The algorithm can be divided into three parts The first ^ point is the part enclosed by the dashed line (S1 to S4). This part shows the interface program. At the beginning (S1), the "data load" command is issued by the flash memory controller and input to the data input/output buffer (6). The input data is recognized as a command and latched in the state machine (8), because at this time there is a non- The displayed command latch signal is input to the command interface (7). In the next step (S2), the address data of the specified page address is input from the controller to the data input such as/output buffer (6), and then latched. Input data It is recognized as a page address and locked in the state machine (8), because at this time an unshown latch signal is input to the command interface (7) ° Next (S3), 532B-program-data is input to the data input/output buffer (6). The input data is latched to data memory 1 (DS1) because the "data load" command is latched at this time. At the end (S4) , The "program" command is generated by the flash memory controller and input to the data input/output buffer (6). The input data is recognized as a command and latched in the state machine (8), because the command latch signal is input to Command interface (7). Triggered by the "program" command, the data latched in the data memory 1 (DS1) is automatically programmed (S5 to S20) to the selected memory cell (M) controlled by the state machine (8).

The second part of the algorithm is the writing of the first channel of steps S5 to S10. "First, the starting Vpgm is set

02143467.0 The 12V programming counter embedded in the state machine (8) is set to 0 (S5). Then the first programming pulse is applied to the selected word line, such as WL2 (S6) shown in Table I ). If the money stored in the data memory 1 (DS1) is "0" data, the corresponding bit line (BL) is grounded ("program activation" table 1). On the other hand, if the data memory 1 (DS1) is latched "T data is in the data, the corresponding bit line (BL) is connected to Vdd ("Programming Disable Table 1) After programming, the state of the selected memory cell is verified. In order to verify, the first channels Check 10 is executed (S7). In this operation, the threshold voltage is checked whether it has reached the 0.2V check level of the first channel, as shown in Table I. If it is detected that the threshold voltage has been reached, the DS is locked Data "0" in 1 becomes data "1". If it is detected that the threshold voltage is not reached, the data "0" latched in DS1 will continue to be maintained. Data that already exists^αΓ is also maintained. In this way, since the data "0" becomes data T one by one, and the data T does not depend on the state of the memory cell to be maintained independently, eventually all the data latched on the data memory DS1 will become Τ data. This means that all memories are successfully programmed after being judged by the verification level from the first channel. After the verification operation, it will be checked whether all the data latched in the data memory DS1 have become data "1". (S8). If all have become Τ, the first channel writing is terminated and the second channel writing starts. If it has not become Τ data, the algorithm proceeds to step S9.

In step S9, the count value of the programming counter is checked. If the count value is less than 20, the Vpgm level is increased by 0.2V, and the count value is increased by 1 (S10), and the algorithm returns to the programming step S6. If the count value is not less than 20, the state machine The status data in is set to "failure", and then the algorithm terminates (S11).

The third part of the algorithm is the second channel write (S12 to S20). Initially, the second channel read 10 is executed (S12). In this operation, the memory cell with a threshold voltage higher than 0V is extracted, and " 0" data is set to the corresponding data memory 1 (DS1). T data is set to the remaining data memory 1 (DS1).

Next, the verification 10 of the second channel is executed (S13). In this operation, those memory cells whose threshold voltage is above 0V and below 0.4V are verified by using the second channel verification level of 0.4V and have been stored The data on the data memory 1 (DS1) is extracted. The threshold voltage is checked to see whether it has reached the verification level of the second channel as shown in Table I. If it is detected that the threshold voltage has been reached, the data in DS] is locked "0" becomes data T. If it is detected that the voltage of the same value has not reached, the data "0" latched in DS1 will continue to be maintained. The existing data T" is also retained.

After verification 10 (S13) of the second channel, the initial Vpgm is reset to 13.4V and the meter is programmed at the same time

02143467.0 The first register is reinitialized to 0 (S14). Next, the first programming pulse 13.4V is applied to the selected word line as shown in Table I (S15). If it is latched in the data memory 1 (DS1), yes "0" data, the corresponding bit line (BL) is grounded ("program activation" table 1)" On the other hand, if the data latched in the data memory 1 (DS1) is T data, the corresponding bit line (BL) is Connect to Vdd ("Programming prohibited").

After programming (S15), the state of the selected memory cell is verified. For verification, verification 10 of the second channel is performed (S16). In this operation, the threshold voltage is checked whether it reaches the second channel The 0.4V calibration level is shown in Table I. If it is detected that the threshold voltage has been reached, the data "0" latched in DS1 becomes data T. If it is detected that the threshold voltage is not reached, the data "0" latched in DS1 continues to be maintained. The existing data T also In this way, because the data "0" _ each becomes data T, and the data T" does not depend on the state of the memory cell to be maintained independently, eventually all the data that continues to be stored on the data memory DS1 will become T data. This means that all memories have been successfully programmed. After the verification step (S16), it will check whether all the data latched in the data memory DSI have become data T (S17). If all have been changed When it becomes "1", the second channel write is terminated and the entire program algorithm is terminated, and the status data is set to "pass" (S20). If it does not become "1" data, the algorithm proceeds to step S18.

In step S1 & the count value of the programming counter is checked. If the count value is less than 13, the Vpgm level is increased by 0.2V, and the count value is increased by 1 (S19), and the algorithm returns to the programming step S6. If the count value is not less than 13, the state machine The status data is set to "failure", and then the algorithm terminates (S11).

Figure 22 shows an exemplary algorithm for programming the even-numbered rows of the higher page according to the technique described with reference to Figures 12, 13 and 14. The algorithm can be divided into three parts. The first part is the dotted line (S1 to S4) The enclosed part. This part is exactly the same as the steps S1 to S4 shown in FIG. 21.

The second part of the algorithm is the writing of the first channel of steps S5 to S13. First, reading 10 of the first channel is executed (S5). In this operation, the threshold voltage higher than 0V is selected, and then " 0" data is set to the corresponding data memory 2 (DS2). T data is set to the remaining data memory 2 (DS2). The memory cell start Vpgm is set to 14V and the programming counter is set to 0( S6). Next, the first programming pulse is applied to the selected word line, such as WL2 (S7) shown in Table I. If the data latched in the data memory 1 (DS1) is "0" data, the corresponding bit The line (BL) is grounded ("program activation" table I). On the other hand, if the data latched in the data memory 1 (DS1) is T data,

02143467.0 The corresponding bit line (BL) is secreted to Vdd ("program prohibition" ΛΙ).

After programming, the state of the selected memory cell is verified. For verification, verification 01 is performed at the first location (S8). In this operation, the threshold voltage is checked to see whether the threshold voltage has reached as shown in Table I 2.4V verification level. If it is detected that the threshold voltage has been reached, the data "0" latched in DS1 becomes data "1". If it is detected that the threshold voltage has been reached, the data latched in DS1 becomes "0" It is the data T. If it is detected that the threshold voltage has not been reached, the data "0" stored in DS1 continues to be maintained. The existing data T" is also retained. At the second location, the verification 00 of the first channel is executed (S9). In this operation, the threshold voltage is detected whether it reaches the 1.2V verification level of the first channel , As shown in Table I. If it is detected that the threshold voltage has been reached and the data stored in the corresponding data memory (DS2) is "0" data, the data "0" latched in DS1 becomes data T.

If the relevant data memory 2 (DS2) has T data, the "0" data stored in the data memory 1 (DS1) remains unchanged, regardless of the detection result. If it is detected that the threshold voltage has not been reached, the data "0" latched in DS1 continues to protect the existing data T" and is also retained.

In this way, since the data "0 becomes data "T one by one, and the data T does not depend on the state of the memory cell to be maintained independently, eventually all the data latched in the data storage DS1 will become T data. This means that all memories are successfully programmed after being judged by the verification level "01" state from the first channel and the verification level "00" state of the first channel.

After the verification operation, it will check whether all the data latched in the data storage DS1 have become data T (S10). If they have become T, the first channel writing is terminated and the second channel Start writing. If it does not become T data, the algorithm proceeds to step S11.

In step S11, the count value of the program counter is checked. If the count value is less than 20, the Vpgm level is increased by 0.2V, and the count value is increased by 1 (S12), and the algorithm returns to the programming step S7. If the count value is not less than 20, the state data in the state machine is set to "failed", Then the algorithm terminates (S13).

The third part of the algorithm is the second channel write (S14 to S22). At first, the read 00 of the second channel is executed (S14). In this operation, the memory cell with a threshold voltage higher than IV is extracted, and " "0" data is set to the corresponding data memory 1 (DS1). "1" data is set to each remaining data memory 1 (DSl).

Next, the verification 00 of the second channel is executed (S15). In this operation, those memory cells whose threshold voltage is above IV and below 1.4V are verified by using the second channel verification level of 1.4V and have been stored. The data on the data memory 1 (DS1) is extracted. The voltage of the same value is checked whether it has reached the

02143467.0 The 1.4V calibration level of the second channel shown in Table I. If it is detected that the threshold voltage has been reached, the data "0" that continues to exist in DS1 becomes data T «If it is detected that the threshold voltage is not reached, The data "0" stored in DS1 continues to be maintained. The existing data T is also maintained.

After verifying 00 (S15) of the second channel, the starting Vpgm is reset to 14.4V and the programming counter is reinitialized to 0 (S16). Next, the first programming pulse 14.4V is applied to the selected word line , As shown in Table I (S17). If the data latched in the data memory 1 (DS1) is "0" data, the corresponding bit line (BL) is grounded ("Programming Excitation" Table I). On the other hand, If the data latched in the data memory l (DSl) is T" data, the corresponding bit line (BL) is connected to Vdd ("program prohibition" ΛΙ).

After programming (S17), the state of the selected memory cell is verified. In order to verify, the verification 00 of the second channel is executed (S18). In this operation, the threshold voltage is detected whether it reaches the second channel As shown in Table I, "If it is detected that the threshold voltage has been reached, the data "0" latched in DS1 becomes data T. If it is detected that the threshold voltage is not reached, it is latched in DS1. The data "0" continues to be maintained. The existing data "1" is also maintained. In this way, because the data "0" _ each becomes data T", and the data T does not depend on the state of the memory cell independently Keep, eventually all the data locked in the data memory DS1 will become T data. This means that all the memories have been successfully programmed · After the verification step (S18), it will be checked whether all the data locked in the data memory DS1 All become data "T (S19). If all have become T", the second channel writing is terminated and the entire program algorithm is terminated. Set the status data to "Pass" (S22). If it does not become T data, the algorithm proceeds to step S20.

In step S20, the count value of the programming counter is detected. If the count value is less than 13, the Vpgm level is increased by 0.2V, and the count value is increased by 1 (S21), and the algorithm returns to the programming step S17. If the count value is not less than 13, the status data is set to "failure", and then the algorithm terminates (S13).

In the algorithm described in Figure 22, writing to the second channel of the memory cells to be programmed to the state "01" is avoided, because writing to the second channel of the "01" state also requires the largest Vpgm and will also cause failures. Necessary programming interrupt. However, if necessary, according to the present invention, it can be easily achieved.

Figure 23 shows an exemplary algorithm that implements the techniques described in Figures 12, 19 and 15 to program even columns with lower data pages. The algorithm is similar to that shown in Figure 21. The difference lies in the Vpgm step of the first channel write Long size (S10) and the maximum count value (S9) of the programming counter written in the related first channel. Here

02143467.0 The Vpgm step size is increased from 0.2V to 0.4V, which is to speed up the writing of the first channel.

Figure 24 shows an exemplary algorithm for programming even-numbered columns with higher data pages using the techniques described in Figures 12, 19, and 15. The algorithm is similar to that shown in Figure 22. The difference is the Vpgm step size (S12) written in the first channel and the related maximum count value of the programming counter (S9) written in the first channel. The Vpgm step size here is from 0.2V Increase to 0.4V, this is to speed up the first channel write.

Figures 25 and 26 show exemplary programming algorithms for executing the methods shown in Figures 12, 13 and 14 when combined with the programming algorithms shown in Figures 21 and 22, respectively. The algorithm shown in Figure 25 is for odd numbers The algorithm for programming the column. This algorithm does not have the process of writing the second channel in the programming algorithm for even-numbered columns as shown in Figure 21. The verification level of the first channel's verification 10 has changed from 0.2V to 0.4 V, this is to set the distribution to be higher than 0.4V as in the second channel writing. The algorithm shown in Figure 26 is an algorithm for programming odd columns. This algorithm does not have the process of writing the second channel in the programming algorithm for even number columns as shown in Figure 22.The verification level of the verification 00 of the first channel has been changed from 1.2V to 1.4V. This is for In the second channel writing, the distribution is set to be higher than 1.4V, and the distribution is set to be higher than 1.4V. The combination of algorithms shown in Figures 21, 22, 25 and 26 can compensate for the Yupin effect. Therefore, the programming ability is Improved.

Figures 27 and 28 show exemplary programming algorithms for executing the methods shown in Figures 12, 19, and 15 when combined with the programming algorithms shown in Figures 23 and 24, respectively. The algorithm shown in Figure 27 is an algorithm for programming odd-numbered columns. This algorithm does not have the process of writing the second channel in the programming algorithm for even-numbered columns shown in Figure 23. The calibration of the first channel's check 10 The verification level has changed from 0.2V to 0.4V. This is to set the distribution to be higher than 0.4V as in the second channel writing. The algorithm shown in Figure 28 is correct. Algorithm for programming odd rows. This algorithm does not have the process of writing the second channel in the programming algorithm for even columns as shown in Figure 24. The verification level of the verification 00 of the first channel has changed from 1.2V to 1.2V. 1. 4V, this is to set the distribution to be higher than 1.4V as in the second channel writing.

The combination of algorithms shown in Figures 23, 24, 27 and 28 can compensate for the Yupin effect. Therefore, the programming ability is improved.

Figure 29 shows an exemplary programming sequence used to perform the methods shown in Figures 12, 13 and 14. In each block, data programming is performed in the order of page addresses, from the even bit lines of the word line WL0 The lower page of the word line WL3 to the higher page of the odd bit line of the word line WL3. This sequence is formed by taking the Yupin effect into account.

02143467.0 Figure 30 shows an exemplary reading algorithm for reading compressed low data pages according to the method shown in Figures 16, 17. The part surrounded by dotted lines (S1 and S2) shows the interface process. Initially (S1 ), the "data read" command is issued by the flash memory controller and input to the data input/output buffer (6). The input data is recognized as a command and locked in the state machine (8), because there is an undisplayed command at this time The latch signal is input to the command interface (7). In the next step (S2), the address data of the specified page address is input from the controller to the data input/output buffer (6), and then latched. The input data is recognized as a page The address is also latched in the state machine (8), because at this time an unshown latch signal is input to the command interface (7). Triggered by the address data, the data stored in the selected memory cell (M) is Automatically read out (S4 and S5) controlled by the state machine (8).

In read 01, the memory cell with a threshold voltage higher than 2V is selected, and then the T data is set to the corresponding data memory 2 (DS2). The "0" data is set to the remaining data memory 2 (DS2) ). Next, read 10 is executed. In this operation. The memory cell whose threshold voltage is higher than 0V and lower than 2V is selected. If it is detected that the threshold voltage is lower than 0V or data memory 2 (DS2) stores T data, T" data is set to data memory 1 (DS1), Otherwise it is "0".

The data stored in the data memory] (DS1) is output to the outside through the data input/output buffer in synchronization with the read signal (not shown) input to the command interface (7)." Figure 31 shows the data according to Figures 16, 17 The method shown is an exemplary reading algorithm for reading compressed low data pages. The part enclosed by the dashed lines (S1 and S2) is the same as that shown in FIG. 30. In reading 00, the threshold voltage is higher than IV The memory cell is selected, and then the "0" data is set to the corresponding data memory] (DS1). The T" data is set to the remaining data memory 1 (DS1). Stored in the data memory 1 (DS1) The data is output to the outside through the data input/output buffer in synchronization with the read signal.

Although different aspects of the present invention have been described with reference to specific embodiments, it should be understood that the present invention should be protected according to the scope of the following claims"

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